High speed audio and control integrated bus and device

Abstract

The application provides a high-speed audio and control integrated bus and device, which comprises: SCLK: a clock for providing communication; STX: a device for transmitting data from a master device; SRX: a device for receiving data from a master device. The master device is connected with one or two slave devices through the bus. The application realizes the transmission of audio data, the control of registers and the data frame synchronization technology between the master device and the multiple slave devices through only three bus ports, so as to reduce the wiring difficulty of the system board, reduce the communication failure and save the cost of the system.

Description

Technical Field

[0001] This invention relates to the field of voice electronic transmission technology, and more specifically, to a high-speed audio and control integrated bus and device. Background Technology

[0002] In all audio chips, voice communication primarily uses the PCM communication interface, involving the frame synchronization signal FSYNC, the voice transmission clock signal PCLK, the voice input signal DRX, and the voice output signal DTX. The control signals for the registers use the SPI protocol, with a chip select signal CS, a control transmission clock signal SCK, a control input signal SDI, and a control output signal SDO. Both interfaces require eight pins, reducing the chip's area and performance. In daily use, increased signal interference on the PCB further reduces reliability, frequently resulting in buzzing noises.

[0003] The TLV320AIC3263 audio chip from Texas Instruments uses a PCM voice interface and an SPI control interface, resulting in a total of 81 pins. In actual product packaging and chip soldering processes, the excessive number of pins can lead to reliability issues. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of this invention is to provide a high-speed audio and control integrated bus and device.

[0005] According to the present invention, a high-speed audio and control integrated bus includes:

[0006] SCLK: The clock used for communication;

[0007] STX: Used to send data from the device to the master device;

[0008] SRX: Used to receive data from the master device from the slave device;

[0009] The master device is connected to one or two slave devices via a bus.

[0010] Preferably, the idle state potential of the bus is: SCLK is at a high level, STX is at a high level, and SRX is at a low level.

[0011] Preferably, the bus communication frequency includes 4.096MHz and 8.192MHz, wherein the 4.096MHz SCLK communication rate supports general audio quality communication, and the 8.192MHz SCLK communication rate supports high-definition audio quality communication.

[0012] Preferably, the bus supports audio communication frame synchronization. The audio communication frame synchronization technology involves the master device sending a pull-down signal for one SCLK cycle and a high-level signal for one SCLK cycle at a time interval of 125µs to separate frame synchronization and communication data.

[0013] Preferably, the data transmitted on the bus includes:

[0014] Read / write control protocol: 6 control bits, 14 address bits, 10 data length bits, and multiple data bits;

[0015] Audio data transmission protocol: 6 bits of control bits, 8 bits of audio data bits, or 16 bits of audio data bits.

[0016] Preferably, the 6-bit control bits include:

[0017] Read / write control bits: 1'b0 indicates a write operation, and 1'b1 indicates a read operation;

[0018] Register block bits: 1'b0 indicates register operation, 1'b1 indicates memory block operation;

[0019] Voice operation bits: 1'b0 indicates control operation, 1'b1 indicates voice operation;

[0020] Device selection bits: 1'b0 indicates selection from the first device, 1'b1 indicates selection from the second device;

[0021] Burst mode bits: 2'b00 indicates single-byte data operation, 2'b01 indicates double-byte data operation, 2'b10 indicates fixed-length data operation, and 2'b11 is a reserved bit.

[0022] Preferably, the 16 bits of audio data include:

[0023] Continuous audio data mode: 8 bits of audio data followed immediately by 8 bits of audio data;

[0024] Discrete audio data mode: 8 bits of audio data are followed by several idle states, and then another 8 bits of audio data.

[0025] Preferably, the 14-bit address bits include:

[0026] 1-bit channel selection: 1'b0 indicates channel 0 is selected, 1'b1 indicates channel 1 is selected;

[0027] A 13-bit address indicates that the address space is from 0 to 8191.

[0028] A high-speed audio and control integrated bus device according to the present invention includes a transistor S1 and a pull-up resistor r. tx First buffer, second buffer, SGEN module, SENC module, SDEC module, VENG module and CHAN module;

[0029] The gate of transistor S1 is connected to STX, the source of transistor S1 is grounded, and the drain of transistor S1 is connected to pull-up resistors r. tx The input terminal of the first buffer is connected to the input terminal of the first buffer, the output terminal of the first buffer is connected to the SGEN module, the SGEN module is connected to the control terminal of the first buffer and the control terminal of the second buffer respectively, and the SGEN module is connected to SCLK. The input terminal of the second buffer is connected to the gate of transistor S1, and the output terminal of the second buffer is connected to the SENC module.

[0030] The SDEC module is connected to the SRX, and the SDEC module is connected to the CHAN module and the VENG module respectively. The CHAN module and the VENG module are both connected to the SENC module.

[0031] The SGEN module is a serial controller that controls the generation time of the receive frame synchronization signal;

[0032] The SENC module is a serial encoder that encodes the control data and voice data to be sent to the master device according to the HVCI protocol.

[0033] The CHAN module is a control register;

[0034] The SDEC is a serial decoder that decompresses the received serial data in HVCI protocol format.

[0035] Preferably, the CHAN module includes a CHAN_A module and a CHAN_B module, which are respectively connected to the SDEC module and the SENC module. The CHAN_A module is the control register of channel A, and the CHAN_B module is the control register of channel B.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. This invention provides a solution to reduce the number of pins required for external communication and control, which can improve the quality of voice communication and increase the bandwidth of control data in terms of control speed.

[0038] 2. This invention offers significant economic benefits in terms of chip cost. By utilizing STX's frame synchronization technology, it reduces the need for independent frame synchronization signal pins. Using a 16-bit discrete audio transmission mode, it supports stereo voice data transmission. Using a 16-bit continuous audio transmission mode, it supports ultra-fidelity voice data transmission.

[0039] 3. This invention supports a scheme with two slave devices, which can increase the communication frequency of SCLK from 4.096MHz to 8.192MHz, thereby ensuring that the data rate of communication of a single slave device remains unchanged. Attached Figure Description

[0040] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0041] Figure 1 This is a structural diagram of the high-speed audio and control integrated bus of the present invention;

[0042] Figure 2 This is an internal module diagram of a device containing HVCI bus protocol status.

[0043] Figure 3 This is a schematic diagram of a pair of buffers in an embodiment of the present invention;

[0044] Figure 4 This is a diagram of the write control protocol for the HVCI bus of this invention;

[0045] Figure 5 This is a diagram of the read control protocol for the HVCI bus of this invention;

[0046] Figure 6 This is a diagram showing the 8-bit audio data transmission of the HVCI bus in this invention.

[0047] Figure 7 This is a diagram showing the 16-bit continuous audio data transmission of the HVCI bus in this invention.

[0048] Figure 8 This is a diagram showing the 16-bit discrete audio data bit transmission of the HVCI bus in this invention. Detailed Implementation

[0049] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0050] This invention implements a high-speed audio and control integrated bus (HVCI bus), referring to... Figure 1 As shown, the HVCI bus includes SCLK for providing the communication clock, STX for slave devices to send data to the master device, and SRX for slave devices to receive data from the master device. The HVCI bus allows for connections between one or two slave devices and the master device. By using only three bus ports, it enables audio data transmission, register control, and data frame synchronization between the master device and multiple slave devices, thereby reducing system board routing complexity, minimizing communication failures, and saving system costs.

[0051] The HVCI bus supports communication rates of 4.096MHz and 8.192MHz. The 4.096MHz SCLK communication rate supports general audio quality communication, while the 8.192MHz SCLK communication rate supports high-definition audio quality communication.

[0052] The idle states supported by the HVCI bus are: SCLK is high, STX is high, and SRX is low.

[0053] The audio communication frame synchronization technology supported by the HVCI bus is as follows: every 125us interval, the master device will send a pull-down signal for one SCLK cycle and a high-level signal for one SCLK cycle on the STX port to separate frame synchronization and communication data.

[0054] The data transmitted on the HVCI bus includes: Read / Write Control Protocol: 6 control bits, 14 address bits, 10 data length bits, and several data bits. Audio Data Transmission Protocol: 6 control bits, 8 audio data bits, or 16 audio data bits. For a 4.096MHz SCLK, a maximum of 480 control data bits can be transmitted per frame; for an 8.192MHz SCLK, a maximum of 992 control data bits can be transmitted per frame.

[0055] The 6-bit control bits include: Read / Write Control Bit (RW): 1'b0 indicates a write operation, 1'b1 indicates a read operation; Register Block Bit (RegBlock): 1'b0 indicates a register operation, 1'b1 indicates a memory block operation; Voice Operation Bit (VO): 1'b0 indicates a control operation, 1'b1 indicates a voice operation; Device Select Bit (DS): 1'b0 indicates selecting the first slave device, 1'b1 indicates selecting the second slave device; Burst Mode Bit (BM): 2'b00 indicates a single-byte data operation, 2'b01 indicates a double-byte data operation, 2'b10 indicates a fixed-length data operation, and 2'b11 is a reserved bit.

[0056] The 16-bit audio data includes: continuous audio data mode: 8 bits of audio data followed immediately by 8 bits of audio data; discrete audio data mode: 8 bits of audio data followed by several idle states, and then another 8 bits of audio data.

[0057] The 14-bit address includes: 1 bit for channel selection (CH): 1'b0 indicates channel 0 is selected, and 1'b1 indicates channel 1 is selected; 13 bits for address (Addr): indicating that the address space is from 0 to 8191.

[0058] The present invention also discloses a device supporting the HVCI bus protocol, with reference to... Figure 2 and Figure 3 As shown, the structure of the device is as follows.

[0059] Includes transistor S1, pull-up resistor r tx First buffer, second buffer, SGEN module, SENC module, SDEC module, VENG module and CHAN_A module;

[0060] The gate of transistor S1 is connected to STX, the source of transistor S1 is grounded, and the drain of transistor S1 is connected to pull-up resistors r. tx The input terminal of the first buffer is connected to the input terminal of the first buffer, the output terminal of the first buffer is connected to the SGEN module, the SGEN module is connected to the control terminal of the first buffer and the control terminal of the second buffer respectively, and the SGEN module is connected to SCLK. The input terminal of the second buffer is connected to the gate of transistor S1, and the output terminal of the second buffer is connected to the SENC module.

[0061] The SDEC module is connected to the SRX, and the SDEC module is connected to the CHAN_A module and the VENG module respectively. Both the CHAN_A module and the VENG module are connected to the SENC module.

[0062] The SGEN module is a serial controller that controls the generation time of the receive frame synchronization signal;

[0063] The SENC module is a serial encoder that encodes the control data and voice data to be sent to the master device according to the HVCI protocol.

[0064] The CHAN_A module is the control register for channel A;

[0065] The SDEC is a serial decoder that decompresses the received serial data in HVCI protocol format.

[0066] It also includes a CHAN_B module, which is connected to the SDEC module and the SENC module respectively. The CHAN_B module is the control register of channel B.

[0067] In the aforementioned device, frame synchronization technology utilizes NMOS transistor S1 and internal pull-up resistor r tx This is implemented using a pair of buffers with control ports. The control port signal SENB of the buffer is generated by the SGEN module. Upon initial chip power-up, the SGEN module is in a ready-to-receive state, the SENB signal is high, and the iSTX signal is an inverted follower of the STX port signal. Upon detection of the frame synchronization signal, in the next cycle of SCLK, the SGEN module is in a received state, the SENB signal is low, and iSTX is high impedance. After 125µs, the SGEN module is in a ready-to-receive state, and the SENB signal is high. If a pull-down signal of STX is detected, frame synchronization detection is successful; otherwise, frame synchronization detection fails. The value of the corresponding status register FRAME_SYNC_Status in the SGEN module will be set.

[0068] Connected to the SRX pin is the SDEC module, which parses messages on the serial bus to obtain the corresponding control content. If the VO bit is 1'b1, the data output by the SDEC module will be sent to the VENG for audio data processing. If the VO bit is 1'b0, the data output by the SDEC module will be sent to either the CHAN_A module (CH == 1'b0) or the CHAN_B module (CH == 1'b1), both of which are modules with register control. Simultaneously, data from the CHAN_A, CHAN_B, and VENG modules can be encoded by the module's SENC and then sent to the master device.

[0069] The device supports the following HVCI bus write control protocols: Figure 4If the control bits are 6'b10_0010, the address bits are 14'b00_0000_1000, and the data length bits are 10'b00_0001_0000, then subsequent data write operations will be performed on the control register starting at address 8, with a data length of 16 bytes. (Read control protocol if...) Figure 5 If the control bit is 6'b00_0010, the address bit is 14'b00_0000_1000, and the data length bit is 10'b00_0001_0000, then the subsequent data will be read from the register starting at address 8 of the control register. The data length is 16 bytes.

[0070] The device supports HVCI bus audio data reception, such as Figure 6 If the control bit is 6'b10_1000, it indicates that device 1 will receive subsequent single-byte audio data. 16-bit continuous audio data transmission... Figure 7 If the control bit is 6'b10_1001, it indicates that device 1 will receive subsequent two bytes of audio data. The internal register RXSTART indicates whether the audio data is discrete or continuous. If RXSTART equals 0, it indicates continuous audio data transmission, such as... Figure 7 If RXSTART equals 8, it indicates discrete audio data transmission. Figure 8 This indicates that the audio data interval is 8 SCLK cycles.

[0071] This device can be used with slave devices containing HVCI bus protocol status, and its SCLK, STX, and SRX ports are connected to the GPIO interface on the master device.

[0072] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A high-speed audio and control integrated bus device, characterized in that, include: SCLK: The clock used for communication; STX: Used to send data from the device to the master device; SRX: Used to receive data from the master device from the slave device; The master device is connected to one or two slave devices via a bus; It also includes: high-speed audio and control integrated bus devices; The high-speed audio and control integrated bus device includes a transistor S1 and a pull-up resistor. First buffer, second buffer, SGEN module, SENC module, SDEC module, VENG module and CHAN module; The gate of transistor S1 is connected to STX, the source of transistor S1 is grounded, and the drain of transistor S1 is connected to pull-up resistors. The input terminal of the first buffer is connected to the input terminal of the first buffer, the output terminal of the first buffer is connected to the SGEN module, the SGEN module is connected to the control terminal of the first buffer and the control terminal of the second buffer respectively, and the SGEN module is connected to SCLK. The input terminal of the second buffer is connected to the gate of transistor S1, and the output terminal of the second buffer is connected to the SENC module. The SDEC module is connected to the SRX, and the SDEC module is connected to the CHAN module and the VENG module respectively. The CHAN module and the VENG module are both connected to the SENC module. The SGEN module is a serial controller that controls the generation time of the receive frame synchronization signal; The SENC module is a serial encoder that encodes the control data and voice data to be sent to the master device according to the HVCI protocol. The CHAN module is a control register; The SDEC is a serial decoder that decompresses the received serial data in HVCI protocol format.

2. The high-speed audio and control integrated bus device according to claim 1, characterized in that: The idle state potentials of the bus are: SCLK is high, STX is high, and SRX is low.

3. The high-speed audio and control integrated bus device according to claim 1, characterized in that: The bus communication frequencies include 4.096MHz and 8.192MHz. The 4.096MHz SCLK communication rate supports general audio quality communication, while the 8.192MHz SCLK communication rate supports high-definition audio quality communication.

4. The high-speed audio and control integrated bus device according to claim 1, characterized in that: The data transmitted on the bus includes: Read / write control protocol: 6 control bits, 14 address bits, 10 data length bits, and multiple data bits; Audio data transmission protocol: 6 bits of control bits, 8 bits of audio data bits, or 16 bits of audio data bits.

5. The high-speed audio and control integrated bus device according to claim 4, characterized in that: The 6-bit control bits include: Read / write control bits: 1'b0 indicates a write operation, and 1'b1 indicates a read operation; Register block bits: 1'b0 indicates register operation, 1'b1 indicates memory block operation; Voice operation bits: 1'b0 indicates control operation, 1'b1 indicates voice operation; Device selection bits: 1'b0 indicates selection from the first device, 1'b1 indicates selection from the second device; Burst mode bits: 2'b00 indicates single-byte data operation, 2'b01 indicates double-byte data operation, 2'b10 indicates fixed-length data operation, and 2'b11 is a reserved bit.

6. The high-speed audio and control integrated bus device according to claim 4, characterized in that: The 16-bit audio data includes: Continuous audio data mode: 8 bits of audio data followed immediately by 8 bits of audio data; Discrete audio data mode: 8 bits of audio data followed by several idle states, and then another 8 bits of audio data.

7. The high-speed audio and control integrated bus device according to claim 4, characterized in that: The 14-bit address includes: 1-bit channel selection: 1'b0 indicates channel 0 is selected, 1'b1 indicates channel 1 is selected; A 13-bit address indicates that the address space is from 0 to 8191.

8. The high-speed audio and control integrated bus device according to claim 1, characterized in that: The CHAN module includes a CHAN_A module and a CHAN_B module, which are connected to the SDEC module and the SENC module, respectively. The CHAN_A module is the control register for channel A, and the CHAN_B module is the control register for channel B.

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