A data processing method, an electronic device, and a storage medium

Abstract

The application relates to the computer technical field and discloses a data processing method, an electronic device and a storage medium. The method comprises the following steps: obtaining to-be-processed data; performing bit extraction on the to-be-processed data; wherein the bit extraction on the to-be-processed data comprises the following steps: performing a first operation on an immediate number field in a self-defined instruction according to the bit number of the to-be-processed data to obtain a first immediate number and a second immediate number, the bit number of the first immediate number and the bit number of the second immediate number corresponding to the bit number of the to-be-processed data; performing bit extraction on the to-be-processed data according to the first immediate number and the second immediate number to obtain a first result; and storing the first result into a target register according to the address of the target register in the self-defined instruction. The application further discloses an electronic device and a storage medium. The data processing method adopts one self-defined instruction to realize the bit extraction operation, reduces the instruction number of the bit extraction operation, reduces the calculation time of the bit extraction operation, and improves the processor calculation speed.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular to a data processing method, electronic device, and storage medium. Background Technology

[0002] Computers use bitwise operations to directly manipulate binary data in memory, resulting in very fast data processing. Bit Field Extraction (BFX) is a type of bitwise operation that extracts a specific field from binary data, places it at the lower end of the data range, and sets the higher end of the data range to 0 to obtain new binary data. It is frequently used in the field of communications.

[0003] For example, in neural network algorithms, images and other objects are input into convolutional (or CNN) layers for feature extraction. The resulting feature vectors are then passed to pooling layers, fully connected layers, etc. Since there are many feature vectors, the corresponding computation time required by the processor will also be long. Users typically use bit-decimation operations to scale the feature vectors, selecting bits from the feature vectors and removing unnecessary bits, thereby reducing processor computation time while meeting user needs.

[0004] If the computation time of bit extraction operations can be reduced, the processor's performance and computational efficiency can be further improved. Summary of the Invention

[0005] In view of this, embodiments of this application provide a data processing method, an electronic device, and a storage medium. According to user needs, a single custom instruction can be used to perform bit extraction operations on the data to be processed, extracting the fields that need to be retained from the data. This reduces the number of instructions used for bit extraction operations to only one, improving processor computational efficiency while meeting user requirements. Specifically, the start bit position and offset of the bit extraction operation can be obtained by performing operations on the operand field in the custom instruction. The end bit position of the bit extraction operation is then obtained by adding the two immediate values. The operand, i.e., the data to be processed, can be obtained through the addresses of the source and destination registers in the custom instruction. Finally, the result obtained from executing the custom instruction is placed into the destination register.

[0006] In a first aspect, this application provides a data processing method applied to an electronic device, comprising:

[0007] Obtain the data to be processed;

[0008] Bit extraction is performed on the processed data;

[0009] Bit extraction of the data to be processed includes:

[0010] The first immediate number and the second immediate number are obtained by performing a first operation on the immediate number field in the custom instruction based on the number of bits of the data to be processed. The number of bits of the first immediate number and the number of bits of the second immediate number correspond to the number of bits of the data to be processed.

[0011] The first result is obtained by bit-decimating the data to be processed based on the first and second immediate values.

[0012] The first result is stored in the target register based on the address of the target register in the custom instruction.

[0013] In one possible implementation of the first aspect above, a first immediate value and a second immediate value are obtained by performing a first operation on the immediate number field in the custom instruction based on the number of bits of the data to be processed, including:

[0014] If the number of bits in the data to be processed is m, where m is a positive integer, then the immediate number field is subjected to the first operation to obtain the first immediate number and the second immediate number;

[0015] Wherein, if the number of digits of the first immediate number is n1 and the number of digits of the second immediate number is n2, then 2 to the power of n1 is greater than or equal to m and 2 to the power of n2 is greater than or equal to m, and n1 and n2 are positive integers.

[0016] In one possible implementation of the first aspect described above, the first operation includes splitting and / or recombining the immediate digital segment.

[0017] In one possible implementation of the first aspect above, obtaining a first result by bit-decimating the data to be processed based on the first immediate value and the second immediate value includes:

[0018] Add the first immediate value and the second immediate value to obtain the third data;

[0019] Extract the values ​​from the first immediate digit to the third data digit from the data to be processed as the extracted data;

[0020] The extracted data will be arranged sequentially, starting from the 0th position.

[0021] The remaining bits after data extraction are set to 0 to obtain the first result. The number of bits in the first result is equal to the number of bits in the data to be processed.

[0022] The first immediate value is the starting bit position of the bit extraction operation; the second immediate value is the offset value of the bit extraction operation; and the third data is the ending bit position of the bit extraction operation.

[0023] In one possible implementation of the first aspect described above, the data to be processed includes a vector.

[0024] In one possible implementation of the first aspect described above, the address of the source register in the user-defined instruction is related to the address of the target register.

[0025] The addresses of the registers are the same.

[0026] In one possible implementation of the first aspect described above, the address of the source register in the user-defined instruction is related to the address of the target register.

[0027] The addresses of the memory are not equal.

[0028] Secondly, this application provides a data processing apparatus, comprising:

[0029] The acquisition unit is used to acquire data to be processed.

[0030] The bit extraction unit is used to extract bits from the data to be processed.

[0031] Bit extraction of the data to be processed includes:

[0032] The first immediate number and the second immediate number are obtained by performing a first operation on the immediate number field in the custom instruction based on the number of bits of the data to be processed. The number of bits of the first immediate number and the number of bits of the second immediate number correspond to the number of bits of the data to be processed.

[0033] The first result is obtained by bit-decimating the data to be processed based on the first and second immediate values.

[0034] The first result is stored in the target register based on the address of the target register in the custom instruction.

[0035] Thirdly, this application provides a readable storage medium storing instructions that, when executed on a terminal device, constitute the data processing method described in the first aspect.

[0036] Fourthly, this application provides an electronic device, including a memory for storing instructions executed by one or more processors of the electronic device, and a processor, one of the processors of the electronic device, for performing the data processing method described in the first aspect.

[0037] The first immediate value mentioned above is the starting bit position of the bit extraction operation; the second immediate value is the offset value of the bit extraction operation; and the third value is the ending bit position of the bit extraction operation.

[0038] This application obtains two immediate values ​​required for bit decimation operation by performing operations on the immediate number field in a user-defined instruction. These include an immediate value representing the least significant bit of the bit operation and an immediate value representing the offset. Then, the start bit position and end bit position of the bit decimation operation are obtained based on the two immediate values. The bit decimation operation is then performed on the data to be processed, thereby achieving the goal of performing the bit decimation operation with only one instruction, reducing the computation time of the bit decimation operation, and improving the performance of the processor. Attached Figure Description

[0039] Figure 1 According to some embodiments of this application, an application scenario diagram of a data processing method is shown;

[0040] Figure 2 According to some embodiments of this application, a schematic diagram of a bit extraction operation method is shown;

[0041] Figure 3 According to some embodiments of this application, a schematic diagram of a custom instruction format is shown;

[0042] Figure 4 According to some embodiments of this application, a method is shown that... Figure 3 The diagram illustrates how operands in a custom instruction are obtained as immediate values.

[0043] Figure 5 According to some embodiments of this application, a schematic diagram of a processor hardware module is shown;

[0044] Figure 6 According to some embodiments of this application, a flowchart of a data processing method is shown;

[0045] Figure 7 According to some embodiments of this application, a schematic diagram of a hardware module of an electronic device is shown. Detailed Implementation

[0046] The illustrative embodiments of this application include, but are not limited to, the data processing methods, electronic devices, and media described in the embodiments.

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of the embodiments of this application will be further described in detail below with reference to the accompanying drawings and implementation schemes. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] To more clearly illustrate the solutions of the embodiments of this application, some terms involved in the embodiments of this application will be explained below.

[0049] Arm Cortex-M series processors: Based on the Arm M architecture definition, they provide low-latency and highly deterministic operation for embedded systems. Starting with the Cortex-M1 series, the core gradually includes TrustZone features, digital signal processing extensions, ARM custom instructions, coprocessor interfaces, etc.

[0050] M-profile Vector Extension (MVE), also known as Arm Helium technology, is a vector processing extension scheme for Arm Cortex-M series processors. It includes over 150 new scalar and vector instructions, supporting integer and floating-point data types. For small, feature-constrained embedded devices, it can provide up to 15x machine learning performance and 5x signal processing performance while maintaining efficiency.

[0051] Bit Field Extract (BFX): An instruction used to extract the value of a range of bits from an operand.

[0052] Immediate addressing: This mode places the operand immediately after the opcode in the instruction code segment. During program execution, the program directly calls the operand without needing to fetch it from other address units. The operand written in the instruction is also called an immediate value.

[0053] Immediate values ​​are data that are part of the instruction itself, rather than stored in memory or registers. Immediate values ​​are typically used in instructions to load values ​​or perform arithmetic or logical operations on constants.

[0054] Figure 1 A diagram illustrating an application scenario of a data processing method is provided. (Reference) Figure 1 The image to be processed is input into the electronic device 100. The processor 101 of the electronic device 100 will process the data of the image to be processed. If there is a lot of data to be processed in the image to be processed, the calculation time of the processor 101 will also be long. The user will use the processor 101 to perform bit extraction operation on the data to be processed in the image to be processed according to the needs, so as to reduce the number of bits of the data to be processed, and then use the result of the bit extraction operation for further calculation.

[0055] Figure 2 A schematic diagram of the bit extraction operation is shown. (Reference) Figure 2The source operand has 32 bits. The bit-decimation operation requires two immediate values: the LSB (Least Significant Bit), which is the starting bit position for the bit-decimation operation in the source operand, and an offset, which is the range of bits to be decimated. The sum of the two immediate values ​​is the MSB (Most Significant Bit), which is the ending bit position for the bit-decimation operation in the source operand. The bit-decimation operation on the source operand involves extracting bits from the LSB to the MSB position, using the bit at the LSB position as the 0th bit of the result, and then sequentially inserting the bits from the LSB to the MSB position into the source operand, shifting the MSB forward, and padding the 31st bit with zeros to obtain the bit-operation result.

[0056] Below is a test program that performs bit-decimation operations.

[0057] #define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff <<(to))))

[0058] void matrix_mul_matrix_bitextract (ee_u32 N, MATRES *C, MATDAT *A,MATDAT *B) {

[0059] ee_u32 i, j, k; / / i, j, k are defined as loop variables.

[0060] for (i = 0; i < N; i++) {

[0061] for (j = 0; j < N; j++) {

[0062] C[i*N+j] = 0; / / Initialization.

[0063] for (k = 0; k < N; k++) {

[0064] MATRES tmp = A[i*N+k] * B[k*N+j]; / / Multiply the two elements of matrix A and matrix B, and store the result in the temporary variable tmp.

[0065] C[i*N+j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5,7);

[0066] / / Extract the corresponding bits of tmp, multiply them, and accumulate them. Store the result in the target result matrix C.

[0067] }

[0068] }

[0069] }

[0070] }

[0071] The test program above defines a function to implement bit decimation. Here, x represents the operand to be decimated, from represents the starting bit position of the bit decimation operation, and to represents the ending bit position of the bit decimation operation. The function implements bit decimation by multiplying two N×N matrices and then extracting the corresponding bits from the multiplication result for accumulation. N is a positive integer, C is a pointer to the matrix storing the calculation result, A and B are pointers to the matrices storing the operands, and ee_u32, MATRES, and MATDAT are user-defined data types defined by this test program.

[0072] In existing processors, multiple instructions are required to execute the above program. Table 1 below shows, for example, the nine instructions used to execute the above program in an Arm Cortex-M series processor. Among them, the VADD, VSHR, and VAND instructions are used to implement bit decimation operations. VADD is an instruction that performs addition of two vectors and stores the result in a vector register; VSHR is an instruction that performs a right shift operation on a vector; and VAND is an instruction that performs AND operation on two vectors and stores the result in a vector register.

[0073] Table 1:

[0074]

[0075] As mentioned earlier, in existing assembly instruction sets, such as the MVE instruction set corresponding to Arm Cortex-M series processors, three instructions are used to implement bit decimation operations. The calculation time is relatively long, and the involvement of multiple instructions in the calculation increases the workload of the processor and reduces the performance of the processor.

[0076] The embodiments of this application will now be described in conjunction with the accompanying drawings.

[0077] To address the aforementioned issues, this application proposes a custom instruction approach. By performing calculations on the immediate data field of a single custom instruction, two immediate values ​​are obtained for the bit decimation operation: an immediate value representing the least significant bit of the bit operation and an immediate value representing the offset. The start and end bit positions of the bit decimation operation are then obtained using these two immediate values. Finally, the bit decimation operation is performed on the data to be processed. This approach achieves the goal of executing the bit decimation operation with only one instruction, reducing the computation time of the bit decimation operation and improving processor performance.

[0078] Specifically, Figure 3 This illustration shows the format of a custom instruction in an embodiment of this application. Existing instruction sets, such as the MVE instruction set, include three custom instructions: VCX1, VCX2, and VCX3. Users can add custom functions to these three custom instructions according to their needs. The MVE instruction set is a vector processing extension scheme for Arm Cortex-M series processors. Figure 3 The image shows the format of the VCX1A custom instruction in the MVE instruction set. The VCX1A instruction is a 32-bit instruction. Bits 0-5 ("op4"), 7 ("op3"), 16-19 ("op2"), and 24 ("op1") are the immediate number field; bits 8-10 ("coproc") are the coprocessor code; bits 12-15 ("Qd") and 22 ("D") represent register addresses; bit 28 ("A") is 1, indicating that the address in the register represented by "Qd" and "D" is both the source and destination register addresses; bits 6 ("1"), 11 ("0"), 20 and 21 ("01"), 23 ("0"), bits 25-27 ("011"), and bits 29-31 ("111") are used to distinguish it from other instructions.

[0079] The following is combined with Figure 3 and Figure 4 This document illustrates a flowchart illustrating how, in some embodiments of this application, two immediate values ​​for a bit-decimation operation are obtained via the immediate data field in the VCX1 instruction. (See reference...) Figure 3 and Figure 4If a user needs to perform a bit-decimation operation, it can be executed using the VCX1A instruction. In this instruction, the addresses in the registers represented by "Qd" and "D" are both the address of the source register and the address of the destination register. First, the processor obtains the 32-bit operand to be decimated using the address of the source register. Then, the processor performs operations on the four immediate fields "op1", "op2", "op3", and "op4" included in the VCX1A instruction to obtain the two immediate values ​​required for the bit-decimation operation. One immediate value is the starting bit position of the bit-decimation operation, and the other is the offset value of the bit-decimation operation. Since the operand is 32 bits, and 2 to the power of 5 equals 32, the immediate values ​​must be binary numbers greater than or equal to 5 bits. This can be achieved by performing operations on the four immediate fields "op1", "op2", "op3", and "op4" to obtain two binary fields greater than or equal to 5 bits, which are used to represent the two immediate values ​​respectively. Since the immediate field "op4" is 6 bits, "op3" is 1 bit, "op2" is 4 bits, and "op1" is 1 bit in the VCX1 instruction, we can obtain the first immediate value (the start bit position) of the bit decimation operation by retrieving the values ​​of these three immediate fields, for example, by concatenating them. Then, we can use the immediate field "op4" as the second immediate value (the offset value) and add the first and second immediate values ​​to obtain the end bit position. After obtaining the start and end bit positions, we can perform the bit decimation operation on the corresponding field in the data to be processed by executing the VCX1A instruction.

[0080] It's understandable that in the MVE instruction set architecture, the operands for bit-decimation operations can be 32 bits. The number of bits in the operands corresponds to different instruction set architectures. If the number of bits in the operands changes, the number of bits used to represent the immediate binary value must also change. For example, if the operands are 32 bits (2 to the power of 5 equals 32), then the number of bits used to represent the immediate binary value must be greater than or equal to 5 bits. That is, the four immediate fields "op1", "op2", "op3", and "op4" must be able to be processed into two binary fields of greater than or equal to 5 bits. Conversely, if the operands are 16 bits (2 to the power of 4 equals 16), then the number of bits used to represent the immediate binary value must be greater than or equal to 4 bits. That is, the four immediate fields "op1", "op2", "op3", and "op4" must be able to be processed into two binary fields of greater than or equal to 4 bits. Since the required number of bits in the operands may vary across different instruction set architectures, this will not be discussed further here.

[0081] The following describes a hardware module structure of a processor for executing the above instructions in an embodiment of this application.

[0082] refer to Figure 5 The processor 101 includes an instruction cache module 700, a memory access pipeline 200, an instruction set architecture definition instruction module 300, a user-defined instruction module 400, a register file 500, and a memory 600.

[0083] The instruction cache module 700 is used to temporarily store instructions waiting to be processed; the memory access pipeline 200 is used to retrieve the data required for executing instructions from the memory 600 and store the instruction execution result from the register file 500 into the memory 600; the instruction set architecture definition instruction module 300 is used to execute instructions defined in the instruction set architecture; the user-defined instruction module 400 is used to execute user-defined instructions; the register file 500 is used to temporarily store the data required for executing instructions; and the memory 600 is used to permanently store data and programs.

[0084] The following is combined with Figure 5 and Figure 6 This paper introduces a data processing method provided in some embodiments of this application. The VCX1A instruction from the MVE instruction set is used as a custom instruction in this embodiment. The VCX1A instruction is a VCX1 instruction provided by the MVE instruction set where "A" equals 1, such as... Figure 6 As shown, the steps of the above method may include:

[0085] S100, retrieve the data to be processed from register file 500.

[0086] The data to be processed, i.e. the operands, can be retrieved from memory 600 through memory access pipeline 200 and stored in register file 500, or stored in register file through instruction module 300 defined by instruction set architecture or custom instruction module 400. No specific restrictions are imposed here.

[0087] S200, the instruction cache module 700 sends the decoded custom instruction to the custom instruction module 400.

[0088] The instruction cache module 700 sends the decoded VCX1A instruction to the custom instruction module 400.

[0089] S300, the custom instruction module 400 obtains the data to be processed in the register file 500 through the source register address in the custom instruction.

[0090] In the VCX1A instruction, the "Qd" and "D" fields represent the addresses of the source and destination registers of the operands for the bit-decimation operation in register file 500.

[0091] The custom instruction module 400 can obtain the data to be processed from the register file 500 based on the "Qd" and "D" fields in the VCX1A instruction, which are the source register addresses.

[0092] S400, the custom instruction module 400 obtains two immediate values ​​for bit operations based on the immediate number field in the custom instruction.

[0093] For example, the custom instruction module 400 can form the first immediate value {op1:op2:op3} by concatenating the three immediate value fields “op1”, “op2” and “op3”, which provides the starting bit position of the bit decimation operation, i.e., LSB; the custom instruction module 400 uses the “op4” field as the second immediate value, i.e. the offset of the bit decimation operation.

[0094] S500, the custom instruction module 400 performs bit extraction operations on the data to be processed based on the two immediate values ​​mentioned above.

[0095] The custom instruction module 400 adds the first immediate value and the second immediate value to obtain the position of the final bit of the bit extraction operation, i.e., the MSB. The custom instruction module 400 extracts the fields from LSB to MSB in the data to be processed, takes the LSB bit as the 0th bit of the bit extraction operation result, and sequentially puts the bits from LSB to MSB in the data to be processed into the lower segment of the data. Then, it pads the higher segment of the data after the MSB bit with zeros to obtain the bit extraction operation result. The number of bits in the bit operation result is equal to the number of bits in the data to be processed.

[0096] S600, the custom instruction module 400, puts the bit extraction operation result into the target register in the register file 500 according to the address of the target register in the custom instruction.

[0097] It is understandable that the address of the destination register and the address of the source register can be equal or unequal, and both can vary depending on the instruction.

[0098] This application enables bit extraction operations to be performed with only one custom instruction, reducing the computation time of bit operations, improving the computer's running speed, and enhancing the computer's performance.

[0099] The test was conducted using one of the bit-decimation operations described above, as shown in the test program above:

[0100] #define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff <<(to))))

[0101] void matrix_mul_matrix_bitextract (ee_u32 N, MATRES *C, MATDAT *A,MATDAT *B) {

[0102] ee_u32 i, j, k; / / i, j, k are defined as loop variables.

[0103] for (i = 0; i < N; i++) {

[0104] for (j = 0; j < N; j++) {

[0105] C[i*N+j] = 0; / / Initialization.

[0106] for (k = 0; k < N; k++) {

[0107] MATRES tmp = A[i*N+k] * B[k*N+j]; / / Multiply the two elements of matrix A and matrix B, and store the result in the temporary variable tmp.

[0108] C[i*N+j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5,7);

[0109] / / Extract the corresponding bits of tmp, multiply them, and accumulate them. Store the result in the target result matrix C.

[0110] }

[0111] }

[0112] }

[0113] }

[0114] The above test program defines a function to implement bit extraction. Here, x represents the operand to be extracted, from represents the start bit position of the bit operation, and to represents the end bit position of the bit operation. The function implements bit extraction by multiplying two N×N matrices and then extracting the corresponding bits from the multiplication result for accumulation. N is a positive integer, C is a pointer to the matrix storing the calculation result, A and B are pointers to the matrices storing the operands, and ee_u32, MATRES, and MATDAT are user-defined data types defined by this test program.

[0115] As described in Table 1 above, the MVE instruction set requires 9 instructions as shown in Table 1 to execute the above program, of which VADD, VSHR, and VAND instructions are used to implement bit decimation operations. However, using the custom instruction design method for bit decimation provided in some embodiments of this application, only 6 instructions as shown in column 3 of Table 2 are needed to execute the above program, of which the VCX1A instruction is used to implement bit decimation operations.

[0116] The VLDRH instruction downloads data from the processor to a vector register; the VMUL instruction performs a multiplication of two vectors and stores the result in a vector register; the VADD instruction performs an addition of two vectors and stores the result in a vector register; the VSHR instruction performs a right shift operation on a vector; the VAND instruction performs an AND operation on two vectors and stores the result in a vector register; and the VMLAVA instruction multiplies corresponding elements of two vectors, sums the results, and stores the final result in a register.

[0117] Considering the time overlap between the VLDRH instruction and the subsequent algorithm instructions, the processor would normally need 8.5 cycles to execute the program in the original MVE instruction set, but only 5.5 cycles in the instruction set using the design method of this application, thus improving the processor's computation time and performance.

[0118] Table 2:

[0119]

[0120] To facilitate understanding of the technical solutions of the various embodiments of this application, the hardware structure of the electronic device 100 will be described below.

[0121] further, Figure 7 According to some embodiments of this application, a schematic diagram of the structure of an electronic device 100 is shown. For example... Figure 7 The illustrated electronic device 100 includes one or more processors 101, system memory 102, non-volatile memory (NVM) 103, communication interface 104, input / output (I / O) device 105, and system control logic 106 for coupling the processor 101, system memory 102, non-volatile memory 103, communication interface 104 and input / output (I / O) device 105.

[0122] Wherein: the processor 101 may include one or more processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a neural network processing unit (NPU), a micro-programmed control unit (MCU), an AI (Artificial Intelligence) processor, or a field programmable gate array (FPGA) processing module or processing circuit, or other data processing devices including this application, to implement bit extraction of data. The specific processor type is not specifically required here.

[0123] In some embodiments, the processor 101 may include the aforementioned data processing device to process the bit extraction operation involved when bit extraction of data is required. Since the device is designed with custom instructions according to user needs, bit operations can be implemented with only one instruction, resulting in high computational efficiency.

[0124] System memory 102 is volatile memory, such as random-access memory (RAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc. System memory is used for temporary storage of data and / or instructions; for example, in some embodiments, system memory 102 may be used to store the aforementioned custom instructions, etc.

[0125] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a Secure Digital (SD) memory card, etc.

[0126] Specifically, system memory 102 and non-volatile memory 103 may each include a temporary copy and a permanent copy of instruction 107. Instruction 107 may include: executed by at least one of processors 101 to cause electronic device 100 to implement the data processing methods provided in the embodiments of this application.

[0127] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby enabling communication with any other suitable device via one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104.

[0128] Input / output (I / O) device 105 may include input devices such as keyboard, mouse, etc., and output devices such as monitor, etc. Users can interact with electronic device 100 through input / output (I / O) device 105.

[0129] System control logic 106 may include any suitable interface controller to provide any suitable interface to other modules of terminal 100. For example, in some embodiments, system control logic 106 may include one or more memory controllers to provide an interface to system memory 102 and non-volatile memory 103.

[0130] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 may also be integrated on the same chip with the logic of one or more controllers for system control logic 106 to form a system-on-chip (SoC).

[0131] Understandable. Figure 7 The structure of the electronic device 100 shown is merely an example. In other embodiments, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0132] Various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or combinations of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0133] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a Digital Signal Processor (DSP), a microcontroller, an Application Specific Integrated Circuit (ASIC), or a microprocessor.

[0134] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0135] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0136] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0137] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0138] It should be noted that, in the examples and description of this patent, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0139] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A data processing method applied to electronic devices, characterized in that, include: Obtain the data to be processed; Bit extraction is performed on the data to be processed; Bit extraction of the data to be processed includes: If the number of bits in the data to be processed is m, where m is a positive integer, then the immediate number field is subjected to a first operation to obtain a first immediate number and a second immediate number; wherein, if the number of bits in the first immediate number is n1 and the number of bits in the second immediate number is n2, then 2 to the power of n1 is greater than or equal to m, and 2 to the power of n2 is greater than or equal to m, where n1 and n2 are positive integers; the first immediate number is the starting bit position of the bit decimation operation, and the second immediate number is the offset value of the bit decimation operation; Add the first immediate value and the second immediate value to obtain the third data, which is the position of the termination bit of the bit extraction operation; Extract the values ​​from the first immediate digit to the third digit in the data to be processed as the extracted data; The extracted data are arranged sequentially, starting from the 0th position; The remaining bits after the data extraction are set to 0 to obtain a first result, and the number of bits in the first result is equal to the number of bits in the data to be processed. The first result is stored in the target register according to the address of the target register in the custom instruction.

2. The method according to claim 1, characterized in that, The first operation includes splitting and / or recombining the immediate digital segment.

3. The method according to claim 1, characterized in that, The data to be processed includes vectors.

4. The method according to claim 1, characterized in that, The source register in the custom instruction The address of the device is equal to the address of the target register.

5. The method according to claim 1, characterized in that, The source register in the custom instruction The address of the device is not equal to the address of the target register.

6. A data processing apparatus, characterized in that, include: The acquisition unit is used to acquire data to be processed. Bit extraction unit, used for bit extraction of the data to be processed; Bit extraction of the data to be processed includes: If the number of bits in the data to be processed is m, where m is a positive integer, then the immediate number field is subjected to a first operation to obtain a first immediate number and a second immediate number; wherein, if the number of bits in the first immediate number is n1 and the number of bits in the second immediate number is n2, then 2 to the power of n1 is greater than or equal to m, and 2 to the power of n2 is greater than or equal to m, where n1 and n2 are positive integers; the first immediate number is the starting bit position of the bit decimation operation, and the second immediate number is the offset value of the bit decimation operation; Add the first immediate value and the second immediate value to obtain the third data, which is the position of the termination bit of the bit extraction operation; Extract the values ​​from the first immediate digit to the third digit of the data to be processed as the extracted data; The extracted data are arranged sequentially, starting from the 0th position; The remaining bits after the data extraction are set to 0 to obtain a first result, and the number of bits in the first result is equal to the number of bits in the data to be processed. The first result is stored in the target register according to the address of the target register in the custom instruction.

7. A readable storage medium, characterized in that, The readable storage medium stores instructions that, when executed on a terminal device, cause it to perform the data processing method of any one of claims 1 to 5.

8. An electronic device, characterized in that, include: Memory, used to store instructions executed by one or more processors of an electronic device, and, A processor is one of the processors in an electronic device, used to execute the data processing method according to any one of claims 1 to 5.

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