Ship electrical drawing layout method based on priori rule and deep neural network

Abstract

The application provides a ship electrical drawing layout method based on prior rules and a deep neural network, through a qualified connection scene, a determined completion layout wiring task and no wiring intersection or wiring failure, a function of automatic layout wiring in electrical drawing design is realized.In most actual electrical wiring tasks, the application effectively improves the automation degree in the electrical layout wiring work, improves the layout speed of the drawing and the reliability of the layout wiring, realizes correct, fast and reasonable automatic wiring layout of the electrical drawing, has fast operation speed, low source occupation, fully utilizes a singular value decomposition method to extract features, and reduces the operation complexity of the neural network.

Description

Technical Field

[0001] This invention belongs to the field of intelligent equipment design technology, specifically involving a method for ship electrical drawing layout based on prior rules and deep neural networks. Background Technology

[0002] Electrical systems play a crucial role in the research, design, and production of modern ships, making the creation of electrical drawings an essential part of the ship design process. After decades of technological development and evolution, modern ship design now extensively utilizes CAD software to assist technical personnel, reducing their workload. Simultaneously, with the widespread application of computer systems in related design fields, most of the design data for modern ship systems has been digitized. Having achieved the initial goal of design informatization, current technologies are now gradually moving towards intelligent design.

[0003] In modern naval design engineering, CAD technology has been widely applied, and traditional pen-and-paper drawing methods have been largely phased out. Modern naval electrical wiring drawings are primarily created by engineers using computer-aided CAD software. While CAD software significantly improves the speed of drawing compared to pen and paper, it still relies on manual step-by-step operations, making the process relatively slow. A skilled engineer may need approximately three days to create a complex drawing, and even simpler drawings can take several hours. This slow drawing speed leads to longer iteration cycles during research and development, reducing the efficiency of naval design and development. Furthermore, human error in CAD software drawing inevitably leads to various oversights. Therefore, the slow speed and low reliability of manual drawing have become bottlenecks restricting further improvements in the efficiency of naval design.

[0004] The main problems with manual CAD software drawing include three aspects:

[0005] First, the manual operation of software involves numerous and cumbersome steps, with corresponding coupling and interrelationships between each design step. Generally, the design of conventional ship electrical drawings follows these steps: engineers first need to import component labels from the component library based on the component model and parameters, then drag the components to their corresponding positions on the drawing, and finally perform wiring and connections according to the connection relationships in the spreadsheet. During this process, the component layout may need to be adjusted according to the actual wiring situation, and the routing may need to be adjusted accordingly. This iterative adjustment process continues until the design is completed. This complex manual design process directly leads to slow drawing speed and significantly hinders the ship design progress.

[0006] Secondly, the diversity of drawing data makes the reuse of layout designs extremely difficult. Due to the variety of drawings, it is hard to find a scientific method for reusing them. This means that the drawing process described above must be repeated for each drawing, and engineering technicians have to mechanically repeat this process for each drawing, greatly reducing the efficiency of drawing. This large amount of repetitive work not only reduces the design efficiency of technical staff but also easily leads to design oversights.

[0007] Third, manual drafting has low reliability. Complex processes and a large volume of drawing work are done manually by engineering technicians. The workload of design work increases dramatically as the number of drawings and the number of drafters grows. Although the probability of a technician making a mistake in a technical drawing is extremely small, according to the law of large numbers, the sheer volume of work inevitably leads to errors. Checking for these small errors requires significant manpower and time. Therefore, as the size and number of drawings gradually increase, the reliability of manual drafting gradually decreases.

[0008] Because manual design and drafting suffers from slowness and low efficiency, increasing attention is being paid to intelligent, automated computer-aided drafting. Artificial intelligence (AI) technology has also provided new means to solve electrical drawing design problems. However, theoretical research on AI-guided layout and routing problems is still in its early stages, lacking a scalable reward design system and an end-to-end learning paradigm. Researchers at Shanghai Jiao Tong University in China proposed a joint learning method called DeepPlace for placing macro and standard cells, achieving end-to-end layout task learning, in order to solve layout problems in chip design. Researchers from Google in the US have also conducted extensive research on chip layout problems. Google researchers proposed a chip layout planning algorithm based on deep reinforcement learning. This algorithm treats the chip layout planning problem as a reinforcement learning problem and applies an edge-based graph convolutional neural network architecture, which can learn and represent the characteristics of the chip, ultimately solving the automated design problem of chip layout through extensive training. Researchers at Simon Fraser University in Canada proposed a graph-constrained generative adversarial network (GAN) for layout problems in architectural design, where the generator and discriminator are built on a relational architecture. They implemented the relational connections between the generator and discriminator by encoding constraints into the graph structure of its relational network. Meanwhile, due to the close connection between layout problems and graph theory, some scientists from Canada have proposed a series of graph neural networks as solvers or methods to enhance accurate solvers, combining combinatorial optimization and reasoning scenarios. Based on the above research, some research results on the invariance of permutations and input sparsity of graph neural networks are also introduced. The above research mainly focuses on various layout problems. Regarding routing problems, researchers at Tianjin University in China have proposed a co-evolutionary algorithm for ship pipeline routing design. This method divides the workspace into three-dimensional grid cells and combines maze algorithms, non-dominated sorting genetic algorithms II, and co-evolutionary non-dominated sorting genetic algorithms to achieve an optimization program that can extract the best compromise pipeline from Pareto optimal solutions.

[0009] In summary, while some solutions and technical methods exist for layout and routing problems, current research often focuses on individual layout or routing issues. In scenarios where layout and routing are coupled and interfere with each other, there is still no comprehensive method to systematically solve these problems. Furthermore, existing layout optimization algorithms heavily utilize various end-to-end neural network algorithms, whose performance is highly dependent on the amount of data. Since end-to-end neural networks are primarily data-driven and lack prior knowledge support, they have a certain error rate and cannot completely avoid routing failures or errors. Therefore, they are still far from practical production applications. Summary of the Invention

[0010] The technical problem to be solved by this invention is to provide a ship electrical drawing layout method based on prior rules and deep neural networks, which can be used to automate the layout and wiring in electrical drawing design.

[0011] The technical solution adopted by this invention to solve the above-mentioned technical problems is: a ship electrical drawing layout method based on prior rules and deep neural networks, comprising the following steps:

[0012] S1: Classify the topology of electrical drawings, analyze the topology characteristics, and list the tree diagram;

[0013] S2: Formulate prior rules for layout and routing based on the properties and structure of multi-way trees in graph theory; complete the basic layout through the defined process and constraints; the basic layout includes component series scenarios, component subgraph series scenarios, and component subgraph parallel scenarios;

[0014] S3: Use neural networks to fine-tune and optimize layout parameters in wiring and layout to make the layout of the drawings reasonable and aesthetically pleasing.

[0015] According to the above scheme, the specific steps in step S1 are as follows:

[0016] A tree diagram is a graph that does not contain loops; tree diagrams can be connected in series and in parallel; tree diagrams include components and subgraphs; a component is the smallest indivisible node in the graph; a subgraph is used to describe a part of the components or subgraphs that have been laid out to form a whole.

[0017] Furthermore, in step S2, the specific steps are as follows:

[0018] S21: Develop prior rules based on different scenarios of series and parallel connections, decompose the tree diagram in a bottom-up manner, apply the corresponding prior rules for layout, and then combine them to form a complete layout; the core principle of developing prior rules for layout and routing is to ensure that cable connections do not intersect; and to improve the space utilization of each small structure layout while ensuring that cables do not intersect.

[0019] S22: Optimize the layout using an iterative method, arranging and adjusting the layout from bottom to top. After the component layout of each part is completed, pack the subgraphs and subgraphs, subgraphs and components, and components into a whole in a subgraph, and iterate to form a new subgraph. The final layout diagram is obtained by forming a subgraph containing all components.

[0020] Furthermore, in step S2,

[0021] The unit in the component-connected scene layout includes only components, and the components are connected in series;

[0022] In scenarios where components are connected in series, the prior rule is to prioritize space utilization.

[0023] The algorithm for arranging components in a series connection scenario is as follows:

[0024] First, calculate the number of nodes for the width and height based on the set aspect ratio of the subgraph, and then round up the floating-point number of the width and height nodes.

[0025] Then, a trial-and-error method is used to see if there is a sub-image whose size can be reduced; if not, the length and width after rounding up are used as the required length and width; if so, the reduced length and width are used.

[0026] After determining the number of nodes in terms of length and width, arrange the components in a serpentine pattern to complete the layout of the connected component scene.

[0027] Furthermore, in step S2,

[0028] The component sub-image chaining scenario is a chained layout of different component sub-images, with the last sub-image being larger and the preceding components being standard components of the same size;

[0029] In scenarios where component subgraphs are connected, the prior rule prioritizes space utilization.

[0030] The algorithm for arranging component subgraphs in a chained scenario is as follows:

[0031] First, place the largest sub-image at the top, and use the width of the sub-image as the width of the new layout;

[0032] Then, arrange the components below the largest sub-image using a serpentine layout method; if the starting point of the starting component is to the left, extend the corresponding connection point of the component to the left; if the starting point of the starting component is to the right, start a new row below this layout and place the corresponding connection point of the component at the far left of the new row, so that the actual connection point of the layout is in the lower left, thus completing the layout of the component sub-images connecting the scene.

[0033] Furthermore, in step S2,

[0034] The parallel subgraph scenario refers to the merging of subgraphs and components of different sizes.

[0035] In the scenario of parallel connection of component subgraphs, the priority rule is to avoid cable intersections, and the second consideration is the space utilization of the layout.

[0036] The algorithm for arranging component subgraphs in parallel scenarios is as follows:

[0037] Sort all components and sub-diagrams that need to be connected in parallel, placing the larger sub-diagrams first and the smaller sub-diagrams or components last.

[0038] Then arrange the sub-figures and components from left to right in order of largest to smallest, until all are arranged;

[0039] Finally, place the parent component at the bottom center of the entire layout, and set the actual connection point to the bottom center to complete the layout of the parallel component sub-graphs.

[0040] According to the above scheme, in step S2, a node iteration method is introduced, and a depth-first search iteration strategy is selected to traverse the entire multi-way tree and lay out all elements:

[0041] First, starting from the parent node (initial node), determine whether the parent node (initial node) and the connected nodes conform to the layout of the basic layout scenario; if they conform, use the corresponding basic layout scenario rules for layout; if they do not conform, start from the first child node of the node and continue to determine whether they conform to the basic layout scenario, and perform tree search and layout according to the depth-first algorithm until a layout scenario that conforms to the basic layout scenario is reached.

[0042] After the layout is completed, replace the components and sub-graphs in that section with the layout-completed sub-graphs; when all components under a node are laid out, it must conform to the basic layout scenario and be laid out as a complete sub-graph; finally, a complete drawing layout containing all components is obtained;

[0043] After completing all the layout tasks, connect the wires in the order of connection to obtain a direct connection diagram without intersections, thus completing the wiring task and realizing the drawing of the entire electrical wiring diagram.

[0044] According to the above scheme, the specific steps in step S3 are as follows:

[0045] S31: Statistically analyze the connection matrix, aspect ratio, and spacing of existing drawings using traditional computer vision algorithms to obtain a dataset for training the neural network; use the neural network to learn the wiring parameter settings under different conditions from existing wiring data.

[0046] S32: Before the input data, including the parameters of component connection relationships, enters the neural network, the singular value decomposition method is used to preprocess the input data, filter out some noise and extract features, in order to reduce the processing difficulty of the neural network and improve the processing efficiency of the neural network.

[0047] First, a connection relationship matrix is ​​used to describe the connection relationships between all components; the size of the connection relationship matrix of the drawing consisting of n components is set to n x n; in the matrix, the elements of the coordinates formed by the rows and columns corresponding to two components with a connection relationship are set to 1, and the elements of the coordinates formed by the rows and columns corresponding to components without a connection relationship are set to 0.

[0048] Then, singular value decomposition is performed on the matrix, and the 40 largest singular values ​​are selected as input parameters.

[0049] S33: The relevant information of the drawing is used as an input vector and fed into the neural network for prediction; after the forward propagation calculation of the neural network, the output results are two regression values: the aspect ratio and the optimal spacing of the sub-figure, which are applied to the layout of the actual drawing; the neural network obtains the optimal output result through internal iterative calls.

[0050] A system architecture for a ship electrical drawing layout method based on prior rules and deep neural networks includes a connection relation database, a component attribute database, a neural network parameter optimizer, and a prior rule layoutr; the connection relation database is connected to the input of the neural network parameter optimizer, and the connection relation database, the component attribute database, and the neural network parameter optimizer are respectively connected to the input of the prior rule layoutr;

[0051] The connection relationship database and the component attribute database are imported manually; the connection relationship database is used to describe the connection relationships between various components; the component attribute database is used to describe the parameters and attributes of each component.

[0052] The neural network parameter optimizer includes fully connected layers and convolutional layers. The neural network parameter optimizer is used to receive topological features, perform forward propagation using a pre-trained neural network, and calculate layout parameters including spacing and layout ratio based on the component connection relationships in the drawing to optimize the layout of the drawing.

[0053] The prior rule layouter is used to perform layout based on prior rules summarized by humans, applying layout parameters and connection data; prior rules are used to define the layout process and methods; layout parameters are used to constrain the spacing between various elements and the layout ratio.

[0054] Furthermore, it also includes a connection matrix compressor, which is connected in series between the connection relation database and the neural network parameter optimizer. It is used to compress the corresponding connection parameters, extract topological features, and input them into the neural network parameter optimizer using singular value decomposition.

[0055] The beneficial effects of this invention are as follows:

[0056] 1. The ship electrical drawing layout method based on prior rules and deep neural networks of the present invention, by determining the completion of the layout and wiring task for connection scenarios that meet the conditions, and without the occurrence of wiring intersection or wiring failure, realizes the function of automated layout and wiring in electrical drawing design.

[0057] 2. In most practical electrical wiring tasks, this invention effectively improves the automation level of electrical layout and wiring work, increases the layout speed of drawings and the reliability of layout and wiring; and realizes the correct, fast and reasonable automatic wiring layout of electrical drawings.

[0058] 3. Fast running speed; for most drawing sizes, layout and wiring tasks can be completed within 10 seconds.

[0059] 4. This invention has low resource consumption and makes full use of the singular value decomposition method to extract features, thereby reducing the computational complexity of the neural network. Attached Figure Description

[0060] Figure 1 This is a system architecture diagram of an embodiment of the present invention.

[0061] Figure 2 This is a schematic diagram of series and parallel connections according to an embodiment of the present invention.

[0062] Figure 3 This is a layout rule classification diagram of an embodiment of the present invention.

[0063] Figure 4 This is a scenario diagram of components connected in series according to an embodiment of the present invention.

[0064] Figure 5 This is a scenario diagram of component sub-diagrams connected in series according to an embodiment of the present invention.

[0065] Figure 6 This is a parallel scenario diagram of component sub-diagrams in an embodiment of the present invention.

[0066] Figure 7 This is a transformation diagram of the connection topology and connection relationship matrix in an embodiment of the present invention.

[0067] Figure 8 This is a flowchart of singular value decomposition and neural network processing according to an embodiment of the present invention.

[0068] Figure 9 This is a flowchart of the node iteration operation in an embodiment of the present invention.

[0069] Figure 10 This is a schematic diagram of step 1 of the complex scene layout in an embodiment of the present invention.

[0070] Figure 11 This is a schematic diagram of step 2 of the complex scene layout in an embodiment of the present invention.

[0071] Figure 12 This is a schematic diagram of step 3 of the complex scene layout in an embodiment of the present invention.

[0072] Figure 13 This is a schematic diagram of step 4 of the complex scene layout in an embodiment of the present invention.

[0073] Figure 14 This is a schematic diagram of the complex scene layout result according to an embodiment of the present invention. Detailed Implementation

[0074] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0075] See Figure 1 The ship electrical drawing layout method based on prior rules and deep neural networks according to embodiments of the present invention includes the following steps:

[0076] First, the topology of electrical drawings was classified and its characteristics were analyzed. It was found that the topology of the vast majority of electrical drawings belonged to tree diagrams.

[0077] Then, combining the properties and structure of multi-way trees in graph theory, a set of placement and routing rules was summarized and analyzed. This scheme, based on prior knowledge rules, can complete basic placement and routing through defined processes and constraints. Some software modules can work independently without using a large amount of data for training, and this does not cause differences in routing success rate.

[0078] After the layout and routing are completed, a neural network is used to fine-tune and optimize the layout parameters in the routing and layout, making the layout of the drawing more reasonable and aesthetically pleasing.

[0079] Overall structure

[0080] The overall structure of the system mainly consists of two parts: a prior rule layouter and a neural network parameter optimizer.

[0081] A priori rule layout tool can perform layout based on manually summarized prior rules and apply layout parameters. Prior rules define the layout process and methods, while layout parameters constrain the spacing between various elements and the proportions of the layout. Based on prior rules, layout parameters, and connection data, the priori rule layout tool can achieve effective and correct layout, solving the "whether or not" problem of layout functionality.

[0082] A neural network parameter optimizer can calculate the corresponding layout parameters based on the component connections in a drawing. After receiving topological features, the optimizer uses a trained neural network for forward propagation to calculate the required spacing, layout scale, and other layout parameters. These parameters indirectly control the drawing layout through a prior knowledge-based layout manager. By using a neural network parameter optimizer, the layout of a drawing can be effectively optimized, solving the problem of "how good" the layout is.

[0083] To complement the neural network parameter optimizer, an auxiliary component called a connection matrix compressor was added to the system to extract topological features.

[0084] Before inputting the component connection relationship data, the neural network parameter optimizer uses a connection matrix compressor to compress the corresponding connection parameters. This connection matrix compressor uses singular value decomposition to extract and compress features. Finally, the extracted and compressed feature output is used as the input to the neural network parameter optimizer.

[0085] The prior rule layouter requires three sets of data during layout: a connection relationship database, a component attribute database, and layout parameters. The connection relationship database describes the connections between components; the component attribute database describes the parameters and attributes of each component; and the layout parameters describe the layout proportions and spacing. Of these three parameters, only the connection relationship database and the component attribute database need to be manually imported; the layout parameters are calculated by the connection matrix compressor and the neural network parameter optimizer using the connection relationship database.

[0086] Implementation method

[0087] 1. Prior rules for basic subgraphs

[0088] In actual electrical wiring scenarios, the vast majority of wiring diagrams are tree-shaped. For the few non-tree-shaped wiring diagrams, they can be converted into tree-shaped wiring diagrams through some engineering methods. Therefore, the prior rules for drawing layout are designed for tree-shaped diagrams.

[0089] First, we will introduce some characteristics and properties of tree-structured wiring diagrams. Figure 1 Generally, a tree diagram refers to a graph that does not contain loops. Such graphs have two connection methods: serial and parallel, as shown in the diagram below. Therefore, any tree diagram can be constructed through combinations and cascades of serial and parallel connections. Thus, the prior rules are designed based on both serial and parallel scenarios. The entire tree is decomposed from the bottom up, and the corresponding prior rules are applied for layout. These are then combined to form a complete layout. In the actual layout process, to facilitate rule formulation, serial scenarios are divided into two cases with separate rules designed to improve space utilization.

[0090] Based on the characteristics of the aforementioned tree-like wiring diagram, two layout principles are proposed. The design and formulation of these prior rules are based on two core principles: first, ensuring that cable connections do not intersect; and second, maximizing the space utilization of each small structure while ensuring that cables do not intersect. The following section will design a layout and wiring method based on these two principles.

[0091] To better understand the prior rules described in this article, some relevant definitions will be explained first.

[0092] Definition 1: Component; In this article, a component refers to the smallest node in the drawing that cannot be further divided. Since different components are basically similar in size in the drawing, these components are approximated to the same size for easier subsequent processing.

[0093] Definition 2: Subgraph; A subgraph describes a subset of components or subgraphs that have been laid out to form a whole. During the layout process, iterative methods are extensively used for optimization, resulting in a bottom-up approach to placement and adjustment. Therefore, after the layout of each component is complete, a subgraph is used to integrate these components and their layout into a whole. Simultaneously, as the layout progresses, subgraphs, components, and subgraphs are packaged into a single unit after layout completion, forming a new subgraph. Thus, subgraphs can iterate on their own. Finally, it should be noted that the subgraph containing all components is the final layout diagram.

[0094] After defining the concepts above, we will continue to describe the possible scenarios and corresponding prior rules during the layout process. A bottom-up layout logic is used, so it is not difficult to exhaustively list all three basic layout scenarios: component chaining, component subgraph chaining, and component subgraph paralleling. The scenarios and rules for these three basic layouts are described below. The classification and relationship of the rules for the three basic layout scenarios are shown in the following figure.

[0095] Component Serial Connection Scenario: This scenario refers to a layout where the units consist only of components connected in series. This layout effectively satisfies the principle of no cable intersections by ensuring the components are arranged in sequence. Therefore, the main consideration for this scenario is space utilization. Based on space utilization considerations, the number of nodes for the length and width of the sub-graphs is first calculated according to the set aspect ratio. Since the calculated number of nodes may not be an integer, the floating-point number is first rounded up. Then, a trial-and-error method is used to see if any of the sub-blocks can be slightly reduced in size. If not, the rounded-up length and width are used as the required length and width; if so, the reduced length and width are used. After determining the number of nodes for the length and width, the components are arranged in a serpentine pattern in sequence to complete the layout of the component serial connection scenario.

[0096] Component Subgraph Serialization Scenario: The serialized layout of different component subgraphs actually only exists in one scenario: the last subgraph is larger, and the preceding components are standard component sizes and identical. Similar to the scenario above, the principle of no cable intersections is relatively easy to satisfy; therefore, the corresponding rules are primarily based on maximizing space utilization. Based on the actual serialization characteristics, the following arrangement algorithm is designed. First, place the largest subgraph at the top, using its width as the width of the new layout. Then, arrange the components below the largest subgraph using a serpentine routing method. Therefore, the position of the first component is not fixed. If the starting point of the component is to the left, extend the corresponding connection point to the left. If the starting point of the component is to the right, start a new row below this layout, placing the corresponding connection point at the far left of the new row. This ensures that the actual connection point of the layout remains in the lower left corner. Following these steps completes the layout for the component subgraph serialization scenario.

[0097] Parallel subgraph layout scenarios: This involves merging subgraphs and components of different sizes in parallel compared to serial merging. In this layout scenario, simply pursuing space utilization using layout algorithms such as greedy algorithms might lead to cable intersections, causing routing difficulties. However, the goal is to minimize cable intersections. Therefore, for this scenario, avoiding cable intersections should be the top priority, followed by consideration of space utilization. Because cable intersections need to be avoided, this scenario is more challenging to layout. However, by eliminating the need for sequential order, the algorithm can be more flexible in the actual layout process, resulting in a more scientific overall layout. In terms of actual layout, to avoid cable intersections, a sorting algorithm is first used to sort all components and subgraphs that need to be connected in parallel, placing larger subgraphs in front and smaller subgraphs or components behind. Then, the subgraphs and components are arranged from left to right in order of size, until all are arranged. Finally, the parent component is placed at the bottom center of the entire layout, and the actual connection point is also set to the bottom center, thus completing the layout of the parallel component subgraph scenario.

[0098] 2. Parameter Optimization Neural Network

[0099] Neural network optimization methods have shown good optimization results in many scenarios. As a core theory of modern machine learning, neural networks, through the study of the neural network structure of organisms, use computer hardware and software systems to simulate the structure and function of the central nervous system of animals. These computer-based mathematical computational models are used to predict and estimate certain mathematical mappings.

[0100] However, the optimization methods of neural networks still have certain limitations. Deep learning cannot effectively achieve the desired goals in some complex situations. There are many reasons for this failure, mainly the following two: First, the accumulation of data is difficult. Due to the extremely high dimensionality of the state space in end-to-end optimization methods in complex scenarios, a huge amount of data is required as training data for the neural network. Acquiring this data is inherently difficult, and the workload of data cleaning and filtering is also relatively large. Second, end-to-end neural networks in complex scenarios often have a very large number and dimensionality of hidden layers. Training and optimizing neural networks in these scenarios often requires a large investment of computing resources. Along with this large investment of computing resources, there is also huge power consumption and complex equipment management costs. This high barrier prevents end-to-end neural networks from entering some complex scenarios.

[0101] To address the layout parameter optimization problem, this invention also introduces a neural network optimization method. Since numerous parameter optimization issues exist during the wiring process in drawings, a neural network is needed to learn the wiring parameter settings under different conditions from massive amounts of existing wiring data. During prediction, relevant drawing information is first used as an input vector and fed into the neural network for calculation. After forward propagation, the relevant parameters can be calculated by the neural network and applied to the actual drawing layout.

[0102] To improve the processing efficiency of neural networks, singular value decomposition (SVD) is used to reduce the processing difficulty. This design can significantly improve the working efficiency and computation speed of neural networks, and also provides a feasible technical solution for using neural networks to perform optimization in complex scenarios.

[0103] Before the component connection parameters are input into the neural network, singular value decomposition (SVD) is used to filter out some noise and extract features. Before the input data enters the neural network for processing, it needs to be preprocessed. First, all the connection relationships between components are described by a connection matrix. For example, for a drawing composed of n components, the size of the connection matrix is ​​n x n. If two components are connected, the elements of the coordinates formed by the corresponding rows and columns of the two components are set to 1; otherwise, they are set to 0. Since the components themselves are almost the same size, this part of the data is not included in the neural network calculation. Therefore, singular value decomposition is performed on this matrix, and the 40 largest singular values ​​are selected as input parameters.

[0104] Once the input parameters are determined, a neural network is used to predict them. After forward propagation calculations, the output parameters of the neural network are the aspect ratio and optimal spacing of the subgraph.

[0105] The input to the neural network is the compressed output of the connection matrix compressor mentioned earlier. The neural network primarily contains fully connected layers and convolutional layers. After forward propagation, the output consists of two regression values: one is the aspect ratio of the sub-image, and the other is the optimal spacing. During the training process, traditional computer vision algorithms are used to statistically analyze the connection matrix of existing drawings and their corresponding aspect ratios and spacings, resulting in a dataset used to train the neural network.

[0106] Furthermore, this neural network can be iteratively invoked. For example, if a subgraph containing some elements wants to obtain its aspect ratio and optimal spacing ratio, it can also call this neural network internally to make predictions.

[0107] Iterative calls to this neural network can effectively improve the rationality and scientific nature of drawing layouts. This makes the generation of drawings more in line with human cognitive habits and improves layout efficiency.

[0108] 3. Node Iteration Method

[0109] Due to the randomness of placement and routing scenarios, a node iteration method is needed to help traverse and place all components. In actual placement, the number of components to be placed is uncertain, as is the structure tree. To ensure the system's adaptability and adaptability to placement tasks in different scenarios, algorithms must be used to traverse the entire tree. An iterative method is chosen so that the program can automatically determine the placement based on the number of components and their connections. For the actual placement scenarios and information, a corresponding node iteration algorithm is designed using a top-down iterative and bottom-up placement approach. Therefore, a depth-first search iteration strategy is chosen, as this method has lower memory requirements than breadth-first search. Furthermore, for the application scenario, the depth-first strategy does not affect the placement result; therefore, the depth-first search iteration strategy is ultimately selected.

[0110] The actual node iteration process is shown in the diagram below. Starting from the parent node (initial node), it checks whether the parent node and its connected nodes conform to the three basic layout scenarios. If they do, the corresponding basic layout scenario rules are used for layout. If not, it starts from the first child node of that node and continues to check if it conforms to the three basic layout scenarios. That is, a depth-first search algorithm is used for tree search and layout until a layout scenario conforming to the basic layout scenario is reached. After layout, the corresponding components and subgraphs are replaced with the completed subgraphs. When all components under a node are laid out, it must conform to a basic layout scenario and can therefore be laid out as a complete subgraph. Finally, a complete layout containing all components is obtained. After completing all layout tasks, connections can be made according to the connection order. It is easy to see that if the layout is done using the above method, direct connections will not intersect, thus completing the wiring task and realizing the drawing of the entire electrical wiring diagram.

[0111] The pseudocode for the node iteration method is:

[0112]

[0113] Take a simple electrical topology consisting of 8 components as an example, such as Figure 10 As shown;

[0114] The iteration and rule matching begin with "Component 1". It's easy to see that "Component 1" and its subordinate structures do not conform to the three basic layout scenarios. Therefore, the child nodes of "Component 1" are searched. The child node "Component 2" and its subordinate structures also do not conform to the three basic layout scenarios. Therefore, the child nodes of "Component 2" are explored further. At this point, the first child node of "Component 2", "Component 4", and its subordinate nodes conform to the "component chaining scenario" of the three basic layout scenarios. Therefore, the rules of the "component chaining scenario" are applied to calculate the layout of "Component 4" and its three subordinate nodes, and these four nodes are replaced with a subgraph containing its own information and layout information. Thus, the topological layout of the entire graph is as follows: Figure 11 As shown.

[0115] When "son" Figure 1 After replacing it in the entire graph, matching “Component 5” with the rules revealed that “Component 5” is a single node with no series or parallel relationship, so no processing is required.

[0116] After all child nodes of "Component 2" have been processed, the search at the current level ends. It returns that Component 2 and its subordinate components and subgraphs conform to the "parallel component subgraph scenario" of the three basic layout scenarios. Similarly, the "parallel component subgraph scenario" rule is applied to calculate the layout of "Component 2" and one of its subordinate subgraphs and one component, and this part is also replaced with "child..." Figure 2 ",like Figure 12 As shown.

[0117] When "Component 2" and the part below it are replaced with "Sub-component" Figure 2 Following this, similarly, "Component 1" and its subgraphs and components can also be laid out using the "Component Subgraph Parallel Scenario" rule. Thus, the layout of a circuit with a series-parallel topology of 8 nodes is successfully completed, as shown below. Figure 13 As shown in the diagram. Finally, connect these components with cables according to the connection order to form a complete circuit wiring diagram. It is worth noting that during the layout and routing process, because the cable arrangement has been fully considered and appropriate planning and trade-offs have been made, the routing does not require complex pathfinding and routing methods. It can even be completed using very simple straight lines and broken lines. The final result is shown in the diagram. Figure 14 As shown.

[0118] The above embodiments are only used to illustrate the design concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes or modifications made based on the principles and design ideas disclosed in the present invention are within the protection scope of the present invention.

Claims

1. A method for ship electrical drawing layout based on prior rules and deep neural networks, characterized by: Includes the following steps: S1: Classify the topology of electrical drawings, analyze the topology characteristics, and list the tree diagram; S2: Formulate prior rules for layout and routing based on the properties and structure of multi-way trees in graph theory; complete the basic layout through the defined process and constraints; the basic layout includes component series connection scenarios, component subgraph series connection scenarios, and component subgraph parallel connection scenarios; the specific steps are as follows: S21: Develop prior rules based on different scenarios of series and parallel connections, decompose the tree diagram in a bottom-up manner, apply the corresponding prior rules for layout, and then combine them to form a complete layout; the core principle of developing prior rules for layout and routing is to ensure that cable connections do not intersect; and to improve the space utilization of each small structure layout while ensuring that cables do not intersect. S22: Optimize the layout using an iterative method, arranging and adjusting the layout from bottom to top. After the component layout of each part is completed, pack the subgraphs and subgraphs, subgraphs and components, and components into a whole in a subgraph, and iterate to form a new subgraph, forming a subgraph containing all components to obtain the final layout diagram. S3: Use neural networks to fine-tune and optimize layout parameters in wiring and layout to make the layout of the drawings reasonable and aesthetically pleasing.

2. The ship electrical drawing layout method based on prior rules and deep neural networks according to claim 1, characterized in that: In step S1, the specific steps are as follows: A tree diagram is a graph that does not contain loops; tree diagrams can be connected in series and in parallel; tree diagrams include components and subgraphs; a component is the smallest indivisible node in the graph; a subgraph is used to describe a part of the components or subgraphs that have been laid out to form a whole.

3. The ship electrical drawing layout method based on prior rules and deep neural networks according to claim 1, characterized in that: In step S2 The unit in the component-connected scene layout includes only components, and the components are connected in series; In scenarios where components are connected in series, the prior rule is to prioritize space utilization. The algorithm for arranging components in a series connection scenario is as follows: First, calculate the number of nodes for the width and height based on the set aspect ratio of the subgraph, and then round up the floating-point number of the width and height nodes. Then, a trial-and-error method is used to see if there is a sub-image whose size can be reduced; if not, the length and width after rounding up are used as the required length and width; if so, the reduced length and width are used. After determining the number of nodes in terms of length and width, arrange the components in a serpentine pattern to complete the layout of the connected component scene.

4. The ship electrical drawing layout method based on prior rules and deep neural networks according to claim 1, characterized in that: In step S2 The component sub-image chaining scenario is a chained layout of different component sub-images, where the last sub-image is larger than the others, and the preceding components are standard components of the same size; In scenarios where component subgraphs are connected, the prior rule prioritizes space utilization. The algorithm for arranging component subgraphs in a chained scenario is as follows: First, place the largest sub-image at the top, and use the width of the sub-image as the width of the new layout; Then arrange the components below the largest subgraph using a serpentine routing method; if the starting point of the component is to the left, extend the corresponding connection point of the component to the left. If the starting point of the element is to the right, start a new line below the layout and place the connection point of the element at the far left of the new line, so that the actual connection point of the layout is in the lower left corner, thus completing the layout of the element subgraph connection scene.

5. The ship electrical drawing layout method based on prior rules and deep neural networks according to claim 1, characterized in that: In step S2 The parallel subgraph scenario refers to the merging of subgraphs and components of different sizes. In the scenario of parallel connection of component subgraphs, the priority rule is to avoid cable intersections, and the second consideration is the space utilization of the layout. The algorithm for arranging component subgraphs in parallel scenarios is as follows: Sort all components and sub-diagrams that need to be connected in parallel, placing the larger sub-diagrams first and the smaller sub-diagrams or components last. Then arrange the sub-figures and components from left to right in order of largest to smallest, until all are arranged; Finally, place the parent component at the bottom center of the entire layout, and set the actual connection point to the bottom center to complete the layout of the parallel component sub-graphs.

6. The ship electrical drawing layout method based on prior rules and deep neural networks according to claim 1, characterized in that: In step S2, a node iteration method is introduced, and a depth-first search iteration strategy is selected to traverse the entire multi-way tree and lay out all elements: First, starting from the parent node, determine whether the parent node and the connected nodes conform to the layout of the basic layout scenario. If they do, use the corresponding basic layout scenario rules for layout. If they do not, start from the first child node of the node and continue to determine whether it conforms to the basic layout scenario. Perform tree search and layout according to the depth-first algorithm until a layout scenario that conforms to the basic layout scenario is reached. After the layout is completed, replace the components and sub-graphs in that section with the layout-completed sub-graphs; when all components under a node are laid out, it must conform to the basic layout scenario and be laid out as a complete sub-graph; finally, a complete drawing layout containing all components is obtained; After completing all the layout tasks, connect the wires in the order of connection to obtain a direct connection diagram without intersections, thus completing the wiring task and realizing the drawing of the entire electrical wiring diagram.

7. The ship electrical drawing layout method based on prior rules and deep neural networks according to claim 1, characterized in that: In step S3, the specific steps are as follows: S31: Statistically analyze the connection matrix, aspect ratio, and spacing of existing drawings using traditional computer vision algorithms to obtain a dataset for training the neural network; use the neural network to learn the wiring parameter settings under different conditions from existing wiring data. S32: Before the input data, including the parameters of component connection relationships, enters the neural network, the singular value decomposition method is used to preprocess the input data, filter out some noise and extract features, in order to reduce the processing difficulty of the neural network and improve the processing efficiency of the neural network. First, a connection relationship matrix is ​​used to describe the connection relationships between all components; the size of the connection relationship matrix of the drawing consisting of n components is set to n x n; in the matrix, the elements of the coordinates formed by the rows and columns corresponding to two components with a connection relationship are set to 1, and the elements of the coordinates formed by the rows and columns corresponding to components without a connection relationship are set to 0. Then, singular value decomposition is performed on the matrix, and the 40 largest singular values ​​are selected as input parameters. S33: Use the relevant information of the drawing as an input vector and feed it into the neural network for prediction; After forward propagation calculation by the neural network, the output results are two regression values: the aspect ratio and the optimal spacing of the sub-figure, which are applied to the layout of the actual drawing; the neural network obtains the optimal output result through internal iterative calls.

8. A system architecture for the ship electrical drawing layout method based on prior rules and deep neural networks as described in any one of claims 1 to 7, characterized in that: It includes a relational database, a component attribute database, a neural network parameter optimizer, and a prior rule layoutr; the relational database is connected to the input of the neural network parameter optimizer, and the relational database, the component attribute database, and the neural network parameter optimizer are respectively connected to the input of the prior rule layoutr. The connection relationship database and the component attribute database are imported manually; the connection relationship database is used to describe the connection relationships between various components; the component attribute database is used to describe the parameters and attributes of each component. The neural network parameter optimizer includes fully connected layers and convolutional layers. The neural network parameter optimizer is used to receive topological features, perform forward propagation using a pre-trained neural network, and calculate layout parameters including spacing and layout ratio based on the component connection relationships in the drawing to optimize the layout of the drawing. The prior rule layouter is used to perform layout based on prior rules summarized by humans, applying layout parameters and connection data; prior rules are used to define the layout process and methods; layout parameters are used to constrain the spacing between various elements and the layout ratio.

9. The system architecture according to claim 8, characterized in that: It also includes a connection matrix compressor, which is connected in series between the connection relation database and the neural network parameter optimizer. It is used to compress the corresponding connection parameters, extract topological features, and input them into the neural network parameter optimizer using the singular value decomposition method.

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