FPGA design method based on steepest descent method for double-constraint problem

Abstract

The embodiment of the application discloses a FPGA design method based on the steepest descent method, comprising: determining a FPGA design feasible region under double constraint conditions; calculating a feasible solution in the feasible region by using the steepest descent method; determining an optimal solution in the feasible region from the feasible solution; selecting an experience threshold and comparing the experience threshold with the optimal solution to judge whether there is a balanced design scheme; if there is a balanced design, discarding the previous feasible region, determining a new feasible region, repeating the previous steps in the new feasible region, and stopping until there is no balanced alternative scheme. The FPGA design method provided by the application is a design method balancing the contradiction between resources and real-time, and can be widely applied to various fields with the contradiction between resources and real-time. The application has engineering guiding significance and can guide FPGA designers to carry out system-level optimization design.

Description

Technical Field

[0001] This invention relates to the field of FPGA design, particularly its applicability to FPGA edge computing and other FPGA real-time processing fields. Background Technology

[0002] FPGA engineering design always faces the challenge of balancing real-time performance with resource utilization. Existing technical solutions include the following:

[0003] One approach is to utilize the internal resources of the FPGA. This solution employs a double data rate technique with the DSP48. The DSP48 operates at 500MHz, while the two input data streams can enter at 250MHz, and are then mixed before being processed by the DSP48. By using different clock frequencies between the different architectures, processing power is improved, and the system's real-time performance is enhanced. By implementing two int8 multiplications using a single DSP48E2, DSP resources are fully utilized, further improving system real-time performance.

[0004] There are also solutions that employ heterogeneous processors. This approach moves computations that consume significant FPGA resources to the DSP, thereby saving FPGA resources and improving the system's real-time performance.

[0005] Another approach involves adjusting the algorithm processing. This solution reduces resource usage and improves system real-time performance by resolving the mapping algorithm.

[0006] The above technical solutions are feasible in engineering, but they each have the following problems:

[0007] The technical solution employs full utilization of the FPGA's internal resources without increasing FPGA resources. However, due to the introduction of two clocks, cross-clock domain processing requires a buffer structure, consuming some FPGA resources. Furthermore, as the system architecture and functionality become more complex, the increase in clock domains will complicate system debugging and maintenance.

[0008] Using heterogeneous processors can reduce the resources consumed by FPGAs, but the communication rate between heterogeneous processors needs to be considered, and this communication rate can easily become a bottleneck restricting real-time performance.

[0009] While adjusting the algorithm processing can reduce algorithm complexity, resource consumption, and improve system real-time performance, it often comes at the cost of performance degradation, such as system accuracy.

[0010] In summary, the above solutions adjust the relationship between real-time performance and resources by introducing other factors, but they do not directly address the inherent contradiction between these two factors. To address this issue, this invention proposes an FPGA design method based on the steepest descent method to solve the dual constraint problem of resources and real-time performance. This design method maintains the designed FPGA algorithm flow unchanged, uses the FPGA as the core processor, keeps the clock consistent, and adjusts the interrelationships between structures to balance the dual constraint problem. Summary of the Invention

[0011] To address the dual-constraint problem encountered in FPGA design, this invention provides an FPGA design method based on the steepest descent method, comprising the following steps:

[0012] S1: Under the constraints of FPGA internal resources and FPGA system time, determine the feasible region of FPGA design. The solution corresponding to each design point in the feasible region is a feasible FPGA design scheme.

[0013] S2: Calculate feasible solutions in the feasible region using the steepest descent method;

[0014] S3: Determine the optimal solution in the feasible region from the feasible solutions;

[0015] S4: Select an empirical threshold based on the system requirements of the FPGA design. If the optimal solution is greater than or equal to the empirical threshold, the design point corresponding to the optimal solution is said to conform to a balanced design, that is, the FPGA design scheme corresponding to the design point is a balanced design scheme in the feasible region; if the optimal solution is less than the empirical threshold, there is no balanced design scheme in the feasible region.

[0016] S5: If a balanced design exists, discard the previous feasible region, determine a new feasible region, and repeat S2, S3, and S4 in the new feasible region until there is no balanced alternative.

[0017] The design method provided by this invention maintains the original FPGA algorithm flow, uses the FPGA as the core processor without introducing other processors, keeps the clock consistent, and only adjusts the interrelationships between structures to balance the dual constraints of real-time performance and resources. Furthermore, this design method has general applicability and can be widely applied in various fields where resource and real-time performance conflict. In addition, it evaluates optimization schemes from a system perspective, avoiding local optimization rather than system optimization. For example, a compromise design where system processing power increases by 2% but resource usage increases by 10%. This invention has engineering guidance significance, enabling FPGA designers to conduct system-level optimization designs. Attached Figure Description

[0018] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the drawings described below are only a few embodiments disclosed in this specification. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the gradient calculation results of matrix transpose under different schemes. The first bar represents the ratio of ΔR / R0 (γ), the second bar represents the ratio of ΔT / T0 (β), and the third bar represents the gradient value.

[0020] Figure 2 This is a flowchart illustrating the FPGA design method based on the steepest descent method for the double-constraint problem provided by the present invention. Detailed Implementation

[0021] The solutions provided by the embodiments of this specification will now be described with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. The described embodiments are only a part of the embodiments in this specification, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this specification without inventive effort are within the scope of protection of this application.

[0022] The design method provided by this invention is applicable to FPGA real-time processing fields such as FPGA edge computing. This patent uses real-time processing of on-board synthetic aperture radar signals as an example to illustrate the feasibility and implementation process of this method.

[0023] Its design concept comes from the steepest descent method.

[0024] A nonlinear function f(X) has continuous first-order partial derivatives, and X contains n variables. Then the gradient is defined as:

[0025]

[0026] The steepest descent method uses the negative gradient direction as the search direction. The value of f(X) increases the fastest along the gradient direction, and conversely, the value of f(X) decreases the fastest along the negative gradient direction.

[0027] For m different schemes in FPGA design, the critical resources and time consumed are R1, T1, R2, T2, and R, respectively. m T m ...The on-chip resources are R0, and the system processing time is T0. In the two-dimensional space R, T, the above scheme represents discrete points in the two-dimensional space, and the gradient ▽G between the points is defined as follows:

[0028]

[0029] Where ΔR represents the absolute amount of resource difference between schemes, ΔT represents the absolute amount of time difference, and ▽G reflects the relationship between resource and time changes between schemes. Let γ = ΔR / R0, the value of γ reflects the impact of resource changes on total resources. Let β = ΔT / T0, the value of β reflects the impact of time changes on system processing time. It is worth noting that since FPGAs contain various resources, R0, the total resources of the FPGA chip, also corresponds to a constant for different types of logic resources. Conversely, T0, the total system time, is not fixed and depends on the scheme design.

[0030] In a fast-processing scenario, taking a two-dimensional RT space as an example, the analysis steps applying ▽G are as follows:

[0031] (1) Under the condition of satisfying the FPGA physical constraints R j ≤R0 and time constraint T j Under the condition ≤T0, m initial points (R) are obtained through synthesis and estimation. j ,T j ), 1≤j≤m and j∈Z.

[0032] (2) T k =MIN(T) j ), 1≤k≤m and k∈Z as the initial state, T j Given that 1 ≤ j ≤ m, j ∈ Z and j ≠ k as the next state, calculate (R k ,T k ) and (R j ,T j ▽G between )

[0033] (3) Find the maximum value: ▽G(k,l)=max{▽G(k,j)(1≤j≤m,j∈Zandj≠k)}

[0034] (4) If 1≤l≤m and l≠k, such that ▽G(k,l)≥G gate Then it is said to be relative to (R) k ,T k ), (R l ,T l (R) is more in line with the balanced design; otherwise, it is called (R) k ,T k There is no balanced alternative. gate , is an empirical threshold, which developers select based on system requirements.

[0035] (5) If a balanced design exists, discard (R) k ,T k Points form a new feasible region, let T k=T l Repeat steps (2), (3), and (4) in the new feasible domain to find other balance alternatives. If other balance alternatives exist, replace the current balance design and continue to repeat steps (2), (3), and (4); if no other balance alternatives exist, the current balance design is the best balance solution for the FPGA system design.

[0036] This patent uses the coarse registration and interferogram generation process in InSAR as an example to illustrate the implementation process of this method. G is selected. gate =3, the following is a detailed analysis in conjunction with the InSAR process.

[0037] Generating the interferogram requires calculating all 16K×4K image points, while the coarse registration process only needs to process 512×512 points. Therefore, the interferogram generation process requires significantly more computational resources and time compared to the coarse registration process. Consequently, the computation time for generating the interferogram is crucial to the total system runtime.

[0038] Structural testing results show that lookup table (LUT) resources are used most extensively in generating interferograms. Therefore, LUTs are considered the key resources. The total LUT resources are 433,200, with a utilization rate of 10%; the total FIFO (First-In, First-Out) queue (FF) resources are 866,400, with a utilization rate of 3%; the total embedded block RAM (BRAM) resources are 1,470, with a utilization rate of 0.5%; and the total DSP resources are 3,600, with a utilization rate of 7%. The specific resource allocation is shown in Table 1.

[0039] Table 1 Vivado Overall Results

[0040]

[0041] 1. FPGA design method for double-constrained steepest descent of interferogram generation scheme

[0042] The system uses an FPGA as its core processor and does not incorporate clocks from other processors such as DSPs or CPUs. To maintain consistency, with a 100MHz operating clock, theoretically, calculating 512×512 points requires 262,144 clock cycles, or 2.62ms. Therefore, the ideal coarse registration time T... c It takes 7.86 ms. Generating an interferogram and calculating 16K×4K points requires 64M clock cycles, or 640 ms, i.e., T. g As shown in Table 2. T i Calculate the total time Ti = Tc + Tg for each scheme.

[0043] Table 2. Resource usage and theoretical computation time for generating interferograms at different parallelism levels.

[0044]

[0045] At this point, we obtain R. LUT With T i Calculate ▽G, taking △cb as an example:

[0046] △R=△R LUT =|41723-20914|=20809

[0047] △T=|160-320|=160

[0048] R0 = R LUT =433200

[0049] T0 = ​​T i =Tc + Tg = 167.86

[0050]

[0051] Therefore, γ and β of △cb are:

[0052] γ = ΔR / R0 = 4.80355494%

[0053] β=△T / T0=95.31752651%

[0054] The ▽G of △cb is:

[0055]

[0056] The value of γ reflects the impact of resource changes on the FPGA LUT in the interferogram generation scheme. The closer the optimization of the feasible scheme is to equilibrium, the larger γ is; conversely, the worse the optimization of the feasible scheme, the smaller γ is.

[0057] The value of β reflects the impact of time variation on the FPGA system processing time in the interferogram generation scheme. The closer the optimization of the feasible scheme is to equilibrium, the smaller β is, and vice versa.

[0058] Other calculation processes are omitted, and the results are shown in Table 3:

[0059] Table 3 shows the ▽G values ​​for different parallelism schemes in generating interferograms.

[0060] △cb 20809 4.80355494 160 167.86 95.31752651 0.050395296 △ca 31246 7.212834718 480 167.86 285.9525795 0.025223884 △ba 10437 2.409279778 320 327.86 97.60263527 0.024684577

[0061] Because the condition ▽G≥G is not satisfied gate =3, there is no balanced alternative, and solution C is the optimal design in the current feasible region. The ∂G values ​​for different degrees of parallelism are all less than 0.1, indicating that higher processing power can be achieved using fewer resources—the higher the parallelism, the more resources are used, and the higher the processing power.

[0062] During the calculation of the interferometric phase in the generated interferogram, due to the accuracy limitations of the POS system, residual errors caused by baseline instability still exist in the interferometric phase after motion compensation. Baseline error is a crucial factor determining the accuracy of interferometric elevation measurement; even a small error can significantly impact the interferometric phase and elevation measurement. Therefore, it is necessary to compensate for this error using baseline error estimation methods. FPGA performs real-time pipelined calculations for accuracy compensation on a row-by-row basis. Therefore, the more resources used, the more accurate the accuracy calculation results; higher parallelism and stronger real-time performance also lead to more accurate results.

[0063] Therefore, the dual-constraint problem may also be about accuracy versus resources, accuracy versus real-time performance, etc. With a slight modification to the formula, calculating ▽G with different degrees of parallelism can also yield a balanced alternative that meets the requirements of balanced design.

[0064] 2. FPGA Design Method for Double-Constrained Steepest Descent of Matrix Transpose Scheme

[0065] To accelerate the coarse registration process, a two-dimensional FFT operation is required. Matrix transpose affects the computational efficiency of the FFT in the azimuth and range directions. Due to the influence of the Vivado HLS tool, the matrix transpose scheme in this patent exhibits different efficiencies for different burst lengths, as shown in Table 4. The efficiency η and the key resource in matrix transpose are R. BRAM Resource usage R i This is the measured value, while the coarse registration time T c It was calculated based on efficiency and coarse registration time of 7.86 ms.

[0066] Table 1 Resource usage and theoretical calculation time for the matrix transpose scheme

[0067]

[0068] Similarly, the gradient calculation results of matrix transpose across different schemes are as follows: Figure 1 As shown in the figure, the calculated ▽G value for △gh is 8.16, which is the maximum value of the gradient in the current feasible region. Compared with scheme g, scheme h degrades the overall system time by 1.1%, but saves resources by 8.7%. The ▽G values ​​for △hi and △hj are much less than 3, indicating that scheme h is more in line with the balanced design than scheme g, and is the balanced design scheme in the current feasible region.

[0069] This invention provides an FPGA design method based on steepest descent for the double-constraint problem. Figure 2 This is a flowchart illustrating the design methodology, with the specific steps shown below:

[0070] S201: Determining the Feasibility Domain of FPGA Design under Dual Constraints

[0071] Under the constraints of FPGA internal resources and FPGA system time, the feasible region of FPGA design is determined. The solution corresponding to each design point in the feasible region is a feasible FPGA design scheme, which includes the FPGA resources and time consumed.

[0072] S202: Calculate feasible solutions in the feasible region using the steepest descent method.

[0073] Find the initial point in the feasible region that minimizes the time consumption as the initial state, and the other initial points in the feasible region as the next states. Calculate the gradient value ∠G for the initial state and each next state. The specific gradient is defined as follows: Where △R is the absolute value of the resource difference between schemes, △T is the absolute value of the time difference between schemes, R0 is the total amount of resources inside the FPGA, and T0 is the total time of the FPGA system.

[0074] S203: Determine the optimal solution in the feasible region from the feasible solutions.

[0075] The optimal solution is the maximum value of gradient ∽G. max The corresponding design point, and the FPGA feasible design scheme corresponding to the design point, is the optimal design scheme in the current feasible domain.

[0076] S204: Compare the empirical threshold with the optimal solution to determine if there is a balanced design scheme.

[0077] Select an empirical threshold G based on the system requirements of the FPGA design. gate If ▽G max ≥G gate This is called the gradient ▽G max The corresponding optimal solution conforms to a balanced design, meaning that the scheme corresponding to the optimal solution is determined to be a balanced design scheme in the feasible region; if ▽G max <G gate Then there is no balanced design scheme in the feasible region.

[0078] S205: Repeat steps 2-4 until no balanced alternative can be found.

[0079] If a balanced design exists, discard the previous feasible region and determine a feasible region with the new design point as the element. Repeat S202, S203, and S204 in the new feasible region until there is no balanced alternative.

[0080] The FPGA design method provided by this invention is a design approach that balances the conflict between resource constraints and real-time performance, and can be widely applied in various fields where resource constraints and real-time performance are at odds. This invention is described in the context of InSAR, but is not limited to this field. Furthermore, the dual-constraint problem may involve accuracy versus resources, accuracy versus real-time performance, etc. The formulas may be slightly modified, but the essence remains the same as the concept of this patent and is also protected.

[0081] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. An FPGA design method based on the steepest descent method for the double-constraint problem, comprising the following steps: S1: Under the constraints of FPGA internal resources and FPGA system time, determine the feasible region of FPGA design. The solution corresponding to each design point in the feasible region is a feasible FPGA design scheme. S2: Find the design point with the minimum time consumption in the feasible region as the initial state; Treat other design points in the feasible region as next states; Calculate the gradient value ▽G for the initial state and each next state respectively; The specific gradient is defined as ▽G= , where △R is the absolute value of the resource difference between schemes, △T is the absolute value of the time difference between schemes, R0 is the total amount of resources inside the FPGA, and T0 is the total time of the FPGA system; S3: Determine the optimal solution in the feasible region from the feasible solutions; S4: Select an empirical threshold based on the system requirements of the FPGA design. If the optimal solution is greater than or equal to the empirical threshold, the design point corresponding to the optimal solution is said to conform to a balanced design, that is, the FPGA design scheme corresponding to the design point is a balanced design scheme in the feasible region; if the optimal solution is less than the empirical threshold, there is no balanced design scheme in the feasible region. S5: If a balanced design exists, discard the previous feasible region, determine a new feasible region, and repeat S2, S3, and S4 in the new feasible region until there is no balanced alternative.

2. The method according to claim 1, characterized in that: The feasible FPGA design schemes in S1 include the FPGA internal resources and system time consumed by the scheme.

3. The method according to claim 1, characterized in that: The optimal solution in S4 is the maximum value of gradient ▽G, and the FPGA feasible design scheme corresponding to the maximum value design point is the optimal design scheme in the current feasible region.

4. The method according to claim 1, characterized in that: Let γ= The value of γ reflects the impact of resource changes on the total FPGA resources; let β = The value of β reflects the impact of time variation on the processing time of the FPGA system.

5. The method according to claim 1, characterized in that: For different FPGA design schemes, the optimal solution can be found using ▽G from the system level to the module level. At the same time, ▽G can also serve as a standard for evaluating and optimizing schemes at the system level, by comparing the impact of schemes before and after optimization on the system using ▽G.

6. The method according to claim 1, characterized in that: The method uses an FPGA as the core processor and keeps the system clock consistent.

7. The method according to claim 1, characterized in that: The constraints also include, but are not limited to, FPGA computing accuracy and FPGA internal resources, FPGA computing accuracy and real-time performance, etc.

8. The method according to claim 1, characterized in that: The balanced design scheme in S4 is only a balanced design scheme in the current feasible domain. Only when S2, S3, and S4 are repeated in all feasible domains and no other balanced alternative scheme is found can the balanced design scheme be called the best balanced scheme for the current FPGA design.

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