Pipe latch circuit for performing continuous data output operations

Abstract

A pipeline latch circuit for performing a continuous data output operation is provided. The pipeline latch circuit includes a data latch circuit configured to latch input data based on an input control signal and output the latched input data as latch data based on an output control signal, a sense amplifier circuit configured to sense and amplify the latch data based on the output control signal, and a data driver circuit configured to drive output data from the latch data based on the output control signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0060349, filed on May 10, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a semiconductor device including a pipeline latch circuit. Background Technology

[0004] Typically, semiconductor devices include pipelined latch circuits for outputting continuous data. A pipelined latch circuit stores data transferred from a memory cell array and outputs the data sequentially in sync with a clock signal. The number of data latches in a pipelined latch circuit varies depending on the amount of data to be input and latched, and the number of data latches constituting the pipelined latch circuit is determined by factors such as the latency information of the semiconductor device. Furthermore, the data latches included in a pipelined latch circuit can be connected in series or in parallel. Summary of the Invention

[0005] According to embodiments of the present disclosure, an electronic device may be provided, comprising: a data latch circuit configured to latch input data based on an input control signal and to output the latched input data as latched data based on an output control signal; a sensing amplification circuit configured to sense and amplify the latched data based on a sum output control signal; and a data driving circuit configured to drive output data from the latched data based on the sum output control signal.

[0006] Furthermore, according to another embodiment of this disclosure, an electronic device can be provided, comprising: a first data latch configured to latch input data to a first node when a pulse of a first bit of an input control signal is generated, and to output the input data latched to the first node as latched data when a pulse of a first bit of an output control signal is generated; a second data latch configured to latch input data to a second node when a pulse of a second bit of an input control signal is generated, and to output the input data latched to the second node as latched data when a pulse of a second bit of the output control signal is generated; and a sensing amplification circuit configured to sense and amplify the latched data based on the output control signal to drive output data.

[0007] Furthermore, according to another embodiment of this disclosure, a method for performing continuous data output operation can be provided, the method comprising: latching input data and inverted input data based on an input control signal; outputting the latched input data as latched data and the latched inverted input data as inverted latched data based on an output control signal; sensing and amplifying the latched data and inverted latched data based on the output control signal; and driving output data from the latched data and inverted latched data based on the output control signal. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a circuit diagram according to an embodiment of a data latch circuit, the data latch circuit including... Figure 1 In the semiconductor device shown.

[0010] Figure 3 This is a circuit diagram of an embodiment of a control signal generation circuit, which includes... Figure 1 In the semiconductor device shown.

[0011] Figure 4 This is a circuit diagram according to an embodiment of a sensing amplification circuit, the sensing amplification circuit including... Figure 1 In the semiconductor device shown.

[0012] Figure 5 This is a circuit diagram according to an embodiment of a data driving circuit, the data driving circuit including... Figure 1 In the semiconductor device shown.

[0013] Figures 6 to 16 It is shown Figures 1 to 5 A diagram illustrating the operation of the semiconductor device described in the text.

[0014] Figure 17 This is a timing diagram illustrating the continuous data output operation of a pipeline latch circuit included in a semiconductor device. Detailed Implementation

[0015] In the following description of the embodiments, when a parameter is referred to as "predetermined," it may mean that the value of the parameter is predetermined when it is used in a process or algorithm. The value of the parameter may be set at the start of the process or algorithm, or it may be set during a period of time when the process or algorithm is executed.

[0016] It will be understood that although the terms “first,” “second,” “third,” etc., are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another and are not intended to imply the order or number of elements. Therefore, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this disclosure.

[0017] Furthermore, it should be understood that when a component is referred to as "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0018] Logic "high" and logic "low" levels can be used to describe the logic levels of electrical signals. Signals with a logic "high" level can be distinguished from signals with a logic "low" level. For example, when a signal with a first voltage corresponds to a signal with a logic "high" level, a signal with a second voltage corresponds to a signal with a logic "low" level. In one embodiment, a logic "high" level can be set to a voltage level higher than that of a logic "low" level. Furthermore, according to embodiments, the logic levels of signals can be set to different or opposite levels. For example, a signal with a logic "high" level in one embodiment may be set to a logic "low" level in another embodiment.

[0019] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0020] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor device 100 may include an input / output control circuit (I / O CNT) 11, a pipeline latch control circuit (PL CNT) 13, a data storage circuit (DATA STG) 15, and a pipeline latch circuit 17.

[0021] The input / output control circuit 11 can receive commands (CMD), addresses (ADD), and clocks (CLK) from external devices of the semiconductor device 100. These external devices can be semiconductor controllers (not shown) or test devices (not shown). The input / output control circuit 11 can include a command decoder (not shown) for decoding the command CMD and an address decoder (not shown) for decoding the address ADD. The input / output control circuit 11 can control the pipe latch control circuit 13 and the data storage circuit 15 based on the command CMD, address ADD, and clock CLK to control the input / output of data to / from the pipe latch circuit 17. The input / output control circuit 11 can control the data storage circuit 15 so that input data DIN is output from the data storage circuit 15. The input / output control circuit 11 can control the pipe latch control circuit 13 so that the input data DIN output from the data storage circuit 15 is input to the data latch circuit 171 included in the pipe latch circuit 17. The input / output control circuit 11 can control the pipe latch control circuit 13, so that the data input to the data latch circuit 171 is output.

[0022] The pipeline latch control circuit 13 can be controlled by the input / output control circuit 11 to generate an input control signal PIN and an output control signal POUT, which are used for inputting data to / outputting data from the pipeline latch circuit 17. The pipeline latch control circuit 13 can also be controlled by the input / output control circuit 11 to generate an input control signal PIN for inputting input data DIN to the data latch circuit 171. Furthermore, the pipeline latch control circuit 13 can be controlled by the input / output control circuit 11 to generate an output control signal POUT for outputting latched data from the data latch circuit 171. Each of the input control signal PIN and the output control signal POUT may include multiple bits, and the number of bits included in each of the input control signal PIN and the output control signal POUT may be set differently depending on the embodiment.

[0023] The data storage circuit 15 can be controlled by the input / output control circuit 11 to output the input data DIN to be input to the pipe latch circuit 17. The data storage circuit 15 may include a memory cell array accessed by an address ADD input to the input / output control circuit 11. According to an embodiment, the data storage circuit 15 can be implemented using a buffer memory.

[0024] The pipe latch circuit 17 can receive the input control signal PIN and the output control signal POUT from the pipe latch control circuit 13. The pipe latch circuit 17 can receive input data DIN from the data storage circuit 15. The pipe latch circuit 17 can latch the input data DIN based on the input control signal PIN. The pipe latch circuit 17 can generate latched data LD and inverted latched data LDB from the latched input data DIN based on the output control signal POUT. The pipe latch circuit 17 can sense and amplify the latched data LD and inverted latched data LDB based on the output control signal POUT. The pipe latch circuit 17 can drive the output data DOUT based on the sensed and amplified latched data LD and inverted latched data LDB and based on the output control signal POUT. The pipe latch circuit 17 may include a data latch circuit (LAT CTR) 171, an output control signal generation circuit (SPO GEN) 173, a sensing amplification circuit 175, and a data drive circuit (DRV) 177.

[0025] The data latch circuit 171 can receive the input control signal PIN and the output control signal POUT from the pipe latch control circuit 13, receive the input data DIN from the data storage circuit 15, and invert and buffer the input data DIN to generate inverted input data DNB. The data latch circuit 171 can latch the input data DIN and the inverted input data DNB based on the input control signal PIN. The data latch circuit 171 can output the latched input data DIN and the inverted input data DNB as latched data LD and inverted latched data LDB based on the output control signal POUT.

[0026] The output control signal generation circuit 173 can receive the output control signal POUT from the pipe latch control circuit 13. The output control signal generation circuit 173 can generate an output control signal SPO and an inverted output control signal SPOB based on the output control signal POUT. The output control signal generation circuit 173 can generate an output control signal SPO with pulses generated synchronously with the pulses of the bits included in the output control signal POUT. The output control signal generation circuit 173 can invert and buffer the output control signal SPO to generate the inverted output control signal SPOB.

[0027] The sensing amplifier circuit 175 can receive latched data LD and inverted latched data LDB from the data latch circuit 171. The sensing amplifier circuit 175 can also receive an output control signal SPO from the output control signal generation circuit 173. The sensing amplifier circuit 175 can sense and amplify the latched data LD and inverted latched data LDB based on the output control signal SPO. When a pulse of the output control signal SPO is generated, the sensing amplifier circuit 175 can sense and amplify the latched data LD and inverted latched data LDB.

[0028] The data drive circuit 177 can receive latched data LD and inverted latched data LDB from the data latch circuit 171. The data drive circuit 177 can also receive the inverted output control signal SPOB from the output control signal generation circuit 173. The data drive circuit 177 can drive the output data DOUT based on the inverted output control signal SPOB, the latched data LD, and the inverted latched data LDB. When a pulse of the inverted output control signal SPOB is generated, the sense amplifier circuit 175 can drive the output data DOUT based on the latched data LD and the inverted latched data LDB sensed and amplified by the sense amplifier circuit 175.

[0029] Figure 2 This is a circuit diagram based on an embodiment of the data latch circuit 171. (See diagram below.) Figure 2 As shown, the data latch circuit 171 may include an inverter 20 and first data latches 21_1 to Nth data latches 21_N. The inverter 20 can invert and buffer the input data DIN input through node n201 to generate inverted input data DNB and output the inverted input data DNB to node n203.

[0030] The first data latch 21_1 may include NMOS transistors 211_1, 212_1, 217_1, and 218_1, as well as inverters 214_1 and 215_1. NMOS transistor 211_1 may be connected between node n201 and node n211_1, and NMOS transistor 211_1 may be included in the first bit of the input control signal PIN. <1> The NMOS transistor 211_1 is turned on when the pulse is generated. When the NMOS transistor 211_1 is turned on, the input data DIN input through node n201 can be transmitted to node n211_1 and latched. The NMOS transistor 212_1 can be connected between node n203 and node n213_1, and the NMOS transistor 212_1 can include the first bit of the input control signal PIN. <1> The NMOS transistor 212_1 is turned on when the pulse is generated. When the NMOS transistor 212_1 is turned on, the inverted input data DNB of node n203 can be transmitted to node n213_1 and latched. Inverter 214_1 can invert and buffer the signal of node n211_1 to output the inverted and buffered signal to node n213_1. Inverter 215_1 can invert and buffer the signal of node n213_1 to output the inverted and buffered signal to node n211_1. Inverters 214_1 and 215_1 can latch the signals of node n211_1 and node n213_1. NMOS transistor 217_1 can be connected between node n213_1 and node n221, and NMOS transistor 217_1 can include the first bit POUT in the output control signal POUT. <1> The NMOS transistor 217_1 is turned on when the pulse is generated. When the NMOS transistor 217_1 is turned on, the inverted input data DIB latched at node n213_1 can be output as the inverted latched data LDB at node n221. The NMOS transistor 218_1 can be connected between node n211_1 and node n223, and the first bit POUT of the NMOS transistor 218_1 can be included in the output control signal POUT. <1> The NMOS transistor 218_1 is turned on when the pulse is generated. When the NMOS transistor 218_1 is turned on, the input data DIN latched to node n211_1 can be output as latched data LD.

[0031] The second data latch 21_2 may include NMOS transistors 211_2, 212_2, 217_2, and 218_2, as well as inverters 214_2 and 215_2. NMOS transistor 211_2 may be connected between node n201 and node n211_2, and NMOS transistor 211_2 may be included in the second bit of the input control signal PIN. <2> The NMOS transistor 211_2 is turned on when the pulse is generated. When the NMOS transistor 211_2 is turned on, the input data DIN input through node n201 can be transmitted to node n211_2 and latched. The NMOS transistor 212_2 can be connected between node n203 and node n213_2, and the NMOS transistor 212_2 can be included in the second bit of the input control signal PIN. <2> The NMOS transistor 212_2 is turned on when the pulse is generated. When the NMOS transistor 212_2 is turned on, the inverted input data DIB of node n203 can be transmitted to node n213_2 and latched. Inverter 214_2 can invert and buffer the signal of node n211_2 and output the inverted and buffered signal to node n213_2. Inverter 215_2 can invert and buffer the signal of node n213_2 and output the inverted and buffered signal to node n211_2. Inverters 214_2 and 215_2 can latch the signals of node n211_2 and node n213_2. NMOS transistor 217_2 can be connected between node n213_2 and node n221, and NMOS transistor 217_2 can include the second bit POUT in the output control signal POUT. <2> The NMOS transistor 217_2 is turned on when the pulse is generated. When the NMOS transistor 217_2 is turned on, the inverted input data DNB latched at node n213_2 can be output as the inverted latched data LDB at node n221. The NMOS transistor 218_2 can be connected between node n211_2 and node n223, and the second bit POUT included in the output control signal POUT of the NMOS transistor 218_2 can be used to control the output. <2> The NMOS transistor 218_2 is turned on when the pulse is generated. When the NMOS transistor 218_2 is turned on, the input data DIN latched to node n211_2 can be output as latched data LD.

[0032] The Nth data latch 21_N may include NMOS transistors 211_N, 212_N, 217_N, and 218_N, as well as inverters 214_N and 215_N. NMOS transistor 211_N may be connected between node n201 and node n211_N, and NMOS transistor 211_N may be included in the Nth bit of the input control signal PIN. <n>The NMOS transistor 211_N is turned on when the pulse is generated. When the NMOS transistor 211_N is turned on, the input data DIN input through node n201 can be transmitted to node n211_N and latched. The NMOS transistor 212_N can be connected between nodes n203 and n213_N, and the NMOS transistor 212_N can be included in the Nth bit of the input control signal PIN. <n>The NMOS transistor 212_N is turned on when the pulse is generated. When the NMOS transistor 212_N is turned on, the inverted input data DIB of node n203 can be transmitted to node n213_N and latched. Inverter 214_N can invert and buffer the signal of node n211_N and output the inverted and buffered signal to node n213_N. Inverter 215_N can invert and buffer the signal of node n213_N and output the inverted and buffered signal to node n211_N. Inverters 214_N and 215_N can latch the signals of node n211_N and node n213_N. NMOS transistor 217_N can be connected between node n213_N and node n221, and NMOS transistor 217_N can include the Nth bit POUT in the output control signal POUT. <n>The NMOS transistor 217_N is turned on when the pulse is generated. When the NMOS transistor 217_N is turned on, the inverted input data DIB latched at node n213_N can be output as the inverted latched data LDB at node n221. The NMOS transistor 218_N can be connected between node n211_N and node n223, and the NMOS transistor 218_N can be included in the Nth bit of the output control signal POUT. <n>The NMOS transistor 218_N is turned on when the pulse is generated. When the NMOS transistor 218_N is turned on, the input data DIN latched at node n211_N can be output as latched data LD.

[0033] When the first bit of the input control signal PIN is PIN <1> When the pulse is generated, the data latch circuit 171 can latch the input data DIN and the inverted input data DINB, and when the first bit of the output control signal POUT is generated... <1> When the pulse is generated, the data latch circuit 171 can output the latched input data DIN and the inverted input data DINB as latched data LD and inverted latched data LDB. Furthermore, when the second bit of the input control signal PIN is input... <2> When the pulse is generated, the data latch circuit 171 can latch the input data DIN and the inverted input data DINB, and when the second bit of the output control signal POUT is generated... <2> When the pulse is generated, the data latch circuit 171 can output the latched input data DIN and the inverted input data DINB as latched data LD and inverted latched data LDB. Similarly, when the Nth bit of the input control signal PIN is input... <n>When the pulse is generated, the data latch circuit 171 can latch the input data DIN and the inverted input data DINB, and when the Nth bit of the output control signal POUT is generated... <n>When the pulse is generated, the data latch circuit 171 can output the latched input data DIN and the inverted input data DINB as latched data LD and inverted latched data LDB.

[0034] Figure 3 This is a circuit diagram based on an embodiment of the output control signal generation circuit 173. (See diagram for example.) Figure 3 As shown, the output control signal generation circuit 173 may include an OR gate 221 and an inverter 223. The OR gate 221 can receive the first bit POUT of the output control signal POUT. <1> The Nth bit of the output control signal POUT <n>To perform an OR operation. When the first bit of the output control signal POUT is... <1> The Nth bit of the output control signal POUT <n>When at least one bit in the output control signal POUT is generated at a logic "high" level, OR gate 221 can generate an output control signal SPO with a pulse generated at a logic "high" level. Inverter 223 can invert and buffer the output control signal SPO to generate an inverted output control signal SPOB. When the first bit of the output control signal POUT is generated... <1> The Nth bit of the output control signal POUT <n>When at least one bit in the signal is generated at a logic "high" level, the output control signal generation circuit 173 can generate an output control signal SPO with a pulse generated at a logic "high" level and an inverted output control signal SPOB with a pulse generated at a logic "low" level.

[0035] Figure 4 This is a circuit diagram based on an embodiment of the sensing amplifier circuit 175. (See diagram below.) Figure 4 As shown, the sensing amplifier circuit 175 may include PMOS transistors 231, 233, 235 and 237 and NMOS transistors 239, 241 and 243.

[0036] PMOS transistor 231 can be connected between the drive voltage VP and node n231, and can be turned on based on the output control signal SPO. When the output control signal SPO is set to a logic "low" level, PMOS transistor 231 can be turned on to drive the inverted latched data LDB output from node n231 to the drive voltage VP. PMOS transistor 233 can be connected between the drive voltage VP and node n233, and can be turned on based on the output control signal SPO. When the output control signal SPO is set to a logic "low" level, PMOS transistor 233 can be turned on to drive the latched data LD output from node n233 to the drive voltage VP. According to an embodiment, the drive voltage VP can be set to a power supply voltage VDD applied from an external device (not shown) of semiconductor device 100, or it can be set to an internal voltage generated from the power supply voltage VDD.

[0037] PMOS transistor 235 can be connected between the drive voltage VP and node n231, and can be turned on based on latched data LD. When the level of latched data LD is set to be one level lower than the level of inverted latched data LDB, PMOS transistor 235 can be turned on to drive the inverted latched data LDB to the drive voltage VP, wherein the lower level is a preset sensing level or a level higher than the preset sensing level. PMOS transistor 237 can be connected between the drive voltage VP and node n233, and can be turned on based on the inverted latched data LDB of node n231. When the level of inverted latched data LDB is set to be one level lower than the level of latched data LD, PMOS transistor 237 can be turned on to drive the latched data LD to the drive voltage VP, wherein the lower level is a preset sensing level or a level higher than the preset sensing level.

[0038] NMOS transistor 239 can be connected between nodes n231 and n235 and can be turned on based on latched data LD. NMOS transistor 241 can be connected between nodes n233 and n235 and can be turned on based on inverted latched data LDB. NMOS transistor 243 can be connected between node n235 and ground voltage VSS and can be turned on based on output control signal SPO. NMOS transistor 243 can be turned on when a pulse is generated that is set to a logic "high" level with output control signal SPO. When NMOS transistor 243 is turned on, NMOS transistor 239 can be turned on to drive inverted latched data LDB to ground voltage VSS when the level of latched data LD is set to be one level higher than the level of inverted latched data LDB, wherein the higher level is a preset sensing level or a level higher than the preset sensing level. When NMOS transistor 243 is turned on, and the level of the inverted latched data LDB is set to be one level higher than the level of the latched data LD, NMOS transistor 241 can be turned on to drive the latched data LD to the ground voltage VSS, wherein the higher level is a preset sensing level or a level higher than the preset sensing level.

[0039] When the level difference between latched data LD and inverted latched data LDB is set to a preset sensing level or a level higher than the preset sensing level, the sensing amplifier circuit 175 can sense and amplify the latched data LD and inverted latched data LDB. For example, when the level of latched data LD is set to be one level higher than the level of inverted latched data LDB, the sensing amplifier circuit 175 can sense the level difference between latched data LD and inverted latched data LDB to drive the latched data LD to the drive voltage VP and drive the inverted latched data LDB to the ground voltage VSS, wherein the higher level is the preset sensing level or a level higher than the preset sensing level. The preset sensing level can be set according to the dimensions and PVT (process, voltage, temperature) characteristics of PMOS transistors 231, 233, 235, and 237 and NMOS transistors 239, 241, and 243. As another example, when the level of the inverted latched data LDB is set to be one level higher than the level of the latched data LD, the sensing amplifier circuit 175 can sense the level difference between the latched data LD and the inverted latched data LDB to drive the latched data LD to the ground voltage VSS and drive the inverted latched data LDB to the drive voltage VP, wherein the higher level is a preset sensing level or a level higher than the preset sensing level.

[0040] Figure 5 This is a circuit diagram based on an embodiment of the data drive circuit 177. (As shown) Figure 5 As shown, the data driving circuit 177 may include a pull-up signal generator 251, a pull-down signal generator 253, a driver 255, and an output latch 257.

[0041] Pull-up signal generator 251 may include NOR gate 261 and inverter 263, and may perform an OR operation on the inverted output control signal SPOB and latched data LD to generate pull-up signal PU. When the latched data LD is driven to a logic "low" level, pull-up signal generator 251 can generate pull-up signal PU activated to a logic "low" level by generating a pulse set to a logic "low" level with the inverted output control signal SPOB. Pull-down signal generator 253 may be implemented using NOR gates that perform NOR operations, and may perform an NOR operation on the inverted output control signal SPOB and inverted latched data LDB to generate pull-down signal PD. When the inverted output control signal SPOB is driven to a logic "low" level by generating a pulse set to a logic "low" level, pull-down signal generator 253 can generate pull-down signal PD activated to a logic "low" level by generating a pulse set to a logic "low" level with the inverted output control signal SPOB. Driver 255 may include PMOS transistor 265 and NMOS transistor 266. PMOS transistor 265 can be connected between drive voltage VP and node n251, and can drive node n251 to drive voltage VP when pull-up signal PU is activated to logic "low". NMOS transistor 266 can be connected between node n251 and ground voltage VSS, and can drive node n251 to ground voltage VSS when pull-down signal PD is activated to logic "high". Output latch 257 may include inverters 267 and 269. Output latch 257 can invert and buffer the signal of node n251 and output the inverted and buffered signal as the output data DOUT of node n253. Output latch 257 can latch the signals of node n251 and node n253.

[0042] When a pulse is generated that is set to a logic "low" level with the inverted output control signal SPOB, the data driver circuit 177 can drive the output data DOUT when the logic levels of the latched data LD and the inverted latched data LDB sensed and amplified by the sense amplifier circuit 175 are driven to the inverted logic level. As an example, when a pulse is generated that is set to a logic "low" level with the inverted output control signal SPOB, the data driver circuit 177 can drive the output data DOUT to a logic "high" level when the latched data LD is set to a logic "high" level and the inverted latched data LDB is set to a logic "low" level. As another example, when a pulse is generated that is set to a logic "low" level with the inverted output control signal SPOB, the data driver circuit 177 can drive the output data DOUT to a logic "low" level when the latched data LD is set to a logic "low" level and the inverted latched data LDB is set to a logic "high" level.

[0043] The following will be for reference Figures 6 to 16 The operation of the semiconductor device 100 configured as described above is described.

[0044] First, such as Figure 6 and Figure 7 As shown, when the first bit PIN is generated at time T11_1 and set to have the input control signal PIN, <1> When a logic "high" level 'H' pulse is received, the input data DIN, which is set to a logic "high" level 'H', is transmitted to node n211_1 and latched, and the inverted input data DINB, which is set to a logic "low" level 'L', can be transmitted to node n213_1 and latched.

[0045] Next, as Figure 6 and Figure 8 As shown, when the first bit POUT is generated at time T13_1 and set to have the output control signal POUT, <1> When a logic "high" level 'H' pulse is received, the latched data LD, which is set to have a logic "high" level 'H', can be generated based on the logic "high" level 'H' of the input data DIN latched to node n211_1, and the inverted latched data LDB, which is set to have a logic "low" level 'L', can be generated based on the logic "low" level 'L' of the inverted input data DINB latched to node n213_1.

[0046] Next, as Figure 6 and Figure 9 As shown, when the first bit POUT is generated at time T13_1 and set to have the output control signal POUT, <1> When a pulse of logic "high" level 'H' is generated, an output control signal SPO can be generated with a pulse set to logic "high" level 'H', and an inverted output control signal SPOB can be generated with a pulse set to logic "low" level 'L'.

[0047] Next, as Figure 6 and Figure 10 As shown, when a pulse is generated that is set to have a logic "high" level 'H' with the output control signal SPO, when the level of the inverted latched data LDB is set to be one level lower than the level of the latched data LD (where the lower level is a preset sensing level or a level higher than the preset sensing level), the latched data LDB can be amplified by the NMOS transistor 237, which is turned on by sensing the level of the inverted latched data LDB, and the latched data LDB can be generated to have a logic "high" level 'H'. Furthermore, when a pulse is generated that is set to have a logic "high" level 'H' with the output control signal SPO, when the level of the latched data LD is set to be one level higher than the level of the inverted latched data LDB (where the higher level is a preset sensing level or a level higher than the preset sensing level), the inverted latched data LDB can be amplified by the NMOS transistor 239, which is turned on by sensing the level of the latched data LD, and the inverted latched data LDB can be generated to have a logic "low" level 'L'.

[0048] Next, as Figure 6 and Figure 11 As shown, when a pulse is generated that is set to a logic "low" level 'L' with the inverted and output control signal SPOB, when the latched data LD is generated to a logic "high" level 'H' and the inverted latched data LDB is generated to a logic "low" level 'L', the NMOS transistor 266 can be turned on to generate output data DOUT set to a logic "high" level 'H'.

[0049] Next, as Figure 6 and Figure 12 As shown, when the second bit PIN is generated at time T11_2 and set to have the input control signal PIN, <2> When a logic "high" level 'H' pulse is received, the input data DIN, which is set to a logic "low" level 'L', can be transmitted to node n211_2 and latched, and the inverted input data DINB, which is set to a logic "high" level 'H', can be transmitted to node n213_2 and latched.

[0050] Next, as Figure 6 and Figure 13 As shown, when the second bit POUT is generated at time T13_2 and set to have the output control signal POUT, <2> When a logic "high" level 'H' pulse is received, the latched data LD, which is set to a logic "low" level 'L', can be generated based on the logic "low" level 'L' of the input data DIN latched in node n211_2, and the inverted latched data LDB, which is set to a logic "high" level 'H', can be generated based on the logic "high" level 'H' of the inverted input data DINB latched in node n213_2.

[0051] Next, as Figure 6 and Figure 14 As shown, when the second bit POUT is generated at time T13_2 and set to have the output control signal POUT, <2> When a pulse of logic "high" level 'H' is generated, an output control signal SPO can be generated with a pulse set to logic "high" level 'H', and an inverted output control signal SPOB can be generated with a pulse set to logic "low" level 'L'.

[0052] Next, as Figure 6 and Figure 15 As shown, when a pulse is generated that is set to have a logic "high" level 'H' with the output control signal SPO, when the level of the latched data LD is set to be one level lower than the level of the inverted latched data LDB (where the lower level is a preset sensing level or a level higher than the preset sensing level), the inverted latched data LDB can be amplified by the PMOS transistor 235, which is turned on by sensing the level of the latched data LD, and the inverted latched data LDB can be generated to have a logic "high" level 'H'. Furthermore, when a pulse is generated that is set to have a logic "high" level 'H' with the output control signal SPO, when the level of the inverted latched data LDB is set to be one level higher than the level of the latched data LD (where the higher level is a preset sensing level or a level higher than the preset sensing level), the level of the inverted latched data LDB can be amplified by the NMOS transistor 241, which is turned on by sensing the latched data LD, and the level of the inverted latched data LDB can be generated to have a logic "low" level 'L'.

[0053] Next, as Figure 6 and Figure 16 As shown, when a pulse is generated that is set to a logic "low" level 'L' with the inverted and output control signal SPOB, the PMOS transistor 265 can be turned on to generate output data DOUT set to a logic "low" level 'L' when the inverted latched data LDB is generated to a logic "high" level 'H' and the latched data LD is generated to a logic "low" level 'L'.

[0054] Next, as Figure 6 As shown, when the Nth bit PIN is generated at time T11_N and set to have the input control signal PIN, <n>When a pulse of logic "high" level 'H' is received, input data DIN that is set to logic "high" level 'H' can be latched, and inverted input data DINB that is set to logic "low" level 'L' can be latched.

[0055] Next, as Figure 6 As shown, when the Nth bit POUT is generated at time T13_N and set to have the output control signal POUT, <n>When a pulse of logic "high" level 'H' is generated, latched data LD can be generated that is set to logic "high" level 'H', and inverted latched data LDB can be generated that is set to logic "low" level 'L'.

[0056] Next, as Figure 6 As shown, when the Nth bit POUT is generated at time T13_N and set to have the output control signal POUT, <n>When a pulse of logic "high" level 'H' is generated, an output control signal SPO can be generated with a pulse set to logic "high" level 'H', and an inverted output control signal SPOB can be generated with a pulse set to logic "low" level 'L'.

[0057] Next, as Figure 6 As shown, when a pulse is generated that is set to have a logic "high" level 'H' similar to the output control signal SPO, and the level of the inverted latched data LDB is set to be one level lower than the level of the latched data LD (where the lower level is a preset sensing level or a level higher than the preset sensing level), the sensed and amplified latched data LD can be generated to have a logic "high" level 'H'. Furthermore, when a pulse is generated that is set to have a logic "high" level 'H' similar to the output control signal SPO, and the level of the latched data LD is set to be one level higher than the level of the inverted latched data LDB (where the higher level is a preset sensing level or a level higher than the preset sensing level), the sensed and amplified inverted latched data LDB can be generated to have a logic low level 'L'.

[0058] Next, as Figure 6 As shown, when a pulse is generated that is set to a logic "low" level 'L' with an inverted output control signal SPOB, when latched data LD is generated to a logic "high" level 'H' and inverted latched data LDB is generated to a logic "low" level 'L', output data DOUT that is set to a logic "high" level 'H' can be generated.

[0059] When the level difference between latched data LD and inverted latched data LDB is set to a preset sensing level or a level higher than the preset sensing level, the semiconductor device 100 can drive the output data DOUT at high speed based on the latched data LD and inverted latched data LDB sensed and amplified by the sensing amplifier circuit 175. Therefore, even if the number of data latches included in the data latch circuit 171 increases and the load of the output node to which the data latches are connected increases, the semiconductor device 100 can quickly drive the output data DOUT if the level difference between latched data LD and inverted latched data LDB is only above the preset sensing level.

[0060] Figure 17 This is a timing diagram illustrating the continuous data output operation of the pipe latch circuit 17 included in the semiconductor device 100.

[0061] First, with K set to 1 (S301), when the Kth bit of the input control signal PIN is generated... <k>When the pulse is applied (S303), the input data DIN and the inverted input data DNB can be latched (S305).

[0062] Next, when the Kth bit of the output control signal POUT is generated... <k>When the pulse is received (S307), the pulse of the control signal SP0 and the pulse of the inverted and output control signal SPOB can be generated and output, and the latched data LD and the inverted latched data LDB can be sensed and amplified (S311). The output data DOUT can be generated based on the sensed and amplified latched data LD and the inverted latched data LDB (S313).

[0063] Next, it is determined whether K is the same as the number L of data latches included in the pipe latch circuit 17 (S315). When K is not equal to L, K can be incremented by 1 (S317), and steps S303 to S313 can be repeated. When K is equal to L, the operation of the pipe latch circuit 17 can be terminated because the data latched into all the data latches included in the pipe latch circuit 17 is output as output data DOUT.

[0064] The present concept has been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered limiting but illustrative. The scope of the present concept is not limited to the foregoing description but is defined by the appended claims, and all significant features within the equivalent scope should be construed as being included in the present concept.< / k> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A pipe latch circuit, comprising: A data latch circuit, the data latch circuit being configured to latch input data based on an input control signal comprising multiple bits and to output the latched input data as latched data based on an output control signal comprising multiple bits; A sensing amplification circuit, configured to sense and amplify the latched data based on and output a control signal; as well as A data driving circuit configured to output data from the latched data drive based on the output control signal; The output control signal is generated from the output control signal.

2. The pipe latch circuit as described in claim 1, wherein, When the pulse of the first bit of the input control signal is generated, the data latch circuit latches the input data to the first node, and when the pulse of the first bit of the output control signal is generated, the data latch circuit outputs the input data latched to the first node as the latched data.

3. The pipe latch circuit as described in claim 2, wherein, When the pulse of the Kth bit of the input control signal is generated, the data latch circuit latches the input data to the Kth node, and when the pulse of the Kth bit of the output control signal is generated, the data latch circuit outputs the input data latched to the Kth node as the latched data, where "K" is a natural number of 2 or greater.

4. The pipe latch circuit of claim 1, further comprising an output control signal generation circuit configured to generate the output control signal, the output control signal having a pulse generated when a pulse of at least one bit of the bits included in the output control signal is generated.

5. The pipe latch circuit as described in claim 1, wherein, The data latch circuit performs an inverted buffering of the input data to generate inverted input data, latches the inverted input data based on the input control signal, and outputs the latched inverted input data as inverted latched data based on the output control signal.

6. The pipe latch circuit as described in claim 5, wherein, When the level of the latched data is set to be one level higher than the level of the inverted latched data, the sensing amplifier circuit drives the latched data to a driving voltage and drives the inverted latched data to a ground voltage, wherein the higher level is a preset sensing level or a level higher than the preset sensing level.

7. The pipe latch circuit as described in claim 5, wherein, When the level of the inverted latched data is set to be one level higher than the level of the latched data, the sensing amplifier circuit drives the inverted latched data to a driving voltage and drives the latched data to a ground voltage, wherein the higher level is a preset sensing level or a level higher than the preset sensing level.

8. The pipe latch circuit as described in claim 5, wherein, When the pulses of the output control signal are generated, the sensing amplifier circuit senses and amplifies the latched data and the inverted latched data.

9. The pipe latch circuit as described in claim 1, wherein, When the pulse of the inverted output control signal, generated by inverting the output control signal, is generated, the data driving circuit drives the output data based on the latched data and the inverted latched data.

10. The pipe latch circuit as described in claim 9, wherein, The data driving circuit generates a pull-up signal based on the inverted output control signal and the latched data, generates a pull-down signal based on the inverted output control signal and the inverted latched data, and drives the output data based on the pull-up signal and the pull-down signal.

11. A pipe latch circuit, comprising: A first data latch is configured to latch input data to a first node when a pulse of the first bit of an input control signal is generated, and to output the input data latched to the first node as latched data when a pulse of the first bit of an output control signal is generated. The second data latch is configured to latch the input data to the second node when a pulse of the second bit of the input control signal is generated, and to output the input data latched to the second node as the latched data when a pulse of the second bit of the output control signal is generated. as well as A sensing amplification circuit, configured to sense and amplify the latched data based on an output control signal to drive output data; The output control signal is generated from the output control signal.

12. The pipe latch circuit of claim 11, further comprising an output control signal generation circuit configured to generate the output control signal, the output control signal having a pulse generated when at least one of a pulse of a first bit included in the output control signal or a pulse of a second bit included in the output control signal is generated.

13. The pipe latch circuit as described in claim 11, wherein, The first data latch circuit performs an inverted buffer on the input data to generate inverted input data. When the pulse of the first bit of the input control signal is generated, the inverted input data is latched to the third node. When the pulse of the first bit of the output control signal is generated, the inverted input data latched to the third node is output as inverted latched data.

14. The pipe latch circuit as described in claim 13, wherein, The second data latch circuit performs an inverted buffering of the input data to generate the inverted input data. When the pulse of the second bit of the input control signal is generated, the inverted input data is latched to the fourth node, and when the pulse of the second bit of the output control signal is generated, the inverted input data latched to the fourth node is output as the inverted latched data.

15. The pipe latch circuit as described in claim 11, wherein, When the level of the latched data is set to be one level higher than the level of the inverted latched data, the sensing amplifier circuit drives the latched data to a driving voltage and drives the inverted latched data to a ground voltage, wherein the higher level is a preset sensing level or a level higher than the preset sensing level.

16. The pipe latch circuit as claimed in claim 11, wherein, When the level of the inverted latched data is set to be one level higher than the level of the latched data, the sensing amplifier circuit drives the inverted latched data to a driving voltage and drives the latched data to a ground voltage, wherein the higher level is a preset sensing level or a level higher than the preset sensing level.

17. The pipe latch circuit as claimed in claim 11, wherein, When the pulses of the output control signal are generated, the sensing amplifier circuit senses and amplifies the latched data and the inverted latched data.

18. The pipeline latch circuit of claim 11, further comprising a data driving circuit configured to drive the output data based on the latched data and the inverted latched data when a pulse of an inverted output control signal generated by inverting and buffering the output control signal is generated.

19. The pipe latch circuit as described in claim 18, wherein, The data driving circuit generates a pull-up signal based on the inverted output control signal and the latched data, generates a pull-down signal based on the inverted output control signal and the inverted latched data, and drives the output data based on the pull-up signal and the pull-down signal.

20. A method for performing a continuous data output operation, comprising: Input data and inverted input data are latched based on an input control signal comprising multiple bits, and the latched input data is output as latched data based on an output control signal comprising multiple bits, and the latched inverted input data is output as inverted latched data. The latched data and the inverted latched data are sensed and amplified based on the output control signal; as well as The output data is driven based on the latched data, the inverted latched data, and the output control signal; The output control signal is generated from the output control signal.

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