Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. Epitaxial regions can be formed in particular locations on a semiconductor wafer and have particular asymmetric characteristics, such as a direction of slope or tilt, an angle of slope or tilt, and / or other asymmetric characteristics. The asymmetric epitaxial regions can be formed using various plasma-based fin-etching techniques described herein. The particular asymmetric characteristics can increase a metal landing footprint in the particular locations on the semiconductor wafer (e.g., preferred particular locations on a semiconductor substrate) to reduce contact resistance between the epitaxial regions and associated conductive structures formed to the epitaxial regions. This can increase performance of the semiconductor devices, reduce a rate and / or likelihood of defect formation, and / or increase yield of the semiconductor devices, among other examples.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to the epitaxial region of semiconductor devices. Background Technology

[0002] Fin-based transistors are three-dimensional structures, such as fin field-effect transistors (FFETs) and nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, and nanoribbon transistors), which include channel regions extending above a semiconductor substrate that is a three-dimensional structure. A gate structure, configured to control the flow of charge carriers within the channel regions, wraps around the fins of the semiconductor material. As an example, in a fin field-effect transistor, the gate structure wraps around three sides of the fins (i.e., the channel regions), thereby increasing control over the channel regions (i.e., switching the fin field-effect transistor). As another example, in a nanostructure transistor, the gate structure wraps around multiple channel regions in the fin structure, such that the gate structure surrounds each channel region. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a semiconductor device, comprising forming a plurality of fin structures in a substrate of a semiconductor wafer in a device region of the semiconductor wafer; and forming a merged epitaxial region on the fin structures, wherein the merged epitaxial region includes a first epitaxial region and a second epitaxial region, the first epitaxial region and the second epitaxial region being connected in at least a portion of the first epitaxial region and at least a portion of the second epitaxial region, wherein the first epitaxial region is closer to the outer edge of the semiconductor wafer than the second epitaxial region, and wherein the height of the top surface of the first epitaxial region is greater than the height of the top surface of the second epitaxial region.

[0004] This disclosure provides a method for manufacturing a semiconductor device, comprising forming a plurality of fin structures in a substrate of a semiconductor wafer in a device region of the semiconductor wafer, wherein the fin structures include a first fin structure; and a second fin structure adjacent to the first fin structure and closer to the center of the semiconductor wafer relative to the first fin structure; forming spacer layers on a plurality of tops and a plurality of sidewalls of the fin structures; etching the fin structures, wherein etching the fin structures forms first fin sidewall spacers and second fin sidewall spacers, the second fin sidewall spacers being located on the opposite side of the first fin structure; and after etching the fin structures, forming merged source / drain regions on the first fin structure and the second fin structure, wherein because the height of the first fin sidewall spacers is greater than the height of the second fin sidewall spacers, the merged source / drain regions are inclined toward the center of the semiconductor wafer.

[0005] This disclosure provides a semiconductor device including a merged epitaxial region and a non-merged epitaxial region, wherein the merged epitaxial region is inclined toward the non-merged epitaxial region, and wherein the non-merged epitaxial region is inclined toward the merged epitaxial region. Attached Figure Description

[0006] The embodiments of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure.

[0007] Figure 1A as well as Figure 1B A schematic diagram illustrating an exemplary environment in which the systems and / or methods described in this disclosure may be implemented.

[0008] Figure 2 This is a schematic diagram of an exemplary semiconductor wafer and an exemplary device area of ​​the semiconductor wafer as described in this disclosure.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J as well as Figure 4KA schematic diagram illustrating an exemplary embodiment described in this disclosure.

[0010] Figure 5 This is a schematic diagram of another exemplary device region of a semiconductor wafer described in this disclosure.

[0011] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B as well as Figure 8C A schematic diagram illustrating an exemplary embodiment described in this disclosure.

[0012] Figure 9 As described in this disclosure Figures 1A-1B A schematic diagram of an exemplary element of one or more devices.

[0013] Figure 10 , Figure 11 as well as Figure 12 This is a schematic diagram of an exemplary process for forming a semiconductor device as described in this disclosure.

[0014] The reference numerals in the attached figures are explained as follows: 100: Environment 102: Depositioning station 104: Exposure machine 106: Developing machine 108: Etching machine 110: Leveling machine 112: Electroplating machine 114: Wafer / Die Transfer Equipment 116: Process Chamber 118: Plasma Supply System 120: Disk 122: Focusing Ring 124: Sheath 126: Air Inlet 128: Exhaust port 130: Vacuum pump 132: Flow path 134: Internal Plasma Source 136: External Plasma Source 138a: Radio frequency source 138b: Radio frequency source 200: Semiconductor wafer 200a: Quadrant 200b: Quadrant 200c: Quadrant 200d: Quadrant 202: Device Area 204: Substrate 206: Fin structure 206a: Fin structure 206b: Fin structure 206c: Fin structure 208: Hybrid fin structure 208a: Hybrid fin structure 208b: Hybrid fin structure 208c: Hybrid fin structure 210: Shallow trench isolation zone 212: Dummy Gate Structure 214: Gate dielectric layer 216: Gate electrode layer 218: Hard mask layer 220: Source / Drain Region 300: Example 302: Hard mask layer 304: Dielectric layer 306: Low dielectric constant dielectric material layer 308: High dielectric constant dielectric material layer 400: Example 402: Sealing spacer layer 404: Block spacer layer 406: Spacer layer 406a / 406b / 406c: Fin sidewall spacers 406d / 406e / 406f: Fin sidewall spacers 408a: The first part of the photoresist layer 408b: The second part of the photoresist layer 410: Ions 412: Groove 414: Direction 416: Size 418: Size 420: Extensional area 420a: Extensional region 420b: Extensional region 420c: Extensional region 422: Merge the outer extension area 424: Merge Regions 426a: terminal 426b: terminal 428a: Side view 428b: Side view 430: Size 432: Size 434: Size 436: Size 438: Size 440: Size 442: Size 444: Size 446: Size 500: Device Area 502: Direction 600: Example 602: Contact Etching Stop Layer 604: Interlayer dielectric layer 606: Opening 608: Gate structure 610: High dielectric constant dielectric layer 612: Work Function Adjustment Layer 614: Metal Electrode Structure 700: Example 702: Opening 704: Conductive Structure 706: Suspension Area 802: Power 804: Bias 806: Distance 808: Angle 810: Distance 812: Angle 900: Device 910: Bus 920: Processor 930: Memory 940: Input element 950: Output element 960: Communication Components 1000: Manufacturing Process 1010: Square 1020: Square 1100: Manufacturing Process 1110: Square 1120: Square 1130: Square 1140: Box 1200: Process 1210: Square 1220: Square AA: Section BB: Cross-section P1: First power setting P2: Second power setting V1: First non-zero bias setting V2: Second non-zero bias setting Detailed Implementation

[0015] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0016] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0017] As semiconductor manufacturing nodes advance (e.g., reducing the linewidth of optical lithography patterning and making epitaxial regions smaller), achieving electrical contact with epitaxial regions in semiconductor devices becomes increasingly difficult because the available area for electrical contact with epitaxial regions via conductive structures (e.g., source / drain contacts or MDs) is reduced. Reducing the area of ​​electrical contact can lead to increased contact resistance and decreased device performance. Furthermore, the reduced area of ​​electrical contact can create voids and / or other types of discontinuities between the conductive structures and the epitaxial regions, increasing defects and reducing semiconductor device yield.

[0018] Some embodiments described in this disclosure provide techniques and apparatuses for forming multiple asymmetric epitaxial regions at specific locations on a semiconductor wafer. As described in this disclosure, the epitaxial regions can be formed at specific locations on the semiconductor wafer and have specific asymmetric characteristics, such as the direction of slope or tilt, the angle of slope or tilt, and / or other asymmetric characteristics. The asymmetric epitaxial regions can be formed using various plasma-based fin structure etching techniques described in this disclosure. Specific asymmetric characteristics can increase the metal landing coverage at specific locations on the semiconductor wafer (e.g., preferably optimized locations on a semiconductor substrate) to reduce the contact resistance between the epitaxial region and the associated conductive structure formed to the epitaxial region. This can increase the performance of the semiconductor device, reduce the rate and / or likelihood of defect formation, and / or increase the yield of the semiconductor device, among other examples.

[0019] Figure 1A as well as Figure 1B A schematic diagram illustrating an exemplary environment in which the systems and / or methods described in this disclosure can be implemented. For example... Figure 1A As illustrated, environment 100 may include multiple semiconductor process tools 102, 104, 106, 108, 110, 112, and wafer / die transfer tool 114. The multiple semiconductor process tools 102, 104, 106, 108, 110, and 112 may include deposition tool 102, exposure tool 104, developing tool 106, etching tool 108, planarization tool 110, electroplating tool 112, and / or other types of semiconductor process tools. The tools included in the exemplary environment 100 may be found in other examples such as semiconductor cleanrooms, semiconductor foundries, semiconductor processing facilities, and / or semiconductor manufacturing facilities.

[0020] The deposition equipment 102 is a semiconductor deposition equipment that includes a semiconductor process chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition equipment 102 includes a spin coating equipment capable of depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition equipment 102 includes a chemical vapor deposition (CVD) equipment, such as a plasma-enhanced chemical vapor deposition (PECVD) equipment, a high-density plasma chemical vapor deposition (HDP-CVD) equipment, a sub-atmospheric chemical vapor deposition (SACVD) equipment, a low-pressure chemical vapor deposition (LPCVD) equipment, an atomic layer deposition (ALD) equipment, a plasma-enhanced atomic layer deposition (PEALD) equipment, or other types of chemical vapor deposition equipment. In some embodiments, the deposition equipment 102 includes a physical vapor deposition (PVD) equipment, such as a sputtering equipment or other types of physical vapor deposition (PVD) equipment. In some embodiments, deposition stage 102 includes an epitaxial stage configured to form multiple films and / or multiple regions by epitaxial growth. In some embodiments, exemplary environment 100 includes a variety of deposition stages 102.

[0021] Exposure equipment 104 is a semiconductor manufacturing process equipment capable of exposing a photoresist layer to a radiation source, such as ultraviolet light (UV) (e.g., deep ultraviolet light, extreme ultraviolet light, and / or similar UV sources), X-ray, electron beam, and / or similar radiation sources. Exposure equipment 104 exposes the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include a pattern forming one or more semiconductor device layers, a pattern forming a structure of one or more semiconductor devices, a pattern etching various portions of a semiconductor device, and / or similar patterns. In some embodiments, exposure equipment 104 includes a scanner, a stepper, or a similar type of exposure equipment.

[0022] The developing unit 106 is a semiconductor processing unit capable of developing a photoresist layer that has been exposed to a radiation source, in order to develop a pattern transferred from the exposure unit 104 to the photoresist layer. In some embodiments, the developing unit 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing unit 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing unit 106 develops the pattern by using a chemical developer to dissolve either the exposed or unexposed portions of the photoresist layer.

[0023] Etching machine 108 is a semiconductor manufacturing process machine capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching machine 108 may include a wet etching machine, a dry etching machine, and / or similar etching machines. In some embodiments, etching machine 108 includes a chamber filled with etchant, in which a substrate is placed for a specific period of time to remove a specific number of portions of the substrate. In some embodiments, etching machine 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gases to etch one or more portions isotropically or directionally.

[0024] Planarization equipment 110 is a semiconductor process equipment capable of polishing or planarizing various film layers on wafers or semiconductor devices. For example, planarization equipment 110 may include a chemical mechanical planarization (CMP) equipment and / or other types of planarization equipment capable of polishing or planarizing film layers on the surface of deposited or electroplated materials. Planarization equipment 110 can use a combination of chemical and mechanical forces (e.g., chemical etching and abrasive polishing) to polish or planarize the surface of the semiconductor device. Planarization equipment 110 can use abrasives and corrosive chemical abrasive slurries combined with polishing pads and retaining rings (e.g., typically larger than the diameter of the semiconductor device). The polishing pads and semiconductor device can be pressed together by a dynamic polishing head and held in position by the retaining rings. The dynamic polishing head can rotate on different axes of rotation to remove material and plan any irregularities in the topography of the semiconductor device, making the semiconductor device flat or planar.

[0025] Electroplating machine 112 is a semiconductor manufacturing process machine capable of electroplating one or more metals onto a substrate (e.g., a wafer, a semiconductor device, and / or a similar substrate) or a portion thereof. For example, electroplating machine 112 may include copper electroplating apparatus, aluminum electroplating apparatus, nickel electroplating apparatus, tin electroplating apparatus, compound material or alloy (e.g., tin-silver, tin-lead, and / or similar materials) electroplating apparatus, and / or one or more other types of conductive materials, metals, and / or similar materials electroplating apparatus.

[0026] The wafer / die transfer machine 114 includes mobile machinery, robotic arms, trams or railcars, overhead hoist transfer (OHT) systems, automated material handling systems (AMHS), and / or other types of machines configured to transfer substrates and / or semiconductor devices between semiconductor process machines 102, 104, 106, 108, 110, and 112; configured to transfer substrates and / or semiconductor devices between multiple process chambers of the same semiconductor process machine; and / or configured to transfer substrates and / or semiconductor devices to and from other locations, such as wafer racks, storage rooms, or other locations. In some embodiments, the wafer / die transfer machine 114 may be a programmed device configured to travel a specific path and / or operate semi-automatically or automatically. In some embodiments, the semiconductor process environment 100 includes multiple wafer / die transfer machines 114.

[0027] The wafer / die transfer station 114 may be included in a cluster station or other type of station containing multiple process chambers, and may be configured to transfer substrates and / or semiconductor devices between multiple process chambers; configured to transfer substrates and / or semiconductor devices between a process chamber and a buffer; configured to transfer substrates and / or semiconductor devices between a process chamber and an intermediary station such as an equipment front end module (EFEM); and / or configured to transfer substrates and / or semiconductor devices between a process chamber and a transfer carrier (e.g., a front opening unified pod (FOUP)), and other examples. In some embodiments, the wafer / die transfer station 114 may be included in a multi-chamber (or cluster) configuration of the deposition station 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation reactions, and / or other types of contaminants or byproducts from the substrate and / or semiconductor device) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, as described in this disclosure, the wafer / die transfer station 114 is configured to transfer substrates and / or semiconductor devices between multiple process chambers of the deposition station 102 without disrupting or removing the vacuum (or at least a partial vacuum) between the multiple process chambers and / or between multiple process operations in the deposition station 102.

[0028] Figure 1B This is a cross-sectional schematic diagram of a plasma-based etching machine 108. The plasma-based etching machine 108 includes dry etching machine types that use ions to etch or remove multiple portions formed on a semiconductor wafer or multiple films / structures. In some embodiments, the plasma-based etching machine 108 is a plasma etching machine for etching multiple metals on a semiconductor wafer. In some embodiments, the plasma-based etching machine 108 is a decoupled plasma source (DPS) machine, an inductively coupled plasma (ICP) machine, a transformer coupled plasma (TCP) machine, or other types of plasma etching machines.

[0029] like Figure 1BThe illustrated plasma-based etching apparatus 108 includes a process chamber 116. The process chamber 116 includes a hermetically sealed chamber, allowing it to be pressurized (e.g., pressurized to a vacuum or partial vacuum). In some embodiments, the process chamber 116 is sized to accommodate wafers of a specific size, such as 200 mm wafers. In other embodiments, the process chamber 116 is sized to accommodate semiconductor wafers of various sizes, such as 150 mm, 200 mm, 300 mm, and / or other sizes. The plasma-based etching apparatus 108 includes a plasma supply system 118 configured to generate and supply plasma to the process chamber 116.

[0030] A chuck 120 is included in a process chamber 116. The chuck 120 is configured to support and hold a semiconductor wafer within the process chamber 116. The chuck 120 includes an electrostatic chuck (e-chuck or ESC) or other type of chuck (e.g., a vacuum chuck), configured to grip and / or hold the semiconductor wafer within the process chamber 116 during semiconductor wafer fabrication (e.g., during plasma etching). In embodiments where the chuck 120 includes an electrostatic chuck, the chuck 120 is configured to generate an electrostatic attraction between the chuck 120 and the semiconductor wafer based on a voltage applied to the chuck 120. Furthermore, voltage can be supplied to the chuck 120 from a power supply. The voltage generates an electrostatic attraction capable of holding the semiconductor wafer to the chuck 120.

[0031] The size and shape of the chuck 120 may depend on the size and shape of the semiconductor wafer to be processed in the plasma-based etching apparatus 108. For example, the chuck 120 may be circular and capable of supporting all or part of a circular semiconductor wafer. In some embodiments, the chuck 120 is made of one or more materials that are resistant to abrasion and / or corrosion caused by the materials used to generate the plasma, and said materials can generate an attractive force between the chuck 120 and the semiconductor wafer. For example, the chuck 120 may be made of a metal, such as aluminum, stainless steel, or other suitable materials.

[0032] A focus ring 122 may be included in the process chamber 116. The focus ring 122 (also referred to as an edge ring or single ring) comprises an annular structure located around a portion of the chuck 120. The focus ring 122 is configured to focus plasma onto the semiconductor wafer on the chuck 120 within the process chamber 116 by orienting (or reorienting) at least a portion of the plasma toward the semiconductor wafer. In this way, the focus ring 122 can increase electrical and plasma fluid uniformity within the process chamber 116. In some embodiments, a voltage is applied to the focus ring 122 (e.g., from a power supply) such that the focus ring 122 provides electrical and plasma uniformity. The size and shape of the focus ring 122 may depend on the size and shape of the semiconductor wafer to be processed in the plasma-dominant etching apparatus 108. For example, the focus ring 122 may be circular and may include an opening that allows the focus ring 122 to surround the semiconductor wafer on the chuck 120. In some embodiments, the focusing ring 122 is made of one or more materials that can resist wear and / or corrosion caused by the materials used to generate plasma, and said materials can provide electrical and plasma uniformity for the semiconductor wafer. For example, the focusing ring 122 may be made of metal, such as aluminum, stainless steel, and / or other suitable materials.

[0033] During plasma operation of a semiconductor wafer in a plasma-based etching apparatus 108, a bias voltage can be applied to the chuck 120 to generate an electric field between the semiconductor wafer and the plasma in the process chamber 116. The bias voltage may include a negative bias voltage, which will cause an excess of positively charged ions in the plasma layer above the semiconductor wafer. This dense layer of positively charged ions is called a sheath 124, and may also be referred to as a plasma sheath, electrostatic sheath, or Debye sheath. The bias voltage can be used to control the flow rate and direction of ions in the plasma within the process chamber 116 to adjust the etching characteristics of the plasma.

[0034] The plasma supply system 118 may include a process gas source to provide a gas flow (e.g., argon or other types of gas flow) to the process chamber 116. The plasma supply system 118 may provide plasma and gas flow to the process chamber 116 via an inlet port 126 on a first side (e.g., the top side). The plasma and gas flow are removed from the process chamber 116 via an exhaust port (or outlet port) 128 on the opposite side (e.g., the bottom side). The plasma-dominant etching stage 108 includes a vacuum pump 130 to facilitate the generation of a flow path 132 for the plasma and gas flow between the inlet port 126 and the exhaust port 128. For example, and as... Figure 1B As illustrated in the example, flow path 132 begins at inlet 126, extends outward within process chamber 116 and flows around chuck 120 and focusing ring 122, and flows downward below chuck 120 toward exhaust port 128. Vacuum pump 130 may be further configured to control the pressure within process chamber 116 and to generate a vacuum (or partial vacuum) within process chamber 116.

[0035] as Figure 1B As further illustrated, the plasma supply system 118 includes an inner plasma source 134 and an outer plasma source 136. The inner plasma source 134 and the outer plasma source 136 each contain independently controllable plasma sources, and their combination is configured to control and shape the plasma within the process chamber 116. For example, power, voltage, and / or other parameters can be independently configured to supply plasma to the inner plasma source 134 and the outer plasma source 136 to the process chamber 116, such that the plasma contains a specific electric field distribution, a specific ion composition and / or ion distribution, and / or a specific ion bombardment direction or angle, and other examples, such that the intensity of the plasma in a specific region of the process chamber 116 is greater than the intensity of the plasma in other regions of the process chamber 116.

[0036] Internal plasma source 134 and external plasma source 136 are connected to radio frequency (RF) sources 138a and 138b, respectively. RF sources 138a and 138b may be referred to as biased RF sources because they are configured to provide or supply radio frequency or alternating current to internal plasma source 134 and external plasma source 136, respectively, to bias them. Internal plasma source 134 and / or external plasma source 136 can be biased to increase or decrease the strength of the attraction between ions in the plasma, which can be used to increase or decrease the etch rate (or etch rate distribution) of the semiconductor wafer. RF sources 138a and 138b may each be electrically grounded and may each contain an RF power supply or other power source capable of operating within a suitable frequency range (such as approximately 10 MHz). 6 Hertz) to approximately 30 MHz or approximately 300 MHz to approximately 300 GHz (10 9 Other examples include devices that generate and provide / supply radio frequency current (Hertz).

[0037] To generate plasma, radio frequency (RF) sources 138a and 138b can each provide RF or AC power to the inner plasma source 134 and the outer plasma source 136, respectively. The RF or AC power can pass through and / or along the coiled conductors of the inner plasma source 134 and the outer plasma source 136, generating a time-varying electromagnetic field through electromagnetic induction. This time-varying electromagnetic field generates an electromotive force, which energizes the electron-containing gas flow entering the process chamber 116, thereby forming plasma.

[0038] Figure 1A as well as Figure 1B The number and configuration of devices shown are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or different configurations. Figure 1A and / or Figure 1B The device configuration is shown in the illustration. Furthermore... Figure 1A and / or Figure 1B The two or more devices shown can be implemented within a single device, or Figure 1A and / or Figure 1B The single device illustrated may be implemented in multiple distributed devices. Additionally or alternatively, the device combination of environment 100 (e.g., one or more devices) may perform one or more functions described herein that are performed by another device combination of environment 100.

[0039] Figure 2This is a schematic diagram of an exemplary semiconductor wafer 200 and an exemplary device region 202 of the semiconductor wafer 200 as described in this disclosure. The semiconductor wafer 200 may comprise a circular / round semiconductor wafer having a diameter of approximately 200 mm, approximately 300 mm, or other examples such as 450 mm. The semiconductor wafer 200 may also be replaced by any polygonal, square, rectangular, arc-shaped, or other non-circular workpiece, such as a polygonal substrate.

[0040] Semiconductor wafer 200 may be logically divided or partitioned into multiple quadrants, including quadrants 200a, 200b, 200c, and 200d. Each quadrant comprises a portion of the surface area of ​​the top surface of semiconductor wafer 200. Furthermore, each quadrant extends between approximately the center of semiconductor wafer 200 and an edge (e.g., an outer edge) of semiconductor wafer 200. In other embodiments, semiconductor wafer 200 may be divided or partitioned into subsets of other configurations.

[0041] One or more quadrants of a semiconductor wafer 200 may contain one or more device regions 202. Figure 2 The exemplary device region 202 illustrated is located in quadrant 200a. Device region 202 may include or be included in one or more semiconductor devices, integrated circuits, system-on-chips (SoCs), and / or other semiconductor-based electrical devices. Semiconductor devices may include, for example, memory devices, processors, logic devices, diodes, semiconductor lasers, and / or ring oscillators (ROs), and other examples. Ring oscillators include multiple logic devices (e.g., NOT gates) and may be included on semiconductor wafer 200, for example, for testing at various stages of the fabrication of other semiconductor devices on semiconductor wafer 200.

[0042] The semiconductor device in device region 202 may include one or more transistors or other devices. The transistors may include fin-based transistors, such as fin field-effect transistors (finFETs), nanostructure transistors, and / or other types of transistors. In some embodiments, device region 202 includes a p-type metal oxide semiconductor (PMOS) region, an n-type metal oxide semiconductor (NMOS) region, a complementary metal oxide semiconductor (CMOS) region, and / or other types of device regions.

[0043] Device area 202 includes substrate 204. Substrate 204 includes silicon (Si) substrate, substrate formed of silicon-containing material, III-V compound semiconductor material substrate such as gallium arsenide (GaAs), silicon on insulator (SOI) substrate, germanium (Ge) substrate, silicon-germanium (SiGe) substrate, or other types of semiconductor substrate.

[0044] Fin structure 206 is contained above (and / or extends above) the substrate 204 of device region 202. Fin structure 206 provides an active region for forming one or more devices (e.g., fin-dominated transistors) and may therefore be referred to as an active fin structure. In some embodiments, fin structure 206 comprises silicon (Si) material or other elemental semiconductor materials such as germanium (Ge). In some embodiments, fin structure 206 comprises alloy semiconductor materials such as silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium arsenide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof. In some embodiments, fin structure 206 is doped using n-type and / or p-type dopants.

[0045] The fin structure 206 is manufactured using suitable semiconductor fabrication techniques, such as masking, photolithography, and / or etching processes, among other examples. As an example, the fin structure 206 can be formed by etching a portion of a substrate 204 to create multiple recesses in the substrate 204. The recesses can then be filled using a recessed or etch-back insulating material.

[0046] In some embodiments, hybrid fin structures 208 are included between fin structures 206 in an alternating configuration. Hybrid fin structures 208 may also be referred to as h-fins, dummy fins, and / or non-active fins, among other examples. Hybrid fin structures 208 include fin structures extending in a first direction and approximately parallel to the fin structures 206. In some embodiments, hybrid fin structures 208 are included between two fin structures 206 and extend approximately the same length as the two fin structures 206.

[0047] Hybrid fin structure 208 is configured to provide electrical insulation between one or more structures and / or elements included in device region 202. In some embodiments, hybrid fin structure 208 is configured to provide electrical insulation between two or more fin structures 206 (e.g., two or more active fin structures). In some embodiments, hybrid fin structure 208 is configured to provide electrical insulation between two or more source / drain regions in device region 202. In some embodiments, hybrid fin structure 208 is configured to provide electrical insulation between two or more gate structures or between two or more portions of a gate structure. In some embodiments, hybrid fin structure 208 is configured to provide electrical insulation between the source / drain regions and the gate structure.

[0048] The hybrid fin structure 208 described in this disclosure includes multiple types of dielectric materials. The hybrid fin structure 208 may include one or more low-k dielectric materials (e.g., silicon oxide (SiO2)). x ) and / or silicon nitride (Si x N y Other examples include (e.g., hafnium oxide (HfO)) and one or more high-k dielectric materials (e.g., hafnium oxide (HfO)). x A combination of (and / or other high dielectric constant dielectric materials).

[0049] A shallow trench isolation (STI) region 210 is contained within the substrate 204 and between the fin structure 206 and the hybrid fin structure 208. The shallow trench isolation region 210 can be formed by etching back onto the fin structure 206 and an insulating layer formed on the substrate 204. However, other fabrication techniques for the shallow trench isolation region 210 can also be used. The shallow trench isolation region 210 electrically isolates adjacent active regions in the fin structure 206 and / or adjacent portions of the fin structure 206 and the hybrid fin structure 208. The shallow trench isolation region 210 may contain a dielectric material, such as silicon oxide (SiO2). x ), silicon nitride (Si x N yThe shallow trench isolation region 210 may contain a multilayer structure, such as having one or more liner layers. The materials used may include silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low dielectric constant dielectric materials, and / or other suitable insulating materials.

[0050] A dummy gate structure 212 (or multiple dummy gate structures 212) is included above (e.g., approximately perpendicular to) the fin structure 206 in the device region 202. The dummy gate structure 212 engages with the fin structure 206 on three or more sides. Furthermore, the dummy gate structure 212 may be included above a hybrid fin structure 208 and may engage with the hybrid fin structure 208 on three or more sides. Figure 2 In the described example, the dummy gate structure 212 includes a gate dielectric layer 214, a gate electrode layer 216, and a hard mask layer 218. In some embodiments, the dummy gate structure 212 further includes a capping layer, one or more spacer layers, and / or other suitable film layers. The various film layers of the dummy gate structure 212 can be formed by suitable deposition techniques and patterned by suitable photolithography and etching techniques.

[0051] The term "dummy" as used in this disclosure refers to a sacrificial structure that will be removed at a later stage and replaced by another structure, such as a high-dielectric-constant dielectric and a metal gate structure in a replacement gate process. A replacement gate process refers to fabricating the gate structure at a later stage of the overall gate fabrication process. Therefore, Figure 2 The configuration of device region 202 shown may include an intermediate configuration and may perform additional semiconductor process operations on device region 202 to further process device region 202.

[0052] The gate dielectric layer 214 may include a dielectric oxide layer. The dielectric oxide layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate electrode layer 216 may include a polysilicon material or other suitable materials. The gate electrode layer 216 may be formed by a suitable deposition process, such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), and other examples. The hard mask layer 218 may include any material suitable for patterning the gate electrode layer 216 on the substrate 204 in specific parts / sizes.

[0053] In some embodiments, various film layers of the dummy gate structure 212 are first deposited as blanket layers. Then, the blanket layers are patterned by a process including optical lithography and etching, multiple portions of the blanket layers are removed, and the remaining portions of the blanket layers are retained over the shallow trench isolation region 210, over the fin structure 206, and / or over the hybrid fin structure 208 to form the dummy gate structure 212.

[0054] Source / drain regions 220 are positioned in the opposite region of fin structure 206 to dummy gate structure 212 (e.g., in the opposite region of active fin structure). Source / drain regions 220 comprise multiple regions in device region 202 that will be formed during one or more epitaxial growth operations, and thus the source / drain regions may be referred to as epitaxial regions. The source / drain regions in device region 202 comprise silicon (Si) having one or more dopants, such as those having p-type materials (e.g., boron (B) or germanium (Ge) and other examples), n-type materials (e.g., phosphorus (P) or arsenic (As) and / or other types of dopants). Therefore, device region 202 may include p-type metal-oxide-semiconductor (PMOS) transistors containing p-type source / drain regions, n-type metal-oxide-semiconductor (NMOS) transistors containing n-type source / drain regions, and / or other types of transistors.

[0055] Some source / drain regions may be shared among various transistors in device region 202. In some embodiments, the various source / drain regions may be connected or coupled together, such that the fin-dominant transistor in device region 202 is implemented as two functional transistors. For example, two functional transistors can be implemented if adjacent source / drain regions (e.g., relative to opposite source / drain regions) are electrically connected, such as by epitaxially grown coalescing source / drain regions (e.g., adjacent source / drain regions on the opposite side of the dummy gate structure 212 are coalesced). The coalesced adjacent source / drain regions are referred to in this disclosure as merged epitaxial regions and merged source / drain regions. Other configurations in other examples may implement other numbers of functional transistors.

[0056] Figure 2 Further illustrations show the cross-sections used in subsequent figures, including... Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H , Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E, Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C as well as Figure 7D . Figures 3A to 7D for Figure 2 The diagram illustrates schematic cross-sectional views of various portions of device region 202 and / or other device regions of semiconductor wafer 200, corresponding to various process stages in which fin-based transistors are formed in device region 202 and / or other device regions of semiconductor wafer 200. Section AA is in a plane along the channels in fin structures 206 between opposing source / drain regions 220. Section BB is in a plane perpendicular to section AA, spanning multiple fin structures 206 and multiple hybrid fin structures 208 in the multiple source / drain regions 220. For clarity, these reference sections are labeled with reference numerals in subsequent figures. In some figures, reference numerals for some illustrated elements or components may be omitted for ease of drawing to avoid obscuring other elements or components.

[0057] As mentioned above, Figure 2 This is provided as an example. Other examples may be provided. Figure 2 The descriptions are different.

[0058] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G as well as Figure 3H This is a schematic diagram of an exemplary embodiment 300 described in this disclosure. Exemplary embodiment 300 includes examples of fin structures 206 and hybrid fin structures 208 formed in device regions 202 (and / or other device regions) of a semiconductor wafer 200. Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G as well as Figure 3H From Figure 2 The section BB of the device area 202 is drawn in perspective.

[0059] Transfer to Figure 3AExample embodiment 300 includes semiconductor process operations involving the formation of transistors in and / or on substrate 204 in device region 202. Deposition equipment 102 uses chemical vapor deposition (CVD), physical vapor deposition (PVD), spin-coating, and / or techniques described above. Figure 1A-Figure 1B Other related deposition techniques form a hard mask layer 302 on the substrate 204. The hard mask layer 302 contains a material that exhibits etch selectivity to a specific type of etchant, and this material differs from the material of the substrate 204 to facilitate etching of the substrate 204. For example, the hard mask layer 302 may contain silicon nitride (Si). x N y ) or other suitable materials, and the substrate 204 may contain silicon oxide (SiO2) x (or other suitable materials.)

[0060] like Figure 3B As illustrated, fin structure 206 is formed in substrate 204 within device region 202. In some embodiments, a pattern in a photoresist layer is used to form fin structure 206. In these embodiments, deposition stage 102 forms a photoresist layer on hard mask layer 302. Exposure stage 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development stage 106 develops and removes multiple portions of the photoresist layer to expose the pattern. Etching stage 108 etches into hard mask layer 302 to form a pattern in hard mask layer 302. Substrate 204 is then etched based on the pattern in hard mask layer 302 to form fin structure 206 in a portion of substrate 204. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques. In some embodiments, a photoresist removal stage removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0061] like Figure 3C As illustrated, dielectric layer 304 is formed above and / or on substrate 204 and above and / or on fin structure 206. Deposition equipment 102 uses chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or techniques described above. Figures 1A-1B Other related deposition techniques are used to deposit the dielectric layer 304. In some embodiments, the dielectric layer 304 is compliantly deposited on the fin structure 206 such that the dielectric layer 304 is formed on the top and sidewalls of the fin structure 206.

[0062] like Figure 3DAs illustrated, a low-dielectric-constant dielectric material layer 306 is formed in multiple grooves within the dielectric layer 304 between the fin structures 206. The deposition stage 102 utilizes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or techniques described above. Figure 1A-Figure 1B Other related deposition techniques are used to deposit the low-dielectric-constant dielectric material layer 306. In some embodiments, the low-dielectric-constant dielectric material layer 306 is formed in a dielectric merging operation, in which multiple separated portions of the low-dielectric-constant dielectric material layer 306 are merged together.

[0063] like Figure 3E As illustrated, the low-dielectric-constant dielectric material layer 306 is etched back such that the height of the top surface of the low-dielectric-constant dielectric material layer 306 is lower than the height of the top surface of the dielectric layer 304. The etching apparatus 108 uses plasma etching, wet chemical etching, and / or other types of etching techniques to etch the low-dielectric-constant dielectric material layer 306. In some embodiments, the low-dielectric-constant dielectric material layer 306 is etched back such that the height of the top surface of the low-dielectric-constant dielectric material layer 306 is greater than the height of the top surface of the hard mask layer 302 and greater than the height of the top surface of the fin structure 206. In some embodiments, the low-dielectric-constant dielectric material layer 306 is etched back such that the height of the top surface of the low-dielectric-constant dielectric material layer 306 is less than the height of the top surface of the hard mask layer 302 and greater than the height of the top surface of the fin structure 206. In some embodiments, the low dielectric constant dielectric material layer 306 is etched back such that the height of the top surface of the low dielectric constant dielectric material layer 306 is less than the height of the top surface of the hard mask layer 302 and less than the height of the top surface of the fin structure 206.

[0064] like Figure 3F As illustrated, a high-dielectric-constant dielectric material layer 308 is formed in multiple grooves within the dielectric layer 304 between the fin structures 206. Furthermore, the high-dielectric-constant dielectric material layer 308 is formed on a low-dielectric-constant dielectric material layer 306. The deposition stage 102 uses chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or techniques described above. Figures 1A-1B Other related deposition techniques are used to deposit the high dielectric constant dielectric material layer 308. In some embodiments, the high dielectric constant dielectric material layer 308 is formed in a dielectric merging operation, in which multiple separated portions of the high dielectric constant dielectric material layer 308 are merged together.

[0065] like Figure 3GAs illustrated, a high-dielectric-constant dielectric material layer 308 is etched to form a hybrid fin structure 208. Each hybrid fin structure 208 includes a portion of a low-dielectric-constant dielectric material layer 306 and a portion of a high-dielectric-constant dielectric material layer 308. The high-dielectric-constant dielectric material layer 308 is etched such that the height of its top surface is less than the height of the top surface of the dielectric layer 304. The etching apparatus 108 uses plasma etching, wet chemical etching, and / or other types of etching techniques to etch the high-dielectric-constant dielectric material layer 308.

[0066] In some embodiments, the high-dielectric-constant dielectric material layer 308 is etched back such that the height of the top surface of the high-dielectric-constant dielectric material layer 308 is greater than the height of the top surface of the hard mask layer 302 and greater than the height of the top surface of the fin structure 206. In some embodiments, the high-dielectric-constant dielectric material layer 308 is etched back such that the height of the top surface of the high-dielectric-constant dielectric material layer 308 is less than the height of the top surface of the hard mask layer 302 and greater than the height of the top surface of the fin structure 206. In some embodiments, the high-dielectric-constant dielectric material layer 308 is etched back such that the height of the top surface of the high-dielectric-constant dielectric material layer 308 is less than the height of the top surface of the hard mask layer 302 and less than the height of the top surface of the fin structure 206.

[0067] like Figure 3H As illustrated, the dielectric layer 304 is etched to form shallow trench isolation regions 210 between adjacent fin structures 206 and / or between adjacent fin structures 206 and hybrid fin structure pairs 208. This exposes multiple portions of the fin structures 206, allowing epitaxial regions (or source / drain regions) to be formed on the exposed portions of the fin structures 206 above the shallow trench isolation regions 210.

[0068] In some embodiments, the pattern in the photoresist layer is used to etch the dielectric layer 304 to form the shallow trench isolation region 210. In these embodiments, a deposition stage 102 forms the photoresist layer on the dielectric layer 304 and on a high-dielectric-constant dielectric material layer 308. An exposure stage 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development stage 106 develops and removes multiple portions of the photoresist layer to expose the pattern. An etching stage 108 etches the dielectric layer 304 based on the pattern to form the shallow trench isolation region 210. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques. In some embodiments, a photoresist removal stage removes the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique based on the pattern to form the shallow trench isolation region 210. In some embodiments, the dielectric layer 304 is etched based on the etch selectivity between the material of the dielectric layer 304 and the material of the high dielectric constant dielectric material layer 308 (e.g., there is no hard mask or photoresist layer on the high dielectric constant dielectric material layer 308).

[0069] As mentioned above, Figures 3A to 3H This is provided as an example. Other examples may be provided. Figures 3A to 3H The descriptions are different.

[0070] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J as well as Figure 4K This is a schematic diagram of an exemplary embodiment 400 described in this disclosure. Exemplary embodiment 400 includes an example of forming an asymmetric epitaxial region (or asymmetric source / drain region) in the source / drain region 220 of the device region 202 (and / or other device region) of the semiconductor wafer 200. Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J as well as Figure 4K From Figure 2 Drawing from one or more sectional perspectives, including from Figure 2 AA perspective view of section 202 of the central device area and from Figure 2 Cross-sectional perspective (BB) of the central device region 202. In some embodiments, in conjunction with... Figures 3A to 3D After the described fin formation process, operations related to exemplary embodiment 400 are performed.

[0071] like Figure 4A As illustrated, a dummy gate structure 212 is formed in device region 202. The dummy gate structure 212 is formed and included above fin structure 206 and surrounds the sides of fin structure 206, such that the dummy gate structure 212 surrounds fin structure 206 on at least three sides. Similarly, the dummy gate structure 212 is formed and included above hybrid fin structure 208 and surrounds the sides of hybrid fin structure 208, such that the dummy gate structure 212 surrounds hybrid fin structure 208 on at least three sides.

[0072] The dummy gate structure 212 is a placeholder formed as an actual gate structure (e.g., a replacement high-k gate structure or a metal gate structure) that will be formed as a transistor contained in device region 202. The dummy gate structure 212 can be formed as part of a replacement gate process, allowing other film layers and / or other structures to be formed prior to the formation of the replacement gate structure.

[0073] The dummy gate structure 212 includes a plurality of gate dielectric layers 214, a plurality of gate electrode layers 216, and a plurality of hard mask layers 218. The gate dielectric layers 214 may include a dielectric oxide layer. As an example, each of the gate dielectric layers 214 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods (e.g., by deposition equipment 102). Each of the gate electrode layers 216 may each include a polysilicon material or one or more other suitable films. For example, the gate electrode layers 216 may be formed by suitable deposition processes (e.g., by deposition equipment 102), such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), etc. Each of the hard mask layers 218 may each include any material suitable for patterning the gate electrode layers 216 to a specific size / characteristic. Examples include silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof, etc. The hard mask layer 218 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other deposition techniques (e.g., by deposition stage 102).

[0074] like Figure 4AAs further illustrated, a sealing spacer layer 402 is included on multiple sidewalls of the dummy gate structure 212. The sealing spacer layer 402 can be deposited compliantly (e.g., via deposition equipment 102) and can comprise silicon oxycarbide (SiOC), nitrogen-free silicon oxycarbide (SiOC), or other suitable materials. The sealing spacer layer 402 can be formed using other exemplary deposition techniques such as atomic layer deposition (ALD), in which various types of precursor gases containing silicon (Si) and carbon (C) are sequentially supplied in multiple cycles to form the sealing spacer layer 402.

[0075] like Figure 4A As further illustrated, a bulk spacer layer 404 may be formed on the sealing spacer layer 402. The bulk spacer layer 404 may be formed of a material similar to that of the sealing spacer layer 402. However, the formation of the bulk spacer layer 404 may not require the plasma surface treatment used on the sealing spacer layer 402. Furthermore, the bulk spacer layer 404 may be formed to a greater thickness than the sealing spacer layer 402.

[0076] In some embodiments, the sealing spacer layer 402 and the bulk spacer layer 404 are compliantly deposited (e.g., by means of deposition unit 102) on the dummy gate structure 212 and on the fin structure 206. The sealing spacer layer 402 and the bulk spacer layer 404 are then patterned (e.g., by means of deposition unit 102, exposure unit 104, and development unit 106) and etched (e.g., by means of etching unit 108) to remove the sealing spacer layer 402 and the bulk spacer layer 404 from the plurality of tops of the dummy gate structure 212, from the fin structure 206, and from the self-mixing fin structure 208.

[0077] like Figure 4B as well as Figure 4C As illustrated, spacer layer 406 is formed on fin structure 206, on hybrid fin structure 208, and on shallow trench isolation region 210. Spacer layer 406 comprises silicon oxycarbide (SiOC), nitrogen-free silicon oxycarbide (SiOC), and silicon nitride (SiO2). x N y ), and / or other suitable materials. In some embodiments, spacer layer 406 comprises multiple spacer layers. In some embodiments, spacer layer 406 and one or more layers of sealing spacer layer 402 and / or bulk spacer layer 404 are the same spacer layer(s). Deposition stage 102 uses chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other techniques described above. Figure 1A-Figure 1B Other related deposition techniques were used to deposit spacer layer 406. For example... Figure 4B as well as Figure 4C As illustrated, spacer layer 406 is compliantly deposited on multiple top surfaces and multiple sidewalls of fin structure 206, multiple top surfaces and multiple sidewalls of hybrid fin structure 208, and multiple top surfaces of shallow trench isolation region 210.

[0078] like Figure 4D As illustrated, multiple portions of the spacer layer 406 are removed from the top surface of the fin structure 206 and the top surface of the hybrid fin structure 208. The etching apparatus 108 can remove multiple portions of the spacer layer 406. This etching operation, which removes multiple portions of the spacer layer 406, can be referred to as a fin top opening operation and can be performed to facilitate the etching of the fin structure 206.

[0079] Subsequently, a photoresist layer is formed over and / or on multiple portions of the device region 202 to cover or protect multiple portions of the device region 202 during the etching of the fin structures 206. The deposition stage 102 may use spin coating or other suitable deposition techniques to form the photoresist layer. The photoresist layer may be formed such that multiple fin structures 206 are located between a first portion 408a and a second portion 408b of the photoresist layer. Therefore, the fin structures 206 located between the first portion 408a and the second portion 408b of the photoresist layer are exposed to facilitate the etching of the fin structures 206.

[0080] like Figure 4E As illustrated, a semiconductor wafer 200 can be placed in the process chamber 116 of a plasma-based etching machine 108 to etch a fin structure 206 located between a first portion 408a and a second portion 408b of a photoresist layer. The semiconductor wafer 200 is placed above and / or on a chuck 120 such that a focusing ring 122 surrounds the semiconductor wafer 200. The plasma-based etching machine 108 performs a plasma-based etching operation to etch the fin structure 206 while the semiconductor wafer 200 is located in the process chamber 116. The plasma-based etching operation is also known as a strained source / drain (SSD) etching operation.

[0081] To perform the plasma-based etching operation, a plasma supply system 118 generates and supplies plasma to the process chamber 116 via an inlet 126. The plasma in the process chamber 116 is supplied to the semiconductor wafer 200 via a flow path 132, facilitated by the use of a bias voltage on a chuck 120. The bias voltage on the chuck 120 causes ions in the plasma sheath 124 to bombard the fin structure 206, thereby causing ion etching of the fin structure 206.

[0082] like Figure 4F as well as Figure 4G As illustrated, ions 410 in the plasma etch the fin structure 206. In some embodiments, the fin structure 206 is etched such that the top surface of the fin structure 206 is approximately at the same height as the top of the shallow trench isolation region 210. In some embodiments, the fin structure 206 is etched such that the top surface of the fin structure 206 is recessed, wherein a groove 412 in the fin structure 206 extends to below the height of the top of the shallow trench isolation region 210.

[0083] Ions 410 also etch spacer layer 406. The remaining portion of spacer layer 406 on the sidewalls of fin structure 206 forms fin sidewall spacers. For example, fin sidewall spacer 406a is formed on a first side of fin structure 206a, while fin sidewall spacer 406b is formed on a second (opposite) side of fin structure 206a. As another example, fin sidewall spacer 406c is formed on a first side of fin structure 206b, while fin sidewall spacer 406d is formed on a second (opposite) side of fin structure 206b. As another example, fin sidewall spacer 406e is formed on a first side of fin structure 206c, while fin sidewall spacer 406f is formed on a second (opposite) side of fin structure 206c.

[0084] Fin structures 206a and 206b comprise adjacent fin structures. Fin structures 206a and 206b are adjacent to one side of the hybrid fin structure 208, which is opposite to one side of the hybrid fin structure 208 adjacent to fin structure 206c. Fin structures 206a and 206b are closer to the edge of the semiconductor wafer 200 than fin structure 206c. Fin structure 206a is closer to the edge of the semiconductor wafer 200 than fin structure 206b. Therefore, fin structure 206c is closer to the center of the semiconductor wafer 200 than fin structures 206a and 206b, while fin structure 206b is closer to the center of the semiconductor wafer 200 than fin structure 206a. The center of the semiconductor wafer 200 is relative to the area shown in the diagram. Figure 4F The location or orientation of the structure in the central device area 202 is indicated by reference numeral 414.

[0085] like Figure 4GAs further illustrated, plasma ions 410 polymerize on the sidewalls of the first portion 408a of the photoresist layer, which passivates the first portion 408a. This passivation reduces the etching rate of plasma ions 410 on the sidewalls of the first portion 408a located and / or near the photoresist layer (e.g., relative to the sidewalls of the first portion 408a farther from the photoresist layer). The reduced etching rate of plasma ions on the sidewalls of the first portion 408a located and / or near the photoresist layer results in uneven etching of the fin structure 206a, which in turn causes uneven height of the fin structure 206a (or uneven grooves 412 in the top surface). In particular, due to the reduced etching rate, the fin structure 206a has a greater height on the side of the fin structure 206a facing or toward the sidewall of the first portion 408a of the photoresist layer.

[0086] Therefore, the height of the fin sidewall spacer 406a is greater than the height of the fin sidewall spacer 406b. The exemplary dimension 416 includes the difference between the heights of the fin sidewall spacers 406a and 406b. In some embodiments, the difference between the heights of the fin sidewall spacers 406a and 406b ranges from about 2 nanometers to about 5 nanometers to facilitate and / or enable the formation of the asymmetric epitaxial region discussed in this disclosure. However, other values ​​of the difference between the heights of the fin sidewall spacers 406a and 406b are also within the scope of this disclosure. Furthermore, the height of the fin sidewall spacer 406a may be greater than the heights of the fin sidewall spacers 406c and 406d because the etch rate located at or near the fin structure 206b is greater than the etch rate located at or near the sidewalls of the first portion 408a of the photoresist layer.

[0087] like Figure 4G As further illustrated, plasma ions 410 aggregate on the sidewalls of the second portion 408b of the photoresist layer, which passivates the second portion 408b of the photoresist layer. This passivation reduces the etching rate of plasma ions 410 on the sidewalls of the second portion 408b located and / or near the photoresist layer (e.g., the etching rate relative to the sidewalls of the second portion 408b far from the photoresist layer). The reduced etching rate of plasma ions on the sidewalls of the second portion 408b located and / or near the photoresist layer results in uneven etching of the fin structure 206c, which in turn causes uneven height of the fin structure 206c (or uneven grooves 412 in the top surface). In particular, due to the reduced etching rate, the fin structure 206c has a larger height on the side of the fin structure 206c facing or toward the sidewall of the second portion 408b of the photoresist layer.

[0088] Therefore, the height of the fin sidewall spacer 406f is greater than the height of the fin sidewall spacer 406e. The exemplary dimension 418 includes the difference between the heights of the fin sidewall spacers 406f and 406e. In some embodiments, the difference between the heights of the fin sidewall spacers 406f and 406e ranges from about 2 nanometers to about 5 nanometers to facilitate and / or enable the formation of the asymmetric epitaxial region discussed in this disclosure. However, other values ​​of the difference between the heights of the fin sidewall spacers 406f and 406e are also within the scope of this disclosure.

[0089] In some embodiments, the hybrid fin structure 208a (located between the merged epitaxial region 422 (and fin structures 206a and 206b) and the epitaxial region 420c (and fin structure 206c)) may be slightly etched during the etching operation to etch fin structures 206a, fin structure 206b, and fin structure 206c. This may result in a reduction in the height of the hybrid fin structure 208a. A first portion 408a of the photoresist layer is formed above and / or on the hybrid fin structure 208b, which is adjacent to the opposite side of the merged epitaxial region 422 (and the opposite side of fin structures 206a and fin structure 206b) of the hybrid fin structure 208a. Similarly, a second portion 408b of the photoresist layer is formed above and / or on the hybrid fin structure 208c, which is adjacent to the opposite side of the merged epitaxial region 420c (which is the hybrid fin structure 208a) and the opposite side of the fin structure 206c. After the etching operation, the heights of the hybrid fin structures 208b and 208c may be greater than the height of the hybrid fin structure 208a because the photoresist layer protects the hybrid fin structures 208b and 208c during the etching operations of the fin structures 206a, 206b, and 206c.

[0090] like Figure 4H as well as Figure 4IThe diagram illustrates an epitaxial region 420 formed in a recess in a device region 202 of a semiconductor wafer 200 above and / or on fin structures 206 (e.g., above and / or on fin structures 206a, 206b, and 206c). The deposition stage 102 forms the epitaxial region 420 during an epitaxial operation, wherein a film of epitaxial material is deposited on the fin structures 206a, 206b, and 206c, such that the film of the epitaxial region 420 is formed by epitaxial growth of a specific crystal arrangement. The epitaxial region 420 includes a top surface adjacent to and at least partially below and / or below one or more dummy gate structures 212. Furthermore, the epitaxial region 420 extends at least partially above the top surface of the fin structures 206. The epitaxial region 420 corresponds to the source / drain region of the transistor contained in the device region 202.

[0091] like Figure 4I As illustrated, an extensional region 420a is formed on fin structure 206a, an extensional region 420b is formed on fin structure 206b, and an extensional region 420c is formed on fin structure 206c. Extensional region 420a extends into a groove 412 in the top surface of fin structure 206a, extends above fin sidewall spacers 406a and 406b, and extends laterally outward beyond the sidewall of fin structure 206a. Extensional region 420b extends into a groove 412 in the top surface of fin structure 206b, extends above fin sidewall spacers 406c and 406d, and extends laterally outward beyond the sidewall of fin structure 206b. The extension region 420c extends into the groove 412 in the top surface of the fin structure 206c, extends above the fin sidewall spacers 406e and 406f, and extends laterally outward beyond the sidewall of the fin structure 206c.

[0092] like Figure 4I As illustrated, extensional regions 420a and 420b are joined and / or connected in a merging region 424 within a portion of extensional region 420a and a portion of extensional region 420b. This results in the formation of a merged extensional region 422 above and / or on fin structures 206a and 206b. The merged extensional region 422 may also be referred to as a two-fin (2F) extensional region. Extensional region 420c is not merged with other extensional regions and is referred to as a non-merged extensional region, a single extensional region, a one-fin (1F) extensional region, or a standalone extensional region.

[0093] like Figure 4IAs further illustrated, the merged epitaxial region 422 is slanted or tilted toward the epitaxial region 420c (e.g., the non-merged epitaxial region). Furthermore, the merged epitaxial region 422 is slanted or tilted toward the center of the semiconductor wafer 200 and away from the edge of the semiconductor wafer 200. This slant or tilt is caused by the difference in height between the epitaxial regions 420a and 420b that form the merged epitaxial region 422. Specifically, because the height of epitaxial region 420a is greater than the height of epitaxial region 420b, the merged epitaxial region 422 is slanted or tilted toward the epitaxial region 420c (and toward the center of the semiconductor wafer 200). Due to the uneven etching of the fin structure 206a and the fact that the height of the fin sidewall spacers 406a is greater than the height of the fin sidewall spacers 406b, 406c, and 406d, the height of epitaxial region 420a is greater than the height of epitaxial region 420b.

[0094] like Figure 4I As further illustrated, the epitaxial region 420c (e.g., a non-merged epitaxial region) is skewed or tilted toward the merged epitaxial region 422. Furthermore, the epitaxial region 420c is skewed or tilted toward the edge of the semiconductor wafer 200 and away from the center of the semiconductor wafer 200. This skewness or tilt is caused by uneven etching of the fin structure 206c and by the fact that the height of the fin sidewall spacers 406f is greater than the height of the fin sidewall spacers 406e. In some embodiments, the epitaxial region 420c is skewed or tilted toward the merged epitaxial region 422 (and toward the edge of the semiconductor wafer 200) because the end (or edge) 426a of the epitaxial region 420c toward the merged epitaxial region 422 has a lower positioning relative to the opposite end (or edge) 426b of the epitaxial region 420c toward the center of the semiconductor wafer 200. In some embodiments, the epitaxial region 420c is skewed or tilted toward the merged epitaxial region 422 (and toward the edge of the semiconductor wafer 200) because the side 428a of the epitaxial region 420c toward the merged epitaxial region 422 and adjacent to the fin sidewall spacer 406e has a lower positioning relative to the opposite side 428b of the epitaxial region 420c toward the center of the semiconductor wafer 200 and adjacent to the fin sidewall spacer 406f.

[0095] The material used to form the epitaxial region 420 (e.g., silicon (Si), gallium (Ga), or other types of semiconductor materials) may be doped with p-type dopants (e.g., dopants containing electron acceptor atoms that generate holes in the material), n-type dopants (e.g., dopants containing electron donor atoms that generate free electrons in the material), and / or other types of dopants. This material may be doped by adding impurities (e.g., p-type dopants, n-type dopants) to the source gas used during the epitaxial operation. Examples of p-type dopants that can be used in the epitaxial operation include boron (B) or germanium (Ge). The material of the formed p-type source / drain region includes silicon-germanium (Si). x Ge 1-x (where x can range from approximately 0 to approximately 100) or other types of p-type doped semiconductor materials. Examples of n-type dopants that can be used in epitaxial operations include phosphorus (P) or arsenic (As), among others. The material for the formed n-type source / drain regions includes silicon phosphide (Si). x P y (or other types of n-type doped semiconductor materials.)

[0096] In some embodiments, the hybrid fin structure 208a (located between the merged epitaxial region 422 (and fin structures 206a and 206b) and the epitaxial region 420c (and fin structure 206c)) may be slightly etched during the etching operation to etch fin structures 206a, fin structure 206b, and fin structure 206c. This may result in a reduction in the height of the hybrid fin structure 208a. A first portion 408a of the photoresist layer is formed above and / or on the hybrid fin structure 208b, which is adjacent to the opposite side of the merged epitaxial region 422 (and the opposite side of fin structures 206a and fin structure 206b) of the hybrid fin structure 208a. Similarly, a second portion 408b of the photoresist layer is formed above and / or on the hybrid fin structure 208c, which is adjacent to the opposite side of the merged epitaxial region 420c (which is the hybrid fin structure 208a) and the opposite side of the fin structure 206c. After the etching operation, the heights of the hybrid fin structures 208b and 208c may be greater than the height of the hybrid fin structure 208a because the photoresist layer protects the hybrid fin structures 208b and 208c during the etching operations of the fin structures 206a, 206b, and 206c.

[0097] In some embodiments, it is possible to perform on the topic of Figure 4E , Figure 4F , Figure 4G , Figure 4H as well as Figure 4IThe operations and / or techniques described herein are used to form p-type and n-type epitaxial regions in device region 202 in multiple epitaxial operations. In these embodiments, the p-type and n-type epitaxial regions can be formed using different deposition chambers of the same deposition stage 102 (e.g., a cluster stage) or using different deposition stages 102. The sub-region in device region 202 where the p-type epitaxial region will be formed can be masked by photoresist, which can be performed regarding Figure 4E , Figure 4F , Figure 4G , Figure 4H as well as Figure 4I The operations and / or techniques described herein, for forming an n-type epitaxial region in another sub-region of device region 202, allow for the removal of a photoresist layer. The sub-region where the n-type epitaxial region has been formed can be masked by the photoresist, and can perform operations related to... Figure 4E , Figure 4F , Figure 4G , Figure 4H as well as Figure 4I The operations and / or techniques described herein are used to form a p-type epitaxial region in a subregion of device region 202. Alternatively, the p-type epitaxial region may be formed before the n-type epitaxial region is formed.

[0098] P-type and n-type epitaxial regions can be formed using different precursors and different dopants. For p-type epitaxial regions, precursors such as germanium (Ge) precursors (e.g., GeH4 or other germanium precursors) and silicon precursors (e.g., silane (SiH4), dichlorosilane (DCS), or other silicon precursors) can be used in combination with etchants (e.g., hydrogen chloride (HCl) or other etchants), carrier gases (e.g., hydrogen (H2) or other carrier gases), and p-type dopant sources (e.g., boron dopant sources (e.g., B...). x H y (or other boron dopant sources). For n-type epitaxial regions, precursors such as silicon precursors (e.g., silane (SiH4), dichlorosilane (DCS), or other silicon precursors) can be used in combination with etchants (e.g., hydrogen chloride (HCl) or other etchants), carrier gases (e.g., hydrogen (H2) or other carrier gases), and n-type dopant sources (e.g., phosphorus dopant sources (e.g., PH3)). x (or other phosphorus dopant sources), arsenic dopant sources (e.g., AsH) x (or other arsenic dopant sources).

[0099] Figure 4J The various dimensions of the extensional region 420 and the various dimensions of the fin sidewall spacers 406a, 406b, 406c, 406d, 406e, and 406f are shown. For example... Figure 4JAs illustrated, exemplary dimension 430 includes the difference between the height of the top surface of the epitaxial region 420a of the merged epitaxial region 422 and the height of the top surface of the epitaxial region 420b of the merged epitaxial region 422. In some embodiments, this difference ranges from about 2 nanometers to about 10 nanometers to facilitate the tilting of the merged epitaxial region 422. However, other values ​​of this difference are also within the scope of this disclosure. Figure 4J As illustrated, exemplary dimension 432 includes an angle of skew or tilt of the merging extensional region 422. In some embodiments, this angle ranges from about 1 degree to about 30 degrees to facilitate tilting of the merging extensional region 422. However, other values ​​of this angle are also within the scope of this disclosure.

[0100] like Figure 4J As illustrated, exemplary dimension 434 includes the width of the merged epitaxial region 422. In some embodiments, the width of the merged epitaxial region 422 ranges from approximately 40 nanometers to approximately 70 nanometers to provide sufficient landing area for the conductive structure to be formed to the merged epitaxial region 422. However, other values ​​for this width are also within the scope of this disclosure. Figure 4J As illustrated, exemplary dimension 436 includes the difference between the height of the top surface of the epitaxial region 420a and the height of the top surface of the adjacent hybrid fin structure 208. In some embodiments, the height of the top surface of the epitaxial region 420a is greater than the height of the top surface of the adjacent hybrid fin structure 208. In some embodiments, this difference ranges from about 0.5 nanometers to about 5 nanometers. However, other values ​​of this difference are also within the scope of this disclosure.

[0101] like Figure 4J As illustrated, exemplary dimension 438 includes the difference between the height of the top surface of the epitaxial region 420b and the height of the top surface of the adjacent hybrid fin structure 208. In some embodiments, the height of the top surface of the epitaxial region 420b is less than the height of the top surface of the adjacent hybrid fin structure 208. In some embodiments, this difference ranges from approximately 2.5 nanometers to approximately 15 nanometers. However, other values ​​of this difference are also within the scope of this disclosure.

[0102] like Figure 4J As illustrated, the exemplary dimension 440 includes an angle of skewness or tilt of the epitaxial region 420c. In some embodiments, this angle ranges from approximately 1 degree to approximately 18 degrees to facilitate the tilting of the epitaxial region 420c. However, other values ​​of this angle are also within the scope of this disclosure. Figure 4JAs illustrated, exemplary dimension 442 includes the width of epitaxial region 420c. In some embodiments, the width of epitaxial region 420c ranges from approximately 20 nanometers to approximately 45 nanometers to provide sufficient landing area for the conductive structure to be formed to epitaxial region 420c. However, other values ​​for this width are also within the scope of this disclosure. In some embodiments, the ratio of the combined width of epitaxial region 422 to the width of epitaxial region 420c ranges from approximately 9:8 to approximately 3.5:1. However, other values ​​for this ratio are also within the scope of this disclosure.

[0103] like Figure 4J As illustrated, the height of the top surface of the epitaxial region 420c can be greater than the height of the top surface of the adjacent hybrid fin structure 208. The exemplary dimension 444 includes the difference between the height of the top surface of the epitaxial region 420c and the height of the top surface of the adjacent hybrid fin structure 208. In some embodiments, this height difference ranges from about 1 nanometer to about 10 nanometers. However, other values ​​of this difference are also within the scope of this disclosure. Furthermore, the height of the top surface of the epitaxial region 420c can be greater than the height of the top surface of the epitaxial region 420a, and can be greater than the height of the top surface of the epitaxial region 420b.

[0104] like Figure 4J As illustrated, the exemplary dimension 446 includes the height difference between the height of the hybrid fin structure 208a between the merged epitaxial region 422 (and fin structures 206a and 206b) and the epitaxial region 420c (and fin structure 206c), and the height of the hybrid fin structures 208b and 208c. The heights of the hybrid fin structures 208b and 208c may be greater than the height of the hybrid fin structure 208a. This height difference may be due to minor etching of the hybrid fin structure 208a that may occur during the etching operations of etching the fin structures 206a, 206b, and 206c.

[0105] Figure 4K A three-dimensional perspective view of the device region 202 of the semiconductor wafer 200 after the formation of the epitaxial region 420 is shown. (See diagram below.) Figure 4K As illustrated, the merged epitaxial region 422 is included on a plurality of fin structures 206. Epitaxial regions 420c (e.g., non-merged epitaxial regions) are included on a single fin structure 206c. Epitaxial regions 420 are formed on one or more sides of the dummy gate structure 212.

[0106] As mentioned above, Figures 4A to 4K This is provided as an example. Other examples may be provided. Figures 4A to 4K The descriptions are different.

[0107] Figure 5This is a schematic diagram of another example of a device region 500 of the semiconductor wafer 200 described in this disclosure. Device region 500 may approximate device region 202 and may include similar structures and / or films. However, device region 202 and device region 500 are contained in different quadrants of the semiconductor wafer 200. For example, device region 202 is contained in quadrant 200a, while device region 500 is contained in quadrant 200d. Device region 500 may be contained in or may be included in one or more semiconductor devices, integrated circuits, silicon-on-insulator (SiI) devices, and / or other semiconductor-based electrical devices. Semiconductor devices may include, for example, memory devices, processors, logic devices, diodes, semiconductor lasers, and / or ring oscillators, and other examples.

[0108] Quadrant 200d is the quadrant diagonally opposite to quadrant 200a. Therefore, the skewness or tilt of the epitaxial region in one or more first semiconductor devices (e.g., a first ring oscillator) included in device region 500 may be opposite to the skewness or tilt of the epitaxial region in one or more second semiconductor devices (e.g., a second ring oscillator) included in device region 202.

[0109] As an example, the height of the first epitaxial region 420a in device region 500 can be greater than the height of the first epitaxial region 420b in device region, such that the first merged epitaxial region 422 in device region 500 is skewed or tilted toward the center of semiconductor wafer 200 and away from the edge of semiconductor wafer 200 in quadrant 200d. The center of semiconductor wafer 200 is relative to the area shown in the diagram. Figure 5 The position or orientation of the structure in device region 500 is indicated by reference numeral 502. Conversely, the height of the second epitaxial region 420a in device region 202 can be greater than the height of the second epitaxial region 420b in device region 202, such that the second merged epitaxial region 422 in device region 202 is skewed or tilted toward the center of semiconductor wafer 200 and away from the edge of semiconductor wafer 200 in quadrant 200a. Therefore, the first merged epitaxial region 422 is tilted toward the second merged epitaxial region 422, and the second merged epitaxial region 422 is tilted toward the first merged epitaxial region 422.

[0110] As another example, the asymmetric structure of the first epitaxial region 420c in device region 500 causes the first epitaxial region 420c to be skewed or tilted away from the center of semiconductor wafer 200 and toward the edge of semiconductor wafer 200 in quadrant 200d. Conversely, the asymmetric structure of the second epitaxial region 420c in device region 202 causes the second epitaxial region 420c to be skewed or tilted away from the center of semiconductor wafer 200 and toward the edge of semiconductor wafer 200 in quadrant 200a. Therefore, the first epitaxial region 420c is skewed away from the second epitaxial region 420c and toward the first merged epitaxial region 422, while the second epitaxial region 420c is skewed away from the first epitaxial region 420c and toward the second merged epitaxial region 422.

[0111] Shape, skewness, tilt, height, and / or other parameters result in a specific configuration of asymmetric epitaxial regions in each quadrant of the semiconductor wafer 200, enabling an increase in the landing area (e.g., contact surface area) of the contact structures formed to the asymmetric epitaxial regions. This reduces contact resistance in multiple quadrants of the semiconductor wafer 200, while simultaneously allowing for an increase in semiconductor device density on the semiconductor wafer 200.

[0112] As mentioned above, Figure 5 This is provided as an example. Other examples may be provided. Figure 5 The descriptions are different.

[0113] Figure 6A , Figure 6B , Figure 6C as well as Figure 6D This is a schematic diagram of an exemplary embodiment 600 described in this disclosure. Exemplary embodiment 600 includes an exemplary dummy gate replacement process, wherein the dummy gate structure 212 is replaced with a high-dielectric-constant gate structure and / or a metal gate structure. Figure 6A , Figure 6B , Figure 6C as well as Figure 6D It is from device region 202 (or other device region, such as device region 500) of semiconductor wafer 200. Figure 2 The mid-section AA plane perspective is used for illustration. In some embodiments, regarding... Figures 4A to 4K After the described extensional region is formed, execution is performed regarding... Figures 6A to 6D The described dummy gate replacement process.

[0114] like Figure 6AAs illustrated, a contact etch stop layer (CESL) 602 is compliantly deposited (e.g., via deposition machine 102) over the epitaxial region 420, over the dummy gate structure 212, and on the sidewalls of the bulk spacer layer 404. The contact etch stop layer 602 provides a mechanism to stop the etching process when forming contacts or vias in the device region 202. The contact etch stop layer can be formed of a dielectric material having a different etch selectivity than adjacent film layers or elements. The contact etch stop layer 602 may contain or be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, the contact etch stop layer 602 may contain or be silicon nitride (Si). x N y Other examples include silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or combinations thereof. The contact etch stop layer 602 can be deposited using deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or other deposition techniques.

[0115] like Figure 6B As illustrated, an interlayer dielectric (ILD) 604 is formed (e.g., via deposition equipment 102) above and / or on the contact etch stop layer 602. The interlayer dielectric 604 fills the area between the dummy gate structures 212 above the epitaxial region 420. The interlayer dielectric 604 is formed to allow a replacement gate structure process to be performed in the device region 202, wherein a metal gate structure is formed to replace the dummy gate structure 212. The interlayer dielectric 604 may be referred to as the zeroth interlayer dielectric (ILD zero; ILD0).

[0116] In some embodiments, an interlayer dielectric layer 604 is formed to a height (or thickness) such that the interlayer dielectric layer 604 covers the dummy gate structure 212. In these embodiments, a subsequent chemical mechanical polishing operation (e.g., performed by a planarization machine 110) is performed to planarize the interlayer dielectric layer 604 such that the top surface of the interlayer dielectric layer 604 is at approximately the same height as the top surface of the dummy gate structure 212. This increases the uniformity of the interlayer dielectric layer 604.

[0117] like Figure 6CAs illustrated, a gate replacement operation (e.g., by means of one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112) is performed to remove the dummy gate structure 212 from device region 202. The removal of the dummy gate structure 212 leaves openings (or recesses) 606 between the bulk spacer layers 404 and between the epitaxial regions 420. The dummy gate structure 212 may be removed in one or more etching operations incorporating plasma etching techniques, which may include wet etching techniques and / or other types of etching techniques.

[0118] like Figure 6D As illustrated, a gate replacement operation continues, wherein deposition stage 102 and / or electroplating stage 112 form a gate structure (e.g., a replacement gate structure) 608 in openings 606 between bulk spacer layers 404 and between epitaxial regions 420. Gate structure 608 may comprise a metal gate structure, a high-dielectric-constant gate structure, or other types of gate structures. Gate structure 608 may comprise an interface layer (not shown), a high-dielectric-constant dielectric layer 610, a work function adjustment layer 612, and a metal electrode structure 614 formed in openings 606 to form gate structure 608. In some embodiments, gate structure 608 may comprise materials and / or films of other compositions.

[0119] As mentioned above, Figures 6A to 6D This is provided as an example. Other examples may be provided. Figures 6A to 6D The descriptions are different.

[0120] Figure 7A , Figure 7B , Figure 7C as well as Figure 7D This is a schematic diagram of an exemplary embodiment 700 described in this disclosure. Exemplary embodiment 700 includes examples of forming conductive structures in device region 202 (or other device region, such as device region 500) of a semiconductor wafer 200. One or more Figure 7A , Figure 7B , Figure 7C as well as Figure 7D From Figure 2 Mid-section AA plane perspective and / or from in Figure 2 The mid-section BB plane perspective is used for drawing.

[0121] like Figure 7A as well as Figure 7BAs illustrated, an opening (or recess) 702 is formed through one or more dielectric layers and reaches the epitaxial region 420. Specifically, a contact etch stop layer 602 and an interlayer dielectric layer 604 are etched between gate structures 608 in device region 202 to form a first opening 702 to the merged epitaxial region 422 (e.g., a merged source / drain region) and a second opening to the epitaxial region 420c (e.g., a non-merged epitaxial region or a non-merged source / drain region). In some embodiments, the opening 702 is formed in a portion of the source / drain region 420 such that a recess extends into a portion of the source / drain region 420.

[0122] In some embodiments, a pattern in the photoresist layer is used to form the opening 702. In these embodiments, a deposition stage 102 forms a photoresist layer on the interlayer dielectric layer 604 and on the gate structure 608. An exposure stage 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development stage 106 develops and removes multiple portions of the photoresist layer to expose the pattern. An etching stage 108 etches the interlayer dielectric layer 604 and the contact etch stop layer 602 based on the pattern to form the opening 702. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques. In some embodiments, a photoresist removal stage removes the remaining portions of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique based on the pattern to form the opening 702.

[0123] like Figure 7C as well as Figure 7D As illustrated, conductive structures 704 (e.g., metal source / drain contacts (MDs)) are formed in openings 702 in device region 202. Specifically, conductive structures 704 are formed above and / or on the merged epitaxial region 422, and another conductive structure 704 is formed above and / or on the epitaxial region 420c. Deposition equipment 102 and / or electroplating equipment 112 utilize chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, and other techniques described above. Figure 1A-Figure 1B The described deposition techniques, and / or other techniques different from those described above, are as follows: Figure 1A-Figure 1B The described deposition technique is used to deposit the conductive structure 704. The deposition apparatus 102 and / or the electroplating apparatus 112 use a conductive material to fill the opening 702 to form the conductive structure 704. The conductive structure 704 includes ruthenium (Ru) metal source / drain contacts, tungsten (W) metal source / drain contacts, cobalt (Co) metal source / drain contacts, or metal source / drain contacts formed of other metals.

[0124] like Figure 7D As further illustrated, a conductive structure 704 is formed in the merged epitaxial region 422, such that the conductive structure 704 extends laterally above the fin structures 206a and 206b, and above the epitaxial regions 420a and 420b. Furthermore, the skewness or tilt of the merged epitaxial region 422 towards the epitaxial region 420c provides an increased landing area for the conductive structure 704 on the merged epitaxial region 422, because the skewness or tilt of the merged epitaxial region 422 allows an overhang region 706 of the conductive structure 704 to be formed along the side of the merged epitaxial region 422 towards the epitaxial region 420c. The overhang region 706 increases the surface area or contact area between the conductive structure 704 and the merged epitaxial region 422, which reduces the contact resistance between the conductive structure 704 and the merged epitaxial region 422.

[0125] like Figure 7D As further illustrated, the skewness or tilt of the epitaxial region 420c toward the merging epitaxial region 422 provides an increased landing area for the conductive structure 704 on the epitaxial region 420c, because the skewness or tilt of the epitaxial region 420c allows the suspension region 706 of the conductive structure 704 to form along the side of the epitaxial region 420c toward the merging epitaxial region 422. The suspension region 706 increases the surface area or contact area between the conductive structure 704 and the epitaxial region 420c, which reduces the contact resistance between the conductive structure 704 and the epitaxial region 420c.

[0126] As mentioned above, Figures 7A to 7D This is provided as an example. Other examples may be provided. Figures 7A to 7D The descriptions are different.

[0127] Figure 8A , Figure 8B as well as Figure 8C This is a schematic diagram of an exemplary embodiment 800 described in this disclosure. Exemplary embodiment 800 includes a plasma-based etching technique that can be used to form the etched fin structure 206 of the asymmetric epitaxial region described in this disclosure. Regarding... Figures 8A to 8C The plasma-based etching technique described herein can be used in etching equipment 108, such as plasma-based etching equipment 108, in conjunction with one or more other etching techniques to etch the fin structure 206 used to form the asymmetric epitaxial region. Furthermore, regarding... Figures 8A to 8C The plasma-based etching technology described can be compared with... Figures 4E to 4G Used together with / or the operations described elsewhere in this disclosure.

[0128] Figure 8AAn exemplary power setting for the plasma power 802 supplied to the chuck 120 of the plasma-based etching machine 108, and an exemplary bias setting for the bias voltage 804 are illustrated. Figure 8A As illustrated, during the plasma-dominant etching operation of the etched fin structure 206, the amplitude of the power 802 and the amplitude of the bias voltage 804 can be changed or adjusted for one or more time periods.

[0129] like Figure 8A As illustrated, the power 802 of the plasma used for etching the fin structure 206 can be adjusted between a first power setting P1 and a second power setting P2. The power 802 can be adjusted between the first power setting P1 and the second power setting P2 in a periodic and / or aperiodic manner. In some embodiments, the frequency of adjustment or switching between the first power setting P1 and the second power setting P2 is based on the radio frequency pulse duty cycle, which may include duty cycle ranges such as approximately 10% to approximately 30%, approximately 40% to approximately 60%, or approximately 70% to approximately 90%, among other examples.

[0130] like Figure 8A As further illustrated, the amplitude of the second power setting P2 is greater than the amplitude of the first power setting P1. As an example, the power associated with the first power setting P1 can range from approximately 300 watts to approximately 500 watts, while the power associated with the second power setting P2 can range from approximately 1100 watts to approximately 1300 watts. However, other values ​​of the power associated with the first power setting P1, and other values ​​of the power associated with the second power setting P2, are also within the scope of this disclosure.

[0131] Power 802 can be adjusted to a second power setting P2 to increase the plasma intensity. This increases the quantity and / or rate of ions 410 supplied to the semiconductor wafer 200. Power 802 can be adjusted to a first power setting P1 to decrease the plasma intensity. This decreases the quantity and / or rate of ions 410 supplied to the semiconductor wafer 200.

[0132] like Figure 8AAs further illustrated, the bias voltage 804 applied to the chuck 120 in the etched fin structure 206 can be adjusted between a first non-zero bias voltage setting V1 and a second non-zero bias voltage setting V2 (e.g., relative to an "on" bias voltage as a non-zero bias voltage and a "off" bias voltage as a zero bias voltage). The bias voltage 804 can be adjusted between the first non-zero bias voltage setting V1 and the second non-zero bias voltage setting V2 in a periodic and / or aperiodic manner. In some embodiments, the frequency of adjustment or switching between the first non-zero bias voltage setting V1 and the second non-zero bias voltage setting V2 is based on the RF pulse duty cycle, which may include duty cycle ranges such as approximately 10% to approximately 30%, approximately 40% to approximately 60%, or approximately 70% to approximately 90%, among other examples.

[0133] like Figure 8A As further illustrated, the amplitude of the first non-zero bias setting V1 is greater than the amplitude of the second non-zero bias setting V2. As an example, the voltage associated with the first non-zero bias setting V1 can range from approximately 200 volts to approximately 400 volts, while the voltage associated with the second non-zero bias setting V2 can range from approximately 100 volts to approximately 150 volts. However, other values ​​of the voltage associated with the first non-zero bias setting V1, and other values ​​of the voltage associated with the second non-zero bias setting V2, are also within the scope of this disclosure.

[0134] The bias voltage 804 can be adjusted to a first non-zero bias voltage V1 to increase the directionality of ion 410 movement in the process chamber 116. Specifically, the bias voltage 804 can be adjusted to the first non-zero bias voltage V1 to increase the verticality of ion 410 movement in the process chamber 116, resulting in more anisotropic movement of ions 410. This increases the etching rate of the fin structure 206 on the semiconductor wafer 200 and reduces the aggregation (i.e., passivation) of ions 410 on the sidewalls of the first portion 408a and the second portion 408b of the photoresist layer. The bias voltage 804 can be adjusted to a second non-zero bias voltage V2 to reduce the directionality of ion 410 movement in the process chamber 116. Specifically, the bias voltage 804 can be adjusted to the second non-zero bias voltage V2 to increase the isotropic movement of ions 410 in the process chamber 116. This reduces the etching rate of the fin structure 206 on the semiconductor wafer 200 and increases the polymerization (i.e., passivation) of ions 410 on the sidewalls of the first portion 408a and the second portion 408b of the photoresist layer.

[0135] While providing power to the semiconductor wafer 200, the plasma-based etching stage 108 can alternate or switch between combinations of settings in two or more plasma-based etching operations for etching fin structures 206. The two or more combinations may include, for example, a first combination including a first power setting P1 and a first non-zero bias V1, and a second combination including a second power setting P2 and a second non-zero bias V2. In some embodiments, the duration (or pulse) used in the first combination may be greater than the duration (or pulse) used in the second combination, which can provide an increased etching rate and reduced passivation. In some embodiments, the duration (or pulse) used in the second combination may be greater than the duration (or pulse) used in the first combination, which can provide a reduced etching rate and increased passivation. In some embodiments, the duration (or pulse) used in the second combination and the duration (or pulse) used in the first combination may be approximately the same duration.

[0136] Alternating between a first combination (including a first power setting P1 and a first non-zero bias V1) and a second combination (including a second power setting P2 and a second non-zero bias V2) results in uneven etching of the fin structure 206, which in turn causes one or more fin sidewall spacers of the fin structure 206 to have different heights. For example, alternating between the first and second combinations may result in a difference between the height of fin sidewall spacer 406a and the height of fin sidewall spacer 406b (e.g., exemplary dimension 416) (e.g., the height of fin sidewall spacer 406a may be greater than the height of fin sidewall spacer 406b). As another example, alternating between the first and second combinations may result in a difference between the height of fin sidewall spacer 406e and the height of fin sidewall spacer 406f (e.g., exemplary dimension 418) (e.g., the height of fin sidewall spacer 406f may be greater than the height of fin sidewall spacer 406e).

[0137] Specifically, the second combination increases passivation on the sidewalls of the first portion 408a of the photoresist layer. Passivation may reduce the etch rate of ions 410 on the sidewalls of the fin sidewall spacers 406a near the sidewalls of the first portion 408a of the photoresist layer, relative to the etch rate of ions 410 on the fin sidewall spacers 406b. The first combination increases the directionality of ions 410, which reduces the uniformity of etching and ion coverage. Due to the combination of the reduced etch rate from passivation and the increased directionality of ions 410, the fin sidewall spacers 406b are etched at a faster rate than the fin sidewall spacers 406a.

[0138] Similarly, the second combination can increase passivation on the sidewalls of the second portion 408b of the photoresist layer. Passivation may reduce the etch rate of ions 410 on the fin sidewall spacers 406f near the sidewalls of the second portion 408b of the photoresist layer, relative to the etch rate of ions 410 on the fin sidewall spacers 406e. The first combination can increase the directionality of ions 410, which reduces the uniformity of etching and ion coverage. Due to the combination of the reduced etch rate from passivation and the increased directionality of ions 410, the fin sidewall spacers 406e are etched at a faster rate than the fin sidewall spacers 406f. This results in the height of the fin sidewall spacers 406f being greater than the height of the fin sidewall spacers 406e.

[0139] Figure 8B as well as Figure 8C An illustrative height setting of the focusing ring 122 of a plasma-based etching stage 108 is shown. For example... Figure 8B as well as Figure 8C As illustrated, the directionality or angle of the plasma used to etch the fin structure 206 can be adjusted by adjusting the height of the focusing ring 122 relative to the top surface of the semiconductor wafer 200. This adjustment can be made individually or in conjunction with the top surface of the focusing ring. Figure 8A The plasma setup described herein, combined with / or other techniques, can be used to control the etching direction of the fin structure 206 to form sidewall spacers of different heights on the fin structure 206 (e.g., non-uniform sidewall spacers).

[0140] like Figure 8B As illustrated, the height of the top surface of the focusing ring 122 may be greater than the height of the top surface of the semiconductor wafer 200. The height of the top surface of the focusing ring 122 may be greater than the height of the top surface of the semiconductor wafer 200 by a distance 806. This may cause plasma to be supplied to the semiconductor wafer 200 at an angle 808 (e.g., an outer angle). The distance 806 may be increased to increase the outward direction of the plasma, while the distance 806 may be decreased to decrease the outward direction of the plasma. Furthermore, the angle of the plasma may be larger at or near the edge of the semiconductor wafer 200, and smaller at or near the center of the semiconductor wafer 200, because the plasma flow path 132 flows from the inlet 126 above the center of the semiconductor wafer 200 to the periphery of the edge of the semiconductor wafer 200 (e.g., an inward-to-outward flow path).

[0141] like Figure 8CAs illustrated, the height of the top surface of the focusing ring 122 may be less than the height of the top surface of the semiconductor wafer 200. The height of the top surface of the focusing ring 122 may be less than the height of the top surface of the semiconductor wafer 200 at a distance 810. This may cause plasma to be supplied to the semiconductor wafer 200 at an angle 812 (e.g., an interior angle). The distance 810 may be increased to increase the inward direction of the plasma, while the distance 810 may be decreased to decrease the inward direction of the plasma.

[0142] As mentioned above, Figures 8A to 8C This is provided as an example. Other examples may be provided. Figures 8A to 8C The descriptions are different.

[0143] Figure 9 This is a schematic diagram illustrating exemplary elements of device 900. In some embodiments, one or more semiconductor process equipment 102, 104, 106, 108, 110, 112, and / or wafer / die transfer equipment 114 may include one or more devices 900 and / or one or more elements of device 900. Figure 9 As illustrated, device 900 may include bus 910, processor 920, memory 930, input element 940, output element 950, and communication element 960.

[0144] Bus 910 includes one or more elements enabling wired and / or wireless communication between components of devices 900. Bus 910 can... Figure 9Two or more elements are coupled together, such as through operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. Processor 920 includes a central processing unit (CPU), graphics processing unit (GPU), microprocessor, controller, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or other types of processing elements. Processor 920 is implemented in hardware, firmware, or a combination of hardware and firmware. In some embodiments, processor 920 includes one or more processors capable of being programmed to perform one or more operations or functions described elsewhere in this disclosure.

[0145] Memory 930 includes volatile and / or non-volatile memory. For example, memory 930 may include random access memory (RAM), read-only memory (ROM), hard disk drive (HDD), and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 930 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., connected via a universal serial bus connection). Memory 930 may be a non-transitory computer-readable medium. Memory 930 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of device 300. In some embodiments, memory 930 includes one or more memories, such as those coupled to one or more processors (e.g., processor 920) via bus 910.

[0146] Input element 940 enables device 900 to receive input, such as user input and / or sensor input. For example, input element 940 may include a touchscreen, keyboard, touchpad, mouse, button, microphone, switch, sensor, global positioning system (GPS) sensor, accelerometer, gyroscope, and / or actuator. Output element 950 enables device 900 to provide output, such as through a display, speaker, and / or light-emitting diodes (LEDs). Communication element 960 enables device 900 to communicate with other devices, such as via wired and / or wireless connections. For example, communication element 960 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0147] Device 900 may perform one or more operations or processes described in this disclosure. For example, a non-transitory computer-readable medium (e.g., memory 930) may store a set of instructions (e.g., one or more instructions or code) that are executed by processor 920. Processor 920 may execute this set of instructions to perform one or more operations or processes described in this disclosure. In some embodiments, this set of instructions executed by one or more processors 920 causes one or more processors 920 and / or device 900 to perform one or more operations or processes described in this disclosure. In some embodiments, hard-wired circuitry may be used in place of or in combination with instructions to perform one or more operations or processes described in this disclosure. Additionally or alternatively, processor 920 may be configured to perform one or more operations or processes described in this disclosure. Therefore, the embodiments described in this disclosure are not limited to any particular combination of hardware circuitry and software.

[0148] Figure 9 The number and arrangement of components shown are provided as examples. Device 900 may include additional components, fewer components, different components, or components with... Figure 9 The illustrated components are configured differently. Additionally or alternatively, a set of components of device 900 (e.g., one or more components) may perform one or more functions described herein that are performed by another set of components of device 900.

[0149] Figure 10This is a flowchart illustrating an exemplary process 1000 related to the formation of the semiconductor device described herein. In some embodiments, Figure 10 One or more process blocks can be executed by one or more semiconductor process equipment (e.g., one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112). Additionally or alternatively, Figure 10 One or more process blocks may be executed by elements of one or more devices 900, such as processor 920, memory 930, input element 940, output element 950, and / or communication element 960.

[0150] like Figure 10 As illustrated, process 1000 may be included in the device region of a semiconductor wafer to form multiple fin structures in the substrate of the semiconductor wafer (box 1010). For example, as described in this disclosure, one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112 may form multiple fin structures (e.g., fin structure 206a and fin structure 206b) in the device region (e.g., device region 202 or device region 500) of the semiconductor wafer 200 in the substrate 204 of the semiconductor wafer 200.

[0151] like Figure 10 As further illustrated, process 1000 may include forming a merged epitaxial region on the fin structure (box 1020). For example, as described in this disclosure, one or more semiconductor process stations 102, 104, 106, 108, 110, and 112 may form a merged epitaxial region 422 on the fin structure. In some embodiments, the merged epitaxial region 422 includes a first epitaxial region (e.g., epitaxial region 420a) and a second epitaxial region (e.g., epitaxial region 420b), the first epitaxial region and the second epitaxial region being connected in at least a portion of the first epitaxial region and at least a portion of the second epitaxial region. In some embodiments, the first epitaxial region is closer to the outer edge of the semiconductor wafer 200 than the second epitaxial region. In some embodiments, the height of the top surface of the first epitaxial region is greater than the height of the top surface of the second epitaxial region.

[0152] Process 1000 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or associated with one or more other processes described elsewhere in this disclosure.

[0153] In a first embodiment, process 1000 includes forming a second fin structure in a substrate and forming a third epitaxial region on the second fin structure within a device region of a semiconductor wafer. The third epitaxial region comprises a single epitaxial region, and the third epitaxial region is closer to the center of the semiconductor wafer relative to a merged epitaxial region. A first end of the third epitaxial region is lower than a second end of the third epitaxial region, and the first end is closer to the merged epitaxial region relative to the second end. In a second embodiment, a hybrid fin structure 208 is formed between the fin structure and the second fin structure, either alone or in conjunction with the first embodiment. The first end of the third epitaxial region is closer to the hybrid fin structure relative to the second end of the third epitaxial region. In a third embodiment, the third epitaxial region is formed, either alone or in conjunction with the first or second embodiment, comprising a third epitaxial region whose top surface height is greater than the top surface height of the hybrid fin structure 208. In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the merged epitaxial region 422 includes a merged epitaxial region 422 such that the height of the top surface of the first epitaxial region is greater than the height of the top surface of the hybrid fin structure 208, and the height of the top surface of the second epitaxial region is less than the height of the top surface of the hybrid fin structure 208.

[0154] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the formation of the third epitaxial region includes forming a third epitaxial region such that the height of the top surface of the third epitaxial region is greater than the height of the top surface of the first epitaxial region. In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, process 1000 includes forming an opening 702 in a dielectric layer (e.g., an interlayer dielectric layer 604) connected to the merged epitaxial region 422, and forming a conductive structure 704 in the opening 702 on the merged epitaxial region 422, the conductive structure 704 including a suspension region 706 on the side of the merged epitaxial region 422 facing the third epitaxial region.

[0155] In a seventh embodiment, forming a conductive structure 704, either alone or in combination with one or more of the first to sixth embodiments, includes forming a conductive structure 704 that extends laterally over the first fin structure. In an eighth embodiment, either alone or in combination with one or more of the first to seventh embodiments, the hybrid fin structure 208 includes a first hybrid fin structure 208a, and process 1000 includes forming a second hybrid fin structure 208b adjacent to the first fin structures 206a and 206b opposite to the first hybrid fin structure 208a, and forming a third hybrid fin structure 208c adjacent to the second fin structure 206c opposite to the first hybrid fin structure 208a, wherein the heights of the second hybrid fin structure 208b and the third hybrid fin structure 208c are greater than the height of the first hybrid fin structure 208a.

[0156] although Figure 10 The diagram illustrates exemplary blocks of process 1000. In some embodiments, process 1000 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in the diagram. Figure 10 The illustrated blocks have different configurations. Alternatively, or as an alternative, two or more blocks in process 1000 can be executed in parallel.

[0157] Figure 11 A flowchart illustrating an exemplary process 1100 associated with forming the semiconductor device described herein. In some embodiments, Figure 11 One or more process blocks can be executed by one or more semiconductor process equipment (e.g., one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112). Alternatively or as an alternative, Figure 11 One or more process blocks may be executed by elements of one or more devices 900, such as processor 920, memory 930, input element 940, output element 950, and / or communication element 960.

[0158] like Figure 11 As illustrated, process 1100 may include forming a plurality of fin structures in the substrate of the semiconductor wafer within a device region of the semiconductor wafer (box 1110). For example, as described in this disclosure, one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112 may form a plurality of fin structures 206 in the substrate 204 of the semiconductor wafer 200 within a device region (e.g., device region 202 or device region 500) of the semiconductor wafer 200. In some embodiments, the fin structure 206 includes a first fin structure 206a and a second fin structure 206b, which is adjacent to the first fin structure 206a and closer to the center of the semiconductor wafer 200 relative to the first fin structure 206a.

[0159] like Figure 11 As further illustrated, process 1100 may include forming spacer layers on a plurality of tops and a plurality of sidewalls of the fin structure (box 1120). For example, as described in this disclosure, one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112 may form spacer layers 406 on a plurality of tops and a plurality of sidewalls of the fin structure.

[0160] like Figure 11As further illustrated, process 1100 may include etching the fin structure (box 1130). For example, as described in this disclosure, one or more semiconductor process stations 102, 104, 106, 108, 110, and 112 may etch the fin structure 206 and form a first fin sidewall spacer (e.g., fin sidewall spacer 406a) and a second fin sidewall spacer (e.g., fin sidewall spacer 406b), the second fin sidewall spacer being located on the opposite side of the first fin structure 206a.

[0161] like Figure 11 As further illustrated, process 1100 may include forming merged source / drain regions on the first fin structure and the second fin structure after etching the fin structure (box 1140). For example, as described in this disclosure, one or more semiconductor process stations 102, 104, 106, 108, 110, and 112 may form merged source / drain regions (e.g., merged epitaxial region 422) on the first fin structure 206a and the second fin structure 206b after etching the fin structure 206. In some embodiments, the merged source / drain regions are tilted toward the center of the semiconductor wafer because the height of the first fin sidewall spacers is greater than the height of the second fin sidewall spacers.

[0162] Process 1100 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or associated with one or more other processes described elsewhere in this disclosure.

[0163] In a first embodiment, the fin structure includes a third fin structure 206c, which is closer to the center of the semiconductor wafer 200 than the second fin structure 206b. Etching the fin structure results in the formation of a third fin sidewall spacer (e.g., fin sidewall spacer 406e) and a fourth fin sidewall spacer (e.g., fin sidewall spacer 406f). The fourth fin sidewall spacer is located on the opposite side of the third fin structure 206c and forms a non-merged source / drain region on the third fin structure 206c. Because the height of the fourth fin sidewall spacer is greater than the height of the third fin sidewall spacer, the non-merged source / drain region is tilted towards the merged source / drain region. In a second embodiment, either alone or in combination with the first embodiment, the difference between the height of the first fin sidewall spacer and the height of the second fin sidewall spacer (e.g., exemplary dimension 416) ranges from approximately 2 nanometers to approximately 5 nanometers. In the third embodiment, either alone or in combination with the first and / or second embodiments, etching the fin structure 206 includes providing plasma in the process chamber 116 of the etching machine 108 (e.g., a plasma-dominant etching machine 108). When providing plasma to the semiconductor wafer 200 in the process chamber 116, alternating between a first power setting P1 and a second power setting P2 of the plasma, and when providing plasma to the semiconductor wafer 200 in the process chamber 116, alternating between providing a first non-zero bias V1 to the chuck 120 in the process chamber 116 and providing a second non-zero bias V2 to the chuck 120, wherein the semiconductor wafer 200 is placed on the chuck 120, wherein alternating between the first power setting P1 and the second power setting P2 and alternating between providing the first non-zero bias V1 and the second non-zero bias V2 results in the height of the first fin sidewall spacer being greater than the height of the second fin sidewall spacer, and results in the height of the fourth fin sidewall spacer being greater than the height of the third fin sidewall spacer.

[0164] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, etching the fin structure 206 includes providing plasma into the process chamber 116 of an etching machine 108 (e.g., a plasma-dominant etching machine 108), and alternating between a first combination and a second combination when providing plasma to the semiconductor wafer 200 in the process chamber 116. The first combination includes a first power setting of the plasma and a first non-zero bias voltage of the chuck in the process chamber, and the second combination includes a second power setting of the plasma and a second non-zero bias voltage of the chuck. In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the first power setting P1 is greater than the second power setting P2, and the second non-zero bias voltage V2 is greater than the first non-zero bias voltage V1.

[0165] In the sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, etching the fin structure 206 includes providing plasma in the process chamber 116 of the etching machine 108 (e.g., a plasma-dominant etching machine 108), and a focusing ring 122 surrounding the semiconductor wafer 200 in the process chamber 116, adjusting the height of the focusing ring 122 relative to the semiconductor wafer 200 to cause plasma etching of the fin structure 206 such that the height of the first fin sidewall spacer is greater than the height of the second fin sidewall spacer, and the height of the fourth fin sidewall spacer is greater than the height of the third fin sidewall spacer. In the seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, adjusting the height of the focusing ring 122 includes adjusting the height of the focusing ring 122 such that ions 410 in a plasma sheath (e.g., sheath 124) above the semiconductor wafer 200 bombard the semiconductor wafer 200 at specific angles (e.g., angles 808, 812) to etch the fin structure 206, such that the height of the first fin sidewall spacer is greater than the height of the second fin sidewall spacer, and the height of the fourth fin sidewall spacer is greater than the height of the third fin sidewall spacer.

[0166] In the eighth embodiment, either alone or in combination with one or more of the first to seventh embodiments, etching the fin structure 206 includes forming a photoresist layer adjacent to a first portion 408a of the merged source / drain region between the merged source / drain region and the edge of the semiconductor wafer 200, forming a photoresist layer adjacent to a second portion 408b of the non-merged source / drain region between the non-merged source / drain region and the center of the semiconductor wafer 200, and etching the fin structure 206 located between the first portion 408a and the second portion 408b of the photoresist layer.

[0167] In the ninth embodiment, either alone or in combination with one or more of the first to eighth embodiments, etching the fin structure 206 located between the first portion 408a and the second portion 408b of the photoresist layer comprises etching the fin structure 206 using plasma etching, wherein ions 410 in the plasma passivate the first portion 408a of the photoresist layer, resulting in an etching rate of the first fin sidewall spacers being less than the etching rate of the second fin sidewall spacers, resulting in a height of the first fin sidewall spacers being greater than the height of the second fin sidewall spacers, and wherein ions 410 in the plasma passivate the second portion 408b of the photoresist layer, resulting in an etching rate of the fourth fin sidewall spacers being less than the etching rate of the third fin sidewall spacers, resulting in a height of the fourth fin sidewall spacers being greater than the height of the third fin sidewall spacers.

[0168] although Figure 11The diagram illustrates exemplary blocks of process 1100. In some embodiments, process 1100 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in the diagram. Figure 11 The illustrated blocks have different block configurations. Alternatively, or as an alternative, two or more blocks in process 1100 can be executed in parallel.

[0169] Figure 12 A flowchart illustrating an exemplary process 1200 related to the formation of the semiconductor device described herein. In some embodiments, Figure 12 One or more process blocks can be executed by one or more semiconductor process equipment (e.g., one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112). Alternatively or as an alternative, Figure 12 One or more process blocks may be executed by elements of one or more devices 900, such as processor 920, memory 930, input element 940, output element 950, and / or communication element 960.

[0170] like Figure 12 As illustrated, process 1200 may be included in a first quadrant of a semiconductor wafer to form a first merged epitaxial region and a first non-merged epitaxial region (box 1210). For example, as described in this disclosure, one or more semiconductor process equipment 102, 104, 106, 108, 110, and 112 may form a first merged epitaxial region 422 and a first non-merged epitaxial region (e.g., first epitaxial region 420c) in a first quadrant (e.g., quadrant 200a) of semiconductor wafer 200. In some embodiments, the formed first merged epitaxial region 422 is closer to the edge of semiconductor wafer 200 in the first quadrant than the first non-merged epitaxial region. In some embodiments, the first merged epitaxial region 422 is inclined toward the first non-merged region and toward the center of semiconductor wafer 200. In some embodiments, the first non-merged epitaxial region is inclined toward the first merged epitaxial region 422 and toward the edge of semiconductor wafer 200.

[0171] like Figure 12As further illustrated, process 1200 may be included in a second quadrant of the semiconductor wafer to form a second merged epitaxial region and a second non-merged epitaxial region (block 1220). For example, as described in this disclosure, one or more semiconductor process stations 102, 104, 106, 108, 110, and 112 may form a second merged epitaxial region 422 and a second non-merged epitaxial region (e.g., second epitaxial region 420c) in a second quadrant (e.g., quadrant 200d) of the semiconductor wafer 200. In some embodiments, the second quadrant is a quadrant obliquely opposite to the first quadrant. In some embodiments, the formed second merged epitaxial region 422 is closer to the edge of the semiconductor wafer 200 in the second quadrant than the second non-merged epitaxial region. In some embodiments, the second merged epitaxial region 422 is inclined toward the second non-merged region and toward the center of the semiconductor wafer 200. In some embodiments, the second non-merged epitaxial region is inclined toward the second merged epitaxial region 422 and toward the edge of the semiconductor wafer 200.

[0172] Process 1200 may include additional embodiments, such as any single embodiment or any combination of the embodiments described below and / or associated with one or more other processes described elsewhere in this disclosure.

[0173] In the first embodiment, the first non-merging extensional region (e.g., the first extensional region 420c) is inclined away from the second non-merging extensional region (e.g., the second extensional region 420c), while the second non-merging extensional region is inclined away from the first non-merging extensional region. In the second embodiment, either alone or in combination with the first embodiment, the first merging extensional region 422 is inclined toward the second merging extensional region 422, while the second merging extensional region 422 is inclined toward the first merging extensional region 422.

[0174] In the third embodiment, either alone or in combination with the first and second embodiments, the first merged epitaxial region 422 and the first non-merged epitaxial region (e.g., the first epitaxial region 420c) are included in a first ring oscillator device in the first quadrant (e.g., quadrant 200a) of the semiconductor wafer 200 (e.g., in device region 202), while the second merged epitaxial region 422 and the second non-merged epitaxial region (e.g., the second epitaxial region 420c) are included in a second ring oscillator device in the second quadrant (e.g., quadrant 200d) of the semiconductor wafer 200 (e.g., in device region 500).

[0175] although Figure 12 The diagram illustrates exemplary blocks of process 1200. In some embodiments, process 1200 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in the diagram. Figure 12 The illustrated blocks have different block configurations. Alternatively, or as an alternative, two or more blocks in process 1200 can be executed in parallel.

[0176] In this way, epitaxial regions with specific asymmetric characteristics can be formed at specific locations on a semiconductor wafer. These asymmetric characteristics include aspects such as the direction of slope or tilt, the angle of slope or tilt, and / or other asymmetric characteristics. The asymmetric epitaxial regions can be formed using various plasma-based fin structure etching techniques described in this disclosure. Specific asymmetric characteristics can increase the metal landing coverage area at specific locations on the semiconductor wafer (e.g., preferred locations on the semiconductor substrate) to reduce the contact resistance between the epitaxial region and the associated conductive structure formed to the epitaxial region. This can increase the performance of the semiconductor device, reduce the rate and / or likelihood of defect formation, and / or increase the yield of the semiconductor device, among other examples.

[0177] As described in more detail above, some embodiments described in this disclosure provide a method. This method includes forming a plurality of first fin structures in a substrate of a semiconductor wafer within a device region of the semiconductor wafer. This method also includes forming a second fin structure in a substrate within a device region of the semiconductor wafer. This method includes forming a merged epitaxial region on the first fin structure, wherein the merged epitaxial region includes a first epitaxial region and a second epitaxial region, the first and second epitaxial regions being connected in at least a portion of the first and second epitaxial regions, wherein the first epitaxial region is closer to the outer edge of the semiconductor wafer relative to the second epitaxial region, and wherein the height of the top surface of the first epitaxial region is greater than the height of the top surface of the second epitaxial region. This method further includes forming a third epitaxial region on the second fin structure, wherein the third epitaxial region includes a single epitaxial region, wherein the third epitaxial region is closer to the center of the semiconductor wafer relative to the merged epitaxial region, wherein a first end of the third epitaxial region is lower than a second end of the third epitaxial region, and wherein the first end is closer to the merged epitaxial region relative to the second end.

[0178] As described in more detail above, some embodiments described in this disclosure provide a method. This method includes forming a plurality of fin structures in a device region of a semiconductor wafer substrate, wherein the fin structures include a first fin structure, a second fin structure adjacent to the first fin structure and closer to the center of the semiconductor wafer relative to the first fin structure, and a third fin structure closer to the center of the semiconductor wafer relative to the second fin structure. This method includes forming spacer layers on a plurality of tops and a plurality of sidewalls of the fin structures. This method includes etching the fin structures to form first fin sidewall spacers and second fin sidewall spacers located on opposite sides of the first fin structure, and to form third fin sidewall spacers and fourth fin sidewall spacers located on opposite sides of the third fin structure. This method includes forming merged source / drain regions on the first and second fin structures after etching the fin structures. This method includes forming a non-merged source / drain region on a third fin structure, wherein the merged source / drain region is inclined toward the non-merged epitaxial region because the height of the first fin sidewall spacer is greater than the height of the second fin sidewall spacer, and wherein the non-merged source / drain region is inclined toward the merged source / drain region because the height of the fourth fin sidewall spacer is greater than the height of the third fin sidewall spacer.

[0179] As described in more detail above, some embodiments described in this disclosure provide a method. This method includes forming a first merged epitaxial region and a first non-merged epitaxial region in a first quadrant of a semiconductor wafer, wherein the formed first merged epitaxial region is closer to the edge of the semiconductor wafer in the first quadrant relative to the first non-merged epitaxial region, wherein the first merged epitaxial region is inclined toward the first non-merged epitaxial region and toward the center of the semiconductor wafer, and wherein the first non-merged epitaxial region is inclined toward the first merged epitaxial region and toward the edge of the semiconductor wafer. This method also includes forming a second merged epitaxial region and a second non-merged epitaxial region in a second quadrant of a semiconductor wafer, wherein the second quadrant is a quadrant obliquely opposite to the first quadrant, wherein the formed second merged epitaxial region is closer to the edge of the semiconductor wafer in the second quadrant relative to the second non-merged epitaxial region, wherein the second merged epitaxial region is inclined toward the second non-merged epitaxial region and toward the center of the semiconductor wafer, and wherein the second non-merged epitaxial region is inclined toward the second merged epitaxial region and toward the edge of the semiconductor wafer.

[0180] As described in more detail above, some embodiments described in this disclosure provide a semiconductor device. This semiconductor device includes a merged epitaxial region and a non-merged epitaxial region. The merged epitaxial region is tilted toward the non-merged epitaxial region. The non-merged epitaxial region is tilted toward the merged epitaxial region.

[0181] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments described herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: In a device region of a semiconductor wafer, a plurality of fin structures are formed on a substrate of the semiconductor wafer; Forming a first fin sidewall spacer and a second fin sidewall spacer on opposite sides of a first fin structure of the fin structure; and A merged extensional region is formed on the fin structure. The merged extensional region includes a first extensional region and a second extensional region. The first extensional region is located on the first fin structure, and the first extensional region and the second extensional region are connected in at least a portion of the first extensional region and at least a portion of the second extensional region. The first epitaxial region is closer to an outer edge of the semiconductor wafer than the second epitaxial region. Wherein the height of a top surface of the first epitaxial region is greater than the height of a top surface of the second epitaxial region, and Since the height of the first fin sidewall spacer is greater than the height of the second fin sidewall spacer, the merged epitaxial region is tilted toward a center of the semiconductor wafer.

2. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: In the device region of the semiconductor wafer, a second fin structure is formed in the substrate; as well as A third extensional region is formed on the second fin structure. The third extensional region includes a single extensional region. The third epitaxial region is closer to the center of the semiconductor wafer than the merged epitaxial region. Wherein a first end of the third extensional region is lower than a second end of the third extensional region, and The first end is closer to the merging extension region than the second end.

3. The method for manufacturing a semiconductor device as described in claim 2, further comprising: A hybrid fin structure is formed between the first fin structure and the second fin structure. The first end of the third extensional region is closer to the hybrid fin structure than the second end of the third extensional region.

4. The method for manufacturing a semiconductor device as claimed in claim 3, wherein the hybrid fin structure includes a first hybrid fin structure; as well as The manufacturing method of the semiconductor device further includes: A second hybrid fin structure is formed adjacent to the fin structure on the opposite side relative to the first hybrid fin structure; as well as A third hybrid fin structure is formed adjacent to the second fin structure on the opposite side relative to the first hybrid fin structure. The height of the second hybrid fin structure and the third hybrid fin structure is greater than the height of the first hybrid fin structure.

5. The method of manufacturing a semiconductor device as claimed in claim 3, wherein forming the merged epitaxial region comprises: The formation of this merged extension region results in: The height of the top surface of the first epitaxial region is greater than the height of the top surface of the hybrid fin structure, and The height of the top surface of the second extensional region is less than the height of the top surface of the hybrid fin structure.

6. The method for manufacturing a semiconductor device as claimed in claim 2, further comprising: An opening is formed in a dielectric layer to connect to the merged epitaxial region; as well as A conductive structure is formed in the opening on the merged epitaxial region. The conductive structure includes a suspension region located on the side of the merged epitaxial region facing the third epitaxial region.

7. The method of manufacturing a semiconductor device as claimed in claim 6, wherein forming the conductive structure comprises: The conductive structure is formed such that it extends laterally above the fin structure.

8. A method for manufacturing a semiconductor device, comprising: In a device region of a semiconductor wafer, multiple fin structures are formed on a substrate of the semiconductor wafer. The fin structure includes: A first fin structure; and A second fin structure, which is adjacent to the first fin structure and closer to a center of the semiconductor wafer than the first fin structure; A spacer layer is formed on multiple tops and multiple sidewalls of the fin structure; Etching the fin structure, The fin structure is etched to form a first fin sidewall spacer and a second fin sidewall spacer, the second fin sidewall spacer being located on the opposite side of the first fin structure; and After etching the fin structure, a merged source / drain region is formed on the first fin structure and the second fin structure. Since the height of the first fin sidewall spacer is greater than the height of the second fin sidewall spacer, the merged source / drain region is tilted toward the center of the semiconductor wafer.

9. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the fin structure comprises: A third fin structure, which is closer to the center of the semiconductor wafer than the second fin structure; The fin structure is etched to form a third fin sidewall spacer and a fourth fin sidewall spacer, the fourth fin sidewall spacer being located on the opposite side of the third fin structure; as well as The manufacturing method of the semiconductor device further includes: A non-merged source / drain region is formed on the third fin structure. Since the height of the fourth fin sidewall spacer is greater than the height of the third fin sidewall spacer, the non-merged source / drain region is tilted toward the merged source / drain region.

10. The method of manufacturing a semiconductor device as claimed in claim 9, wherein etching the fin structure comprises: A plasma is provided in a process chamber of an etching machine; When the plasma is supplied to the semiconductor wafer in the process chamber, the plasma is alternated between a first power setting and a second power setting; as well as When supplying the plasma to the semiconductor wafer in the process chamber, alternating between providing a first non-zero bias voltage to a chuck in the process chamber and providing a second non-zero bias voltage to the chuck, wherein the semiconductor wafer is placed on the chuck. The alternation between the first power setting and the second power setting, and the alternation between providing the first non-zero bias voltage and the second non-zero bias voltage, results in the height of the first fin sidewall spacer being greater than the height of the second fin sidewall spacer, and the height of the fourth fin sidewall spacer being greater than the height of the third fin sidewall spacer.

11. The method of manufacturing a semiconductor device as claimed in claim 9, wherein etching the fin structure comprises: A photoresist layer is formed adjacent to a first portion of the merged source / drain region between the merged source / drain region and an edge of the semiconductor wafer; A second portion of the photoresist layer is formed adjacent to the non-merged source / drain region between the non-merged source / drain region and the center of the semiconductor wafer; as well as The fin structure located between the first portion and the second portion of the photoresist layer is etched.

12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein etching the fin structure located between the first portion and the second portion of the photoresist layer comprises: The fin structure was etched using a plasma etching process. The plasma contains multiple ions that passivate the first portion of the photoresist layer, resulting in a lower etching rate for the first fin sidewall spacers than for the second fin sidewall spacers, and consequently, a greater height for the first fin sidewall spacers than for the second fin sidewall spacers; and The ions in the plasma passivate the second portion of the photoresist layer, causing the etching rate of the fourth fin sidewall spacer to be less than that of the third fin sidewall spacer, and causing the height of the fourth fin sidewall spacer to be greater than that of the third fin sidewall spacer.

13. The method of manufacturing a semiconductor device as claimed in claim 8, wherein etching the fin structure comprises: A plasma is provided in a process chamber of an etching machine; as well as When the plasma is supplied to the semiconductor wafer in the process chamber, it alternates between a first combination and a second combination. The first combination includes a first power setting for the plasma and a first non-zero bias voltage for a chuck in the process chamber, and The second combination includes a second power setting for the plasma and a second non-zero bias voltage for the chuck.

14. The method of manufacturing a semiconductor device as claimed in claim 13, wherein the first power setting is greater than the second power setting, and The second non-zero bias voltage is greater than the first non-zero bias voltage.

15. A semiconductor device, comprising: A semiconductor substrate; A first fin structure is located above the semiconductor substrate; A first fin sidewall spacer and a second fin sidewall spacer are located on opposite sides of the first fin structure; A combined epitaxial region is located above the semiconductor substrate and above the first fin structure; as well as A non-merged epitaxial region is located above the semiconductor substrate. The merged extension region slopes toward the non-merged extension region. Wherein the non-merging extension region slopes toward the merging extension region, and Since the height of the first fin sidewall spacer is greater than the height of the second fin sidewall spacer, the merged epitaxial region is tilted toward a center of the semiconductor substrate.

16. The semiconductor device of claim 15, wherein the height of a top surface of a first portion of the merged epitaxial region is greater than the height of a top surface of a second portion of the merged epitaxial region; and The second part is closer to the non-merged extensional region than the first part.

17. The semiconductor device of claim 16, wherein the first portion is located above the first fin structure; The second part is located above a second fin structure; and The non-merged extensional region is located above a third fin structure.

18. The semiconductor device of claim 15, further comprising: A hybrid fin structure is located between the merged extensional region and the non-merged extensional region. The height of one top surface of the non-merged extensional region is greater than the height of one top surface of the hybrid fin structure.

19. The semiconductor device of claim 15, wherein the height of a top surface of the non-merged epitaxial region is greater than the height of a top surface of the merged epitaxial region.

20. The semiconductor device of claim 15, further comprising: A conductive structure is located on the merged epitaxial region. The conductive structure includes a suspension region located on the side of the merged epitaxial region facing the non-merged epitaxial region.

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