Semiconductor device and method of forming the same

Abstract

The present disclosure relates to semiconductor devices and methods of forming the same. A titanium precursor is used to selectively form a titanium silicide (TiSi x ) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening and a silicon is diffused to a top surface of a transistor structure using a reactive gas and plasma. The diffusion of the silicon results in the formation of a silicon-rich surface of the transistor structure which increases the selectivity of the titanium silicide over other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The formation of the selective titanium silicide layer results in the formation of titanium silicon nitride (TiSi x N y ) on the sidewalls in the opening which allows for the formation of a conductive structure, such as a metal source / drain contact, in the opening without the need to add another barrier layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having a transistor spacer structure. Background Technology

[0002] Fin-based transistors are three-dimensional structures comprising channel regions within fins (or portions thereof) that are three-dimensional structures extending onto a semiconductor substrate. Examples of fin-based transistors include fin field-effect transistors (finFETs) and nanostructured transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, and nanoribbon transistors). A gate structure surrounds the fins of semiconductor material and is configured to control the flow of charge carriers within the channel regions. For example, in a finFET, the gate structure surrounds three sides of the fins (and the channel regions), thereby allowing increased control over the channel regions (and the switching of the finFET). As another example, in a nanostructured transistor, the gate structure surrounds multiple channel regions within a fin structure, such that the gate structure surrounds each of the multiple channel regions. Source / drain regions (e.g., epitaxial regions) are located on either side of the gate structure. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor structure, including: forming a first opening through one or more first dielectric layers to a source / drain region; forming silicon nitride (Si). x N y The silicon nitride layer is formed on the sidewalls of one or more first dielectric layers in the first opening; after forming the silicon nitride layer, a plasma-based deposition operation is performed to selectively form titanium silicide (TiSi). x The first opening is formed on the top surface of the source / drain region in the first opening; the first opening is filled with conductive material to form source / drain contacts above the silicon nitride layer and the titanium silicide layer; one or more second dielectric layers are formed above one or more first dielectric layers; a second opening is formed through one or more second dielectric layers to the source / drain contacts; and the second opening is filled with conductive material to form a source / drain interconnect structure connected to the source / drain contacts.

[0004] This disclosure provides a method for forming a semiconductor structure, including: forming an opening through silicon oxide (SiO2). x ) layer and penetrates the silicon nitride (Si) layer located beneath the silicon oxide layer. x N y Plasma-based deposition is performed from the layer to the source / drain region to selectively form titanium silicide (TiSi). xA layer is placed on the top surface of the source / drain region in the opening; the opening is filled with a conductive material to form a conductive structure on the titanium silicide layer; and a line back-end (BEOL) metallization structure is formed on the conductive structure, wherein the conductive structure extends from the source / drain region to the BEOL metallization structure.

[0005] This disclosure provides a semiconductor device, including: a substrate; a semiconductor fin structure extending on the substrate; a first oxide layer located on the fin structure; a transistor structure located above the semiconductor fin structure and in the first oxide layer, wherein the transistor structure includes a source / drain region or a gate structure; a nitride layer located above the first oxide layer; a second oxide layer located above the nitride layer; integrated contacts and interconnects, including: a first region located in the nitride layer; a second region located in the second oxide layer; and a neck region transitioning between the first region and the second region; and titanium silicide (TiSi). x The first region is located between the transistor structure and the integrated contacts and interconnects; and the titanium silicon nitride (TiSi) layer. x N y The first region is located between the nitride layer and the integrated contacts and interconnects. Attached Figure Description

[0006] The various aspects of this disclosure will be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure. Figure 1 A diagram is a schematic representation of an environment in which the systems and / or methods described herein can be implemented. Figure 2 This is a diagram of the region of the exemplary semiconductor device described herein. Figures 3A to 3D , Figures 4A to 4C , Figures 5A to 5D ,and Figures 6A to 6N ,as well as Figures 7A to 7F These are figures illustrating the exemplary embodiments described herein. Figure 8 This is a diagram illustrating the dimensions of a portion of the semiconductor device described herein. Figure 9A and Figure 9B This is a diagram illustrating the elements of a portion of the semiconductor device described herein. Figure 10 This is what is described in this article. Figure 1 A diagram illustrating exemplary elements of one or more devices. Figure 11 and Figure 12This is an exemplary process flow related to the formation of conductive structures in the semiconductor device described herein. The reference numerals in the attached figures are explained as follows: 100: Indicative Environment 102: Deposition equipment 104: Exposure equipment 106: Developing equipment 108: Etching Equipment 110: Flattening equipment 112: Coating equipment 114: Wafer / Die Transport Equipment 200: Semiconductor devices 202: Device Area 204: Substrate 206: Fin structure 208: Shallow trench isolation zone 210: Dummy gate structure 212: Gate dielectric layer 214: Gate electrode layer 216: Hard mask layer 218: Source / Drain Region 300: Illustrative Implementation 302: Shallow trench isolation layer 400: Illustrative Implementation 402: Sealing spacer layer 404: Block spacer layer 406: Groove 408: Source / Drain Region 500: Illustrative Implementation 502: Contact Etching Stop Layer 504: Interlayer dielectric layer 506: Opening 508: Gate structure 510: High-k dielectric layer 512: Work Function Tuning Layer 514: Metal Electrode Structure 600: Illustrative Implementation 602: Opening 602a: Bottom surface 602b: Sidewall 604: Nitride layer 606: Metal silicide layer 608: Metallic silicon nitride layer 610: Metal source / drain contact 612: Etching Stop Layer 614: Interlayer dielectric layer 616: Opening 618: Source / Drain interconnect 620: Etching Stop Layer 622: Interlayer dielectric layer 624: Opening 626: Barrier Layer 628: Lining 630: BEOL metallized structure 632: Cap layer 700: Illustrative Implementation 702: Silicon oxide layer 704: Silicon nitride layer 706: Silicon oxide layer 708: Opening 708a: Bottom surface 708b: Sidewall 710a: Lower area 710b: Upper District 712: Neck area 714: Integrated contacts and interconnects 716a: Lower region 716b: Upper District 718: Neck area 720a: Bottom surface 720b: Top surface 722: Top surface 802: Indicative Dimension 804: Indicative Dimension 806: Indicative Dimension 808: Indicative Dimension 810: Indicative Dimension 812: Indicative Dimensions 814: Indicative Dimensions 816: Indicative Dimensions 900: Indicative element composition 902: Exemplary vertical elemental composition 904: Silicon 906: Germanium 908: Titanium 910: Ruthenium 912: Nitrogen 914: Oxygen 916: Exemplary Level Elemental Compositions 1000: Device 1010: Bus 1020: Processor 1030: Memory 1040: Input element 1050: Output element 1060: Communication Components 1100: Manufacturing Process 1110: Square 1120: Square 1130: Square 1140: Box 1150: Box 1160: Box 1170: Box 1200: Process 1210: Square 1220: Square 1230: Square 1240: Box AA: Section BB: Cross-section CC: Section Detailed Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of this disclosure. Of course, these are merely examples and are not intended to define embodiments of this disclosure. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms may be used, such as "below," "under," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or during manufacturing, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0009] Material selection directly impacts the performance and size reduction of semiconductor devices. The type of conductive material used in the conductive structures of semiconductor devices (e.g., contacts and interconnects) affects the resistivity, parasitic capacitance, defect formation, electromigration, and / or other properties and attributes of the conductive structures. With the advancement of miniaturization in semiconductor devices (and their corresponding conductive structures), the use of cobalt (Co), tungsten (W), and ruthenium (Ru) can provide sustained and / or improved performance due to their high mobility relative to other metals. However, certain combinations of conductive materials can lead to increased defect formation rates and performance degradation. For example, this can occur in electrically and / or physically contacted conductive structures, including corresponding and different types of metals (e.g., heteromaterials).

[0010] In some cases, solid solutioning can occur in binary systems containing conductive structures of corresponding and dissimilar metals. Solid solution can induce atom-to-atom substitution or vacancies at or near the interfaces between conductive structures, which can increase the rate of defect formation in the conductive structures. In other cases, galvanic corrosion can occur in binary systems containing conductive structures of corresponding and dissimilar metals. Galvanic corrosion can lead to corrosion and / or separation of the conductive structures, potentially causing phase transition defects (e.g., between the α and β phases of tungsten (W),) and / or other defects, and / or performance degradation. This can increase parasitic capacitance between conductive structures and may disrupt the connections between them, reducing yield and increasing the failure rate of semiconductor devices.

[0011] Furthermore, some barrier layer materials used in conductive structures can increase sheet resistance, increase contact resistance, and / or reduce the available space in the openings used to form the conductive structure. This reduction in available space can lead to a decrease in the cross-sectional width of the conductive structure (which may be referred to as the "critical dimension" or CD), which may reduce the gap-filling performance of the conductive structure, may increase the likelihood and / or rate of pore formation in the conductive structure, may increase the surface roughness (Rp) of the conductive structure, and / or may lead to another type of defect or performance degradation in the conductive structure.

[0012] Some embodiments described herein provide homogeneous conductive structures and related formation methods. In some embodiments, titanium precursors are used to selectively form titanium silicide (TiSi) on the source / drain regions of a semiconductor device. xA plasma-based deposition process is performed, in which a titanium precursor is provided into the openings of the source / drain regions, and silicon in the source / drain regions is diffused to the top surface of the source / drain regions using reactive gases and plasma. Providing the titanium precursor, reactive gases, and plasma into the openings for a period of time is called a soaking operation. The diffusion of silicon leads to the formation of silicon-rich surfaces in the source / drain regions, which increases the selectivity of titanium silicide formation relative to other materials in semiconductor devices, such as silicon oxide (SiO2). x The titanium precursor reacts with the silicon-rich surface of the source / drain regions to form a titanium silicide layer on the source / drain regions. The selective formation of the titanium silicide layer leads to titanium silicon nitride (TiSi). x N y This is formed on the sidewalls of the opening, which allows for the formation of conductive structures, such as metal source / drain contacts, within the opening without the need for an additional barrier layer, such as titanium nitride (Ti). x N y ) or tantalum nitride (Ta x N y This reduces the complexity of forming metal source / drain contacts and provides a larger volume in the opening (e.g., compared to using another barrier layer), which increases the gap-filling performance of the metal source / drain contacts, reduces the possibility of forming voids, and / or reduces the surface roughness of the metal source / drain contacts.

[0013] Furthermore, the source / drain interconnects can be formed to the metal source / drain contacts, such that the source / drain interconnects and the metal source / drain contacts are formed of the same conductive material, such as ruthenium (Ru), or other types of conductive materials. Including the source / drain interconnects and metal source / drain contacts of the same conductive material reduces the likelihood of solid solution in the source / drain interconnects and metal source / drain contacts, reduces the likelihood of current corrosion in the source / drain interconnects, and / or reduces phase transitions in the source / drain interconnects and metal source / drain contacts (e.g., because ruthenium may have a high-voltage cell (HPC) or Ru-HPC) structure during the deposition process of the source / drain interconnects and metal source / drain contacts at operating temperatures). This reduces the parasitic capacitance between the source / drain interconnects and the metal source / drain contacts, reduces the resistivity between the source / drain interconnects and the metal source / drain contacts, reduces the likelihood of separation between the source / drain interconnects and the metal source / drain contacts, and / or reduces the formation of defects in the source / drain interconnects and the metal source / drain contacts. For example, the back end of line (BEOL) metallization layer of the zeroth metal layer (M0) can be formed as a solid and / or electrically connected to the source / drain interconnects.

[0014] Alternatively, integrated contacts and interconnects can be formed within the opening. The integrated contacts and interconnects comprise a uniform conductive structure extending from the source / drain region (or from the titanium silicide layer on the source / drain region) to the BEOL metallization layer (or to the barrier layer beneath the BEOL metallization layer). The integrated contact and interconnect structure comprises a homogeneous conductive material, such as ruthenium (Ru), or other metals, and is unaffected by defects such as solid solution and current corrosion that can occur in separate (two-part) metallic source / drain contacts and source / drain interconnects formed from corresponding and different types of conductive materials. The integrated contact and interconnect structure also reduces the number of interlayer interfaces between the source / drain region and the BEOL metallization layer, which further reduces the contact resistance between the source / drain region and the BEOL metallization layer.

[0015] Figure 1 This is a diagram of an exemplary environment 100 in which the systems and / or methods described herein can be implemented. (See diagram for example.) Figure 1As shown, environment 100 may include multiple semiconductor processing equipment 102-112 and wafer / die transport equipment 114. The multiple semiconductor processing equipment 102-112 may include deposition equipment 102, exposure equipment 104, developing equipment 106, etching equipment 108, planarization equipment 110, plating equipment 112, and / or another type of semiconductor processing equipment. The equipment included in the exemplary environment 100 may be included in semiconductor clean rooms, semiconductor foundries, semiconductor process facilities, and / or manufacturing facilities, etc.

[0016] Deposition apparatus 102 is a semiconductor processing apparatus that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, deposition apparatus 102 includes spin coating apparatus capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, deposition apparatus 102 includes chemical vapor deposition (CVD) equipment, atomic layer deposition (ALD) equipment, plasma-enhanced atomic layer deposition (PEALD) equipment, or other types of CVD equipment, such as plasma-enhanced CVD (PECVD) equipment, high-density plasma CVD (HDP-CVD) equipment, sub-atmospheric CVD (SACVD) equipment, and low-pressure CVD (LPCVD) equipment. In some embodiments, the deposition apparatus 102 includes physical vapor deposition (PVD) equipment, such as sputtering equipment or another type of PVD equipment. In some embodiments, the deposition apparatus 102 includes epitaxial equipment configured to form layers and / or regions of a device by epitaxial growth. In some embodiments, the exemplary environment 100 includes various types of deposition apparatus 102.

[0017] Exposure apparatus 104 is a semiconductor processing apparatus capable of exposing a photoresist layer to radiation sources such as ultraviolet light (UV) sources (e.g., deep ultraviolet light, extreme ultraviolet light, EUV sources, etc.), X-ray sources, electron beam sources, etc. Exposure apparatus 104 exposes the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, etc. In some embodiments, exposure apparatus 104 includes a scanner, a stepper, or a similar type of exposure apparatus.

[0018] The developer tool 106 is a semiconductor processing apparatus capable of developing a photoresist layer that has been exposed to a radiation source, in order to develop a pattern transferred from the exposure apparatus 104 to the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developer tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0019] Etching equipment 108 is a semiconductor processing apparatus capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching equipment 108 may include wet etching equipment, dry etching equipment, etc. In some embodiments, etching equipment 108 includes a chamber filled with etchant, and a substrate is placed in the chamber for a specific time length to remove a specific amount of one or more portions of the substrate. In some embodiments, etching equipment 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using ionized gas to isotropically or directionally etch one or more portions.

[0020] Planarization apparatus 110 is a semiconductor processing apparatus capable of polishing or planarizing layers of a wafer or semiconductor device. For example, planarization apparatus 110 may include chemical mechanical planarization (CMP) equipment and / or another type of planarization equipment that polishes or planarizes layers or surfaces of deposited or coated materials. Planarization apparatus 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of the semiconductor device. Planarization apparatus 110 may combine a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device) using abrasive and corrosive chemical slurry. The polishing pad and semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. Dynamic polishing heads can rotate on different axes to remove material or even remove any irregularities in the shape of a semiconductor device, making the semiconductor device flat or planar.

[0021] The coating equipment 112 is a semiconductor processing apparatus capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the coating equipment 112 may include a copper electroplating apparatus, an aluminum electroplating apparatus, a nickel electroplating apparatus, a tin electroplating apparatus, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) electroplating apparatus, and / or one or more other types of electroplating apparatus for conductive materials, metals, and / or similar types of materials.

[0022] The wafer / die transport equipment 114 includes a mobile robot, robotarm, tram car or railcar, overhead hoist transport (OTH) system, automated material handling system (AMHS), and / or another type of device, configured to transport substrates and / or semiconductor devices between semiconductor processing equipment 102-112, configured to transport substrates and / or semiconductor devices between processing chambers within the same semiconductor processing equipment, and / or configured to transport substrates and / or semiconductor devices between other locations, such as wafer racks, storage rooms, etc. In some embodiments, the wafer / die transport equipment 114 may be a programmable device that travels along a specific path and / or can operate semi-autonomously or autonomously. In some embodiments, the semiconductor processing environment 100 includes multiple wafer / die transport equipment 114.

[0023] The wafer / die transport device 114 may be included in a cluster device or another type of device that includes multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between multiple processing chambers, such as transporting substrates and / or semiconductor devices between processing chambers and buffers, transporting substrates and / or semiconductor devices between processing chambers and interface devices such as equipment front end modules (EFEMs), and / or transporting substrates and / or semiconductor devices between semiconductor processing chambers and transport carriers (e.g., front opening unified pods, FOUPs). In some embodiments, the wafer / die transport device 114 may be included in a multi-chamber (or clustered) deposition apparatus 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from the substrate and / or semiconductor device) and a plurality of types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, as described herein, the wafer / die transport device 114 is configured to transport the substrate and / or semiconductor device between the process chambers of the deposition apparatus 102 without disrupting or removing the vacuum (or at least a partial vacuum) between the process chambers and / or between the process operations in the deposition apparatus 102.

[0024] supply Figure 1The number and arrangement of the devices shown are for one or more examples. In fact, compared to Figure 1 The apparatus shown may include additional devices, fewer devices, different devices, or devices with different configurations. Furthermore, it can be implemented within a single device. Figure 1 The two or more devices shown may be able to Figure 1 The single device shown is implemented as multiple distributed devices. Additionally or alternatively, a group of devices in environment 100 (e.g., one or more devices) may perform the one or more functions performed by another group of devices in environment 100.

[0025] Figure 2 This is a diagram illustrating an example area of ​​the semiconductor device 200 described herein. Specifically, Figure 2 An exemplary device region 202 of a semiconductor device 200 is illustrated, including one or more transistors or other devices. The transistors may include fin-based transistors, such as fin field-effect transistors (finFETs), nanostructure transistors, and / or other types of transistors. In some embodiments, device region 202 includes a p-type metal-oxide-semiconductor (PMOS) region, an n-type metal-oxide-semiconductor (NMOS) region, a complementary metal-oxide-semiconductor (CMOS) region, and / or another type of device region. Figures 3A to 7F yes Figure 2 The schematic cross-sectional view of the device region 202 of the semiconductor device 200 shown corresponds to the various process stages in which fin-based transistors are formed in the device region 202 of the semiconductor device 200.

[0026] Semiconductor device 200 includes substrate 204. Substrate 204 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, or other types of semiconductor substrates, such as gallium arsenide (GaAs). Substrate 204 may include annular / circular substrates having a diameter of about 200 mm, about 300 mm, or other diameters, such as 450 mm. Substrate 204 may alternatively be any polygonal, square, rectangular, curved, or other non-circular workpiece, such as a polygonal substrate.

[0027] Fin structure 206 is included on (and / or extends thereon) the substrate 204 of device region 202. Fin structure 206 can provide an active region for forming one or more devices (e.g., fin-based transistors). In some embodiments, fin structure 206 comprises silicon (Si) material or another elemental semiconductor material such as germanium (Ge). In some embodiments, fin structure 206 comprises alloy semiconductor materials such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof. In some embodiments, the fin structure 206 is doped with n-type and / or p-type dopants.

[0028] The fin structure 206 is fabricated using suitable semiconductor process technologies, such as masking, photolithography, and / or etching processes. As an example, the fin structure 206 can be formed by etching away a portion of the substrate 204 to create a recess in the substrate 204. The recess can then be filled with an etched or etched-back isolation material to form a shallow trench isolation (STI) region 208 above the substrate 204 and between the fin structures 206. Other fabrication technologies can be used for the STI region 208 and / or for the fin structure 206. The STI region 208 electrically isolates adjacent active regions in the fin structure 206. The STI region 208 may include a dielectric material, such as silicon oxide (SiO2). x Silicon nitride (Si) X N y The STI region 208 may include silicon oxynitride (SiON), fused silica glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. The STI region 208 may include a multilayer structure, such as having one or more layers.

[0029] A dummy gate structure 210 (or multiple dummy gate structures 210) is included in a device region 202 above the fin structure 206 (e.g., approximately perpendicular to the fin structure 206). The dummy gate structure 210 engages the fin structure 206 on three or more sides of the fin structure 206. Figure 2 In the example illustrated, the dummy gate structure 210 includes a gate dielectric layer 212, a gate electrode layer 214, and a hard mask layer 216. In some embodiments, the dummy gate structure 210 further includes a capping layer, one or more spacer layers, and / or another suitable layer. The layers of the dummy gate structure 210 can be formed by suitable deposition techniques and patterned by suitable photolithography and etching techniques.

[0030] As described herein, the term "dummy" refers to a sacrificial structure that will be removed and replaced at a later stage with another structure, such as a high-k dielectric and metal gate structure in a gate replacement process. A gate replacement process refers to the fabrication of the gate structure late in the overall gate fabrication process. Therefore, Figure 2 The configuration of the semiconductor device 200 shown may include an intermediate configuration, and additional semiconductor processing operations may be performed on the semiconductor device 200 to further process the semiconductor device 200.

[0031] The gate dielectric layer 212 may include a dielectric oxide layer. The dielectric oxide layer may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. The gate electrode layer 214 may include polysilicon or other suitable materials. The gate electrode layer 214 may be formed by a suitable deposition process, such as LPCVD or PECVD. The hard mask layer 216 may include any material suitable for patterning the gate electrode layer 214 on the substrate 204 with specific features / sizes.

[0032] In some implementations, the layers of the dummy gate structure 210 are first deposited as blanket layers. Then, the blanket layers are patterned using a process including optical lithography and etching, a portion of the blanket layers are removed, and the remaining portion is left over the STI region 208 and the fin structure 206 to form the dummy gate structure 210.

[0033] Source / drain regions 218 are disposed on both sides of the fin structure 206 relative to the dummy gate structure 210. Source / drain regions 218 include the regions in device region 202 where the source / drain regions will be formed. The source / drain regions in device region 202 include silicon (Si) having one or more of the following dopants: p-type materials (e.g., boron (B) or germanium (Ge), etc.), n-type materials (e.g., phosphorus (P) or arsenic (As), etc.), and / or another type of dopant. Therefore, device region 202 can include PMOS transistors including p-type source / drain regions, NMOS transistors including n-type source / drain regions, and / or other types of transistors.

[0034] Some source / drain regions may be shared among various transistors in device region 202. In some embodiments, the individual source / drain regions may be connected or coupled together, such that the fin-based transistor in device region 202 is implemented as two functional transistors. For example, if adjacent (e.g., rather than adjacent) source / drain regions are electrically connected, for example by merging these regions through epitaxial growth (e.g., merging adjacent source / drain regions, rather than merging source / drain regions on both sides of the dummy gate structure 210), two functional transistors can be implemented. Other configurations in other examples can implement other numbers of functional transistors.

[0035] Figure 2 The reference cross-sections used in the accompanying figures are further illustrated, including... Figures 3A to 7FSection AA is in the plane of the channel in the fin structure 206 between the source / drain regions 218 on both sides. Section BB is in the plane perpendicular to section AA and passes through the source / drain regions 218 in the fin. Section CC is in the plane along another channel in the fin structure 206. For clarity, the following figures refer to these reference sections. In some figures, some reference numerals for parts or features shown may be omitted to avoid confusion with other parts or features in order to facilitate the depiction of the figures.

[0036] As mentioned above, providing Figure 2 As an example. Other examples may be similar. Figure 2 The descriptions are different.

[0037] Figures 3A to 3D This is a diagram of the exemplary embodiment 300 described herein. Exemplary embodiment 300 includes an example of a fin structure 206 forming a transistor in a device region 202 of a semiconductor device 200. Figures 3A to 3D From Figure 2 The cross-section BB in the figure shows a perspective view of the device area 202. (Refer to...) Figure 3A An exemplary embodiment 300 includes a semiconductor processing operation in which transistors are formed in a device region 202 in relation to a substrate 204 therein and / or on therein.

[0038] like Figure 3B As shown, a fin structure 206 is formed in a substrate 204 within a device region 202. In some embodiments, a pattern in a photoresist layer is used to form the fin structure 206. In these embodiments, a deposition apparatus 102 forms a photoresist layer on the substrate 204. An exposure apparatus 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus 106 develops and removes portions of the photoresist layer to expose the pattern. An etching apparatus 108 etches into the substrate 204 to form the fin structure 206. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal apparatus removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to the pattern-based fin structure 206.

[0039] like Figure 3C As shown, the STI layer 302 is formed between the fin structures 206. The deposition apparatus 102 utilizes CVD, PVD, ALD, and other technologies described above. Figure 1The aforementioned deposition technique, and / or another deposition technique, is used to deposit the STI layer 302. In some embodiments, the height of the STI layer 302 is greater than the height of the fin structure 206. In these embodiments, the planarization apparatus 110 performs a planarization (or polishing) operation to planarize the STI layer 302 such that the top surface of the STI layer 302 is substantially flat and smooth, and that the top surface of the STI layer 302 and the top surface of the fin structure 206 have approximately the same height. The planarization operation can increase the uniformity of the STI region 208 formed by the STI layer 302 in the subsequent etch-back operation.

[0040] like Figure 3D As shown, in an etch-back operation, the STI layer 302 is etched to expose a portion of the fin structure 206. The etching apparatus 108 uses plasma etching, wet chemical etching, and / or other types of etching techniques to etch a portion of the STI layer 302. The remaining portion of the STI layer 302 located between the fin structures 206 comprises the STI region 208. In some embodiments, the STI layer 302 is etched such that the height of the exposed portion of the fin structure 206 (e.g., the portion of the fin structure 206 above the top surface of the STI region 208) is the same throughout the device region 202. In some embodiments, a first portion of the STI layer 302 in the device region 202 and a second portion of the STI layer 302 in the device region 202 are etched such that the height of the exposed portion of a first subset of the fin structures 206 and the height of the exposed portion of a second subset of the fin structures 206 are different, allowing the fin height to be adjusted to achieve specific performance characteristics of the device region 202.

[0041] As mentioned above, providing Figures 3A to 3D As an example. Other examples may be similar. Figures 3A to 3D The descriptions are different.

[0042] Figures 4A to 4C This is a diagram of the exemplary embodiment 400 described herein. Exemplary embodiment 400 includes an example of forming a source / drain region in a source / drain region 218 of a device region 202 of a semiconductor device 200. Figures 4A to 4C It is from device area 202. Figure 2 The angle of section AA in the diagram is shown. In some embodiments, the operation described in conjunction with exemplary embodiment 400 is in conjunction with... Figures 3A to 3D The process described is carried out after the fin formation process.

[0043] like Figure 4AAs shown, a dummy gate structure 210 is formed in device region 202. The dummy gate structure 210 is formed and included above and around the sides of fin structure 206, such that the dummy gate structure 210 surrounds fin structure 206 on at least three sides. The dummy gate structure 210 is formed as a placeholder for the actual gate structure to be formed for a transistor (e.g., replacing a high-k gate structure or a metal gate structure), which is included in device region 202. The dummy gate structure 210 can be formed as part of an alternative gate fabrication process, which allows other layers and / or structures to be formed prior to the formation of the alternative gate structure.

[0044] The dummy gate structure 210 includes a gate dielectric layer 212, a gate electrode layer 214, and a hard mask layer 216. Each gate dielectric layer 212 may each include a dielectric oxide layer. As an example, each gate dielectric layer 212 may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods (e.g., via deposition equipment 102). Each gate electrode layer 214 may each include a polysilicon layer or other suitable layer. For example, the gate electrode layer 214 may be formed by a suitable deposition process such as LPCVD or PECVD (e.g., via deposition equipment 102). Each hard mask layer 216 may each include any material suitable for patterning the gate electrode layer 214 to a specific size and / or properties. Examples include silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. The hard mask layer 216 may be deposited by CVD, PVD, ALD, or other deposition techniques (e.g., via deposition equipment 102).

[0045] like Figure 4A As further shown, a sealing spacer layer 402 is included on the sidewall of the dummy gate structure 210. The sealing spacer layer 402 can be deposited conformally (e.g., via deposition apparatus 102) and may include silicon oxycarbide (SiOC), nitrogen-free SiOC, or other suitable materials. The sealing spacer layer 402 can be formed via an ALD operation, which involves sequentially supplying various types of precursor gases of silicon (Si) and carbon (C) in multiple alternating cycles to form the sealing spacer layer 402.

[0046] like Figure 4A As further shown, a bulk spacer layer 404 may be formed on the sealing spacer layer 402. The bulk spacer layer 404 may be formed of a material similar to that of the sealing spacer layer 402. However, the bulk spacer layer 404 may be formed without plasma surface treatment for the sealing spacer layer 402. Furthermore, the bulk spacer layer 404 may be formed to a greater thickness than the sealing spacer layer 402.

[0047] In some embodiments, the sealing spacer layer 402 and the bulk spacer layer 404 are conformally deposited (e.g., by deposition apparatus 102) on the dummy gate structure 210 and the fin structure 206. Then, the sealing spacer layer 402 and the bulk spacer layer 404 are patterned (e.g., by deposition apparatus 102, exposure apparatus 104, and development apparatus 106) and etched (e.g., by etching apparatus 108) to remove the sealing spacer layer 402 and the bulk spacer layer 404 from the top of the dummy gate structure 210 and the top of the fin structure 206.

[0048] like Figure 4B As shown, during the etching operation, a recess 406 is formed in the fin structure 206 located in the device region 202 between the dummy gate structures 210. The etching operation may be referred to as a first strained source / drain (SSD) etching operation, and the recess 406 may be referred to as a strained source / drain recess. In some embodiments, the first etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique.

[0049] In some implementations, multiple etching operations are performed to form recesses 406 for different types of transistors. For example, a photoresist layer may be formed over and / or on a first subset of the fin structure 206 and over and / or on a first subset of the dummy gate structure 210, such that a second subset of the fin structure 206 is located between the second subsets of the dummy gate structure 210, allowing p-type source / drain regions and n-type source / drain regions to be formed in separate epitaxial operations.

[0050] like Figure 4C As shown, source / drain regions 408 are formed in recesses 406 in device region 202 of semiconductor device 200 above substrate 204. Deposition apparatus 102 forms source / drain regions 408 through an epitaxial operation in which a layer of epitaxial material is deposited in the recesses 406, such that a layer of p-type source / drain regions and / or a layer of n-type source / drain regions is formed through epitaxial growth in a specific crystal orientation. Source / drain regions 408 are included between dummy gate structures 210 and are at least partially located below and / or below the dummy gate structures 210. Furthermore, source / drain regions 408 extend at least partially over the top surface of fin structure 206.

[0051] The material used to form the source / drain region 408 (e.g., silicon, gallium, or other types of semiconductor materials) may be doped with p-type dopants (e.g., dopants that include electron acceptor atoms that generate holes in the material), n-type dopants (e.g., dopants that include electron donor atoms that generate mobile electrons in the material), and / or another type of dopant. The material can be doped by adding impurities (e.g., p-type dopants, n-type dopants) to the source gas used during epitaxial operation. Examples of p-type dopants that can be used for epitaxial operation include boron (B) or germanium (Ge). The resulting material for the p-type source / drain region includes silicon germanium (Si). x Ge 1-x (where x can range from about 0 to about 100) or another type of p-doped semiconductor material. Examples of n-type dopants that can be used for epitaxial operations include phosphorus (P) or arsenic (As). Materials resulting in n-type source / drain regions include silicon phosphide (Si). x P y (or another type of n-doped semiconductor material.)

[0052] As mentioned above, providing Figures 4A to 4C As an example. Other examples may be similar. Figures 4A to 4C The descriptions are different.

[0053] Figures 5A to 5D This is a diagram of the exemplary embodiment 500 described herein. The exemplary embodiment 500 includes an exemplary dummy gate replacement process, in which the dummy gate structure 210 is replaced by a high-k gate structure and / or a metal gate structure. Figures 5A to 5D It is from device area 202. Figure 2 The perspective view of section AA is shown in the figure.

[0054] like Figure 5AAs shown, a contact etch stop layer (CESL) 502 is conformally deposited (e.g., via deposition apparatus 102) over the source / drain region 408, over the dummy gate structure 210, and on the sidewalls of the bulk spacer layer 404. CESL 502 provides a mechanism to stop the etching process when forming contacts or vias in the device region 202. CESL 502 may be formed of a dielectric material having a different etch selectivity than adjacent layers or elements. CESL 502 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Furthermore, CESL 502 may include or may be silicon nitride (Si). x N y CESL502 can be deposited using deposition processes such as ALD, CVD, or other deposition techniques. It can be made from silicon carbon nitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxide (SiCO), or combinations thereof.

[0055] like Figure 5B As shown, an interlayer dielectric (ILD) layer 504 (e.g., via deposition apparatus 102) is formed above and / or on CESL 502. The ILD layer 504 fills the region between the dummy gate structures 210 above the source / drain regions 408. The ILD layer 504 is formed to allow for replacement gate structure processes in device region 202, wherein a metal gate structure is formed to replace the dummy gate structure 210. The ILD layer 504 may be referred to as the ILD zero (ILD0) layer.

[0056] In some embodiments, the ILD layer 504 is formed to a height (or thickness) such that the ILD layer 504 covers the dummy gate structure 210. In these embodiments, a subsequent CMP operation (e.g., by planarization device 110) is performed to planarize the ILD layer 504 such that the top surface of the ILD layer 504 is at approximately the same height as the top surface of the dummy gate structure 210. This increases the uniformity of the ILD layer 504.

[0057] like Figure 5CAs shown, a gate replacement operation (e.g., via one or more of semiconductor processing devices 102-112) is performed to remove the dummy gate structure 210 from device region 202. Removing the dummy gate structure 210 leaves an opening (or groove) 506 between the bulk spacer layers 404 and between the source / drain regions 408. The dummy gate structure 210 may be removed in one or more etching operations, including plasma etching techniques, which may include wet chemical etching techniques and / or another type of etching technique.

[0058] like Figure 5D As shown, the gate replacement operation continues, wherein the deposition apparatus 102 and / or the coating apparatus 112 form a gate structure (e.g., a replacement gate structure) 508 in the openings 506 between the bulk spacer layers 404 and between the source / drain regions 408. The gate structure 508 may include a metal gate structure, a high-k gate structure, or other types of gate structures. The gate structure 508 may include an interface layer (not shown), a high-k dielectric layer 510, a work function tuning layer 512, and a metal electrode structure 514 formed therein to form the gate structure 508. In some embodiments, the gate structure 508 may include other components of the material and / or layers.

[0059] As mentioned above, providing Figures 5A to 5D As an example. Other examples may be similar. Figures 5A to 5D The descriptions are different.

[0060] Figures 6A to 6N This is a diagram of an exemplary embodiment 600 described herein. Exemplary embodiment 600 includes an example of a conductive structure for a semiconductor device 200 and an associated metal silicide layer. Figures 6A to 6N It is from device area 202. Figure 2 The perspective view of section AA is shown in the figure.

[0061] like Figure 6A As shown, an opening (or recess) 602 is formed to penetrate one or more dielectric layers and reach the source / drain region 408. Specifically, the CESL 502 and ILD layer 504 located between the gate structure 508 in the device region 202 are etched to form an opening 602 between the gate structure 508 and the source / drain region 408. In some embodiments, the opening 602 is formed in a portion of the source / drain region 408 such that the recess extends into a portion of the source / drain region 408. The opening 602 includes a bottom surface 602a and a plurality of sidewalls 602b, wherein the bottom surface 602a corresponds to the top surface of the associated source / drain region 408, and the plurality of sidewalls 602b correspond to the sides of the CESL 502 and / or ILD layer 504.

[0062] In some embodiments, a pattern in the photoresist layer is used to form the opening 602. In these embodiments, deposition equipment 102 forms a photoresist layer on ILD layer 504 and gate structure 508. Exposure equipment 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development equipment 106 develops and removes a portion of the photoresist layer to expose the pattern. Etching equipment 108 etches into ILD layer 504 to form the opening 602. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, photoresist removal equipment removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the opening 602.

[0063] In some embodiments, a pre-cleaning operation is performed to clean the surfaces in the opening 602 (e.g., bottom surface 602a, sidewalls 602b). Specifically, the semiconductor device 200 may be placed in a processing chamber (e.g., deposition apparatus 102 including a pre-cleaned processing chamber), the processing chamber may be evacuated to at least a partial vacuum, and the surfaces in the pre-cleaned opening 602 may be cleaned using a plasma-based and / or chemical-based pre-cleaning agent. The pre-cleaning operation is performed to clean (e.g., remove) oxides and other contaminants or byproducts from the top surface of the source / drain region 408 and / or other surfaces in the opening 602, which may have been formed after the opening 602 was formed.

[0064] like Figure 6B As shown, a nitride layer 604 is formed on the sidewall 602b in the opening 602. For example, the deposition apparatus 102 forms the nitride layer 604 on the sidewall 602b in the opening 602. The nitride layer 604 may include silicon nitride (Si). x N y The nitride layer 604 may be a CVD, PVD, ALD, and / or other type of deposition operation deposited onto the sidewall 602b in the opening 602. In some embodiments, a barrier layer may be formed on the bottom surface 602a in the opening 602 prior to the formation of the nitride layer 604 to prevent the nitride layer 604 from forming on the source / drain region 408. The barrier layer may be removed after the formation of the nitride layer 604.

[0065] like Figure 6CAs shown, after forming the nitride layer 604, a metal silicide layer 606 is formed on the source / drain region 408 in the opening 602. For example, the deposition apparatus 102 forms the metal silicide layer 606 on the source / drain region 408 in the opening 602. The metal silicide layer 606 can be formed on the source / drain region 408 to reduce the contact resistance between the source / drain region 408 and the conductive structure (e.g., source / drain contacts) to be formed in the opening 602 above the source / drain region 408. Furthermore, the metal silicide layer 606 can protect the source / drain region 408 from oxidation and / or other contamination. The metal silicide layer 606 includes titanium silicide (TiSi). x ( ) layer or another type of metal silicide layer.

[0066] A metal silicide layer 606 is formed during an immersion process, which is performed as part of a plasma-based deposition operation, such as LPCVD or PECVD. The deposition apparatus 102 provides a flow of metal precursor along with a flow of reaction gas (e.g., hydrogen (H2)) into opening 602, or another type of reactant or process gas. The metal precursor is, for example, a titanium precursor (e.g., titanium chloride, TiCl). x (e.g., TiCl4) or another type of titanium precursor. Plasma (e.g., argon (Ar) plasma, helium (He) plasma, nitrogen (N2) plasma, or other types of plasma) is also provided to the opening 602. Titanium (Ti) of titanium chloride, silicon (Si) of the source / drain region, hydrogen (H) in the reaction gas, and plasma reaction are used to selectively form a metal silicide layer 606 (e.g., titanium silicide, TiSi) on the top surface of the source / drain region 408 (which corresponds to the bottom surface 602a in the opening 602). x )layer).

[0067] Gas-phase reactions in plasma-based deposition operations may include: The argon plasma is formed by argon gas, and the hydrochloric acid (HCl) is formed by titanium chloride (TiCl4) and hydrogen gas. The reactions occurring in the source / drain region 408 within opening 602 may include: Argon plasma is used for surface treatment to form mobile silicon atoms in the source / drain region 408. The surface treatment causes the mobile silicon atoms to diffuse towards the top surface of the source / drain region 408, resulting in a silicon-rich surface of the source / drain region 408. The mobile silicon atoms and titanium in titanium chloride react here to selectively form a titanium silicide layer (e.g., a metal silicide layer 606) on the silicon-rich surface of the source / drain region 408. Chlorine (Cl) in titanium chloride and hydrogen in hydrogen gas also react to form hydrochloric acid (HCl) as a byproduct.

[0068] The duration of the plasma-based deposition operation can be included in the range of about 80 seconds to about 160 seconds to form a metal silicide layer 606 of sufficient thickness and to minimize the growth of pure titanium on the metal silicide layer 606. However, other duration values ​​are within the scope of this disclosure. Plasma-based deposition operations can be performed when the temperature in the processing chamber of the deposition apparatus 102 is in the range of about 300 degrees Celsius to about 500 degrees Celsius to provide sufficient metal silicide formation and maintain a sufficiently low titanium deposition rate (e.g., such that the titanium chloride etch rate of titanium on the source / drain region 408 is greater than the titanium deposition rate on the source / drain region 408). However, other values ​​in the temperature range are also within the scope of this disclosure. The pressure in the processing chamber can be in the range of about 1 Torr to about 10 Torr to provide sufficient pressure to promote the reaction between titanium chloride and the source / drain region 408 and to minimize the possibility of titanium chloride condensation in the processing chamber. However, other pressure values ​​are also within the scope of this disclosure. The plasma operating power can range from about 100 watts to about 1500 watts to facilitate sufficient silicon migration in the source / drain region 408 and minimize plasma damage to other structures of the semiconductor device 200. However, other values ​​for operating power are within the scope of this disclosure.

[0069] like Figure 6C As further shown, in the plasma-based deposition operation, a silicon nitride layer 608 is formed on the nitride layer 604 and the metal silicide layer 606. The titanium of titanium chloride, the silicon (e.g., silicon nitride) of the nitride layer 604, the reactive gas, and the plasma reaction selectively form titanium silicon nitride (TiSi). x N y A layer (e.g., a metal silicon nitride layer 608) is on the nitride layer 604.

[0070] The silicon nitride layer 608 can be used as an adhesive layer to promote adhesion between the ILD 504 or the nitride layer 604 and the metal source / drain contacts to be formed in the opening 602, and to minimize the critical dimension (or cross-sectional width) of the reduced metal source / drain contacts. This increases gap-filling performance (or the performance of filling the opening 602 with conductive material to form the metal source / drain contacts), which reduces defect formation in the metal source / drain contacts. The thickness of the silicon nitride layer 608 on the nitride layer 604 can range from about 5 nanometers to about 11 nanometers, as the aforementioned source / drain contacts will be formed in the opening 602, due to the formation of the silicon nitride layer 606 to a sufficient thickness and minimizing the critical dimension shrinkage of the metal source / drain contacts. However, other values ​​for the thickness of the silicon nitride layer 608 are also within the scope of this disclosure.

[0071] Titanium chloride, silicon in the titanium silicide layer, reactant gases, and plasma reaction are used to selectively form titanium silicon nitride (TiSi) on the metal silicide layer 606. x N y A layer (e.g., a metal silicon nitride layer 608) is formed on top of the metal silicon nitride layer 606 due to the reaction of the titanium precursor with silicon in the metal silicon nitride layer 606. Nitrogen originates from nitrogen in the nitride layer 604 on the sidewall 602b of the opening and / or from nitrogen in the plasma used in the plasma-based deposition operation.

[0072] Figure 6D A perspective view of device region 202 of semiconductor device 200 after the formation of metal silicide layer 606. (See diagram below.) Figure 6D As shown, a metal silicide layer 606 is included on the source / drain region 408 at the bottom of the opening 602. The opening 602 may be formed to expose a portion of the top surface of the source / drain region 408, depending on the location where the source / drain contacts will subsequently be formed to the source / drain region 408. For example, the opening 602 may be formed to allow the source / drain contacts to be located on a specific side of the source / drain region 408 to increase the surface area of ​​the source / drain contacts in physical connection with the source / drain region 408 and / or for other purposes.

[0073] like Figure 6EAs shown, metal source / drain contacts (MDs) 610 (e.g., conductive structures) are formed in openings 602 in device region 202. Specifically, source / drain contacts 610 are formed over source / drain region 408, over and / or on metal silicide layer 606, and / or on metal silicon nitride layer 608. In some embodiments, where an additional barrier layer is included on metal silicon nitride layer 608, metal source / drain contacts 610 are formed on a barrier layer (e.g., tantalum nitride barrier layer or titanium nitride barrier layer). In some embodiments, metal source / drain contacts 610 are formed in openings 602 without an additional barrier layer and may be referred to as barrier-free metal source / drain contacts. Deposition apparatus 102 and / or coating apparatus 112 use CVD technology, PVD technology, ALD technology, electroplating technology, and combinations thereof. Figure 1 Another deposition technique described, and / or combinations thereof. Figure 1 Other deposition techniques than those described are used to deposit the source / drain contacts 610. The deposition apparatus 102 fills the opening 602 with a conductive material to form the metal source / drain contacts 610. The metal source / drain contacts 610 include ruthenium (Ru) metal source / drain contacts, tungsten (W) metal source / drain contacts, cobalt (Co) metal source / drain contacts, or metal source / drain contacts formed of another metal.

[0074] like Figure 6F As shown, one or more dielectric layers are formed above and / or on the gate structure 508 and above and / or on the metal source / drain contacts 610. The deposition apparatus 102 may deposit one or more dielectric layers using CVD, PVD, ALD, and / or another deposition technique. The one or more dielectric layers include an etchstop layer (ESL) 612, an ILD layer 614 (e.g., ILD1 layer, ILD2 layer), and / or another dielectric layer.

[0075] like Figure 6GAs shown, an opening (or groove) 616 is formed in and through the ILD layer 614, in and through the ESL 612, and reaches the top surface of the metal source / drain contact 610. In some embodiments, a pattern in the photoresist layer is used to form the opening 616. In these embodiments, a deposition apparatus 102 forms a photoresist layer on the ILD layer 614. An exposure apparatus 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus 106 develops and removes portions of the photoresist layer to expose the pattern. An etching apparatus 108 etches into the ILD layer 614 and the ESL 612 to form the opening 616. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal apparatus removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-forming opening 616.

[0076] like Figure 6H As shown, source / drain interconnects (vias to source / drain or VDs) 618 (e.g., conductive structures) are formed in openings 616 in device region 202. Specifically, source / drain interconnects 618 are formed on metal source / drain contacts 610, such that source / drain interconnects 618 and metal source / drain contacts 610 are electrically and physically connected. Deposition apparatus 102 and / or coating apparatus 112 use CVD technology, PVD technology, ALD technology, electroplating technology, and the foregoing combination. Figure 1 Another deposition technique described, and / or combinations thereof. Figure 1 Other deposition techniques besides those described are used to deposit the source / drain interconnect 618. The deposition apparatus 102 fills the opening 616 with a conductive material to form the source / drain interconnect 618.

[0077] The source / drain interconnect 618 includes ruthenium (Ru) metal source / drain contacts, tungsten (W) metal source / drain contacts, cobalt (Co) metal source / drain contacts, or metal source / drain contacts formed of another metal. Specifically, the source / drain interconnect 618 and the metal source / drain contacts 610 include the same type of material, such as ruthenium (Ru). Therefore, the source / drain interconnect 618 and the metal source / drain contact 610 are made of the same conductive material, which reduces and / or minimizes the occurrence of solid solution between the source / drain interconnect 618 and the metal source / drain contact 610, reduces the occurrence of electrochemical corrosion between the source / drain interconnect 618 and the metal source / drain contact 610, and / or reduces the occurrence of phase transitions in the source / drain interconnect 618 and the metal source / drain contact 610. This reduces the contact resistance between the source / drain interconnect 618 and the metal source / drain contact 610, reduces the surface roughness of the source / drain interconnect 618 and the metal source / drain contact 610, and / or reduces the separation of the source / drain interconnect 618 and the metal source / drain contact 610, etc. Because the source / drain interconnect 618 and the metal source / drain contact 610 use the same material, the contact resistance achievable by the source / drain interconnect structure 618 can be from about 30 ohms to about 80 ohms. Similarly, because the source / drain interconnect 618 and the metal source / drain contact 610 use the same material, the contact resistance achievable by the metal source / drain contact 610 can be from about 30 ohms to about 80 ohms. However, other values ​​for the contact resistance of the source / drain contact 610 and the source / drain interconnect structure 618 are also within the scope of this disclosure.

[0078] like Figure 6I As shown, one or more dielectric layers are formed above and / or on the ILD layer 614 and above and / or on the source / drain interconnect structure 618. The deposition apparatus 102 may deposit one or more dielectric layers using CVD, PVD, ALD, and / or another deposition technique. The one or more dielectric layers include ESL 620, ILD layer 622 (e.g., ILD2 layer or another ILD layer), and / or another dielectric layer.

[0079] like Figure 6JAs shown, an opening (or groove) 624 is formed in and through the ILD layer 622, in and through the ESL 620, and reaches the top surface of the source / drain interconnect structure 618. In some embodiments, a pattern in the photoresist layer is used to form the opening 624. In these embodiments, a deposition apparatus 102 forms a photoresist layer on the ILD layer 622. An exposure apparatus 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus 106 develops and removes a portion of the photoresist layer to expose the pattern. An etching apparatus 108 etches into the ILD layer 622 and the ESL 620 to form the opening 624. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, a photoresist removal apparatus removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique based on pattern-forming opening 624.

[0080] like Figure 6K As shown, a barrier layer 626 is formed in the opening 624. The barrier layer 626 may include tantalum nitride (Ta x N y Barrier layer, titanium nitride (Ti) x N y Barrier layer 626, or other types of barrier layer. Deposition apparatus 102 may use CVD, PVD, ALD and / or another deposition technique to deposit barrier layer 626.

[0081] like Figure 6L As shown, a substrate 628 is formed in an opening 624 on a barrier layer 626. The substrate 628 and barrier layer 626 may be included to reduce, minimize, and / or prevent copper electromigration from a back end of line (BEOL) layer, which will be formed in the opening 624 leading to other areas of the semiconductor device 200 (which may lead to material degradation and reduced device performance). The substrate 628 comprises cobalt (Co) or another type of metal substrate. The deposition apparatus 102 may use CVD, PVD, ALD, and / or another deposition technique to deposit the substrate 628.

[0082] like Figure 6MAs shown, opening 624 is filled with a conductive material, such as copper (Cu), to form a BEOL metallization structure 630. The BEOL metallization structure 630 may include a metal-zero (MO) metalline, a via-one (V1) metal via, and / or other types of BEOL metallization layers. Deposition equipment 102 and / or coating equipment 112 use CVD technology, PVD technology, ALD technology, electroplating technology, and combinations thereof. Figure 1 Another deposition technique described, and / or in addition to the above, Figure 1 Other deposition techniques described were used to deposit BEOL metallized structures 630.

[0083] like Figure 6N As shown, a capping layer 632 is formed on the BEOL metallization structure 630. The capping layer 632 is included to reduce, minimize, and / or prevent copper from migrating upwards into other BEOL layers within the semiconductor device 200. The capping layer 632 includes cobalt (Co) or other types of metallic capping layers. The deposition apparatus 102 may use CVD, PVD, ALD, and / or another deposition technique to deposit the capping layer 632.

[0084] As mentioned above, providing Figures 6A to 6N As an example, other examples may be related to Figure 6A. Figure 6N The descriptions differ. In some implementations, they may be combined with... Figures 6A to 6N The described metal silicide and homogeneous conductive structure formation technique is used to form metal gate contacts and gate interconnect structures above the gate structure 508 or another transistor structure in the device region 202 of the semiconductor device 200.

[0085] 7A to Figure 7F This is a diagram of the exemplary embodiment 700 described herein. Exemplary embodiment 700 includes alternative examples of forming conductive structures and associated metal silicide layers for a semiconductor device 200. Specifically, exemplary embodiment 700 includes examples of forming integrated (monolithic) contacts and interconnects extending from the source / drain regions (or another type of transistor structure) to a BEOL metallization layer (e.g., a MO metal line or another type of BEOL metallization layer). Figures 7A to 7F It is from device area 202. Figure 2 The perspective view of section CC is shown in the figure.

[0086] like Figure 7A As shown, device region 202 may include fin structure 206. Silicon oxide (SiO2) xLayer 702 is included above and / or on fin structure 206, and silicon nitride (Si) is also included. x N y Layer 704 is included above and / or on silicon oxide layer 702. Deposition apparatus 102 uses CVD technology, PVD technology, ALD technology, and / or another deposition technology to deposit silicon oxide layer 702 and silicon nitride layer 704.

[0087] like Figure 7A As further shown, source / drain regions 408 are included above and / or on fin structure 206. Furthermore, source / drain regions 408 are included within (or between portions thereof) the silicon oxide layer 702. Figure 7A As shown in the example, a portion of the silicon nitride layer 704 may extend down into a portion of the silicon oxide layer 702 in a region along the inclined or angled surface of the source / drain region 408.

[0088] like Figure 7B As shown, another silicon oxide layer 706 is formed above and / or on the silicon nitride layer 704 to form SiO. x / Si x N y / SiO x Stacking. Deposition apparatus 102 uses CVD, PVD, ALD, and / or another deposition technique to deposit silicon oxide layer 706. In some embodiments, one or more of silicon oxide layers 702 and / or 706, in addition to ILD 614, are included in device region 202 of the semiconductor device. In some embodiments, one or more of silicon oxide layers 702 and / or 706 serve as alternatives to ILD 614, and device region 202 of the semiconductor device includes silicon oxide layers 702 or 706. In some embodiments, silicon nitride layer 704 is included in device region 202 of the semiconductor device, in addition to CESL 502, nitride layer 604, and / or ESL 602. In some embodiments, silicon nitride layer 704 is included in device region 202 of the semiconductor device as an alternative to CESL 502, nitride layer 604, and / or ESL 612.

[0089] like Figure 7C As shown, an opening (or groove 708) is formed in and through the silicon oxide layer 706, in and through the silicon nitride layer 704, and reaches the source / drain region 408. In some embodiments, the opening 708 is formed in a portion of the source / drain region 408, as illustrated in the example of Figure 7C. The opening 708 includes a bottom surface 708a (which corresponds to the top surface of the source / drain region 408) and a plurality of sidewalls 708b (which correspond to the sides of the silicon oxide layer 706 and the sides of the silicon nitride layer 704).

[0090] In some embodiments, the pattern in the photoresist layer is used to form the opening 708. In these embodiments, deposition apparatus 102 forms a photoresist layer on silicon oxide layer 706. Exposure apparatus 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development apparatus 106 develops and removes portions of the photoresist layer to expose the pattern. Etching apparatus 108 etches into silicon oxide layer 706 and silicon nitride layer 704 to form the opening 708. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching technique. In some embodiments, photoresist removal apparatus removes the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based formation of the opening 708.

[0091] In some embodiments, the sidewall 708b curves within the lower region 710a of the opening 708 through the silicon nitride layer 704, and is generally straight within the upper region 710b of the opening 708 through the silicon oxide layer 706. In some embodiments, the sidewall 708b is inclined or tapered within the upper region 710b of the opening 708. As further shown in Figure 7C, the opening 708 includes a neck region 712 located at the bottom of the silicon oxide layer 706, which is adjacent to the silicon nitride layer 704. The neck region 712 is located between the lower region 710a and the upper region 710b. The opening 708 transitions between the lower region 710a and the upper region 710b in the neck region 712.

[0092] The neck region 712 includes a sharp, tapered, sloping, or curved portion of the sidewall 708b. The width of the opening 708 transitions (e.g., rapidly increases) from a first width at the top of the lower region 710a to the width of the upper region 710b. The neck region 712 appears or is formed due to the difference in etching rates between the silicon nitride layer 704 and the silicon oxide layer 706. Specifically, the etching rate of the silicon oxide layer 706 is greater than that of the silicon nitride layer 704. Because the etchant removes material from the silicon oxide layer 706 faster than from the silicon nitride layer 704, the width of the opening 708 in the upper region 710b of the silicon oxide layer 706 is greater than the width of the opening 708 in the lower region 710a of the silicon nitride layer.

[0093] like Figure 7D As shown, the metal silicide layer 606 (e.g., titanium silicide, TiSi) x A source / drain region 408 is formed in the opening 708. Additionally, a metal silicon nitride layer 608 (e.g., titanium silicon nitride, TiSi) is formed on the source / drain region 408.x N y The metal silicide layer 606 and the metal silicon nitride layer 608 are formed on a portion of the sidewall 708b in the opening 708. The metal silicide layer 606 and the metal silicon nitride layer 608 are formed in a plasma-based deposition operation, which can be performed by the deposition apparatus 102 as described above in conjunction with Figure 6C. Therefore, the metal silicide layer 606 is selectively formed on the source / drain 408, and the metal silicon nitride layer 608 is selectively formed on the lower region 710a of the opening 708 corresponding to the portion of the sidewall 708b where the silicon nitride layer 704 is located. Due to the use of a titanium precursor (e.g., titanium chloride, TiCl) in the plasma-based deposition operation… x (e.g., TiCl4), and because a silicon-rich surface is formed on the source / drain region 408 and the silicon nitride layer 704, the metal silicon nitride layer 608 is selectively formed on the portion of the sidewall 708b corresponding to the silicon nitride layer 704 (rather than on the portion of the sidewall 708b corresponding to the silicon oxide layer 706). Therefore, the metal silicon nitride layer 608 is included below the silicon oxide layer 706 and below the neck region 712 in the opening 708. The metal silicon nitride layer 608 is also included above the silicon oxide layer 702.

[0094] like Figure 7E As shown, opening 708 is filled with conductive material to form integrated contacts and interconnects 714 within opening 708. Deposition equipment 102 and / or coating equipment 112 use the following techniques to deposit the integrated contacts and interconnects 714 in opening 708: CVD technology, PVD technology, ALD technology, electroplating technology, and combinations thereof. Figure 1 Another deposition technique described, and / or in combination with the foregoing. Figure 1 Deposition techniques beyond those described. Titanium precursors used in plasma-based deposition operations (e.g., titanium chloride, TiCl) x For example, TiCl4), and thus silicon-rich surface contacts and interconnects 714 are formed on the source / drain region 408 and the silicon nitride layer 704 above and / or on the metal silicide layer 606 in the opening 708, above and / or on the metal silicon nitride layer 608, and the sidewall 708b corresponding to the portion above and / or on the silicon oxide layer 706 in the opening 708. The integrated contacts and interconnects 714 comprise homogeneous conductive materials, such as ruthenium (Ru) or other metals, and are unaffected by defects such as solid solution and current corrosion, which may occur in separate (two-part) metal source / drain contacts and source / drain interconnects formed of their respective and different types of conductive materials.

[0095] like Figure 7EAs further shown, the integrated contact and interconnect 714 conform to the shape or outline of the opening 708. Therefore, the integrated contact and interconnect 714 includes a lower region 716a in the silicon nitride layer 704, an upper region 716b in the silicon oxide layer 706, and a neck region 718 (which transitions between the lower region 716a and the upper region 716b) between the lower region 716a and the upper region 716b. The lower region 710a of the opening 708 is filled to form the lower region 716a above and / or on the metal silicide layer 606 and above and / or on the metal silicon nitride layer 608; the neck region 712 of the opening 708 is filled to form the neck region 718; and the upper region 710b is filled to form the upper region 716b. The lower region 716a, the neck region 718, and the upper region 716b are formed in a single deposition operation or in the same deposition operation (e.g., without forming any intermediate dielectric layer or etch stop layer).

[0096] The lower region 716a is connected to the source / drain region 408 via the metal silicide layer 606 (and is electrically connected thereto). The lower region 716a is tapered or curved between the neck region 718 and the bottom surface 720a of the lower region 716a. After planarization by the planarization device 110, the height of the top surface 720b of the upper region 716b is approximately equal to the height of the top surface 722 of the silicon oxide layer 706.

[0097] like Figure 7F As shown, a BEOL metallization structure 630 is formed on the integrated contact and interconnect 714, such that the BEOL metallization structure 630 is electrically connected to the top surface 720b of the upper region 716b of the integrated contact and interconnect 714. In some embodiments, one or more barrier layers and / or liner layers are included between the BEOL metallization structure 630 and the integrated contact and interconnect 714. The BEOL metallization structure 630 may include MO metal lines, V1 metal vias, and / or other types of BEOL metallization layers. The deposition apparatus 102 and / or coating apparatus 112 use CVD technology, PVD technology, ALD technology, electroplating technology, and the foregoing combination. Figure 1 Another deposition technique described, and / or in addition to the above, Figure 1 Deposition techniques beyond those described were used to deposit BEOL metallized structures 630.

[0098] like Figure 7FAs further shown, the integrated contact and interconnect 714 extends from the top surface of the source / drain region 408 (or from the metal silicide layer 606 on the top surface of the source / drain region 408) to the bottom surface of the BEOL metallization structure 630. Therefore, the integrated contact and interconnect 714 comprises a single, and / or uniform conductive structure formed of homogeneous conductive material physically and / or electrically connected to the source / drain region 408 and the BEOL metallization structure 630 (e.g., in contrast to separate metal source / drain contacts physically and electrically connected to the source / drain region 408 and separate source / drain interconnect structures physically and electrically connected to the BEOL metallization structure 630). The integrated contact and interconnect 714 also reduces the number of interlayer interfaces between the source / drain region 408 and the BEOL metallization structure 630, which further reduces the contact resistance between the source / drain region 408 and the BEOL metallization structure 630.

[0099] As mentioned above, providing Figures 7A to 7F As an example. Other examples may be similar. Figures 7A to 7F The descriptions differ. In some implementations, they may be combined. Figures 7A to 7F The described metal silicide and homogeneous conductive structure formation techniques are used to form metal gate contacts and gate interconnect structures above the gate structure 508 or another transistor structure in the device region 202 of the semiconductor device 200.

[0100] Figure 8 This is a diagram illustrating the exemplary dimensions of the semiconductor device 200, which is a part of the description herein. Specifically, the exemplary dimensions are associated with one or more structures in device region 202 of the semiconductor device 200.

[0101] like Figure 8 As shown, exemplary dimension 802 includes the height or thickness of silicon oxide layer 706. In some embodiments, the height or thickness of silicon oxide layer 706 ranges from about 5 nanometers to about 50 nanometers to provide sufficient height for forming integrated contacts and interconnects 714 without unduly increasing the height of semiconductor device 200. However, other values ​​for exemplary dimension 802 are also within the scope of this disclosure.

[0102] like Figure 8As further illustrated, exemplary dimension 804 includes the height or thickness of silicon nitride layer 704. In some embodiments, the height or thickness of silicon nitride layer 704 ranges from about 5 nanometers to about 50 nanometers to provide sufficient height for forming integrated contacts and interconnects 714 without unduly increasing the height of semiconductor device 200. However, other values ​​for exemplary dimension 804 are also within the scope of this disclosure. In some embodiments, the ratio between the thickness of silicon nitride layer 704 (e.g., exemplary dimension 804) and the thickness of silicon oxide layer 706 (e.g., exemplary dimension 802) is from about 1:10 to about 10:1 to facilitate the formation of neck regions 718 in integrated contacts and interconnects 714 and reduce or minimize the possibility of over-etching and / or under-etching when forming openings 708. However, other values ​​for the ratio are also within the scope of this disclosure.

[0103] like Figure 8 As further shown, exemplary dimension 806 includes the width of the upper region 716b of the integrated contact and interconnect 714 located at the top surface 720b of the integrated contact and interconnect 714. In some embodiments, the width is in the range of 20 nanometers to 48.5 nanometers to provide sufficient contact area for the BEOL metallization structure 630 and to promote an increase in transistor density in the semiconductor device 200, thereby reducing the possibility of peeling or delamination of the integrated contact and interconnect 714 and / or providing sufficient gap filling and compression performance for the integrated contact and interconnect 714. However, other values ​​for the width are within the scope of this disclosure.

[0104] like Figure 8 As further illustrated, exemplary dimension 808 includes the width of the neck region 718, which contains integrated contacts and interconnects 714 located at the bottom of the neck region 718. In some embodiments, the width ranges from about 28 nanometers to about 34 nanometers, depending on the difference in etch rates between the silicon nitride layer 704 and the silicon oxide layer 706. However, other width values ​​are within the scope of this disclosure.

[0105] like Figure 8 As further illustrated, exemplary dimension 810 includes the height of the integrated contact and interconnect 714 located between the top surface 720b of the integrated contact and interconnect 714 and the top surface of the metal silicide layer 606. In some embodiments, the height ranges from about 38.2 nanometers to about 40.3 nanometers to minimize the loading effect of the integrated contact and interconnect 714 and facilitate the tuning of the integrated contact and interconnect 714. However, other values ​​for the height are within the scope of this disclosure.

[0106] like Figure 8As further illustrated, exemplary dimension 812 includes the thickness of the metal silicon nitride layer 608 at the top of the lower region 716a and at the interface between the silicon nitride layer 704 and the silicon oxide layer 706. In some embodiments, the thickness ranges from about 1 nanometer to about 5 nanometers, depending on the angle or curve of the sidewalls of the lower region 716a (e.g., a steeper angle of the sidewalls may result in a smaller thickness, while a shallower angle of the sidewalls may result in a larger thickness). However, other values ​​for the thickness are also within the scope of this disclosure.

[0107] like Figure 8 As further shown, exemplary dimension 814 includes the thickness of the metal silicon nitride layer 608 at the interface between the metal silicon nitride layer 608 and the metal silicide layer 606. In some embodiments, the thickness ranges from about 5 nanometers to about 11 nanometers, depending on the angle or curve of the sidewalls of the lower region 716a (e.g., a steeper angle of the sidewalls may result in a smaller thickness, while a shallower angle of the sidewalls may result in a larger thickness). However, other values ​​for the thickness are also within the scope of this disclosure.

[0108] The thickness of the silicon nitride layer 608 at the interface between the silicon nitride layer 608 and the metal silicide layer 606 may be greater than the thickness of the metal silicide layer 608 at the interface between the silicon nitride layer 704 and the silicon oxide layer 706. In some embodiments, the thickness of the silicon nitride layer 608 increases from the interface between the silicon nitride layer 608 and the metal silicide layer 606 to the interface between the silicon nitride layer 704 and the silicon oxide layer 706. In some embodiments, the increase in the thickness of the silicon nitride layer 608 is gradual, continuous, and / or uniform. In some embodiments, the increase in the thickness of the silicon nitride layer 608 is non-uniform and / or non-linear.

[0109] like Figure 8 As further shown, exemplary dimension 816 includes the thickness of the metal silicide layer 606. In some embodiments, the thickness ranges from about 5.4 nanometers to about 9.6 nanometers to provide adequate protection for the source / drain regions and sufficient contact resistance between the source / drain regions 408 and the integrated contacts and interconnects 714. However, other thickness values ​​are also within the scope of this disclosure.

[0110] As mentioned above, providing Figure 8 As an example. Other examples may be similar. Figure 8 The descriptions are different.

[0111] Figure 9A and Figure 9B This is a diagram illustrating the elemental composition 900 of the semiconductor device 200 described herein. Figure 9AAn exemplary vertical element composition 902 is illustrated, extending from the fin structure 206 through the source / drain region 408, through the metal silicide layer 606, and through the integrated contact and interconnect 714.

[0112] like Figure 9A As shown, the fin structure 206 primarily comprises silicon (Si) 904 and some germanium (Ge) 906 toward the top of the fin structure 206 (e.g., this may be generated during the formation of the source / drain region 408). The source / drain region 408 primarily comprises a combination of silicon 904 and germanium 906. Additionally, the source / drain region 408 includes some titanium (Ti) 908 toward the top of the source / drain region 408 (e.g., this may be generated between the metal silicide layers 606). The metal silicide layer 606 may primarily comprise silicon 904 and titanium 908. The metal silicide layer 606 may include other elements such as ruthenium (Ru) 910, nitrogen (N2) 912, and / or oxygen (O2) 914. Ruthenium 910 can be obtained facing the top of the metal silicide layer 606 during the formation of the integrated contact and interconnect 714. Due to the use of nitrogen plasma and / or oxidation in and / or on the metal silicide layer 606 during its formation (e.g., due to residual oxides), elements such as nitrogen 912 and / or oxygen 914 may be included. The integrated contact and interconnect 714 may primarily include ruthenium 910, some titanium 908 (generated by migration and / or mixing with the metal silicide layer 606), and other elements such as nitrogen 912 and oxygen 914.

[0113] In some embodiments, the ratio of titanium 908 concentration to nitrogen 912 concentration in the metal silicide layer 606 ranges from about 9.35:1 to about 10.33:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of titanium 908 concentration to oxygen 914 concentration in the metal silicide layer 606 ranges from about 7.02:1 to about 7.98:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of titanium 908 concentration to silicon 904 concentration in the metal silicide layer 606 ranges from about 2.10:1 to about 2.54:1 to achieve sufficiently low surface roughness for integrating contacts and interconnects 714. However, other values ​​are also within the scope of this disclosure. In some embodiments, the presence of chlorine can be tracked in the metal silicide layer 606.

[0114] In some embodiments, the concentration ratio of ruthenium 910 to titanium 908 in the metal silicide layer 606 ranges from about 0.69:1 to about 0.78:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the concentration ratio of ruthenium 910 to nitrogen 912 in the metal silicide layer 606 ranges from about 3.2:1 to about 3.59:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the concentration ratio of ruthenium 910 to oxygen 914 in the metal silicide layer 606 ranges from about 3.58:1 to about 4.01:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the concentration ratio of ruthenium 910 to silicon 904 in the metal silicide layer 606 ranges from about 1.69:1 to about 1.89:1. However, other values ​​are also within the scope of this disclosure.

[0115] Figure 9B An exemplary horizontal elemental composition 916 is illustrated, extending from the silicon nitride layer 608 through the integrated contact and interconnect 714, and through the silicon nitride layer 608.

[0116] like Figure 9B As shown, the silicon metal nitride layer 608 primarily comprises silicon 904, titanium 908, and nitrogen 912. The silicon metal nitride layer 608 may also include some germanium 906 (e.g., this may be generated during the formation of the source / drain region 408) and some residual elements, such as ruthenium 910 and oxygen 914. The integrated contact and interconnect 714 primarily comprises ruthenium 910, some titanium 908 (generated by migration and / or mixing with the silicon metal nitride layer 606 and the silicon metal nitride layer 608), and other elements, such as nitrogen 912 and oxygen 914.

[0117] In some embodiments, the ratio of titanium 908 concentration to nitrogen 912 concentration in the silicon nitride layer 608 ranges from about 4.38:1 to about 4.89:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of titanium 908 concentration to oxygen 914 concentration in the silicon nitride layer 608 ranges from about 5.67:1 to about 6.29:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of titanium 908 concentration to silicon 904 concentration in the silicon nitride layer 608 ranges from about 1.25:1 to about 1.41:1 to achieve sufficiently low surface roughness for the integrated contacts and interconnects 714. However, other values ​​are also within the scope of this disclosure. In some embodiments, the presence of chlorine can be tracked in the silicon nitride layer 608.

[0118] In some embodiments, the ratio of ruthenium 910 concentration to titanium 908 concentration in the silicon nitride layer 608 ranges from about 0.79:1 to about 0.89:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of ruthenium 910 concentration to nitrogen 912 concentration in the silicon nitride layer 608 ranges from about 2.68:1 to about 2.98:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of ruthenium 910 concentration to oxygen 914 concentration in the silicon nitride layer 608 ranges from about 4.32:1 to about 4.87:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of ruthenium 910 concentration to silicon 904 concentration in the silicon nitride layer 608 ranges from about 1.48:1 to about 1.64:1. However, other values ​​are also within the scope of this disclosure.

[0119] In some embodiments, the ratio of titanium 908 concentration to nitrogen 912 concentration in the integrated contact and interconnect 714 ranges from about 1.69:1 to about 1.98:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of titanium 908 concentration to oxygen 914 concentration in the integrated contact and interconnect 714 ranges from about 1.64:1 to about 1.83:1. However, other values ​​are also within the scope of this disclosure. In some embodiments, the ratio of titanium 908 concentration to silicon 904 concentration in the integrated contact and interconnect 714 ranges from about 0.56:1 to about 0.62:1 to achieve a sufficiently low surface roughness of the integrated contact and interconnect 714. However, other values ​​are also within the scope of this disclosure.

[0120] As mentioned above, providing Figure 9A and Figure 9B As an example. Other examples may be similar. Figure 9A and Figure 9B The descriptions are different.

[0121] Figure 10 This is a diagram illustrating exemplary elements of device 1000. In some embodiments, one or more semiconductor processing devices 102-112 and / or wafer / die transport device 114 may include one or more devices 1000, and / or one or more elements of device 1000. Figure 10 As shown, the device 1000 may include a bus 1010, a processor 1020, a memory 1030, an input element 1040, an output element 1050, and a communication element 1060.

[0122] Bus 1010 includes elements that allow wired and / or wireless communication between components of device 100. Bus 1010 can... Figure 10Two or more elements are coupled together, for example, through operational coupling, communication coupling, electronic coupling, and / or electrical coupling. Processor 1020 includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and / or other types of processing elements. Processor 1020 is implemented in hardware, firmware, and / or a combination of hardware and software. In some embodiments, processor 1020 includes one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0123] Memory 130 includes volatile and / or non-volatile memory. For example, memory 1030 may include random access memory, read-only memory, hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1030 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus). Memory 1030 may be a non-transitory computer-readable medium. Memory 1030 stores information, instructions, and / or software (e.g., one or more software applications) related to the operation of device 1000. In some embodiments, memory 1030 includes one or more memories, for example, coupled to one or more processors (e.g., processor 1020) via bus 1010.

[0124] Input element 1040 allows device 1000 to receive input, such as user input and / or sensed input. For example, input element 1040 may include a touchscreen display, keyboard, keypad, mouse, button, microphone, switch, sensor, global positioning system element, accelerometer, gyroscope, and / or actuator. Output element 1050 enables device 1000 to provide output, such as via a display, speaker, and / or one or more light-emitting diodes. Communication element 1060 enables device 1000 to communicate with other devices, such as via wired and / or wireless connections. For example, communication element 1060 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0125] Apparatus 1000 may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1030) may store a set of instructions (e.g., one or more instructions, code) for processor 1020 to execute. Processor 1020 may execute a set of instructions to perform one or more processes described herein. In some embodiments, a set of instructions executed by one or more processors 1020 causes one or more processors 1020 and / or apparatus 1000 to perform one or more operations or processes described herein. In some embodiments, hardware circuitry may be used in place of or in combination with instructions to perform one or more operations or processes described herein. Additionally or alternatively, processor 1020 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0126] Figure 10 The number and arrangement of the components shown are for illustrative purposes only. Device 1000 may include components that are relatively... Figure 10 The components shown may be additional, fewer, different, or differently configured components. Alternatively, a set of components of device 1000 (e.g., one or more components) may perform one or more functions performed by another set of components of device 1000.

[0127] Figure 11 This is a flowchart of an exemplary process 1100 associated with forming conductive structures in a semiconductor device. In some embodiments, Figure 11 One or more process blocks may be performed by one or more semiconductor processing devices (e.g., one or more semiconductor processing devices). Additionally or alternatively, Figure 11 One or more process blocks may be performed by one or more elements of device 1000, such as processor 1020, memory 1030, input element 1040, output element 1050, and / or communication element 1060.

[0128] like Figure 11 As shown, process 1100 may include forming a first opening (block 1110) through one or more first dielectric layers and reaching the source / drain region. For example, as described above, one or more semiconductor processing devices 102-112 may form a first opening (e.g., opening 602) through one or more first dielectric layers (e.g., CESL 502, ILD 504) and reaching the source / drain region 408.

[0129] like Figure 11 As further shown, process 1100 may include forming silicon nitride (Si) on the sidewalls of one or more first dielectric layers in the first opening. x N y (Box 1120). For example, as described above, one or more semiconductor processing devices 102-112 may form silicon nitride (Si) on the sidewalls (e.g., sidewall 602b) of one or more first dielectric layers in the first opening. x N y (e.g., nitride layer 604).

[0130] like Figure 11 As further shown, process 1100 may include performing a plasma-based deposition operation after forming the silicon nitride layer to selectively form titanium silicide (TiSi) on the top surface of the source / drain region in the first opening. x (Box 1130) layer. For example, as described above, after forming the silicon nitride layer, one or more semiconductor processing devices 102-112 may perform a plasma-based deposition operation to selectively form titanium silicide (TiSi). x A layer (e.g., metal silicide layer 606) is placed on the top surface of the source / drain region 408 in the first opening (e.g., the top surface corresponding to the bottom surface 602a of the first opening).

[0131] like Figure 11As further shown, process 1100 may include filling the first opening with a conductive material to form source / drain contacts over the silicon nitride layer and the titanium silicide layer (block 1140). For example, as described above, one or more semiconductor processing devices 102-112 may use a conductive material to fill the first opening to form source / drain contacts 610 over the silicon nitride layer and the titanium silicide layer.

[0132] like Figure 11 As further shown, process 1100 may include forming one or more second dielectric layers over one or more first dielectric layers (block 1150). For example, as described above, one or more semiconductor processing devices 102-112 may form one or more second dielectric layers over one or more first dielectric layers (e.g., ESL 612, ILD 614).

[0133] like Figure 11 As further shown, process 1100 may include forming a second opening (block 1160) through one or more second dielectric layers and reaching the source / drain contact. For example, as described above, one or more semiconductor processing devices 102-112 may form a second opening (e.g., opening 616) through one or more second dielectric layers and reaching the source / drain contact 610.

[0134] like Figure 11 As further shown, process 1100 may include filling the second opening with a conductive material to form a source / drain interconnect structure connected to the source / drain contacts (block 1170). For example, as described above, one or more semiconductor processing devices 102-112 may fill the second opening with a conductive material to form a source / drain interconnect structure 618 connected to the source / drain contacts.

[0135] Process 1100 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or in conjunction with one or more other processes described elsewhere herein.

[0136] In the first embodiment, the plasma-based deposition operation includes depositing titanium chloride (TiCl) x The titanium of titanium chloride, the silicon of the source / drain region 408, the reactive gas, and the plasma are supplied to the first opening, wherein the titanium of titanium chloride, the silicon of the source / drain region 408, the reactive gas, and the plasma react to selectively form titanium silicide (TiSi) on the top surface of the source / drain region 408 in the first opening (e.g., the top surface corresponding to the bottom surface 602a in the first opening). x (e.g., metal silicide layer 606).

[0137] In the second embodiment, either alone or in combination with the first embodiment, titanium chloride, silicon in a silicon nitride layer, a reactant gas, and plasma are reacted to selectively form titanium silicon nitride (TiSi). x N y A layer (e.g., a metal silicon nitride layer 608) is placed on the silicon nitride layer, and a first opening is filled with a conductive material to form a source / drain contact 610, including: filling the first opening with a conductive material to form the source / drain contact 610 on the silicon nitride layer. In a third embodiment, either alone or in combination with the first or second embodiments, titanium chloride, silicon in a titanium silicide layer, a reactive gas, and plasma reaction are used to selectively form titanium silicon nitride (TiSi). x N y A layer (e.g., a metal silicon nitride layer 608) is placed on a titanium nitride layer, and a first opening is filled with a conductive material to form a source / drain contact 610, including: filling the first opening with a conductive material to form a source / drain contact 610 on a titanium silicon nitride layer (e.g., a metal silicon nitride layer 608).

[0138] In the fourth embodiment, the thickness of the titanium nitride silicon layer (e.g., metal silicon nitride layer 608), alone or in combination with one or more of the first to third embodiments, ranges from about 5 nanometers to about 11 nanometers. In the fifth embodiment, the source / drain region 408 is bombarded with plasma during a plasma-based deposition operation, alone or in combination with one or more of the first to fourth embodiments. This results in the formation of mobile silicon atoms in the source / drain region 408, and the mobile silicon atoms diffuse toward the top surface of the source / drain region 408, whereby the mobile silicon atoms react with titanium chloride to form a titanium silicide layer.

[0139] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the reaction gas includes hydrogen (H2), and the plasma includes argon (Ar) plasma, helium (He) plasma, or nitrogen (N2) plasma, wherein the chlorine in titanium chloride, the hydrogen in hydrogen, and the plasma react in a plasma-based deposition operation to form hydrochloric acid (HCl) byproduct.

[0140] although Figure 11 An exemplary block diagram of process 1100 is shown, but in some embodiments, process 1100 may include processes compared to... Figure 11In addition to the boxes shown, there may be fewer boxes, different boxes, or boxes arranged differently. Alternatively or additionally, two or more boxes of process 1100 may be processed simultaneously.

[0141] Figure 12 This is a flowchart of an exemplary process 1200 associated with forming a conductive structure in a semiconductor device. In some embodiments, Figure 12 One or more processing blocks may be performed by one or more semiconductor processing devices (e.g., one or more of semiconductor processing devices 102-112). Additionally or alternatively, Figure 12 One or more processing blocks may be performed by one or more elements of the device 1000, such as processor 1020, memory 1030, input element 1040, output element 1050, and / or communication element 1060.

[0142] like Figure 12 As shown, process 1200 may include forming through silicon oxide (SiO2). x The layer extends through the silicon nitride (SiO2) layer located beneath the silicon oxide layer. x N y An opening (box 1210) is formed from the layer to the source / drain region. For example, as described above, one or more semiconductor processing devices 102-112 may form through silicon oxide (SiO2). x Layer 706 and through silicon nitride (Si) x N y The silicon nitride layer 704 extends to the opening (e.g., opening 708) of the source / drain region 408, with the silicon nitride layer 704 located below the silicon oxide layer 706.

[0143] like Figure 12 As further shown, process 1200 may include performing a plasma-based deposition operation to selectively form titanium silicide (TiSi) on the top surface of the source / drain region 408 in the opening. x Layer (box 1220). For example, as described above, one or more semiconductor processing devices 102-112 may perform a plasma-based deposition operation to selectively form titanium silicide (TiSi) on the top surface of the source / drain region 408 in the opening 708 (e.g., which may correspond to the bottom surface 708a of the opening 708). x (e.g., metal silicide layer 606).

[0144] like Figure 12As further shown, process 1200 may include filling openings with a conductive material to form a conductive structure on the titanium silicide layer, wherein the conductive structure includes a neck region (box 1230) located between a first region and a second region of the conductive structure. For example, as described above, one or more semiconductor processing devices 102-112 may use a conductive material to fill opening 708 to form a conductive structure (e.g., integrated contacts and interconnects 714) on the titanium silicide layer. In some embodiments, the conductive structure includes a neck region 718 located between a first region 716a and a second region 716b of the conductive structure.

[0145] like Figure 12 As further shown, process 1200 may include forming a BEOL metallization structure on the conductive structure (block 1240). For example, as described above, one or more semiconductor processing devices 102-112 may form a BEOL metallization structure 630 on the conductive structure. In some embodiments, the conductive structure extends from the source / drain region 408 to the BEOL metallization structure 630.

[0146] Process 1200 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0147] In a first embodiment, the BEOL metallization structure 630 includes an MO metal line. In a second embodiment, alone or in combination with the first embodiment, the neck region 718 is formed because the etch rate of the silicon oxide layer 706 is greater than the etch rate of the silicon nitride layer 704. In a third embodiment, alone or in combination with one or more of the first and second embodiments, the opening 708 is filled with a conductive material to form a conductive structure, including: filling the opening 708 with a conductive material to form the first region 716a, the second region 716b, and the neck region 718 in the same deposition operation.

[0148] In the fourth embodiment, a plasma-based deposition operation is performed, either alone or in combination with one or more of the first to third embodiments, including: supplying a titanium precursor and a reactive gas stream into an opening and supplying a plasma into the opening, wherein the titanium of the titanium precursor, the silicon of the source / drain region, the reactive gas, and the plasma react to selectively form a titanium silicide layer on the top surface of the source / drain region in the opening. In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the titanium of the titanium precursor, the silicon of the silicon nitride layer 704, the reactive gas, and the plasma react to selectively form titanium silicon nitride (TiSi). x N yA layer (e.g., a metal silicon nitride layer 608) is placed on a silicon nitride layer 704 in an opening 708, and the opening 708 is filled with a conductive material to form a conductive structure, including filling the opening with a conductive material to form a conductive structure on a titanium silicon nitride layer.

[0149] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1200 includes forming titanium nitride (Ti) on a titanium silicide layer. x N y Barrier layer or tantalum nitride (Ta x N y At least one of the barrier layers is filled with a conductive material to form a conductive structure, including: filling the opening 708 with ruthenium (Ru) to form a conductive structure on at least one of the titanium nitride barrier layer or the tantalum nitride barrier layer. In the seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, the plasma in the plasma-based deposition operation causes silicon atoms in the source / drain region 408 to diffuse toward the top surface of the source / drain region 408, resulting in a silicon-rich top surface of the source / drain region 408, and wherein the titanium precursor reacts with the silicon-rich top surface of the source / drain region 408 to form a titanium silicide layer.

[0150] although Figure 12 An exemplary block diagram of process 1200 is shown, but in some embodiments, process 1200 may include a process compared to... Figure 12 In addition to the boxes shown, there may be fewer boxes, different boxes, or boxes arranged differently. Alternatively or additionally, two or more process 1200 boxes may be processed simultaneously.

[0151] Therefore, titanium precursors are used to selectively form titanium silicide (TiSi) in semiconductor devices. x A plasma-based deposition process is performed, in which a titanium precursor is provided into the opening, and silicon is diffused to the top surface of the transistor structure using reactive gases and plasma. Silicon diffusion results in the formation of a silicon-rich surface in the transistor structure, which increases the selectivity of titanium silicide formation relative to other materials in the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form a titanium silicide layer. The selective formation of the titanium silicide layer leads to the formation of titanium silicide (TiSi) on the sidewalls of the opening. x N y This allows conductive structures, such as metal source / drain contacts, to be formed in the opening without adding another barrier layer.

[0152] As described in more detail above, some embodiments described herein provide a method. The method includes: forming a first opening through one or more first dielectric layers to a source / drain region. The method also includes: forming silicon nitride (Si) on the sidewalls of one or more first dielectric layers within the first opening. x N y The method includes: performing a plasma-based deposition operation after forming a silicon nitride layer to selectively form titanium silicide (TiSi) on the top surface of the source / drain region in the first opening. x The method includes: filling a first opening with a conductive material to form a source / drain contact over a silicon nitride layer and a titanium silicide layer. The method includes: forming one or more second dielectric layers over one or more first dielectric layers. The method includes: forming a second opening through one or more second dielectric layers to the source / drain contact. The method includes: filling the second opening with a conductive material to form a source / drain interconnect structure connected to the source / drain contact.

[0153] In some embodiments, plasma-based deposition is performed, including: providing titanium chloride (TiCl) x The process involves the flow of a reaction gas into a first opening and the supply of plasma into the first opening, wherein the titanium of titanium chloride, the silicon of the source / drain region, the reaction gas, and the plasma react to selectively form a titanium silicide layer on the top surface of the source / drain region in the first opening. In some embodiments, the titanium of titanium chloride, the silicon of the silicon nitride layer, the reaction gas, and the plasma react to selectively form titanium silicon nitride (TiSi). x N y A layer is formed on a silicon nitride layer: and a first opening therein is filled with a conductive material to form source / drain contacts, including: filling the first opening with a conductive material to form source / drain contacts on a titanium silicon nitride layer. In some embodiments, titanium chloride, silicon of a titanium silicide layer, a reactive gas, and plasma react to selectively form titanium silicon nitride (TiSi). x N yA layer is formed on a titanium silicide layer: and a first opening is filled with a conductive material to form a source / drain contact, comprising: filling the first opening with a conductive material to form a source / drain contact on a titanium nitride silicon layer. In some embodiments, the reactant gas includes hydrogen (H2); wherein the plasma includes at least one of the following: argon (Ar) plasma, helium (He) plasma, or nitrogen (N2) plasma; and wherein the chlorine in titanium chloride, the hydrogen in hydrogen, and the plasma react in a plasma-based deposition operation to form hydrochloric acid as a byproduct. In some embodiments, the plasma in the plasma-based deposition operation bombards the source / drain region, resulting in the formation of migrating silicon atoms in the source / drain region; and wherein the migrating silicon atoms diffuse toward the top surface of the source / drain region, wherein the migrating silicon atoms react with titanium chloride to form a titanium silicide layer on the top surface of the source / drain region.

[0154] As described in more detail above, some embodiments described herein provide a method. The method includes: forming an opening through silicon oxide (SiO₂). x The layer extends through the silicon nitride (SiO2) layer located beneath the silicon oxide layer. x N y The method includes: performing a plasma-based deposition operation to selectively form a titanium silicide (TiSix) layer on the top surface of the source / drain region within an opening. The method also includes: filling the opening with a conductive material to form a conductive structure on the titanium silicide layer. Finally, the method includes: forming a BEOL metallization structure on the conductive structure, wherein the conductive structure extends from the source / drain region to the BEOL metallization structure.

[0155] In some embodiments, the BEOL metallization structure includes a metal line of the zeroth metal layer (MO). In some embodiments, the conductive structure includes a neck region located between a first region and a second region of the conductive structure; wherein the neck region is due to a higher etch rate of the silicon oxide layer relative to the etch rate of the silicon nitride layer. In some embodiments, filling the opening with a conductive material to form the conductive structure includes: filling the opening with a conductive material to form the first region, the second region, and the neck region in the same deposition operation. In some embodiments, performing a plasma-based deposition operation includes: providing a flow of titanium precursor and reactive gas into the opening; and providing plasma into the opening, wherein the titanium of the titanium precursor, the silicon of the source / drain region, the reactive gas, and the plasma react to selectively form a titanium silicide layer on the top surface of the source / drain region in the opening. In some embodiments, the titanium of the titanium precursor, the silicon of the silicon nitride layer, the reactive gas, and the plasma react to selectively form titanium silicon nitride (TiSi). x N yA layer is formed on a silicon nitride layer in an opening: and wherein the opening is filled with a conductive material to form a conductive structure, including: filling the opening with a conductive material to form a conductive structure on a titanium nitride silicon layer. In some embodiments, the plasma in a plasma-based deposition operation causes silicon atoms in the source / drain regions to diffuse toward the top surface of the source / drain regions, resulting in a silicon-rich top surface of the source / drain regions, and wherein a titanium precursor reacts with the silicon-rich top surface of the source / drain regions to form a titanium silicide layer.

[0156] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a substrate. The semiconductor device includes: a semiconductor fin structure extending over the substrate. The semiconductor device includes: a first oxide layer over the fin structure. The semiconductor device includes: a transistor structure located above the semiconductor fin structure and in the first oxide layer, wherein the transistor structure includes a source / drain region or a gate structure. The semiconductor device includes: a nitride layer located above the first oxide layer. The semiconductor device includes: a second oxide layer located above the nitride layer. The semiconductor device includes: integrated contacts and interconnects, including: a first region located in the nitride layer, a second region located in the second oxide layer, and a neck region transitioning between the first and second regions. The semiconductor device includes: titanium silicide (TiSi) located between the transistor structure and the first region of the integrated contacts and interconnects. x The semiconductor device includes: titanium silicon nitride (TiSi) layer located between the nitride layer and a first region of integrated contacts and interconnects. x N y )layer.

[0157] In some embodiments, the ratio between the thickness of the nitride layer and the thickness of the second oxide layer is in the range of about 1:10 to about 10:1. In some embodiments, the thickness of the titanium nitride silicon layer increases from the first interface between the nitride layer and the second oxide layer to the second interface between the titanium nitride silicon layer and the titanium silicide layer. In some embodiments, a neck region is included in the second oxide layer; and wherein the titanium nitride silicon layer is located below the second oxide layer. In some embodiments, a first ratio of titanium to silicon in the titanium silicide layer is in the range of about 2.10:1 to about 2.54:1; and a second ratio of titanium to silicon in the first region of the integrated contact and interconnect is in the range of about 0.56:1 to about 0.62:1. In some embodiments, the integrated contact and interconnect includes ruthenium (Ru) integrated contact and interconnect; and wherein the semiconductor device further includes: a metal line of a zero-layer metal (MO) located above the second oxide layer and electrically connected to the top surface of the second region of the ruthenium integrated contact and interconnect. In some embodiments, the first region of the integrated contact and interconnect is bent between the neck region and the bottom surface of the first region of the integrated contact and interconnect.

[0158] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A first opening is formed through one or more first dielectric layers and to a source / drain region; Formation of silicon nitride (Si) x N y The layer is on the sidewall of the one or more first dielectric layers in the first opening; After forming the silicon nitride layer, a plasma-based deposition operation is performed to selectively form titanium silicide (TiSi). x The layer is located on the top surface of the source / drain region within the first opening; The first opening is filled with a conductive material to form a source / drain contact above the silicon nitride layer and the titanium silicide layer. One or more second dielectric layers are formed on top of one or more first dielectric layers; A second opening is formed through the one or more second dielectric layers and to the source / drain contact; and The second opening is filled with the conductive material to form a source / drain interconnect structure connected to the source / drain contact.

2. The method for forming a semiconductor device as claimed in claim 1, wherein performing the plasma-based deposition operation includes: Provide titanium chloride (TiCl) x A reaction gas is fed into the first opening; and Provide plasma into the first opening, The titanium in the titanium chloride, the silicon in the source / drain region, the reactive gas, and the plasma react to selectively form the titanium silicide layer on the top surface of the source / drain region in the first opening.

3. The method for forming a semiconductor device as claimed in claim 2, wherein the titanium in the titanium chloride, the silicon in the silicon nitride layer, the reactive gas, and the plasma reaction selectively form a titanium silicon nitride (TiSi). x N y The layer is on the silicon nitride layer; and The first opening is filled with the conductive material to form the source / drain contact, including: The first opening is filled with the conductive material to form the source / drain contact on the titanium nitride silicon layer.

4. The method for forming a semiconductor device as claimed in claim 2, wherein the titanium in the titanium chloride, the silicon in the titanium silicide layer, the reactive gas, and the plasma reaction selectively form a titanium silicon nitride (TiSi). x N y The layer is on the titanium silicide layer: and The first opening is filled with the conductive material to form the source / drain contact, including: The first opening is filled with the conductive material to form the source / drain contact on the titanium nitride silicon layer.

5. The method for forming a semiconductor device as claimed in claim 2, wherein the reactant gas comprises hydrogen (H2); The plasma includes at least one of the following: Argon (Ar) plasma, Helium (He) plasma, or Nitrogen (N2) plasma; and The chlorine in the titanium chloride, the hydrogen in the hydrogen gas, and the plasma react in the plasma-based deposition operation to form hydrochloric acid as a byproduct.

6. The method of forming a semiconductor device as claimed in claim 2, wherein the plasma in the plasma-based deposition operation bombards the source / drain region, resulting in the formation of a plurality of migrating silicon atoms in the source / drain region, and The migrated silicon atoms diffuse toward the top surface of the source / drain region, and the migrated silicon atoms react with the titanium chloride to form the titanium silicide layer on the top surface of the source / drain region.

7. A method for forming a semiconductor device, comprising: Form an opening through silicon monoxide (SiO) x ) layer and penetrates a silicon nitride (Si) layer located beneath the silicon oxide layer. x N y () layer to a source / drain region, A plasma-based deposition process is performed to selectively form titanium silicide (TiSi). x The layer is located on the top surface of the source / drain region within the opening. The opening is filled with a conductive material to form a conductive structure on the titanium silicide layer; and A back-end (BEOL) metallization structure is formed on this conductive structure. The conductive structure extends from the source / drain region to the metallized structure at the back end of the production line.

8. The method of forming a semiconductor device as claimed in claim 7, wherein the metallization structure at the back end of the production line includes a metal line of a zeroth layer metal (MO).

9. The method of forming a semiconductor device as claimed in claim 7, wherein the conductive structure includes a neck region located between a first region and a second region of the conductive structure; and The neck region is caused by the fact that the etching rate of the silicon oxide layer is relatively large compared to the etching rate of the silicon nitride layer.

10. The method of forming a semiconductor device as claimed in claim 9, wherein filling the opening with the conductive material to form the conductive structure comprises: The opening is filled with the conductive material to form the first region, the second region, and the neck region in the same deposition operation.

11. The method of forming a semiconductor device as claimed in claim 7, wherein performing the plasma-based deposition operation includes: A titanium precursor and a reactant gas are supplied to the opening; and Provide a plasma into the opening. The titanium precursor, silicon of the source / drain region, reactive gas, and plasma reaction selectively form the titanium silicide layer on a top surface of the source / drain region in the opening.

12. The method of forming a semiconductor device as claimed in claim 11, wherein the titanium of the titanium precursor, the silicon of the silicon nitride layer, the reactive gas, and the plasma reaction selectively form a titanium silicon nitride (TiSi). x N y The layer is on the silicon nitride layer in the opening; and The conductive structure is formed by filling the opening with the conductive material, including: The opening is filled with the conductive material to form the conductive structure on the titanium nitride silicon layer.

13. The method of forming a semiconductor device as claimed in claim 11, wherein the plasma in the plasma-based deposition operation causes a plurality of silicon atoms in the source / drain region to diffuse toward the top surface of the source / drain region, resulting in a silicon-rich top surface of the source / drain region, and The titanium precursor reacts with the silicon-rich top surface of the source / drain region to form the titanium silicide layer.

14. A semiconductor device, comprising: One substrate; A semiconductor fin structure extends onto the substrate; A first oxide layer is located on the semiconductor fin structure; A transistor structure is located above the semiconductor fin structure and within the first oxide layer. The transistor structure includes a source / drain region or a gate structure; A nitride layer is located above the first oxide layer; A second oxide layer is located above the nitride layer; An integrated contact and interconnects, including: The first region is located within the nitride layer; A second region, located within the second oxide layer; and A neck region, transitioning between the first region and the second region; Titanium silicide (TiSi) x The layer is located between the transistor structure and the first region of the integrated contact and interconnects; and Titanium nitride silicon (TiSi) x N y A layer located between the nitride layer and the first region of the integrated contact and interconnects.

15. The semiconductor device of claim 14, wherein the ratio between the thickness of the nitride layer and the thickness of the second oxide layer is in the range of about 1:10 to about 10:

1.

16. The semiconductor device of claim 14, wherein the thickness of the titanium nitride silicon layer increases from a first interface between the nitride layer and the second oxide layer to a second interface between the titanium nitride silicon layer and the titanium silicide layer.

17. The semiconductor device of claim 14, wherein the neck region is contained within the second oxide layer; and The titanium nitride silicon layer is located beneath the second oxide layer.

18. The semiconductor device of claim 14, wherein a first ratio of titanium to silicon in the titanium silicide layer is in the range of about 2.10:1 to about 2.54:1; and In the first region of the integrated contact and interconnects, a second ratio of titanium to silicon is in the range of about 0.56:1 to about 0.62:

1.

19. The semiconductor device of claim 14, wherein the integrated contact and interconnect comprises a ruthenium (Ru) integrated contact and interconnect; and The semiconductor device further includes: A metal line of a zero-layer metal (M0) is located above the second oxide layer and electrically connected to a top surface of the second region of the ruthenium integrated contact and interconnect.

20. The semiconductor device of claim 14, wherein the first region of the integrated contact and interconnect is bent between the neck region and a bottom surface of the first region of the integrated contact and interconnect.

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