Semiconductor structure and method of manufacturing the same
By forming a combination of conductive support strips and isolation structures in the semiconductor structure, the problem of bit line tilting or necking is solved, the yield of the semiconductor structure is improved and the process flow is simplified.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-08-22
- Publication Date
- 2026-07-31
AI Technical Summary
Bit lines are prone to tilting or necking defects during fabrication, which affects the yield of semiconductor structures.
By forming conductive support strips on the substrate to occupy positions for subsequent bit line structures, and forming isolation structures on the sidewalls of the conductive support strips, at least a portion of the conductive support strips are removed to form a first filling area for filling the bit line structures. The bit line structures are directly formed using a deposition process, avoiding etching processes.
This prevents the bit line structure from exhibiting a narrow neck or bottom taper, which is wider at the top and bottom and narrower in the middle, thus improving the yield of semiconductor structures and simplifying the deposition process.
Smart Images
Figure CN115332181B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM typically consists of multiple memory cells, each usually including a transistor and a capacitor. The capacitor stores data, and the transistor controls the reading and writing of data in the capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on and off states. One of the transistor's source and drain is electrically connected to the bit line (BL), and the other is electrically connected to the capacitor, allowing data to be stored or output via the bit line.
[0003] However, during bit line fabrication, bit lines are prone to defects such as tilting or necking. Summary of the Invention
[0004] In view of the above problems, this disclosure provides a semiconductor structure and its fabrication method to solve the defects of bit lines being prone to tilting or necking.
[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:
[0006] A substrate is provided having multiple active structures, each of the active structures having a bit line contact region;
[0007] A plurality of conductive support strips are formed and spaced apart along a first direction, each of the conductive support strips extending along a second direction; each of the conductive support strips connects to a plurality of bit line contact areas, and the plurality of bit line contact areas are arranged along the second direction; the first direction and the second direction intersect.
[0008] An initial isolation structure is formed covering the sides and top surface of each of the conductive support strips;
[0009] Remove the initial isolation structure located on the top surface of the conductive support strip;
[0010] At least a portion of the thickness of the conductive support strip is removed to form a first filling area; wherein the initial isolation structure that is retained forms an isolation structure;
[0011] A bitline structure is formed within the first filling region.
[0012] In some embodiments, the step of removing at least a portion of the thickness of the conductive support strip includes:
[0013] A portion of the thickness of the conductive support strip is removed, and the remaining conductive support strip forms a bit line contact. The bit line contact is located in the bit line contact area, and the top surface of the bit line contact is flush with the top surface of the substrate. The area enclosed by the bit line contact and the isolation structure forms a first filling area.
[0014] In some embodiments, the step of forming a bit line structure within the first filling region includes:
[0015] Bit lines are formed within the first filling region, and the bit lines and the bit lines in contact form a bit line structure.
[0016] In some embodiments, after the step of providing a substrate having a plurality of active structures, each of which has a bit line contact region, and before the step of forming a plurality of conductive support strips spaced apart along a first direction, the fabrication method further includes:
[0017] A portion of the active structure exposed within the bit line contact area is removed to form a second fill area that exposes the bit line contact area, the second fill area also exposing a portion of the remaining side surface of the active structure.
[0018] In some embodiments, the conductive support strip is made of doped polycrystalline silicon.
[0019] In some embodiments, the step of removing at least a portion of the thickness of the conductive support strip includes:
[0020] All of the conductive support strips are removed to form a first fill area, which exposes the bit line contact area of the active structure.
[0021] In some embodiments, the step of forming a bit line structure within the first filling region includes:
[0022] In the first filling area, bit line contacts and bit lines are formed in a stacked manner, and the bit lines and the bit line contacts constitute a bit line structure.
[0023] In some embodiments, after the step of removing the initial isolation structure located on the top surface of the conductive support strip and before the step of forming a bit line structure in the first filling region, the fabrication method further includes:
[0024] A portion of the active structure is removed to form a second filling region that communicates with the first filling region, the second filling region exposing a portion of the remaining side surface of the active structure.
[0025] In some embodiments, the conductive support strip is made of undoped polycrystalline silicon, and the bit line contact is made of doped polycrystalline silicon.
[0026] In some embodiments, the method includes:
[0027] The bit line contact is formed in the second filling region and a portion of the first filling region; the bit line contact has an extension toward the substrate end, the extension filling the second filling region to cover the side of the active structure exposed in the second filling region.
[0028] In some embodiments, after the step of removing at least a portion of the thickness of the conductive support strip, the method further includes:
[0029] A portion of the sidewall of the initial isolation structure exposed by the first filling area is removed along the first direction to increase the width of the first filling area in the first direction.
[0030] In some embodiments, after providing a substrate having multiple active structures, the fabrication method further includes:
[0031] A repair material is added to the bit line contact area, and the active structure is repaired at a preset temperature.
[0032] In some embodiments, the step of forming a plurality of conductive support strips spaced apart along a first direction includes:
[0033] A conductive support layer is formed on the substrate, the conductive support layer covering the upper surface of the substrate and filling the bit line contact area;
[0034] The conductive support layer is patterned to form a plurality of conductive support strips spaced apart along a first direction, the conductive support strips being spaced apart from the sidewalls of the bit line contact area.
[0035] In some embodiments, the step of forming an initial isolation structure covering the sides and top surface of each of the conductive support bars includes:
[0036] An initial isolation sidewall is formed covering the sides and top of each of the conductive support strips, the initial isolation sidewall forming a groove between adjacent conductive support strips;
[0037] An initial medium layer is formed within the groove, and the initial medium layer fills the groove; the initial medium layer and the initial isolation sidewall constitute the initial isolation structure.
[0038] A second aspect of this disclosure provides a semiconductor structure, which is fabricated by the method described in the first aspect. The semiconductor structure includes:
[0039] A substrate having a plurality of active structures, each of the active structures having a bit line contact region;
[0040] Multiple bit line structures are provided, with multiple bit line structures spaced apart along a first direction, each bit line structure extending along a second direction, and each bit line structure connecting bit line contact areas located in the same column along the second direction;
[0041] An isolation structure that covers the side of the bit line structure.
[0042] In some embodiments, the bit line structure includes a bit line contact and a bit line disposed on the bit line contact, the bit line contact having an extension toward the substrate end, the extension covering a portion of the side surface of the active structure; the bit line includes a bit line blocking layer, a bit line conductive layer and a bit line insulating layer stacked sequentially, the bit line blocking layer being disposed on the bit line contact.
[0043] In the semiconductor structure and fabrication method provided in this disclosure, conductive support strips are first formed on the substrate to occupy positions for the subsequently formed bit line structure. Then, an isolation structure is formed on the sidewalls of the conductive support strips, and at least a portion of the conductive support strips is removed to form a first filling region for filling the bit line structure. In this way, the isolation structure can be used as a support, and the bit line structure can be directly formed in the first filling region using a deposition process, eliminating the need for an etching process. Furthermore, this prevents the formed bit line structure from exhibiting a narrow neck (wide at the top and bottom, narrow in the middle) or a tapered bottom, thus improving the yield of the semiconductor structure.
[0044] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 A schematic diagram of the stacked layers provided for related technologies;
[0047] Figure 2A schematic diagram of bit lines provided for related technologies;
[0048] Figure 3 The process flow of the semiconductor structure fabrication method provided in the embodiments of this disclosure Figure 1 ;
[0049] Figure 4 A layout diagram of the substrate and conductive support strip in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;
[0050] Figure 5 This is a schematic diagram of the formation of bit line contact regions in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
[0051] Figure 6 Schematic diagram of the formation of a conductive support layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 1 ;
[0052] Figure 7 This is a schematic diagram of the patterned mask layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 1 ;
[0053] Figure 8 This is a schematic diagram of the process after forming the conductive support strip in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 1 ;
[0054] Figure 9 A schematic diagram of the semiconductor structure fabrication method provided in this disclosure after the initial isolation sidewalls are formed. Figure 1 ;
[0055] Figure 10 for Figure 9 Enlarged view of region A in the middle;
[0056] Figure 11 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment after the initial isolation structure is formed. Figure 1 ;
[0057] Figure 12 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment after removing part of the initial isolation structure. Figure 1 ;
[0058] Figure 13 A schematic diagram showing the semiconductor structure fabrication method provided in this embodiment of the present disclosure after removing all conductive support strips;
[0059] Figure 14 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment after removing part of the sidewalls of the initial isolation structure. Figure 1 ;
[0060] Figure 15 for Figure 14 Enlarged view of region B in the middle;
[0061] Figure 16 This is a schematic diagram of the bit line structure formed in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 1 ;
[0062] Figure 17 for Figure 16 Enlarged view of region C in the middle;
[0063] Figure 18 The process flow of the semiconductor structure fabrication method provided in the embodiments of this disclosure Figure 2 ;
[0064] Figure 19 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment of the present disclosure after the formation of the second filling region. Figure 1 ;
[0065] Figure 20 for Figure 19 Enlarged schematic diagram of region H in the middle;
[0066] Figure 21 The process flow of the semiconductor structure fabrication method provided in the embodiments of this disclosure Figure 3 ;
[0067] Figure 22 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment of the present disclosure after the formation of the second filling region. Figure 2 ;
[0068] Figure 23 Schematic diagram of the formation of a conductive support layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure. Figure 2 ;
[0069] Figure 24 This is a schematic diagram of the process after forming the conductive support strip in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 2 ;
[0070] Figure 25 for Figure 24 Enlarged schematic diagram of region E in the middle;
[0071] Figure 26 A schematic diagram of the semiconductor structure fabrication method provided in this disclosure after the initial isolation sidewalls are formed. Figure 2 ;
[0072] Figure 27 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment after the initial isolation structure is formed. Figure 2 ;
[0073] Figure 28 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment after removing part of the initial isolation structure. Figure 2 ;
[0074] Figure 29 A schematic diagram showing the semiconductor structure fabrication method provided in this embodiment of the present disclosure after removing part of the conductive support strip;
[0075] Figure 30 This is a schematic diagram of the semiconductor structure fabrication method provided in this embodiment after removing part of the sidewalls of the initial isolation structure. Figure 2 ;
[0076] Figure 31 for Figure 30 Enlarged schematic diagram of region F in the middle;
[0077] Figure 32 This is a schematic diagram of the bit line structure formed in the method for fabricating the semiconductor structure provided in this embodiment of the disclosure. Figure 2 ;
[0078] Figure 33 for Figure 32 A magnified diagram of region G in the middle.
[0079] Figure label:
[0080] 1: Substrate; 2: Layers; 3: Bitline structure;
[0081] 100: Substrate; 110: Active structure; 120: Shallow trench isolation structure; 111: Bit line contact area; 112: Capacitor contact area;
[0082] 200: Conductive support strip; 210: Conductive support layer; 220: Groove;
[0083] 300: Mask layer; 310: Mask pattern;
[0084] 400: Initial isolation structure; 410: Initial isolation sidewall; 411: First initial isolation layer; 412: Second initial isolation layer; 413: Third initial isolation layer; 420: Initial dielectric layer; 430: Groove;
[0085] 500: Isolation structure; 510: Isolation sidewall; 511: First isolation layer; 512: Second isolation layer; 513: Third isolation layer; 520: Medium layer;
[0086] 600: Bit line structure; 610: First filling area; 620: Second filling area; 630: Bit line contact; 640: Bit line; 641: Bit line barrier layer; 642: Bit line conductive layer; 643: Bit line insulating layer. Detailed Implementation
[0087] As described in the background section, bit lines in related technologies suffer from defects such as tilting or necking. The inventors have discovered that the cause of this problem is (see attached document). Figure 1 and attached Figure 2 In related technologies, a stack 2 for forming bit line structures is typically formed on a substrate 1 using a deposition process. Then, the stack is patterned to form bit line structures 3 spaced apart along a first direction. However, due to the large number of film layers in the stack, the etching process can lead to over-etching or under-etching, resulting in defects such as tilting or necking in the formed bit line structures.
[0088] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and its fabrication method. The method involves first forming conductive support strips on a substrate to occupy positions for the subsequently formed bit line structure. Then, an isolation structure is formed on the sidewalls of the conductive support strips, and at least a portion of the conductive support strips is removed to form a first filling region for the bit line structure. This allows the isolation structure to serve as a support, and the bit line structure to be formed within the first filling region using a deposition process. Unlike related technologies, it eliminates the need for etching processes to remove portions of the stacked layers. Furthermore, this prevents the formed bit line structure from exhibiting a narrow neck (wide at the top and bottom, narrow in the middle) or a tapered bottom, thus improving the yield of the semiconductor structure.
[0089] In this case, when some of the conductive support strips are removed, the remaining conductive support strips can still be used as part of the bit line structure, for example, as bit line contacts in the bit line structure, which can simplify the subsequent deposition process.
[0090] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0091] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.
[0092] Example 1
[0093] Please refer to the attached document. Figure 3 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:
[0094] Step S101: Provide a substrate having multiple active structures, each active structure having a bit line contact region.
[0095] The substrate 100 is used to support semiconductor devices disposed thereon. The substrate 100 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.
[0096] Please refer to the attached document. Figure 4 and attached Figure 5 The substrate 100 has multiple active structures 110, which can be arranged in an array. Each active structure 110 is tilted and extends along the substrate. Figure 4 The D-direction extends as shown. Multiple active structures 110 can be separated by shallow trench isolation (STI) structures 120 to ensure independence between each active structure 110. For example, shallow trenches are formed in the substrate using a patterning process, and insulating material is filled within the trenches, thereby defining multiple active structures 110 separated by shallow trench isolation structures on the substrate 100. The patterning process can be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process. The insulating material can include, but is not limited to, silicon oxide.
[0097] Each active structure 110 has a bit line contact region 111, that is, the bottom of the bit line contact region 111 is located in the substrate 100. The bit line contact region 111 is used to form a bit line contact (BLC) to realize the electrical connection between the bit line structure 600 and the active structure 110. It should be understood that the multiple bit line contact regions 111 are arranged in an array.
[0098] It should be noted that each active structure 110 is also provided with a capacitor contact area 112. There can be two capacitor contact areas 112, which are respectively arranged on both sides of the bit line contact area 111 to form a capacitor contact, so as to realize the electrical connection between the capacitor structure and the active structure 110.
[0099] Step S102: Form a plurality of conductive support strips spaced apart along a first direction, each conductive support strip extending along a second direction; each conductive support strip connects to a plurality of bit line contact areas, and the plurality of bit line contact areas are arranged along the second direction; the first direction and the second direction intersect.
[0100] Please continue to refer to the appendix. Figure 4 Each conductive support strip 200 extends along a second direction, which intersects the extension direction of the active structure 110, so that each conductive support strip 200 can connect to multiple bit line contact areas 111 located in the same column. The first direction is attached. Figure 4 The X direction is in the middle, and the second direction is attached. Figure 4 in the Y direction.
[0101] For example, please refer to the appendix. Figure 6 A conductive support layer 210 is formed on the substrate, which covers the upper surface of the substrate 100 and fills the full-line contact area 111.
[0102] A conductive support layer is formed in the bit line contact area 111 using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The conductive support layer 210 extends beyond the bit line contact area 111 and covers the upper surface of the substrate 100.
[0103] Next, please refer to the appendix. Figure 7 and attached Figure 8 A patterned conductive support layer 210 is formed to create a plurality of conductive support strips 200 spaced apart along a first direction, with the conductive support strips 200 spaced apart from the sidewalls of the bit line contact area. A groove 220 is formed between adjacent conductive support strips 200, the depth direction of which is perpendicular to the substrate 100.
[0104] Please continue to refer to the appendix. Figure 5 To be continued Figure 8 A mask layer 300 is formed on the conductive support layer. The mask layer 300 is patterned using a SADP process to form a mask pattern 310 within the mask layer 300. Using the mask pattern 310 as a mask, the conductive support layer 210 is etched to form a plurality of conductive support strips 200 spaced apart along a first direction. The specific SADP process can be found in descriptions in related technologies, and will not be elaborated further in this embodiment.
[0105] It should be noted that, for the same conductive support strip 200, the bottom of a portion of the conductive support strip 200 is located within the bit line contact area 111, while the bottom of the remaining portion of the conductive support strip 200 is located on the substrate 100. The conductive support strip 200 located within the bit line contact area 111 has a predetermined distance from the sidewall of the bit line contact area 111 to facilitate the subsequent formation of an isolation material in this area, preventing electrical connection between the subsequently formed bit line contact and other semiconductor devices located within the substrate.
[0106] Step S103: Form an initial isolation structure covering the sides and top of each conductive support strip.
[0107] For example, please refer to the appendix. Figure 9 and attached Figure 10 An initial isolation sidewall 410 is formed, covering the sides and top surfaces of each conductive support strip 200. The initial isolation sidewall 410 forms a groove 430 between adjacent conductive support strips 200. The initial isolation sidewall 410 includes a first initial isolation layer 411, a second initial isolation layer 412, and a third initial isolation layer 413. The second initial isolation layer 412 is located between the first initial isolation layer 411 and the third initial isolation layer 413, and the first initial isolation layer 411 is connected to the conductive support strip 200.
[0108] The first initial isolation layer 411 and the third initial isolation layer 413 are made of the same material, including but not limited to silicon nitride. The second initial isolation layer 412 is made of silicon oxide, but not limited to.
[0109] Next, please refer to the appendix. Figure 11 An initial medium layer 420 is formed in the groove 430 using a deposition process, and the initial medium layer 420 fills the groove 430. The top surface of the initial medium layer 420 is flush with the top surface of the initial isolation sidewall 410, that is, the top surface of the initial medium layer 420 is flush with the top surface of the third initial isolation layer 413.
[0110] The initial dielectric layer 420 and the initial isolation sidewall 410 constitute the initial isolation structure 400. The material of the initial dielectric layer 420 includes, but is not limited to, silicon oxide.
[0111] Step S104: Remove the initial isolation structure located on the top surface of the conductive support strip.
[0112] Please refer to the attached document. Figure 12For example, the initial isolation structure 400 on the top surface of the conductive support strip 200 and the initial dielectric layer 420 on the same layer as the initial isolation structure 400 are removed by chemical mechanical polishing (CMP). After the initial isolation structure 400 is removed, the top surface of the conductive support strip 200 is exposed.
[0113] Step S105: Remove at least a portion of the thickness of the conductive support strip to form a first filling area; wherein the retained initial isolation structure forms an isolation structure.
[0114] Please refer to the attached document. Figure 13 and attached Figure 29 The conductive support strip 200 located below the initial isolation structure 400 is removed by an etching process to form a first filling region 610 for forming a bit line structure.
[0115] In this step, please continue to refer to the appendix. Figure 13 and attached Figure 14 If all the conductive support strips 200 are removed, the first filling area 610 is defined by the isolation structure 500 and the bit line contact area 111, that is, the bit line contact area 111 is part of the first filling area 610.
[0116] Please refer to the attached document. Figure 29 If a portion of the conductive support strip 200 is removed, at least the conductive support strip 200 located within the bit line contact area 111 should be retained. The retained conductive support strip 200 can serve as the bit line structure 600 (please refer to the appendix). Figure 32 The bit line contacts 630 in the (). At this time, the first fill region 610 is defined by the isolation structure 500.
[0117] It should be noted that, after the step of removing at least a portion of the thickness of the conductive support strip and before the step of forming the bit line structure in the first filling region, the semiconductor structure fabrication method further includes:
[0118] Please refer to the attached document. Figure 14 and attached Figure 15 A portion of the sidewalls of the initial isolation structure 400 exposed by the first filling region 610 is removed along the first direction to increase the width of the first filling region 610 in the first direction. This configuration, by removing a portion of the width of the initial isolation structure 400, increases the width of the first filling region in the first direction, thereby increasing the width of the subsequently formed bit line structure, reducing the resistance of the bit line structure, and improving the sensitivity of the semiconductor structure.
[0119] In this embodiment, a portion of the first initial isolation layer 411 can be removed along the first direction. Of course, all of the first initial isolation layer 411 can also be removed along the first direction, as long as the insulation performance of the subsequently formed isolation sidewall can be guaranteed and the area of the first filling area can be increased.
[0120] The retained initial isolation structure 400 constitutes the isolation structure 500. The isolation structure 500 includes an isolation sidewall 510 and a medium layer 520. The isolation sidewall 510 includes a first isolation layer 511, a second isolation layer 512, and a third isolation layer 513 stacked together.
[0121] Step S106: Form a bitline structure within the first fill region. Please refer to the attached diagram for the structure. Figure 16 and attached Figure 17 .
[0122] In this embodiment, a conductive support strip 200 is first formed on the substrate 100 to occupy the space for the subsequently formed bit line structure 600. Then, an isolation structure 500 is formed on the sidewall of the conductive support strip 200, and at least a portion of the conductive support strip 200 is removed to form a first filling region 610 for forming the bit line structure. Thus, the isolation structure 500 can be used as a support, and the bit line structure 600 can be directly formed within the first filling region 610 using a deposition process, eliminating the need for an etching process. This prevents the formed bit line structure 600 from exhibiting a narrow neck (wide at the top and bottom, narrow in the middle) or a tapered bottom, improving the yield of the semiconductor structure.
[0123] In this case, when part of the conductive support strip 200 is removed, the remaining conductive support strip 200 can still serve as a bit line contact in the bit line structure 600, which simplifies the subsequent deposition process.
[0124] Due to factors such as the material of the conductive support strip 200 and the thickness of the subsequently removed conductive support strip 200, this embodiment has different implementation methods. The following will describe in detail the semiconductor structure fabrication method using two different implementation methods.
[0125] First Implementation Method
[0126] Please refer to the attached document. Figure 18 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:
[0127] Step S201: Provide a substrate having multiple active structures, each active structure having a bit line contact region.
[0128] Step S202: Form a plurality of conductive support strips spaced apart along a first direction, each conductive support strip extending along a second direction; each conductive support strip connects to a plurality of bit line contact areas, and the plurality of bit line contact areas are arranged along the second direction; the first direction and the second direction intersect.
[0129] Step S203: Form an initial isolation structure covering the sides and top of each conductive support strip.
[0130] Step S204: Remove the initial isolation structure located on the top surface of the conductive support strip.
[0131] The steps S201-S204 described above are the same as steps S101-S104 in the above embodiment, and will not be described again in this embodiment.
[0132] Step S205: Remove all conductive support strips to form a first fill region, which exposes the bit line contact region of the active structure.
[0133] At this time, the conductive support strip 200 is made of undoped polycrystalline silicon. The first filling region 610 is defined by the isolation structure 500 and the bit line contact region 111, that is, the bit line contact region 111 is part of the first filling region 610.
[0134] Step S206: Remove part of the active structure to form a second filling area connected to the first filling area, the second filling area exposing part of the side of the remaining active structure.
[0135] Please refer to the attached document. Figure 19 and attached Figure 20 Since the etching selectivity of the active structure 110 is greater than that of the isolation structure 500, under the same etching conditions, the active structure 110 exposed in the bit line contact region 111 can be etched, that is, a portion of the thickness of the active structure 110 exposed in the bit line contact region 111 can be removed, so that the remaining active structure 110 forms a shape that is high in the middle and low on both sides. The remaining active structure 110 and the shallow trench isolation structure 120 form a second filling region 620.
[0136] After the second filling region is formed, a cleaning process can be used to clean the surface of the exposed active structure, remove residual impurities from the surface of the active structure, and further expand the volume of the second filling region.
[0137] Step S207: Add repair material to the bit line contact area and repair the active structure at a preset temperature.
[0138] It should be noted that when a repair material is added to the bit line contact region 111, the repair material will also fill the second filling region 620. Therefore, the active structure 110 exposed in the bit line contact region 111 and the second filling region 620 can be repaired. The repair in this step can refer to lattice repair or surface repair, for example, reducing the roughness of the active structure.
[0139] For example, the repair material may include any one of oxygen, hydrogen, or nitrogen. When the repair material is oxygen, the active structure 110 exposed to the second filling region 620 and the bit line contact region is annealed at 90°C-120°C. The oxygen can treat the surface of the active structure 110 to reduce the surface roughness of the active structure.
[0140] When the repair material is hydrogen or nitrogen, hydrogen or nitrogen can be used as a protective gas to anneal the active structure 110 at a temperature between 300℃ and 500℃. This can remove carbon and oxygen materials exposed on the surface of the active structure in the second filling region 620 and the bit line contact region, and repair the lattice damage of the active structure 110, so as to improve the quality and preparation efficiency of the subsequent film layer and reduce lattice defects.
[0141] Step S208: Form a bit line structure within the first fill region.
[0142] Please continue to refer to the appendix. Figure 16 and attached Figure 17 In the first filling area 610, bit line contacts 630 and bit lines 640 are formed in a stacked manner, and bit lines 640 and bit line contacts 630 constitute bit line structure 600.
[0143] For example, a bit line contact 630 is formed in the second filling region and a portion of the first filling region; the end of the bit line contact 630 facing the substrate 100 has an extension 631, which fills the second filling region to cover the side of the active structure 110 exposed in the second filling region. The bit line contact 630 is made of doped polysilicon.
[0144] Compared with related technologies, this is equivalent to adding an extension 631 to the bit line contact 630, so that the extension 631 also has a contact surface with the active structure 110, thereby increasing the contact area between the bit line contact 630 and the active structure 110 and reducing the contact resistance between the bit line contact 630 and the active structure 110.
[0145] Furthermore, in this embodiment, the bit line contact 630 is formed directly using a deposition process, and this process is performed after the step of removing part of the sidewall of the initial isolation structure exposed in the first filling area along the first direction. This prevents damage to the bit line contact when removing the initial isolation structure 400, thus ensuring the conductivity of the bit line contact.
[0146] Subsequently, a bit line 640 is formed on the bit line contact 630 using a deposition process. The bit line 640 includes a bit line blocking layer 641, a bit line conductive layer 642, and a bit line insulating layer 643 stacked together.
[0147] Bit line barrier layer 641 is disposed on bit line contact 630. The material of bit line barrier layer 641 includes titanium nitride. Bit line barrier layer 641 has both conductive and barrier properties. For example, titanium nitride can prevent the conductive material in bit line conductive layer 642 from penetrating between it and the substrate 100, thus ensuring the conductivity of bit line 64.
[0148] Bit line conductive layer 642 is disposed on bit line blocking layer 641. The material of bit line conductive layer 642 includes tungsten or polycrystalline silicon. Tungsten and polycrystalline silicon have strong conductivity, thereby ensuring the conductivity of bit line 640.
[0149] Bit line insulating layer 643 is disposed on bit line conductive layer 642 to achieve electrical insulation between bit line conductive layer 642 and other semiconductor devices subsequently disposed on bit line insulating layer 643. The material of bit line insulating layer 643 includes silicon nitride, but is not limited to this.
[0150] Second Implementation Method
[0151] The main difference between this embodiment and the first embodiment is that part of the conductive support strip 200 is removed, and the remaining conductive support strip 200 serves as the bit line contact 630.
[0152] Please refer to the attached document. Figure 21 The method for fabricating this semiconductor structure includes the following steps:
[0153] Step S301: Provide a substrate having multiple active structures, each active structure having a bit line contact region.
[0154] Step S301 is the same as step S101 in the above embodiment. For details, please refer to step S101 above. This embodiment will not repeat the details here.
[0155] Step S302: Remove part of the active structure exposed in the bit line contact area to form a second fill area that exposes the bit line contact area. The second fill area also exposes part of the side surface of the remaining active structure.
[0156] Please refer to the attached document. Figure 22Hydrofluoric acid gas or ammonia plasma can be used as etching gases to etch the active structure, or TMAH (tetramethylammonium hydroxide) or other etching solutions can be selected for wet etching of the active structure. Under these etching process conditions, the etching selectivity of the active structure 110 is greater than that of the shallow trench isolation structure 120, allowing etching of the active structure 110 exposed in the bit line contact region 111, i.e., removing the outer portion of the active structure 110 exposed in the bit line contact region 111. In addition, by utilizing the different etching rates of different crystal orientations, the remaining active structure 110 can be formed into a shape that is high in the middle and low on both sides. The remaining active structure 110 and the shallow trench isolation structure 120 form a second filling region 620.
[0157] With attachment Figure 22 Taking the orientation shown as an example, the area above the dashed line is the bit line contact area 111, and the area below the dashed line is the second filling area 620.
[0158] After the second filling region 620 is formed, a cleaning process can be used to clean the surface of the exposed active structure 110, remove residual impurities from the surface of the active structure 110, and further increase the volume of the second filling region 620.
[0159] Step S303: Add repair material to the bit line contact area and repair the active structure at a preset temperature.
[0160] It should be noted that this step can be referred to as step S207, and will not be described in detail here.
[0161] Step S304: Form a plurality of conductive support strips spaced apart along a first direction, each conductive support strip extending along a second direction; each conductive support strip connects to a plurality of bit line contact areas, and the plurality of bit line contact areas are arranged along the second direction; the first direction and the second direction intersect.
[0162] Please refer to the attached document. Figure 23 To be continued Figure 25 This step is a further improvement on step S102. The bottom of the conductive support strip 200 formed in this step will fill the second filling area 620. In subsequent steps, a portion of the conductive support strip 200 will be removed, and the remaining conductive support strip 200 will serve as the bit line contact 630 (see Appendix). Figure 29 When the bit line contact 630 is used, it can wrap the top surface and part of the side surface of the active structure 110, thereby increasing the contact area between the bit line contact 630 and the active structure 110, and thus reducing the contact resistance between the bit line contact 630 and the active structure 110, improving the sensitivity of signal transmission of the bit line structure, and the performance of the semiconductor structure.
[0163] Step S305: Form an initial isolation structure covering the sides and top surface of each conductive support strip. Please refer to the appendix for the structure. Figure 26 and attached Figure 27 .
[0164] Step S306: Remove the initial isolation structure located on the top surface of the conductive support strip. Its structure can be found in the appendix. Figure 28 .
[0165] It should be noted that the preparation process in step S305 can refer to step S103. The preparation process in step S306 can refer to step S104. These will not be elaborated further in this embodiment.
[0166] Step S307: Remove part of the thickness of the conductive support strip, and the remaining conductive support strip forms a bit line contact. The bit line contact is located in the bit line contact area, and the top surface of the bit line contact is flush with the top surface of the substrate; wherein, the area enclosed by the bit line contact and the isolation structure forms the first filling area.
[0167] Please refer to the attached document. Figure 29 Using etching gas or etching solution, the conductive support strip 200 located on the top surface of the substrate 100 is removed, while the conductive support strip 200 located in the second filling area and the bit line contact area is retained. This portion of the conductive support strip 200 constitutes the bit line contact 630. The conductive support strip 200 retained in the second filling area can serve as an extension 631 of the bit line contact 630. Compared with related technologies, this is equivalent to adding an extension 631 to the bit line contact 630, so that the extension 631 also has a contact surface with the active structure 110, thereby increasing the contact area between the bit line contact 630 and the active structure 110 and reducing the contact resistance between them.
[0168] The conductive support strip 200 is made of doped polycrystalline silicon. The dopant ions can be Group V elements from the periodic table, such as phosphorus or arsenic ions. The doping dose is 8.0E20 / cm². 2 Up to 20E20 / cm 2 Between. This arrangement reduces the resistivity of the conductive support strip, thereby increasing its conductivity.
[0169] In this embodiment, by using a portion of the conductive support strip 200 as the bit line contact 630, the subsequent deposition of the material layer used to prepare the bit line contact 630 is avoided. This simplifies the subsequent deposition process and improves the fabrication efficiency of the semiconductor structure.
[0170] Step S307: Remove a portion of the sidewall of the initial isolation structure exposed in the first filling region along the first direction to increase the width of the first filling region in the first direction. Its structure can be found in the attached diagram. Figure 30 and attached Figure 31 .
[0171] It should be noted that the preparation of step S307 can be referred to step S207. This embodiment will not elaborate further here.
[0172] Step S308: A bit line is formed in the first filling region, and the bit lines contact each other to form a bit line structure.
[0173] Please refer to the attached document. Figure 32 and attached Figure 33 Bit lines 640 are formed in the first filling region 610 by a deposition process. Bit lines 640 include a bit line blocking layer 641, a bit line conductive layer 642 and a bit line insulating layer 643 stacked together.
[0174] Example 2
[0175] Please continue attaching. Figure 16 and attached Figure 32 This disclosure provides a semiconductor structure prepared by the method described in Embodiment 1. The semiconductor structure includes a substrate 100, multiple bit line structures 600, and an isolation structure 500.
[0176] The substrate 100 has multiple active structures 110, which can be arranged in an array, with each active structure 110 tilted. Each active structure 110 has a bit line contact region; that is, the bottom of the bit line contact region is located in the substrate 100, and this bit line contact region is used to form a bit line contact 630 (BLC) to achieve electrical connection between the bit line structure 600 and the active structure 110. It should be understood that the multiple bit line contact regions are arranged in an array.
[0177] Multiple bit line structures 600 are spaced apart along a first direction, each bit line structure 600 extends along a second direction, and each bit line structure 600 connects to bit line contact areas located in the same column along the second direction. That is, each bit line structure 600 is used to connect to active structures 110 located in the same column, to read data information from capacitor structures located in the same column through the same bit line structure 600, or to write data information into capacitor structures for storage through the same bit line structure 600.
[0178] An isolation structure 500 covers the side of a bit line structure 600. The isolation structure 500 provides insulation between adjacent bit line structures 600. The isolation structure 500 includes an isolation sidewall 510 and a dielectric layer 520. The isolation sidewall 510 covers the side of the bit line structure 600 and forms a groove between adjacent bit line structures 600. The dielectric layer 520 is disposed in the groove and fills the groove completely.
[0179] In one possible implementation, the bit line structure 600 includes a bit line contact 630 and a bit line 640 disposed on the bit line contact 630. The bit line contact 630 has an extension 631 facing the substrate end, and the extension 631 covers a portion of the side surface of the active structure 110. This configuration can increase the contact area between the bit line contact 630 and the active structure 110, and reduce the contact resistance between the bit line contact 630 and the active structure 110.
[0180] Along the first direction, the width of the bit line contact 630 can be the same as the width of the bit line 640, or the width of the bit line 640 can be greater than the width of the bit line contact 630. In this way, the linewidth of the bit line 640 can be increased, thereby reducing the resistance of the bit line and improving the sensitivity of the semiconductor structure.
[0181] Bit line 640 includes a bit line blocking layer 641, a bit line conductive layer 642, and a bit line insulating layer 643 stacked sequentially. The bit line blocking layer 641 is disposed on the bit line contact 630. The functions of the bit line blocking layer 641, the bit line conductive layer 642, and the bit line insulating layer 643 can be found in the description in Embodiment 1, and will not be repeated here.
[0182] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0183] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.
[0184] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided having multiple active structures, each of the active structures having a bit line contact region; A plurality of conductive support strips are formed and spaced apart along a first direction, each of the conductive support strips extending along a second direction; each of the conductive support strips connects to a plurality of bit line contact areas, and the plurality of bit line contact areas are arranged along the second direction; the first direction and the second direction intersect. An initial isolation structure is formed covering the sides and top surface of each of the conductive support strips; Remove the initial isolation structure located on the top surface of the conductive support strip; A portion of the thickness of the conductive support strip is removed to form a first filling area. The remaining conductive support strip constitutes a bit line contact, which is located in the bit line contact area, and the top surface of the bit line contact is flush with the top surface of the substrate. The retained initial isolation structure forms an isolation structure, and the area enclosed by the bit line contact and the isolation structure forms the first filling area. A bitline structure is formed within the first filling region.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a bit line structure within the first filling region includes: Bit lines are formed within the first filling region, and the bit lines and the bit lines in contact form a bit line structure.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Following the step of providing a substrate having multiple active structures, each active structure having a bit line contact region, and prior to the step of forming multiple conductive support strips spaced apart along a first direction, the fabrication method further includes: The portion of the active structure exposed within the bit line contact area is removed to form a second fill area that exposes the bit line contact area, the second fill area also exposing a portion of the remaining side surface of the active structure.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The conductive support strip is made of doped polycrystalline silicon.
5. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the step of removing a portion of the thickness of the conductive support strip, the method further includes: A portion of the sidewall of the initial isolation structure exposed by the first filling area is removed along the first direction to increase the width of the first filling area in the first direction.
6. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, Following the step of providing a substrate having multiple active structures, the fabrication method further includes: A repair material is added to the bit line contact area, and the active structure is repaired at a preset temperature.
7. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The step of forming a plurality of conductive support strips spaced apart along a first direction includes: A conductive support layer is formed on the substrate, the conductive support layer covering the upper surface of the substrate and filling the bit line contact area; The conductive support layer is patterned to form a plurality of conductive support strips spaced apart along a first direction, the conductive support strips being spaced apart from the sidewalls of the bit line contact area.
8. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The step of forming an initial isolation structure covering the sides and top surface of each of the conductive support strips includes: An initial isolation sidewall is formed covering the sides and top of each of the conductive support strips, the initial isolation sidewall forming a groove between adjacent conductive support strips; An initial medium layer is formed within the groove, and the initial medium layer fills the groove; the initial medium layer and the initial isolation sidewall constitute the initial isolation structure.
9. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1-8; The semiconductor structure includes: A substrate having a plurality of active structures, each of the active structures having a bit line contact region; Multiple bit line structures are provided, with multiple bit line structures spaced apart along a first direction, each bit line structure extending along a second direction, and each bit line structure connecting bit line contact areas located in the same column along the second direction; An isolation structure that covers the side of the bit line structure.
10. The semiconductor structure according to claim 9, characterized in that, The bit line structure includes a bit line contact and a bit line disposed on the bit line contact. The bit line contact has an extension portion facing the substrate end, and the extension portion covers a portion of the side surface of the active structure. The bit line includes a bit line blocking layer, a bit line conductive layer and a bit line insulating layer stacked sequentially, and the bit line blocking layer is disposed on the bit line contact.