Chip package structure and method of forming the same

Abstract

A chip package structure and a method of forming the same. The chip package structure includes a semiconductor die bonded over an interposer substrate. The chip package structure also includes a warpage release layer structure. The warpage release layer structure includes an organic material layer and an overlying high coefficient of thermal expansion material layer having a coefficient of thermal expansion substantially equal to or greater than 9 ppm / °C. The organic material layer is in direct contact with an upper surface of the semiconductor die, and the overlying high coefficient of thermal expansion material layer covers the upper surface of the semiconductor die.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing technology, and more particularly to a chip packaging structure having a warpage release layer structure and a method for forming the same. Background Technology

[0002] Semiconductor devices and integrated circuits are typically manufactured on a single semiconductor wafer. Semiconductor dies on the wafer can be processed or packaged together with other semiconductor devices or dies at the wafer level, and various technologies have been developed for wafer-level packaging.

[0003] In integrated circuit packaging, semiconductor dies can be stacked and bonded to other package components (e.g., interposer substrates and package substrates). However, as the feature size of semiconductor dies continues to shrink, the feature size of the package components (e.g., interposer substrates) used to support the semiconductor dies also decreases. Therefore, forming a reliable chip package is a challenge. Summary of the Invention

[0004] This disclosure provides a chip packaging structure including an interposer substrate, a first semiconductor die, and a warp release layer structure. The first semiconductor die is bonded to the interposer substrate. The warp release layer structure includes a first organic material layer and a first high coefficient of thermal expansion (CTE) material layer. The first organic material layer is in direct contact with the upper surface of the first semiconductor die. The CTE material layer has a CTE coefficient substantially equal to or greater than 9 ppm / °C, and the CTE material layer is formed on the first organic material layer and covers the upper surface of the first semiconductor die.

[0005] This disclosure provides a chip packaging structure including an interposer substrate, a molding compound layer, a first semiconductor die, a second semiconductor die, and a warp release layer structure. The molding compound layer is formed on the interposer substrate. The first and second semiconductor dies are bonded to the interposer substrate and surrounded by the molding compound layer. The warp release layer structure includes a first polyimide layer, a first metal layer, and a second metal layer. The first polyimide layer is in direct contact with the upper surfaces of the first and second semiconductor dies. The first and second metal layers are formed on the first polyimide layer and are separated from each other to respectively cover the upper surfaces of the first and second semiconductor dies.

[0006] This disclosure provides a method for forming a chip package structure, comprising: mounting a first semiconductor die and a second semiconductor die on an interposer substrate; forming an sealing layer on the interposer substrate to surround the first and second semiconductor dies; forming a first organic material layer in direct contact with the upper surfaces of the first and second semiconductor dies and the sealing layer; and forming a first metal layer and a second metal layer on the first organic material layer, wherein the first and second metal layers are separated from each other to respectively cover the upper surfaces of the first semiconductor die and the second semiconductor die. Attached Figure Description

[0007] The complete disclosure is based on the following detailed description and accompanying drawings. It should be emphasized that, in accordance with the general practice of the industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0008] Figures 1A to 1H These are cross-sectional views of various stages of a method for forming a chip package structure according to some embodiments.

[0009] Figure 1H-1 This is a cross-sectional view of a chip package structure according to some embodiments.

[0010] Figure 1H-2 This is a cross-sectional view of a chip package structure according to some embodiments.

[0011] Figures 2A to 2E These are cross-sectional views of various stages of a method for forming a chip package structure according to some embodiments.

[0012] Figure 2E-1 This is a cross-sectional view of a chip package structure according to some embodiments.

[0013] Figure 2E-2 This is a cross-sectional view of a chip package structure according to some embodiments.

[0014] Figures 3A to 3E These are cross-sectional views of various stages of a method for forming a chip package structure according to some embodiments.

[0015] Figure 3E-1 This is a cross-sectional view of a chip package structure according to some embodiments.

[0016] Figure 3E-2 This is a cross-sectional view of a chip package structure according to some embodiments.

[0017] Figure 4 According to some embodiments Figure 2D A plan view of a portion of the warp release layer structure shown.

[0018] Figure 5 According to some embodiments Figure 2D A plan view of a portion of the warp release layer structure shown.

[0019] Figure 6 According to some embodiments Figure 3E A plan view of a portion of the warp release layer structure shown.

[0020] Figure 7 According to some embodiments Figure 3E A plan view of a portion of the warp release layer structure shown.

[0021] The attached figures are labeled as follows:

[0022] 10, 10a, 10b, 20, 20a, 20b, 30, 30a, 30b: Chip package structure

[0023] 100,100',100”,100-1,100-2: Semiconductor die / semiconductor chip

[0024] 100a: Front surface / Active surface

[0025] 100b,100b',100b”: Back surface / Non-active surface

[0026] 100S: Semiconductor substrate

[0027] 102: Conductive pad

[0028] 103: Conductive column

[0029] 104: Passivation layer

[0030] 105: Electrical connectors

[0031] 106: Protrusion Structure

[0032] 112: Basal layer

[0033] 113: Redistribution layer structure

[0034] 116: Intermediate layer substrate

[0035] 118: Passivation layer

[0036] 120: Second material layer

[0037] 122: First material layer

[0038] 130a, 130b: Organic material layers

[0039] 131: Opening

[0040] 132a, 132b: High thermal expansion coefficient material layers

[0041] 133: Opening

[0042] 134a, 134b: Organic material layers

[0043] 135: Patterned photoresist layer

[0044] 136: Electrical connectors

[0045] 140: Patterned photoresist layer

[0046] 142: column

[0047] 200: Carrier substrate

[0048] 1000: Semiconductor wafer

[0049] 1100: Carrier Detailed Implementation

[0050] The following disclosure provides many different embodiments or examples to implement different features of this application. Specific examples of components and their arrangements are described below to illustrate this disclosure. Of course, these embodiments are merely examples and should not be construed as limiting the scope of this disclosure. For example, the specification may describe a first feature formed on or above a second feature, which may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, repeated reference numerals and / or designations may be used in different examples of this disclosure; this repetition is for simplification and clarity and is not intended to limit any specific relationship between the various embodiments and / or structures discussed.

[0051] Furthermore, spatial terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of the relationship between one element or feature and another element(s) in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used herein can be interpreted in the same way.

[0052] The use of the term "substantially" in the specification, such as "substantially flat" or "substantially coplanar," is as understood by those skilled in the art. In some embodiments, the adjective "substantially" may be omitted. Where applicable, the term "substantially" may also include embodiments of "entirely," "completely," "all," etc. Where applicable, the term "substantially" may also refer to 90% or higher, such as 95% or higher, particularly 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor deviations from a particular arrangement, and may include, for example, deviations of up to 10°. The term "substantially" does not exclude "completely," for example, a composition "substantially free" of Y may be completely free of Y.

[0053] Terms used in conjunction with a specific distance or size, such as “about,” should be interpreted as not excluding minor deviations relative to the specific distance or size, and may include, for example, deviations of up to 10%. The term “about” used with the numerical value x may mean x ± 5 or 10%.

[0054] The following describes some embodiments of this disclosure. Figures 1A to 1H These are cross-sectional views of various stages of a process for forming a chip package structure 10 according to some embodiments. Figures 1A to 1H Additional operations are provided before, during, and / or after the stages described herein. For different embodiments, some of the described stages may be replaced or eliminated. Additional features may be added to the semiconductor device structure. For different embodiments, some features described below may be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in a different logical order.

[0055] like Figure 1AAs shown, a semiconductor wafer 1000 is provided. The semiconductor wafer 1000 includes a plurality of semiconductor chips (also referred to as semiconductor dies when cut open). For simplicity, only two adjacent semiconductor chips / dies 100-1 and 100-2 are depicted. In some embodiments, semiconductor chip / dies 100-1 or 100-2 provide logical functionality for a structure. For example, each of semiconductor chips / dies 100-1 and 100-2 is a logic die (e.g., a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, an application processor (AP) die) or a memory die (e.g., a high-bandwidth memory (HBM) die or a static random access memory (SRAM) die), although any suitable semiconductor chip / die may be utilized. In some other embodiments, each of the semiconductor chips / dies 100-1 and 100-2 is a system-on-chip (SoC) die (which includes multiple functions).

[0056] Semiconductor wafer 1000 (and semiconductor dies 100-1 and 100-2 therein) may include a semiconductor substrate 100S. Semiconductor substrate 100S may include an active layer of doped or undoped bulk silicon or silicon-on-insulator (SOI) substrate. Generally, the SOI substrate includes a layer of semiconductor material, such as silicon, germanium, silicon-germanium, or combinations thereof. Semiconductor substrate 100S may include integrated circuit devices (not shown) and interconnect structures (not shown). Integrated circuit devices may include active devices (e.g., transistors). Active devices may be formed within or on semiconductor substrate 100S using any suitable method. In some embodiments, interconnect structures are formed on semiconductor substrate 100S and active devices and are designed to connect various active devices to form functional circuitry. In some embodiments, interconnect structures are formed from alternating layers of dielectric and conductive materials and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). The dielectric layer may include a low-k dielectric layer, for example, having a dielectric constant (k) value of less than about 3.0.

[0057] In some embodiments, conductive pads 102 are formed on the front surface 100a (also referred to as active surfaces) of the semiconductor substrate 100S and electrically coupled to an integrated circuit device (not shown) via interconnect structures (not shown). In some embodiments, conductive pads 102 are bonding pads. Conductive pads 102 may be made of metals such as aluminum, copper, nickel, gold, or combinations thereof. Conductive pads 102 may be formed using a deposition process such as sputtering to form a layer of material, which may then be patterned using suitable processes (e.g., photolithography and etching) to form contact pads.

[0058] In some embodiments, conductive pillars 103, such as copper pillars, copper alloy pillars, or other suitable metal pillars, are formed on conductive pads 102. Conductive pillars 103 are formed on conductive pads 102. For example, conductive pillars 103 can be formed by first placing a photoresist and patterning the photoresist into the desired pattern of the conductive pillar, and then using an electroplating process to form a conductive material (e.g., copper) connected to the conductive pads 102. However, any suitable method can be utilized.

[0059] In some embodiments, a passivation layer 104 is formed to cover a portion of the active surface 100a and the conductive pad 102 of the semiconductor substrate 100S. The material of the passivation layer 104 may be selected from solder resists, polymers such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), molding compounds, etc. Alternatively, the material of the passivation layer 104 may be selected from silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, another suitable material, or a combination thereof.

[0060] In some embodiments, the conductive post 103 protrudes beyond the passivation layer 104. In some other embodiments, the conductive post 103 is embedded within the passivation layer 104.

[0061] In some embodiments, after the conductive pillar 103 is formed, an electrical connector 105 (e.g., a microbump) is correspondingly bonded to the conductive pillar 103 of the semiconductor wafer 1000. For example, the electrical connector 105 may be a solder ball and formed on the conductive pillar 103 using a ball-mounting head (not shown). The electrical connector 105 may be made of a material such as tin, silver, lead-free tin, or copper. The conductive pillar 103 and the overlying electrical connector 105 form a bump structure 106, which serves as an electrical connection between the semiconductor die 100 and an external circuit (not shown).

[0062] According to some embodiments, such as Figure 1BAs shown, after forming the bump structure 106, multiple singulated semiconductor dies 100 are formed. Figure 1B As shown, according to some embodiments, the semiconductor wafer 1000 is flipped to attach the bump structure 106 to a carrier 1100. The carrier 1100 may include an adhesive tape layer that serves as a temporary carrier tape and is easily detachable from the bump structure 106.

[0063] Subsequently, the rear surface 100b of the semiconductor wafer 1000 (also referred to as the non-active surface) is cut along a scribing line (not shown) of the semiconductor wafer 1000 by a sawing process, an etching process, or a combination thereof. For example, the rear surface 100b of the semiconductor wafer 1000 can be cut by a sawing process using one or more blades.

[0064] According to some embodiments, such as Figure 1C As shown, after dicing the semiconductor wafer 1000 to form monomeric semiconductor dies 100-1 and 100-2, an interposer substrate 116 is provided formed on a carrier substrate 200 and bonded to the interconnect structure of the semiconductor dies 100-1 and 100-2. In some embodiments, a carrier substrate 200 is provided having a debonding layer (not shown) coated thereon. The carrier substrate 200 may be a glass carrier substrate, a ceramic carrier substrate, or any carrier substrate suitable for carrying semiconductor wafers for use in a chip packaging structure manufacturing process. The debonding layer may include a light-to-heat conversion (LTHC) layer or an adhesive layer (e.g., a UV-curable adhesive or a thermosetting adhesive layer). The debonding layer may be decomposed under photothermal conditions to remove the carrier substrate 200 from the overlying structure (e.g., the interposer substrate 116) in subsequent steps.

[0065] In some embodiments, the interposer substrate 116 includes a redistribution layer (RDL) structure 113 formed in a base layer 112 and covered by a passivation layer 118, which is attached to the carrier substrate 200 via a release layer.

[0066] The redistribution layer structure 113 can be used as a fan-out redistribution layer structure for routing. More specifically, the redistribution layer structure 113 includes one or more conductive layers (e.g., two or three conductive layers) embedded within one or more dielectric layers (forming the substrate layer 112). The redistribution layer structure 113 not only provides conductive routing for signals but can also provide structures such as integrated inductors or capacitors. In some embodiments, the dielectric layer comprises an organic material, such as polybenzoxazole (PBO), polyimide (PI), one or more other suitable polymer materials, or combinations thereof. In these cases, the interposer substrate 116 is also referred to as an organic substrate or an organic interposer. The dielectric layer can be formed by, for example, a spin coating process, although any suitable method can be used. After the first dielectric layer is formed, an opening (not shown) can be made through the first dielectric layer.

[0067] Once the first dielectric layer has been formed and patterned, a first conductive layer (e.g., copper) is formed over the first dielectric layer and through an opening formed within the first dielectric layer. In some embodiments, the first conductive layer is formed using a suitable formation process, such as electroplating, chemical vapor deposition (CVD), or sputtering. However, while the materials and methods discussed are applicable to forming conductive layers, the materials are merely exemplary. Any other suitable materials, such as aluminum, tungsten, nickel, titanium, gold, platinum, silver, another suitable material, or combinations thereof, and any other suitable formation process, such as chemical vapor deposition or physical vapor deposition (PVD), can be used to form conductive layers.

[0068] Once the first conductive layer has been formed, the second dielectric layer and the second conductive layer can be formed by repeating steps similar to those for the first dielectric layer and the first conductive layer. These steps can be repeated as needed to form electrical connections between the conductive layers. In some embodiments, the deposition and patterning of the conductive and dielectric layers can continue until the redistribution layer structure 113 has the desired number of conductive layers.

[0069] The passivation layer 118 can be a single-layer or multi-layer structure. In some embodiments, the passivation layer 118 is a single layer and has openings that expose some conductive layers of the redistribution layer structure 113. Bonding pads (not shown) can be formed on the exposed redistribution layer structure 113. The passivation layer 118 is made of a dielectric material and provides stress relief for bonding stresses generated during subsequent bonding processes. For example, the passivation layer 118 can be made of a polymeric material, such as polyimide, polybenzoxazole, benzocyclobutene, etc., or combinations thereof. Alternatively or additionally, the passivation layer 118 can include silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, other suitable materials, or combinations thereof.

[0070] Multiple deposition, coating, and / or etching processes can be used to form the interposer substrate 116, which includes a redistribution layer structure 113, a base layer 112, and a passivation layer 118. In some embodiments, one or more thermal processing processes are performed during the formation of the interposer substrate 116. For example, a portion of the passivation layer 118 may be made of a polymer material formed using a process involving thermal operation.

[0071] After the interposer substrate 116 is provided, at least two semiconductor dies 100-1 and 100-2 are removed from the carrier 1100 and placed on the redistribution layer structure 113 using, for example, a pick-and-place tool (not shown), and then the bump structures 106 of the semiconductor dies 100-1 and 100-2 are mounted on the interposer substrate 116.

[0072] For example, two homogeneous semiconductor dies 100-1 and 100-2 can be mounted on the interposer substrate 116 via corresponding bump structures 106. For instance, both semiconductor dies 100-1 and 100-2 are logic dies or system-on-a-chip (SoC) dies. Prior to placing semiconductor dies 100-1 and 100-2, optional under-bump metallization (UBM) layers (not shown) and overlying solder bump structures (not shown) can be formed correspondingly beneath the bump structures 106 and on the interposer substrate 116. In some embodiments, semiconductor dies 100-1 and 100-2 are arranged side-by-side.

[0073] According to some embodiments, after semiconductor dies 100-1 and 100-2 are bonded to the interposer substrate 116, a sealing layer (also called an encapsulation layer) is formed on the interposer substrate 116 to cover semiconductor dies 100-1 and 100-2, such as... Figure 1D As shown. More specifically, as Figure 1D As shown, the sealing layer includes a first material layer 122 and a second material layer 120. The first material layer 122 of the sealing layer surrounds the sidewalls of semiconductor wafers 100-1 and 100-2 and covers the upper surfaces of semiconductor wafers 100-1 and 100-2 (i.e., the rear surfaces 100b (or non-active surfaces) of semiconductor wafers 100-1 and 100-2). The second material layer 120 extends between the opposing sidewalls of semiconductor wafers 100-1 and 100-2, between the interposer substrate 116 and semiconductor wafer 100-1, and between the interposer substrate 116 and semiconductor wafer 100-2.

[0074] In some embodiments, the first material layer 122 is made of a material different from that of the second material layer 120. More specifically, the first material layer 122 is made of a molding compound material. In these cases, the first material layer 122 is referred to as a molding compound layer. In some embodiments, the second material layer 120 is made of an underfill material. In these cases, the second material layer 120 is referred to as an underfill material layer.

[0075] An underfill material layer (e.g., a second material layer 120) is used to protect and support the semiconductor die from operational and environmental degradation, such as stress caused by heat generated during operation. The underfill material may be made of an epoxy resin or other protective material. In some embodiments, the formation of the underfill material layer includes an injection process, a dispensing process, a thin-film lamination process, one or more other suitable processes, or a combination thereof. In some embodiments, a thermosetting process is then used to cure the underfill material layer.

[0076] In some embodiments, after forming the second material layer 120, a molding compound material layer (e.g., a first material layer 122) is formed to seal the second material layer 120, semiconductor die 100-1, and semiconductor die 100-2, such that the sidewalls of semiconductor die 100-1 and semiconductor die 100-2 not covered by the bottom fill material layer are covered by the first material layer 122.

[0077] In some embodiments, the first material layer 122 of the insulating layer includes a molding compound. For example, a liquid molding compound material is applied over the interposer substrate 116, the semiconductor die 100-1, and the semiconductor die 100-2. Subsequently, a heat treatment process is applied to harden the liquid molding compound material.

[0078] According to some embodiments, the molded compound material layer is then etched back to expose the second material layer 120 (e.g., an underfill material layer), the upper surfaces of semiconductor die 100-1 and semiconductor die 100-2, such as... Figure 1E As shown. For example, a planarization process can be used to thin the hardened molding compound material layer (e.g., the first material layer 122). The planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another suitable process, or a combination thereof. As a result, the upper surfaces of the first material layer 122, the second material layer 120, the semiconductor die 100-1, and the semiconductor die 100-2 are substantially flush with each other.

[0079] According to some embodiments, after the planarization process, in Figure 1EA warpage release layer structure is formed on top of the structure shown to reduce warpage, such as... Figures 1F to 1G As shown. In some embodiments, forming the warp release layer structure includes forming an organic material (not shown) to cover... Figure 1E The structure shown. As a result, the organic material is in direct contact with the first material layer 122, the second material layer 120, the upper surfaces of the semiconductor die 100-1 and the semiconductor die 100-2.

[0080] Subsequently, organic materials are patterned to form an organic material layer 130a that directly contacts the back / non-active surface 100b of semiconductor die 100-1 and an organic material layer 130b that directly contacts the back / non-active surface 100b of semiconductor die 100-2. Organic material layers 130a and 130b expose the entire upper surface of the second material layer 120 and cover the entire upper surface of semiconductor die 100-1 and semiconductor die 100-2, respectively.

[0081] In some embodiments, the organic material layers 130a and 130b have a thickness ranging from about 2.5 micrometers to about 5 micrometers and are made of polymeric materials or polymer-containing layers, such as polyimide, polybenzoxazole, benzocyclobutene, etc. The organic material layers may include or be made of polyimide (PI), formed by a suitable deposition process (e.g., spin coating, chemical vapor deposition, or plasma-enhanced chemical vapor deposition (PECVD) process), and patterned by a photolithography process. Therefore, the organic material layers 130a and 130b are also referred to as polyimide layers.

[0082] According to some embodiments, after forming organic material layers 130a and 130b, the formation of the warp release layer structure further includes forming a high coefficient of thermal expansion (CTE) material layer 132a and a high coefficient of thermal expansion material layer 132b respectively on organic material layers 130a and 130b. Figure 1G As shown. In some embodiments, high thermal expansion coefficient material layers 132a and 132b are separated from each other and correspond to semiconductor dies 100-1 and 100-2, respectively. In this way, high thermal expansion coefficient material layers 132a and 132b cover the upper surfaces of semiconductor dies 100-1 and 100-2, respectively.

[0083] In some embodiments, the high thermal expansion coefficient material layer 132a (also referred to as the high thermal expansion coefficient material plate) has the same planar shape as the semiconductor die 100-1, such that the edges of the high thermal expansion coefficient material layer 132a are substantially aligned with the corresponding edges of the semiconductor die 100-1. Similarly, the high thermal expansion coefficient material layer 132b (also referred to as the high thermal expansion coefficient material plate) has the same planar shape as the semiconductor die 100-2, such that the edges of the high thermal expansion coefficient material layer 132b are substantially aligned with the corresponding edges of the semiconductor die 100-2.

[0084] In some embodiments, the high coefficient of thermal expansion material layers 132a and 132b have a coefficient of thermal expansion (CTE) substantially greater than 9 ppm / °C and are made of or comprise a metallic material. The metallic material may include copper (Cu), gold (Au), aluminum (Al), cobalt (Co), tungsten (W), or alloys thereof, and is formed by electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or other suitable processes. For example, a patterned photoresist layer (not shown), such as a dry film, is formed over the organic material layers 130a and 130b and the second material layer 120 by a photolithography process. The patterned photoresist layer has openings directly above the semiconductor dies 100-1 and 100-2 to expose portions of the organic material layers 130a and 130b. Subsequently, an electroplating process is performed to form a metallic material layer (e.g., a copper layer) in each opening of the patterned photoresist layer. The patterned photoresist layer is then removed to form high thermal expansion coefficient material layers 132a and 132b, which include metallic materials. Therefore, the high thermal expansion coefficient material layers 132a and 132b are also referred to as metallic layers.

[0085] A warp-relieving layer structure, comprising organic material layers 130a and 130b and high thermal expansion coefficient material layers 132a and 132b, can be used to prevent or mitigate warping of the subsequently formed chip package structure. As a result, the performance and quality of the chip package structure are improved.

[0086] According to some embodiments, after forming the warp release layer structure, the carrier substrate 200 is removed, and electrical connections 136 (e.g., controlled collapse chip connection (C4) bumps) are formed in the passivation layer 118 of the interposer substrate 116 to form a chip package structure 10, such as... Figure 1H As shown. More specifically, it can be... Figure 1GThe warp release layer structure shown is attached to tape supported by a frame (not shown). Subsequently, the carrier substrate 200 is peeled off to separate the interposer substrate 116 and the overlying structure from the carrier substrate 200. In some embodiments, the peeling process includes projecting light, such as a laser or ultraviolet light, onto the release layer (e.g., a photothermal conversion (LTHC) layer) on the carrier substrate 200, making the carrier substrate 200 easily removable. In some embodiments, the release layer is further removed or peeled off.

[0087] After removing the carrier substrate 200, the electrical connector 136 can be a solder ball, formed in the opening of the passivation layer 118 of the exposed bonding pads (not shown) of the exposed redistribution layer structure 113 using a ball-mounting head (not shown). This forms a chip package structure 10, such as... Figure 1H As shown.

[0088] In some embodiments, the electrical connector 136 is larger than the electrical connector 105. The electrical connector 136 may be made of a material such as tin, silver, lead-free tin, or copper. The electrical connector 136 serves as an electrical connection between the interposer substrate 116 and external circuitry (not shown). An optional under-bump metallization (UBM) layer (not shown) may be formed correspondingly between the bonding pads of the redistribution layer structure 113 and the electrical connector 136.

[0089] It should be noted that although two semiconductor dies 100-1 and 100-2 are formed in the chip package structure 10, the number of semiconductor dies is determined according to design requirements and is not limited to a specific number. Figure 1H The embodiments shown are illustrated. In some embodiments, the chip package structure 10 has two or more semiconductor dies, and each semiconductor die is covered by a corresponding high thermal expansion coefficient material layer.

[0090] According to some embodiments, after forming the chip package structure 10, the electrical connectors 136 are subjected to a flux impregnation process at room temperature to form a flux layer covering each electrical connector 136. Subsequently, the electrical connectors 136 are subjected to a flip chip bonding (FCB) process at high temperature to bond the chip package structure 10 to a package substrate (not shown) for connecting external circuitry (not shown).

[0091] During the flux impregnation process and subsequent flip-chip bonding process, warpage of the chip package structure 10 may occur due to the thermal expansion coefficient mismatch (CTE mismatch) between the semiconductor dies 100-1 and 100-2 and the interposer substrate 116. However, the warpage relief layer structure, which contains a material with a high CTE, can compensate for the difference in CTE between the semiconductor dies and the interposer substrate. In this way, warpage of the chip package structure 10 can be effectively controlled or reduced. Therefore, the problem of uneven flux (or no flux) after the flux impregnation process can be solved or mitigated, thereby increasing the flux impregnation process window. In addition, the problems of cold joint and bridging after the flip-chip bonding process can be solved or mitigated, thereby improving the device yield after the flip-chip bonding process.

[0092] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, in Figure 1H In the chip package structure 10 shown, the edge of the high thermal expansion coefficient material layer 132a is substantially aligned with the corresponding edge of the semiconductor die 100-1, and the edge of the high thermal expansion coefficient material layer 132b is substantially aligned with the corresponding edge of the semiconductor die 100-2. However, the embodiments of this disclosure are not limited thereto. Figure 1H-1 This shows a cross-sectional view of a chip package structure 10a according to some embodiments. Figure 1H-1 The chip packaging structure 10a shown is similar to Figure 1H The chip package structure 10 is shown. In some embodiments, Figures 1A to 1H The materials, forming methods, and / or advantages of the chip packaging structure 10 shown can also be applied to... Figure 1H-1 In the illustrated embodiment, this will therefore not be repeated. Figure 1H The chip packaging structure 10 shown is different from the one shown. Figure 1H-1 In the illustrated chip package structure 10a, the edges of the high thermal expansion coefficient material layers 132a and 132b are not aligned with the corresponding edges of the semiconductor dies 100-1 and 100-2, respectively. More specifically, the edge of the high thermal expansion coefficient material layer 132a is substantially aligned with the corresponding edge of the organic material layer 130a. Furthermore, the edge of the high thermal expansion coefficient material layer 132b is substantially aligned with the corresponding edge of the organic material layer 130b.

[0093] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, Figure 1H The chip package structure 10 shown employs a sealing layer including a bottom filler material layer, but the embodiments disclosed herein are not limited thereto. Figure 1H-2 This shows a cross-sectional view of a chip package structure 10b according to some embodiments. Figure 1H-2 The chip package structure 10b shown is similar to Figure 1H The chip package structure 10 is shown. In some embodiments, Figures 1A to 1H The materials, forming methods, and / or advantages of the chip packaging structure 10 shown can also be applied to... Figure 1H-2 In the illustrated embodiment, this will therefore not be repeated. Figure 1H The chip packaging structure 10 shown is different from the one shown. Figure 1H-2 The sealing layer in the illustrated chip package structure 10b comprises a homogeneous or single material. More specifically, the first material layer 122 is made of the same molding compound as the second material layer 120.

[0094] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, Figure 1H The chip package structure 10 shown includes two homogeneous semiconductor dies (e.g., semiconductor die 100-1 and semiconductor die 100-2), but the embodiments of this disclosure are not limited thereto. Figures 2A to 2E Cross-sectional views are shown of various stages of a method for forming a chip package structure 20 having at least two heterogeneous semiconductor dies, according to some embodiments. In some embodiments, Figures 1A to 1H The materials, forming methods, and / or advantages of the chip packaging structure 10 shown can also be applied to... Figures 2A to 2E The examples shown will not be repeated here.

[0095] It is possible Figures 2A to 2E Additional operations are provided before, during, and / or after the described stages. Some of the described stages may be replaced or eliminated in different embodiments. Additional features may be added to the semiconductor device structure. Some features described below may be replaced or eliminated in different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in a different logical order.

[0096] According to some embodiments, a similar Figure 1E One of the structures shown is, for example Figure 2A As shown. With Figure 1EThe structure shown differs in that, according to some embodiments, this structure includes two heterogeneous semiconductor dies 100 and 100' arranged side-by-side. For example, semiconductor die 100 is a logic die (e.g., a central processing unit (CPU) die, graphics processing unit (GPU) die, microcontroller unit (MCU) die, application processor (AP) die) or a system-on-a-chip (SoC) die. Semiconductor die 100' is a memory die or a die of a different type than semiconductor die 100, having a larger coefficient of thermal expansion than semiconductor die 100. The back / non-active surface 100b of semiconductor die 100 and the back / non-active surface 100b' of semiconductor die 100 are exposed from a sealing layer comprising a first material layer 122 and a second material layer 120.

[0097] According to some embodiments, then in Figure 2A A warped release layer structure is formed on top of the structure shown, such as Figures 2B to 2D As shown. In Figure 2B In the process, organic material layers 130a and 130b are first formed. More specifically, organic material layer 130a is in direct contact with the back / non-active surface 100b of semiconductor die 100, and organic material layer 130b is in direct contact with the back / non-active surface 100b' of semiconductor die 100'.

[0098] and Figure 1F Unlike the organic material layer 130b shown, the organic material layer 130b also includes an opening 131 that exposes a portion of the back / non-active surface 100b' of the semiconductor die 100' and can be arranged in an array. For example, the organic material layers 130a and 130b are made of polymer materials or polymer-containing layers, formed by a suitable deposition process (e.g., spin coating), and patterned by a photolithography process, as described above.

[0099] According to some embodiments, the formation of the warp release layer structure further includes forming high thermal expansion coefficient material layers 132a and 132b respectively on the organic material layers 130a and 130b, such as... Figure 2C As shown. In some embodiments, high thermal expansion coefficient material layers 132a and 132b are separated from each other and correspond to semiconductor dies 100 and 100', respectively. In this way, high thermal expansion coefficient material layers 132a and 132b cover the upper surfaces of semiconductor dies 100 and 100', respectively.

[0100] In some embodiments, the high thermal expansion coefficient material layer 132a has the same planar shape as the semiconductor die 100, such that the edges of the high thermal expansion coefficient material layer 132a are substantially aligned with the corresponding edges of the semiconductor die 100. Similarly, the high thermal expansion coefficient material layer 132b has the same planar shape as the semiconductor die 100', such that the edges of the high thermal expansion coefficient material layer 132b are substantially aligned with the corresponding edges of the semiconductor die 100'.

[0101] As an example, a patterned photoresist layer 135 (e.g., dry film) is formed on organic material layers 130a and 130b and the second material layer 120 using a photolithography process, and the opening 131 (not shown and as shown) is filled. Figure 2B (As shown in the diagram). The patterned photoresist layer 135 has openings directly above the semiconductor dies 100 and 100' to expose portions of the organic material layers 130a and 130b that will form high thermal expansion coefficient material layers 132a and 132b. An electroplating process is then performed to form a metal material layer (e.g., a copper layer) in each opening of the patterned photoresist layer 135. As a result, high thermal expansion coefficient material layers 132a and 132b comprising the metal material are formed. According to some embodiments, subsequently, from... Figure 2C The structure shown removes the patterned photoresist layer 135 to leave high thermal expansion material layers 132a and 132b, which include metallic materials, and forms an opening 133 in the high thermal expansion material layer 132b, as shown. Figure 2D As shown.

[0102] and Figure 1G Unlike the high thermal expansion coefficient material layer 132b shown, after the patterned photoresist layer 135 is removed, the opening 133 of the formed high thermal expansion coefficient material layer 132b correspondingly exposes the opening 131. The openings 131 and 133 form through-holes corresponding to the warp release layer structure of the semiconductor die 100'. In some embodiments, the size and shape of the opening 131 are the same as those of the opening 133, such as... Figure 4 As shown, Figure 4 Illustrations based on some embodiments Figure 2D The diagram shows a portion of the warp release layer structure (e.g., high thermal expansion coefficient material layer 132b). It should be noted that the shape, size, and arrangement of the through holes are based on design requirements and are not limited to... Figure 4 The exemplary embodiments shown. For example, although Figure 4 The through holes shown, including openings 131 and 133, are square, but these through holes can also be circular in some embodiments, such as... Figure 5 As shown. In some other embodiments, these through holes have triangular, rectangular, hexagonal, or other suitable shapes.

[0103] Through holes can be used to reduce the contact area between the high thermal expansion coefficient material layer 132b and the underlying organic material layer 130b. In this way, the thermal expansion coefficient of the high thermal expansion coefficient material layer 132b with openings 133 is less than that of the high thermal expansion coefficient material layer 132a without openings.

[0104] Since the coefficient of thermal expansion of semiconductor die 100' is greater than that of semiconductor die 100 and the coefficient of thermal expansion of high coefficient of thermal expansion material layer 132b is less than that of high coefficient of thermal expansion material layer 132a, a warp release layer structure with through holes can prevent or mitigate the mismatch of coefficients of thermal expansion between semiconductor die 100' and semiconductor die 100 during subsequent flux impregnation and flip chip bonding processes.

[0105] According to some embodiments, after forming a warp release layer structure with through holes, the carrier substrate 200 is removed, and an electrical connector 136 is formed in the passivation layer 118 of the interposer substrate 116 to form a chip package structure 20, such as... Figure 2E As shown.

[0106] It should be noted that although two heterogeneous semiconductor dies 100 and 100' are formed in the chip package structure 20, the number of heterogeneous semiconductor dies is determined according to design requirements and is not limited to a specific number. Figure 2E The illustrated embodiment. In some embodiments, the chip package structure 20 comprises two or more heterogeneous semiconductor dies, and each semiconductor die is covered by a corresponding high thermal expansion coefficient material layer.

[0107] According to some embodiments, after forming the chip package structure 20, the electrical connectors 136 are subjected to a flux impregnation process at room temperature to form a flux layer covering each electrical connector 136. Subsequently, the electrical connectors 136 are subjected to a flip-chip bonding (FCB) process at high temperature to bond the chip package structure 20 to a package substrate (not shown) for connecting external circuitry (not shown).

[0108] The warpage relief layer structure with through-holes can not only mitigate the thermal expansion coefficient mismatch between semiconductor dies 100 and 100' during subsequent flux impregnation and flip-chip bonding processes, but also mitigate the thermal expansion coefficient mismatch between semiconductor dies 100 and 100' and the interposer substrate 116. In this way, warpage of the chip package structure 20 can be effectively controlled or reduced.

[0109] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, in Figure 2EIn the chip package structure 20 shown, the edge of the high thermal expansion coefficient material layer 132a is substantially aligned with the corresponding edge of the semiconductor die 100, and the edge of the high thermal expansion coefficient material layer 132b is substantially aligned with the corresponding edge of the semiconductor die 100'. However, the embodiments of this disclosure are not limited thereto. Figure 2E-1 This shows a cross-sectional view of a chip package structure 20a according to some embodiments. Figure 2E-1 The chip package structure 20a shown is similar to Figure 2E The chip package structure 20 is shown. In some embodiments, Figures 2A to 2E The materials, formation methods, and / or advantages of the chip package structure 20 shown can also be applied to the embodiment shown in Figure 2E-1, and therefore will not be repeated. Figure 2E The chip packaging structure 20 shown is different from that shown. Figure 2E-1 In the illustrated chip package structure 20a, the edges of the high thermal expansion coefficient material layers 132a and 132b are not aligned with the corresponding edges of the semiconductor dies 100 and 100', respectively. More specifically, the edge of the high thermal expansion coefficient material layer 132a is substantially aligned with the corresponding edge of the organic material layer 130a. Furthermore, the edge of the high thermal expansion coefficient material layer 132b is substantially aligned with the corresponding edge of the organic material layer 130b.

[0110] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, Figure 2E The chip package structure 20 shown employs a sealing layer including a bottom filler material layer, but the embodiments disclosed herein are not limited thereto. Figure 2E-2 This shows a cross-sectional view of a chip package structure 20b according to some embodiments. Figure 2E-2 The chip package structure 20b shown is similar to the chip package structure 20 shown in Figure 2E. In some embodiments, Figures 2A to 2E The materials, forming methods, and / or advantages of the chip package structure 20 shown can also be applied to... Figure 2E-2 In the illustrated embodiment, this will therefore not be repeated. Figure 2E The chip packaging structure 20 shown is different from that shown. Figure 2E-2 The sealing layer in the illustrated chip package structure 20b comprises a homogeneous or single material. More specifically, the first material layer 122 is made of the same molding compound as the second material layer 120.

[0111] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, Figure 2E The chip package structure 20 shown includes a semiconductor die 100' with a coefficient of thermal expansion greater than that of the semiconductor die 100, but the embodiments disclosed herein are not limited thereto. Figures 3A to 3ECross-sectional views are shown of various stages of a method for forming a semiconductor die 100' having a coefficient of thermal expansion less than that of the semiconductor die 100, according to some embodiments. In some embodiments, Figures 2A to 2E The materials, forming methods, and / or advantages of the chip package structure 20 shown can also be applied to... Figures 3A to 3E The examples shown will therefore not be repeated. [The rest of the text is missing.] Figures 3A to 3E Additional operations are provided before, during, and / or after the described stages. For different embodiments, some of the described stages may be replaced or eliminated.

[0112] Additional features can be added to the semiconductor device structure. For different embodiments, some of the features described below can be replaced or eliminated. Although some embodiments are discussed with operations performed in a specific order, these operations can be performed in a different logical order.

[0113] According to some embodiments, a similar Figure 1F One of the structures shown is, for example Figure 3A As shown. With Figure 1F The structure shown differs in that, according to some embodiments, this structure includes two heterogeneous semiconductor dies 100 and 100” arranged side-by-side. For example, semiconductor die 100 is a logic die (e.g., a central processing unit (CPU) die, a graphics processing unit (GPU) die, a microcontroller unit (MCU) die, an application processor (AP) die) or a system-on-a-chip (SoC) die. Semiconductor die 100” is a memory die or a die of a different type than semiconductor die 100, having a smaller coefficient of thermal expansion than semiconductor die 100. The back / non-active surface 100b of semiconductor die 100 and the back / non-active surface 100b” of semiconductor die 100” are in direct contact with organic material layers 130a and 130b, respectively.

[0114] According to some embodiments, a column 142 having a coefficient of thermal expansion substantially equal to or greater than 9 ppm / °C is then formed on the organic material layer 130b, such as... Figure 3B As shown. For example, pillar 142 is made of a metallic material (e.g., copper (Cu), gold (Au), aluminum (Al), cobalt (Co), tungsten (W), or alloys thereof). In this case, the formation of pillar 142 includes forming a patterned photoresist layer 140 (e.g., a dry film) over organic material layers 130a and 130b and a second material layer 120 by a photolithography process. The patterned photoresist layer 140 has openings to expose portions of the organic material layer 130b where pillar 142 will be formed. An electroplating process is then performed to form a metallic material layer in each opening of the patterned photoresist layer 140. According to some embodiments, subsequently, from Figure 3B The structure shown removes the patterned photoresist layer 140 to leave pillars 142 on the organic material layer 130b, as... Figure 3C As shown.

[0115] After column 142 is formed, an organic material (not shown) is formed to cover it. Figure 3C The structure is shown. In this way, the organic material is in direct contact with the upper surfaces of organic material layers 130a, 130b, pillars 142, and the second material layer 120. According to some embodiments, the organic material is then patterned to form an organic material layer 134a corresponding to organic material layer 130a and an organic material layer 134b corresponding to organic material layer 130b, as shown. Figure 3D As shown. The formed organic material layer 134b surrounds the pillar 142 and exposes the upper surface of each pillar 142.

[0116] In some embodiments, the stack of organic material layers 130a and 134a and the stack of organic material layers 130b and 134b have a total thickness ranging from about 5 micrometers to about 10 micrometers. The organic materials used to form organic material layers 134a and 134b include or are made of materials that are the same as or different from the organic materials used to form organic material layers 130a and 130b. For example, the organic material may include or be made of polyimide (PI), formed by a suitable deposition process (e.g., spin coating, chemical vapor deposition (CVD), or plasma-assisted chemical vapor deposition (PECVD) process), and patterned by a photolithography process. Therefore, organic material layers 134a and 134b are also referred to as polyimide layers.

[0117] According to some embodiments, after forming organic material layers 134a and 134b, high thermal expansion coefficient material layers 132a and 132b are formed on top of organic material layers 134a and 134b, respectively. Figure 3E As shown. In some embodiments, high thermal expansion coefficient material layers 132a and 132b are separated from each other and correspond to semiconductor dies 100 and 100”, respectively. Thus, high thermal expansion coefficient material layers 132a and 132b cover the upper surfaces of semiconductor dies 100 and 100”, respectively. Furthermore, pillar 142 is covered by and in direct contact with high thermal expansion coefficient material layer 132b. In some embodiments, high thermal expansion coefficient material layers 132a and 132b comprise or are made of the same material as the pillar 142.

[0118] In some embodiments, the high thermal expansion coefficient material layer 132a has the same planar shape as the semiconductor die 100, such that the edges of the high thermal expansion coefficient material layer 132a are substantially aligned with the corresponding edges of the semiconductor die 100. Similarly, the high thermal expansion coefficient material layer 132b has the same planar shape as the semiconductor die 100”, such that the edges of the high thermal expansion coefficient material layer 132b are substantially aligned with the corresponding edges of the semiconductor die 100”.

[0119] and Figure 1H or Figure 2E Unlike the high thermal expansion coefficient material layer 132b shown, the formed high thermal expansion coefficient material layer 132b has pillars 142 extending from its bottom surface, such as... Figure 3E As shown. Figure 6 Illustrations based on some embodiments Figure 3E The diagram shows a portion of the warp release layer structure (e.g., layer 132b, a material with a high coefficient of thermal expansion). It should be noted that the shape, size, and arrangement of the columns are based on design requirements and are not limited to... Figure 6 The exemplary embodiments shown. For example, although Figure 6 The columns 142 shown are square, but these columns 142 can also be circular according to some embodiments, such as... Figure 7 As shown. In some other embodiments, these pillars 142 have triangular, rectangular, hexagonal or other suitable shapes.

[0120] The pillar 142 can be used to increase the contact area between the high thermal expansion coefficient material layer 132b and the underlying organic material layer including the organic material layer 130b. In this way, the thermal expansion coefficient of the high thermal expansion coefficient material layer 132b with the pillar 142 is greater than that of the high thermal expansion coefficient material layer 132a without the pillar.

[0121] Since the coefficient of thermal expansion of semiconductor die 100” is less than that of semiconductor die 100 and the coefficient of thermal expansion of high coefficient of thermal expansion material layer 132b with pillar 142 is greater than that of high coefficient of thermal expansion material layer 132a, the warp release layer structure with pillars can prevent or mitigate the mismatch of coefficients of thermal expansion between semiconductor die 100” and semiconductor die 100 during subsequent flux impregnation and flip chip bonding processes.

[0122] According to some embodiments, after forming the warp release layer structure with pillars 142, the carrier substrate 200 is removed, and electrical connectors 136 are formed in the passivation layer 118 of the interposer substrate 116 to form a chip package structure 30, such as... Figure 3E As shown.

[0123] It should be noted that although two semiconductor dies 100 and 100" are formed in the chip package structure 30, the number of heterogeneous semiconductor dies is determined according to design requirements and is not limited to a specific number. Figure 3E The illustrated embodiment. In some embodiments, the chip package structure 30 comprises two or more heterogeneous semiconductor dies, and each semiconductor die is covered by a corresponding high thermal expansion coefficient material layer.

[0124] According to some embodiments, after forming the chip package structure 30, the electrical connectors 136 are subjected to a flux impregnation process at room temperature to form a flux layer covering each electrical connector 136. Subsequently, the electrical connectors 136 are subjected to a flip-chip bonding (FCB) process at high temperature to bond the chip package structure 30 to a package substrate (not shown) for connecting external circuitry (not shown).

[0125] The warp release layer structure with pillars 142 not only mitigates the thermal expansion coefficient mismatch between semiconductor dies 100 and 100” during subsequent flux impregnation and flip-chip bonding processes, but also mitigates the thermal expansion coefficient mismatch between semiconductor dies 100 and 100” and the interposer substrate 116. In this way, warpage of the chip package structure 30 can be effectively controlled or reduced.

[0126] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, in Figure 3E In the chip package structure 30 shown, the edge of the high thermal expansion coefficient material layer 132a is substantially aligned with the corresponding edge of the semiconductor die 100, and the edge of the high thermal expansion coefficient material layer 132b is substantially aligned with the corresponding edge of the semiconductor die 100". However, the embodiments of this disclosure are not limited thereto. Figure 3E-1 This shows a cross-sectional view of a chip package structure 30a according to some embodiments. Figure 3E-1 The chip package structure 30a shown is similar to Figure 3E The chip package structure 30 shown is illustrated. In some embodiments, the materials, formation methods, and / or advantages of the chip package structure 30 shown in Figures 3A to 3E may also be applied. Figure 3E-1 In the illustrated embodiment, this will therefore not be repeated. Figure 3E The chip packaging structure 30 shown is different from the one shown. Figure 3E-1 In the chip package structure 30a shown, the edges of the high thermal expansion coefficient material layers 132a and 132b are not aligned with the corresponding edges of the semiconductor dies 100 and 100”, respectively. More specifically, the edge of the high thermal expansion coefficient material layer 132a is substantially aligned with the corresponding edges of the organic material layers 130a and 134a. Furthermore, the edge of the high thermal expansion coefficient material layer 132b is substantially aligned with the corresponding edges of the organic material layers 130b and 134b.

[0127] Many changes and / or modifications can be made to the embodiments of this disclosure. For example, Figure 3E The chip package structure 30 shown employs a sealing layer including a bottom filler material layer, but the embodiments disclosed herein are not limited thereto. Figure 3E-2 This shows a cross-sectional view of a chip package structure 30b according to some embodiments. Figure 3E-2 The chip package structure 30b shown is similar to Figure 3E The chip package structure 30 is shown. In some embodiments, Figures 3A to 3E The materials, forming methods, and / or advantages of the chip package structure 30 shown can also be applied to... Figure 3E-2 In the illustrated embodiment, this will therefore not be repeated. Figure 3E The chip packaging structure 30 shown is different from the one shown. Figure 3E-2 The sealing layer in the illustrated chip package structure 30b comprises a homogeneous or single material. More specifically, the first material layer 122 is made of the same molding compound as the second material layer 120.

[0128] Embodiments of this disclosure provide a chip package structure and a method for forming it. The chip package structure includes a semiconductor die bonded onto an interposer substrate. A warpage relief layer structure is formed on the interposer substrate and includes at least one organic material layer in direct contact with the upper surface of the semiconductor die, and a high coefficient of thermal expansion (CTE) material layer formed on the organic material layer. The CTE material layer has a CTE coefficient substantially equal to or greater than 9 ppm / °C. By using the CTE material layer formed on the semiconductor die, stresses formed in the package at high temperatures due to the CTE mismatch between the semiconductor die and the interposer substrate, as well as stresses formed in the package at room temperature, are mitigated, thus reducing package warpage.

[0129] According to some embodiments of this disclosure, a chip packaging structure is provided. The chip packaging structure includes an interposer substrate, a first semiconductor die, and a warp release layer structure. The first semiconductor die is bonded to the interposer substrate. The warp release layer structure includes a first organic material layer and a first high coefficient of thermal expansion material layer. The first organic material layer is in direct contact with the upper surface of the first semiconductor die. The coefficient of thermal expansion of the first high coefficient of thermal expansion material layer is substantially equal to or greater than 9 ppm / °C, and the first high coefficient of thermal expansion material layer is formed on the first organic material layer and covers the upper surface of the first semiconductor die.

[0130] In some embodiments, the chip package structure further includes a second semiconductor die bonded to an interposer substrate. The coefficient of thermal expansion (CTO) of the second semiconductor die is the same as that of the first semiconductor die. The warp release layer structure further includes a second organic material layer and a second high CTO material layer. The second organic material layer is in direct contact with the upper surface of the second semiconductor die. The CTO of the second high CTO material layer is substantially equal to or greater than 9 ppm / °C, and the second high CTO material layer is formed on the second organic material layer and covers the upper surface of the second semiconductor die. In some embodiments, the first and second semiconductor dies are logic dies. In some embodiments, the first and second high CTO material layers are made of copper. In some embodiments, the chip package structure further includes a second semiconductor die bonded to an interposer substrate. The CTO of the second semiconductor die is less than that of the first semiconductor die. The warp release layer structure further includes a second organic material layer, a third organic material layer, a fourth organic material layer, a second high CTO material layer, and a plurality of pillars. The second organic material layer is formed between the first organic material layer and the first high CTO material layer. The third organic material layer is in direct contact with the upper surface of the second semiconductor die. A fourth organic material layer is formed on top of the third organic material layer. The coefficient of thermal expansion of the second high coefficient of thermal expansion material layer is substantially equal to or greater than 9 ppm / °C, and the second high coefficient of thermal expansion material layer is formed on top of the fourth organic material layer, filling multiple openings in the fourth organic material layer and covering the upper surface of the second semiconductor die. The coefficient of thermal expansion of the pillar is substantially equal to or greater than 9 ppm / °C, and the pillar is formed in the fourth organic material layer and covered by the second high coefficient of thermal expansion material layer. In some embodiments, the first semiconductor die is a logic die, and the second semiconductor die is a memory die. In some embodiments, the first and second high coefficient of thermal expansion material layers are made of copper. In some embodiments, the chip package structure further includes a second semiconductor die bonded to an interposer substrate. The coefficient of thermal expansion of the second semiconductor die is greater than that of the first semiconductor die. The warp release layer structure further includes a second organic material layer and a second high coefficient of thermal expansion material layer. The second organic material layer is in direct contact with the upper surface of the second semiconductor die and has multiple first openings exposing portions of the upper surface of the second semiconductor die. The second high thermal expansion coefficient material layer has a thermal expansion coefficient substantially equal to or greater than 9 ppm / °C, and is formed on top of the second organic material layer, having a plurality of second openings correspondingly exposing the first opening and covering the upper surface of the second semiconductor die. In some embodiments, the first semiconductor die is a logic die, and the second semiconductor die is a memory die. In some embodiments, the first and second high thermal expansion coefficient material layers are made of copper.

[0131] According to other embodiments of this disclosure, a chip packaging structure is provided. The chip packaging structure includes an interposer substrate, a molding compound layer, a first semiconductor die, a second semiconductor die, and a warp release layer structure. The molding compound layer is formed on the interposer substrate. The first and second semiconductor dies are bonded to the interposer substrate and surrounded by the molding compound layer. The warp release layer structure includes a first polyimide layer, a first metal layer, and a second metal layer. The first polyimide layer is in direct contact with the upper surfaces of the first and second semiconductor dies. The first and second metal layers are formed on the first polyimide layer and are separated from each other to respectively cover the upper surfaces of the first and second semiconductor dies.

[0132] In some embodiments, the warp release layer structure further includes a second polyimide layer and a plurality of metal pillars. The second polyimide layer is formed on the first polyimide layer and is covered by a first metal layer and a second metal layer. The metal pillars are formed in the second polyimide layer and are covered by the second metal layer. In some embodiments, the metal pillars are in direct contact with the upper surface of the first polyimide layer. In some embodiments, the first polyimide layer has a plurality of first openings exposing portions of the upper surface of the second semiconductor die, and the second metal layer has a plurality of second openings correspondingly exposing the first openings. In some embodiments, the chip package structure further includes an underfill material layer formed between the first semiconductor die and the second semiconductor die, between the interposer substrate and the first semiconductor die, and between the interposer substrate and the second semiconductor die.

[0133] According to other embodiments of this disclosure, a method for forming a chip package structure is provided. The method includes mounting a first semiconductor die and a second semiconductor die on an interposer substrate. The method also includes forming an sealing layer on the interposer substrate to surround the first and second semiconductor dies. The method further includes forming a first organic material layer in direct contact with the upper surfaces of the first and second semiconductor dies and the sealing layer. Furthermore, the method includes forming a first metal layer and a second metal layer on the first organic material layer, wherein the first and second metal layers are separated from each other to respectively cover the upper surfaces of the first and second semiconductor dies.

[0134] In some embodiments, the method further includes forming a plurality of first openings in a first organic material layer on a second semiconductor die before forming the first metal layer and the second metal layer to expose portions of the upper surface of the second semiconductor die, wherein the formed second metal layer has a plurality of second openings correspondingly exposing the first openings. In some embodiments, the method further includes forming a plurality of metal pillars on the first organic material layer on the second semiconductor die and forming a second organic material layer surrounding the metal pillars before forming the first metal layer and the second metal layer. In some embodiments, forming the sealing layer further includes: forming an underfill material layer between the first semiconductor die and the second semiconductor die, between an interposer substrate and the first semiconductor die, and between the interposer substrate and the second semiconductor die; forming a molding compound layer to cover the underfill material layer, the first semiconductor die, and the second semiconductor die; and recessing the molding compound layer to expose the underfill material layer, the upper surface of the first semiconductor die, and the second semiconductor die. In some embodiments, the sealing layer includes a molding compound material and extends between the first semiconductor die and the second semiconductor die, between the interposer substrate and the first semiconductor die, and between the interposer substrate and the second semiconductor die.

[0135] The foregoing outlines features of numerous embodiments to enable those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. A chip packaging structure, comprising: A substrate with an intermediate layer; A first semiconductor die is bonded onto the interposer substrate; A warp release layer structure, comprising: A first organic material layer is in direct contact with an upper surface of the first semiconductor die; and A first high thermal expansion coefficient material layer, having a thermal expansion coefficient substantially equal to or greater than 9 ppm / ℃, is formed on the first organic material layer and covers the upper surface of the first semiconductor die; and A second semiconductor die is bonded onto the interposer substrate. The coefficient of thermal expansion of the second semiconductor die is greater than that of the first semiconductor die, and The warped release layer structure also includes: A second organic material layer, in direct contact with an upper surface of the second semiconductor die and having a plurality of first openings exposing a portion of the upper surface of the second semiconductor die; and A second high thermal expansion coefficient material layer, having a thermal expansion coefficient substantially equal to or greater than 9 ppm / ℃, is formed on the second organic material layer, having a plurality of second openings correspondingly exposing a plurality of the first openings and the upper surface covering the second semiconductor die.

2. The chip packaging structure as described in claim 1, wherein the first semiconductor die is a logic die and the second semiconductor die is a memory die.

3. The chip packaging structure as claimed in claim 1, wherein the first high thermal expansion coefficient material layer and the second high thermal expansion coefficient material layer are made of copper.

4. A chip packaging structure, comprising: A substrate with an intermediate layer; A molded compound layer is formed on the intermediate layer substrate; A first semiconductor die and a second semiconductor die are bonded to the interposer substrate and surrounded by the molding compound layer; as well as A warp release layer structure, comprising: A first polyimide layer is in direct contact with the upper surfaces of the first semiconductor die and the second semiconductor die; and A first metal layer and a second metal layer are formed on the first polyimide layer and are separated from each other to respectively cover the upper surface of the first semiconductor die and the upper surface of the second semiconductor die. The warped release layer structure also includes: A second polyimide layer is formed on the first polyimide layer and covered by the first metal layer and the second metal layer; and Multiple metal pillars are formed in the second polyimide layer and covered by the second metal layer.

5. The chip packaging structure of claim 4, wherein the plurality of metal pillars are in direct contact with an upper surface of the first polyimide layer.

6. The chip packaging structure as described in claim 4, further comprising: A bottom filler material layer is formed between the first semiconductor die and the second semiconductor die, between the interposer substrate and the first semiconductor die, and between the interposer substrate and the second semiconductor die.

7. A method for forming a chip package structure, comprising: A first semiconductor die and a second semiconductor die are mounted on an interposer substrate; A sealing layer is formed on the interposer substrate to surround the first semiconductor die and the second semiconductor die; A first organic material layer is formed that is in direct contact with the upper surfaces of the first semiconductor die, the second semiconductor die, and the sealing layer; A first metal layer and a second metal layer are formed on the first organic material layer, wherein the first metal layer and the second metal layer are separated from each other to respectively cover the upper surface of the first semiconductor die and the upper surface of the second semiconductor die; as well as Before forming the first metal layer and the second metal layer, a plurality of metal pillars are formed on the first organic material layer on the second semiconductor die, and a second organic material layer is formed around the plurality of said metal pillars.

8. The method for forming a chip package structure as described in claim 7, wherein forming the sealing layer further comprises: A bottom filler layer is formed between the first semiconductor die and the second semiconductor die, between the interposer substrate and the first semiconductor die, and between the interposer substrate and the second semiconductor die; A molding compound layer is formed to cover the bottom filler layer, the first semiconductor die, and the second semiconductor die; as well as The molding compound layer is recessed to expose the bottom filler layer, the upper surface of the first semiconductor die, and the upper surface of the second semiconductor die.

9. The method of forming a chip package structure as claimed in claim 7, wherein the sealing layer comprises a molding compound material and extends between the first semiconductor die and the second semiconductor die, between the interposer substrate and the first semiconductor die, and between the interposer substrate and the second semiconductor die.

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