A semiconductor structure and a method of fabricating the same

Abstract

Embodiments of the present application disclose a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate, the substrate comprising opposite upper and lower surfaces; a through-hole structure penetrating through the substrate; a groove in the substrate on the side of the upper surface, and a barrier structure in the groove; and a gap in the substrate on the outside of the side wall of the through-hole structure; wherein the gap is located below the barrier structure, and a first end of the gap is in contact with the bottom of the barrier structure.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a semiconductor structure and its fabrication method. Background Technology

[0002] 3D integrated circuits are defined as a system integration structure that stacks multiple chips in a vertical plane to save space. Most existing 3D integrated circuit technologies use through-silicon vias (TSVs) to achieve electrical connections between multiple chips, but existing TSV structures have significant design problems that affect device operation. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a semiconductor structure and a method for preparing the same.

[0004] According to a first aspect of the present invention, a semiconductor structure is provided, the semiconductor structure comprising:

[0005] A substrate, the substrate including opposing upper and lower surfaces;

[0006] Through-hole structure penetrating the substrate;

[0007] A trench located in the substrate on one side of the upper surface, and a blocking structure located in the trench;

[0008] The void in the substrate located outside the sidewall of the through-hole structure; wherein,

[0009] The gap is located below the blocking structure, and the first end of the gap is in contact with the bottom of the blocking structure.

[0010] In some embodiments, the coefficient of thermal expansion of the barrier structure is less than that of the substrate; and / or, the elastic modulus of the barrier structure is greater than that of the substrate.

[0011] In some embodiments, the width of the bottom of the blocking structure is not less than the width of the gap, and the width of the bottom of the blocking structure and the width of the gap are respectively the widths of the blocking structure and the gap along a first direction, wherein the first direction is a direction parallel to the substrate.

[0012] In some embodiments, the width of the gap increases along a second direction, wherein the second direction is perpendicular to the substrate and points from the lower surface of the substrate to the upper surface of the substrate.

[0013] In some embodiments, the gap includes a first gap near the upper surface of the substrate and a second gap near the lower surface of the substrate;

[0014] The width of the first gap along the first direction is greater than the width of the second gap along the first direction.

[0015] In some embodiments, the width of the first end of the gap that contacts the bottom of the blocking structure along a first direction is equal to the width of the bottom of the blocking structure along the first direction.

[0016] In some embodiments, the semiconductor structure further includes:

[0017] A circuit structure comprising a first portion located on the upper surface of the substrate and a second portion located within the substrate near the upper surface;

[0018] The height of the second part is equal to the sum of the heights of the blocking structure and the first gap.

[0019] In some embodiments, the semiconductor structure further includes:

[0020] A protective layer covering the lower surface of the substrate, the protective layer sealing the opening at the second end of the void, which is positioned opposite the first end.

[0021] In some embodiments, the materials of the barrier structure and the protective layer have a high etching selectivity.

[0022] According to a second aspect of the present invention, a method for fabricating a semiconductor structure is provided, the method comprising:

[0023] A substrate is provided, the substrate including opposing upper and lower surfaces;

[0024] Trenches are formed by etching the substrate from its upper surface, and a first material is filled into the trenches to form a barrier structure.

[0025] Forming a through-hole structure penetrating the substrate;

[0026] The substrate is etched from the lower surface of the substrate to form a groove in the substrate outside the sidewall of the via structure. The barrier structure serves as an etching stop layer for etching the groove, such that the first end of the groove near the upper surface of the substrate stops at the bottom of the barrier structure near the lower surface of the substrate.

[0027] A protective layer is formed covering the lower surface of the substrate, the protective layer covering the opening of the groove to form a void inside the substrate.

[0028] In some embodiments, before forming a groove in the substrate outside the sidewall of the via structure, the method further includes:

[0029] A pre-protective layer is formed covering the lower surface of the substrate;

[0030] Forming a groove in the substrate outside the sidewall of the through-hole structure includes: etching the pre-protective layer and the substrate from the lower surface of the pre-protective layer to form a groove in the pre-protective layer and the substrate;

[0031] Forming a void inside the substrate includes: forming a secondary protective layer covering the lower surface of the pre-protective layer, the secondary protective layer covering the opening of the groove to form a void inside the substrate; wherein the pre-protective layer and the secondary protective layer together constitute a protective layer.

[0032] In some embodiments, the materials of the first material and the pre-protective layer have a high etching selectivity ratio.

[0033] In some embodiments, the coefficient of thermal expansion of the barrier structure is less than that of the substrate; and / or, the elastic modulus of the barrier structure is greater than that of the substrate.

[0034] In some embodiments, the width of the bottom of the blocking structure is not less than the width of the gap, and the width of the bottom of the blocking structure and the width of the gap are respectively the widths of the blocking structure and the gap along a first direction, wherein the first direction is a direction parallel to the substrate.

[0035] In some embodiments, the width of the gap increases along a second direction, wherein the second direction is perpendicular to the substrate and points from the lower surface of the substrate to the upper surface of the substrate.

[0036] In some embodiments, the gap includes a first gap near the upper surface of the substrate and a second gap near the lower surface of the substrate;

[0037] The width of the first gap along the first direction is greater than the width of the second gap along the first direction.

[0038] In some embodiments, the width of the first end of the gap that contacts the bottom of the blocking structure along a first direction is equal to the width of the bottom of the blocking structure along the first direction.

[0039] In some embodiments, after forming the barrier structure, the method further includes:

[0040] A circuit structure is formed, the circuit structure including a first portion located on the upper surface of the substrate and a second portion located within the substrate near the upper surface;

[0041] The height of the second part is equal to the sum of the heights of the blocking structure and the first gap.

[0042] In this embodiment of the invention, by setting a gap on the outer sidewall of the via structure, the gap can block the stress generated by the via structure during contraction or expansion from being transmitted to the surrounding circuit structure, thus ensuring the stability of the device performance. At the same time, it increases the area of ​​the semiconductor structure that is not affected by stress, thereby increasing the number of circuit structures. Furthermore, by setting a blocking structure, it can serve as an etching stop layer when preparing the gap, preventing the gap from penetrating the substrate and causing device instability. Attached Figure Description

[0043] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure in related technologies;

[0044] Figure 2 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention;

[0045] Figures 3a-3b Cross-sectional schematic diagrams of different embodiments of the gaps in the semiconductor structure provided in the embodiments of the present invention;

[0046] Figure 4 This is a cross-sectional schematic diagram of a semiconductor structure provided in another embodiment of the present invention;

[0047] Figure 5a This is a schematic diagram of the planar structure of the annular gap in the semiconductor structure provided in an embodiment of the present invention;

[0048] Figure 5b This is a schematic diagram of the planar structure of the annular gap in the semiconductor structure provided in an embodiment of the present invention;

[0049] Figure 6 A schematic flowchart illustrating the method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0050] Figures 7a to 7j This is a schematic diagram of the device structure during the fabrication process of the semiconductor structure provided in an embodiment of the present invention.

[0051] Explanation of reference numerals in the attached figures:

[0052] 10 - Substrate; 101 - Upper surface; 102 - Lower surface;

[0053] 20, 20' - Circuit structure; 21 - First part; 22 - Second part;

[0054] 30 - Barrier structure; 301 - Groove;

[0055] 401 - Through-hole; 40, 40' - Through-hole structure; 41 - Conductive layer; 42 - Barrier layer; 43 - Insulating layer;

[0056] 50 - Protective layer; 51 - Pre-protective layer; 52 - Secondary protective layer;

[0057] 60 - Gap; 61 - First gap; 62 - Second gap; 601 - Groove;

[0058] 70 - Dielectric layer. Detailed Implementation

[0059] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0060] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid obscuring the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0061] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0062] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0063] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0065] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution of this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0066] Through-hole structures enable interconnections between chips with the shortest distance and smallest spacing, resulting in better electrical performance. Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure in related technologies, such as... Figure 1 As shown, conductive materials such as copper or tungsten are filled in the through-hole structure 40'. However, the stress generated by the conductive material when it contracts or expands will be transmitted to the adjacent circuit structure 20', affecting its electrical performance.

[0067] Based on this, embodiments of the present invention provide a semiconductor structure. Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present invention.

[0068] See Figure 2The semiconductor structure includes: a substrate 10, the substrate 10 including an upper surface 101 and a lower surface 102 opposite to each other; a through-hole structure 40 penetrating the substrate 10; a trench 301 located in the substrate 10 on one side of the upper surface 101, and a blocking structure 30 located in the trench 301; a gap 60 located in the substrate 10 on the outside of the sidewall of the through-hole structure 40; wherein the gap 60 is located below the blocking structure 30, and a first end of the gap 60 contacts the bottom of the blocking structure 30.

[0069] In this embodiment of the invention, by providing a gap on the outer sidewall of the via structure, the gap can block the stress generated by the via structure during contraction or expansion from being transmitted to the surrounding circuit structure, ensuring the stability of device performance. At the same time, it increases the area of ​​the semiconductor structure that is not affected by stress, thereby increasing the number of circuit structures that can be arranged. Furthermore, the barrier structure not only reduces the impact of the stress generated by the via structure on the surrounding circuit structure because its coefficient of expansion is smaller than that of the substrate, but it can also serve as an etching stop layer when etching the gap, simplifying the process and avoiding etching through the substrate, thus improving the stability of device performance.

[0070] In one embodiment, the substrate 10 may be a single-element semiconductor material substrate (e.g., a silicon (Si) substrate), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate), or a silicon-on-insulator (SOI) substrate. This embodiment uses a silicon substrate as an example for illustration. The substrate 10 may include an upper surface 101 on the front side and a lower surface 102 on the back side opposite to the front side.

[0071] In one embodiment, the semiconductor structure further includes a circuit structure 20, the circuit structure 20 including a first portion 21 located on the upper surface of the substrate 10 and a second portion 22 located within the substrate 10 near the upper surface.

[0072] The circuit structure 20 can be any type of circuit suitable for a specific application. For example, the circuit structure 20 may include various N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc., interconnected to perform one or more functions. Functions may include memory structures, processor structures, sensors, amplifiers, power distribution, input / output circuits, etc.

[0073] In one embodiment, the semiconductor structure further includes a dielectric layer 70 located on the upper surface of the substrate. The dielectric layer 70 completely covers the circuit structure 20 to protect the circuit structure.

[0074] The material of the dielectric layer 70 may include silicon oxide, silicon nitride, etc.

[0075] In one embodiment, the semiconductor structure further includes a via structure 40 penetrating the substrate 10. The via structure 40 includes a conductive layer 41, a barrier layer 42, and an insulating layer 43 sequentially disposed in the via 401 along a radially outward direction.

[0076] The conductive layer 41 is located at the innermost side of the through-hole structure 40; the material of the conductive layer 41 may include copper or tungsten and other related integrated circuit conductive materials.

[0077] A barrier layer 42 is formed on the outer side of the conductive layer 41, and the barrier layer 42 is in contact with the conductive layer 41. The barrier layer 42 is an annular structure surrounding the conductive layer 41. The material of the barrier layer 42 may include tantalum, titanium, or other relevant integrated circuit barrier materials.

[0078] An insulating layer 43 is formed on the outer side of the barrier layer 42, and the insulating layer 43 is in contact with the barrier layer 42. The insulating layer 43 is an annular structure surrounding the barrier layer 42. The material of the insulating layer 43 may include silicon oxide, silicon nitride, or other related integrated circuit insulating materials.

[0079] In one embodiment, the semiconductor structure further includes a trench 301 located in the substrate 10 on one side of the upper surface 101, and a barrier structure 30 located in the trench 301.

[0080] In one embodiment, the semiconductor structure further includes a gap 60 located in the substrate 10 outside the sidewall of the via structure 40; wherein the gap 60 is located below the barrier structure 30, and a first end of the gap 60 contacts the bottom of the barrier structure 30. The first end is the end of the gap 60 near the upper surface of the substrate 10.

[0081] The gap 60 is spaced a certain distance from the through hole structure 40.

[0082] The barrier structure 30 can serve as an etching stop layer for etching to form the gap 60, preventing the gap 60 from penetrating the substrate and improving the structural stability of the device. Furthermore, the barrier structure 30 provides a means to control the size of the gap 60. For example, the height of the gap 60 can be controlled by controlling the depth of the barrier structure 30 in the substrate.

[0083] In one embodiment, the coefficient of thermal expansion of the barrier structure 30 is less than that of the substrate 10; and / or, the elastic modulus of the barrier structure 30 is greater than that of the substrate 10. Thus, by selecting a suitable barrier structure material, the effect of reducing the stress generated by the via structure on the surrounding circuit structure can be better mitigated.

[0084] In some embodiments, the material of the barrier structure 30 may include insulating materials such as silicon dioxide or silicon nitride.

[0085] In one specific embodiment, the blocking structure 30 can be a shallow trench isolation structure.

[0086] In one embodiment, the width of the bottom of the blocking structure 30 is not less than the width of the gap 60. The width of the bottom of the blocking structure 30 and the width of the gap 60 are respectively the widths of the blocking structure 30 and the gap 60 along a first direction, wherein the first direction is a direction parallel to the plane of the substrate 10.

[0087] It needs to be explained that the plane containing the upper and lower surfaces of the substrate, or more precisely, the center plane in the thickness direction of the substrate, is defined as the substrate plane.

[0088] Here, the width of the bottom of the barrier structure 30 is not less than the width of the gap 60. In this way, when the barrier structure acts as an etching stop layer in the etching process that forms the gap, the etching energy can be completely stopped on the barrier structure, without penetrating the substrate and affecting the stability of device performance.

[0089] In some embodiments, the width of the gap 60 increases along a second direction, wherein the second direction is perpendicular to the plane of the substrate 10 and points from the lower surface 102 of the substrate 10 to the upper surface 101 of the substrate 10.

[0090] Specifically, in some exemplary embodiments, such as Figure 3a As shown, the width of the gap 60 gradually increases along the second direction. In the semiconductor structure, there are more circuit structures near the upper surface of the substrate 10. Therefore, the closer to the upper surface of the substrate 10, the wider the gap 60. This can better prevent the stress generated by the via structure from being transmitted to the circuit structure near the upper surface of the substrate 10, effectively ensuring the performance of the circuit structure. The gap 60 is narrower near the lower surface of the substrate 10, which can effectively ensure the stability of the entire device structure.

[0091] In other embodiments, the width of the gap 60 may remain constant along the second direction.

[0092] In other exemplary embodiments, such as Figure 3bAs shown, the gap 60 includes a first gap 61 near the upper surface of the substrate 10 and a second gap 62 near the lower surface of the substrate 10; the width of the first gap 61 along the first direction is greater than the width of the second gap 62 along the first direction. Since the circuit structure 20 near the upper surface of the substrate 10 is relatively concentrated, setting the width of the first gap 61 along the first direction to be greater than the width of the second gap 62 along the first direction can minimize the impact on the surrounding circuit structure 20 and reduce the parasitic capacitance between them.

[0093] In one embodiment, the width of the first end of the gap 60 that contacts the bottom of the blocking structure 30 along the first direction is equal to the width of the bottom of the blocking structure 30 along the first direction.

[0094] See also Figure 3b The height h1 of the second part 22 of the circuit structure 20 is equal to the sum of the heights h2 of the blocking structure 30 and the first gap 61. Since the second part 22 of the circuit structure 20 is located in the substrate, and the second part 22 is usually an N-well or P-well formed by ion implantation, the above arrangement can prevent the width of the first gap 61 near the upper surface of the substrate from being too small, so that the stress or expansion generated during the operation of the via structure will affect the second part 22 of the circuit structure, thereby affecting the working performance of the circuit structure.

[0095] In one embodiment, see further. Figure 2 The semiconductor structure further includes a protective layer 50 covering the lower surface of the substrate 10, the protective layer 50 closing the opening of the second end of the gap 60 which is disposed opposite to the first end.

[0096] In practice, the material of the protective layer 50 includes, but is not limited to, silicon nitride or silicon dioxide.

[0097] In one embodiment, the materials of the barrier structure 30 and the protective layer 50 have a high etching selectivity.

[0098] Specifically, for example, if the material of the barrier structure 30 is silicon dioxide, then the material of the protective layer can be silicon nitride. In this way, silicon dioxide and silicon nitride have a high etching selectivity, so that when etching the protective layer to form a gap with the substrate, the etching process can be stopped at the barrier structure.

[0099] In one embodiment, the width of the gap 60 is less than 0.5 μm. It is understood that if the width of the gap 60 is too wide, it will reduce the stability of the substrate. Therefore, the width of the gap 60 is less than 0.5 μm, which can reduce the impact of the stress generated by the via structure on the surrounding circuit structure, while taking into account the stability of the substrate.

[0100] In one embodiment, the blocking structure 30 and / or the gap 60 is one or more annular structures surrounding the through-hole structure 40.

[0101] In some embodiments, the gap 60 and the blocking structure 30 can be one.

[0102] In other embodiments, such as Figure 4 As shown, there can be multiple gaps 60 and blocking structures 30. When there are multiple gaps 60 and blocking structures 30, compared to one, multiple gaps 60 structures can form multi-level stress buffer zones, thereby better reducing the impact of stress generated by the through-hole structure on the surrounding circuit structure and improving the stability of device performance.

[0103] Figure 5a This is a schematic diagram of the planar structure of the annular gap in the semiconductor structure provided in an embodiment of the present invention. Figure 5b This is a schematic diagram of the planar structure of the annular void in the semiconductor structure provided in an embodiment of the present invention. Figure 5a and Figure 5b As shown, in some embodiments, when the gap 60 is formed as an annular structure surrounding the through-hole structure 40, it is preferably a circular annular structure or a square annular structure. Those skilled in the art should recognize that the above embodiments are provided only to further illustrate the application of the present invention and do not imply any limitation on the invention in any way; the gap 60 can also be any other arbitrary annular structure.

[0104] It should be noted that the annular structure of the blocking structure 30 can be consistent with the annular structure of the gap 60. For example, if the gap 60 is an annular structure, then the blocking structure 30 can also be an annular structure.

[0105] This invention also provides a method for fabricating a semiconductor structure, please refer to the appendix for details. Figure 6 As shown in the figure, the method includes the following steps:

[0106] Step 601: Provide a substrate, the substrate including opposing upper and lower surfaces;

[0107] Step 602: Etch the substrate from the upper surface of the substrate to form a trench, and fill the trench with a first material to form a barrier structure;

[0108] Step 603: Form a through-hole structure penetrating the substrate;

[0109] Step 604: Etch the substrate from the lower surface of the substrate to form a groove in the substrate outside the sidewall of the via structure, wherein the barrier structure serves as an etching stop layer for etching the groove, such that the first end of the groove near the upper surface of the substrate stops at the bottom of the barrier structure near the lower surface of the substrate.

[0110] Step 605: Form a protective layer covering the lower surface of the substrate, the protective layer covering the opening of the groove to form a void inside the substrate.

[0111] The method for preparing the semiconductor structure provided in the embodiments of the present invention will be further described in detail below with reference to specific examples.

[0112] Figures 7a to 7j This is a schematic diagram of the device structure during the fabrication process of the semiconductor structure provided in an embodiment of the present invention.

[0113] First, perform step 601, see [link to step 601]. Figure 7a A substrate 10 is provided, which may include an upper surface 101 on the front side and a lower surface 102 on the back side opposite to the front side.

[0114] Next, see Figures 7b to 7c In step 602, the substrate 10 is etched from the upper surface 101 to form a trench 301, and a first material is filled in the trench 301 to form a barrier structure 30.

[0115] In practice, first, see Figure 7b Trench 301 is formed by etching the substrate 10 from the upper surface 101 of the substrate 10.

[0116] Specifically, a mask layer can first be grown on the upper surface of the substrate 10. Then, this mask layer is patterned to display the trench pattern to be etched. This patterning can be achieved using photolithography. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask. When the mask layer is a photoresist mask, it is patterned through steps such as exposure, development, and resist stripping. Next, trenches of a certain depth are etched according to the desired trench pattern.

[0117] Here, for example, a wet or dry etching process can be used to form the trench 301.

[0118] Then, see Figure 7c The trench 301 is filled with a first material to form a barrier structure 30. The first material may include insulating materials such as silicon dioxide or silicon nitride.

[0119] In one embodiment, the coefficient of thermal expansion of the barrier structure 30 is less than that of the substrate 10; and / or, the elastic modulus of the barrier structure 30 is greater than that of the substrate 10. Thus, by selecting a suitable barrier structure material, the effect of reducing the stress generated by the via structure on the surrounding circuit structure can be better mitigated.

[0120] In one specific embodiment, the blocking structure 30 is a shallow trench isolation structure.

[0121] Next, see Figure 7d After step 602, the method further includes forming a circuit structure 20, the circuit structure 20 including a first portion 21 located on the upper surface of the substrate 10 and a second portion 22 located within the substrate 10 near the upper surface.

[0122] The circuit structure 20 can be any type of circuit suitable for a specific application. For example, the circuit structure 20 may include various N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc., interconnected to perform one or more functions. Functions may include memory structures, processor structures, sensors, amplifiers, power distribution, input / output circuits, etc.

[0123] Next, see Figure 7e A dielectric layer 70 is formed on the upper surface of the substrate 10, and the dielectric layer 70 completely covers the circuit structure 20 to protect the circuit structure.

[0124] The material of the dielectric layer 70 may include silicon oxide, silicon nitride, etc.

[0125] Next, proceed to step 603, see [link / reference] Figures 7f to 7g This forms a through-hole structure 40 that penetrates the substrate 10.

[0126] In practice, firstly, as Figure 7f As shown, the substrate 10 is etched from its upper surface to form a through-hole 401 in the substrate 10.

[0127] Specifically, a mask layer can first be grown on the upper surface of the substrate 10, and then the mask layer can be patterned to display the via pattern to be etched. The mask layer can be patterned using a photolithography process. The mask layer can be a photoresist mask or a hard mask patterned based on a photolithography mask; when the mask layer is a photoresist mask, the patterning is performed through steps such as exposure, development, and resist stripping. Then, vias penetrating the substrate are etched according to the via pattern to be etched.

[0128] Here, for example, a wet or dry etching process can be used to form the through hole 401.

[0129] Specifically, etching the substrate 10 from its upper surface to form a via 401 in the substrate 10 includes etching the dielectric layer 70 and the substrate 10 from their upper surfaces to form a via 401 in the dielectric layer 70 and the substrate 10.

[0130] Then, see Figure 7g An insulating layer 43 is formed on the sidewall of the through hole 401. The material of the insulating layer 43 may include, but is not limited to, silicon oxide or silicon nitride and other related integrated circuit insulating materials.

[0131] Next, a barrier layer 42 is formed on the sidewall of the insulating layer 43. Here, the material of the barrier layer 42 includes, but is not limited to, relevant integrated circuit barrier materials such as tantalum or titanium.

[0132] Then, a conductive material is filled into the sidewalls of the barrier layer 42 to form a conductive layer 41 that penetrates the substrate 10. The material of the conductive layer 41 may include copper or tungsten, or other related integrated circuit conductive materials.

[0133] Next, see Figure 7h After step 603 and before step 604, the method further includes: grinding the lower surface of the substrate 10 to thin the substrate to a certain thickness to meet the subsequent void formation, and then forming a pre-protective layer 51 covering the lower surface of the substrate 10. The material of the pre-protective layer 51 includes, but is not limited to, silicon nitride or silicon dioxide.

[0134] Understandably, during the etching process, larger openings typically form on the surface closest to the etching solution. This can damage the device's surface structure and affect its stability. Therefore, to avoid forming large openings on the substrate's lower surface, a pre-protective layer is first applied to the substrate's lower surface. This allows larger openings to form within the pre-protective layer, preventing them from forming within the substrate itself. This protects the substrate surface from damage and improves the stability of the semiconductor structure.

[0135] In one embodiment, the first material of the barrier structure 30 and the material of the pre-protective layer 51 have a high etching selectivity ratio.

[0136] Specifically, for example, if silicon dioxide is selected as the first material, silicon nitride can be selected as the material of the pre-protective layer. In this way, silicon dioxide and silicon nitride have a high etching selectivity, so that when etching the pre-protective layer to form a gap with the substrate, the etching process can be stopped at the barrier structure.

[0137] Then, see Figure 7iStep 604 is executed, etching the substrate 10 from the lower surface of the substrate 10 to form a groove 601 in the substrate 10 outside the sidewall of the via structure 40. The blocking structure 30 serves as an etching stop layer for etching the groove 601, such that the first end of the groove 601 near the upper surface of the substrate 10 stops at the bottom of the blocking structure 30 near the lower surface of the substrate 10.

[0138] Here, the barrier structure 30 can serve as an etching stop layer for etching to form the gap 60, preventing the gap 60 from penetrating the substrate and improving the structural stability of the device. Furthermore, the barrier structure 30 provides a means to control the size of the gap 60. For example, the height of the gap 60 can be controlled by controlling the depth of the barrier structure 30 in the substrate.

[0139] Specifically, forming a groove 601 in the substrate 10 on the outer sidewall of the through-hole structure 40 includes etching the pre-protective layer 51 and the substrate 10 from the lower surface of the pre-protective layer 51 to form the groove 601 in the pre-protective layer 51 and the substrate 10.

[0140] It is worth noting that when etching the pre-protective layer 51 and the substrate 10 using an etching process, by controlling the etching selectivity, an etching process that can etch the pre-protective layer 51 and the substrate 10 without damaging the material of the barrier structure 30 is selected, so that the etching process can stop at the barrier structure 30.

[0141] Next, see Figure 7j A protective layer 50 is formed covering the lower surface of the substrate 10, and the protective layer 50 covers the opening of the groove 601 to form a void 60 inside the substrate 10.

[0142] Specifically, forming a void 60 inside the substrate 10 includes: forming a secondary protective layer 52 covering the lower surface of the pre-protective layer 51, the secondary protective layer 52 covering the opening of the groove 601 to form a void 60 inside the substrate 10; wherein the pre-protective layer 51 and the secondary protective layer 52 together constitute a protective layer 50.

[0143] In practice, the materials of the pre-protective layer and the secondary protective layer can be the same or different. In a specific embodiment, for example, the pre-protective layer and the secondary protective layer are made of the same material, and may include materials such as silicon nitride or silicon dioxide; that is, the material of the protective layer 50 may include materials such as silicon nitride or silicon dioxide.

[0144] In this embodiment of the invention, if the substrate has not undergone grinding and thinning, etching from the front side of the substrate will not be able to form a sufficiently deep void. Furthermore, even if the substrate has undergone grinding and thinning, etching from the front side will still damage the structure on the upper surface of the substrate. Therefore, this embodiment of the invention chooses to etch the substrate 10 from its lower surface, i.e., the back side of the substrate 10, after thinning to form the void 60. Compared to etching the substrate from its upper surface to form the void, this method better protects other device structures and material layers on the upper surface of the substrate, thereby ensuring the stability of the semiconductor structure performance.

[0145] In one embodiment, the width of the bottom of the blocking structure 30 is not less than the width of the gap 60. The width of the bottom of the blocking structure 30 and the width of the gap 60 are respectively the widths of the blocking structure 30 and the gap 60 along a first direction, wherein the first direction is a direction parallel to the plane of the substrate 10.

[0146] It needs to be explained that the plane containing the upper and lower surfaces of the substrate, or more precisely, the center plane in the thickness direction of the substrate, is defined as the substrate plane.

[0147] Here, the width of the bottom of the barrier structure 30 is not less than the width of the gap 60. In this way, when the barrier structure acts as an etching stop layer in the etching process that forms the gap, the etching energy can be completely stopped on the barrier structure, without penetrating the substrate and affecting the stability of device performance.

[0148] In some embodiments, the width of the gap 60 increases along a second direction, wherein the second direction is perpendicular to the plane of the substrate 10 and points from the lower surface 102 of the substrate 10 to the upper surface 101 of the substrate 10.

[0149] Specifically, in some exemplary embodiments, such as Figure 3a As shown, the width of the gap 60 gradually increases along the second direction. In the semiconductor structure, there are more circuit structures near the upper surface of the substrate 10. Therefore, the closer to the upper surface of the substrate 10, the wider the gap 60. This can better prevent the stress generated by the via structure from being transmitted to the circuit structure near the upper surface of the substrate, effectively ensuring the performance of the circuit structure. The gap 60 is narrower near the lower surface of the substrate 10, which can effectively ensure the stability of the entire device structure.

[0150] In other embodiments, the width of the gap 60 remains constant along the second direction.

[0151] In other exemplary embodiments, such as Figure 3bAs shown, the gap 60 includes a first gap 61 near the upper surface of the substrate 10 and a second gap 62 near the lower surface of the substrate 10; the width of the first gap 61 along the first direction is greater than the width of the second gap 62 along the first direction.

[0152] In one embodiment, the width of the first end of the gap 60 that contacts the bottom of the blocking structure 30 along the first direction is equal to the width of the bottom of the blocking structure 30 along the first direction.

[0153] See also Figure 3b The height h1 of the second part 22 of the circuit structure 20 is equal to the sum of the heights h2 of the blocking structure 30 and the first gap 61.

[0154] In one embodiment, the width of the gap 60 is less than 0.5 μm. It is understood that if the width of the gap 60 is too wide, it will reduce the stability of the substrate. Therefore, the width of the gap 60 is less than 0.5 μm, which can reduce the impact of the stress generated by the via structure on the surrounding circuit structure, while taking into account the stability of the substrate.

[0155] In one embodiment, the blocking structure 30 and / or the gap 60 is one or more annular structures surrounding the through-hole structure 40.

[0156] In some embodiments, the gap 60 and the blocking structure 30 can be one.

[0157] In other embodiments, such as Figure 4 As shown, there can be multiple gaps 60 and blocking structures 30. When there are multiple gaps 60 and blocking structures 30, compared to one, multiple gaps 60 structures can form multi-level stress buffer zones, thereby better reducing the impact of stress generated by the through-hole structure on the surrounding circuit structure and improving the stability of device performance.

[0158] Figure 5a This is a schematic diagram of the planar structure of the annular gap in the semiconductor structure provided in an embodiment of the present invention. Figure 5b This is a schematic diagram of the planar structure of the annular void in the semiconductor structure provided in an embodiment of the present invention. Figure 5a and Figure 5b As shown, in some embodiments, when the gap 60 is formed as an annular structure surrounding the through-hole structure 40, it is preferably a circular annular structure or a square annular structure. Those skilled in the art should recognize that the above embodiments are provided only to further illustrate the application of the present invention and do not imply any limitation on the invention in any way; the gap 60 can also be any other arbitrary annular structure.

[0159] It should be noted that the annular structure of the blocking structure 30 can be consistent with the annular structure of the gap 60. For example, if the gap 60 is an annular structure, then the blocking structure 30 can also be an annular structure.

[0160] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including opposing upper and lower surfaces; Through-hole structure penetrating the substrate; A trench located in the substrate on one side of the upper surface, and a blocking structure located in the trench; The void in the substrate located outside the sidewall of the through-hole structure; wherein, The gap is located below the barrier structure, and the first end of the gap is in contact with the bottom of the barrier structure; the barrier structure is used to reduce the influence of the stress generated by the through-hole structure on the surrounding circuit structure, and serves as an etching stop layer when etching the gap.

2. The semiconductor structure according to claim 1, characterized in that, The coefficient of thermal expansion of the barrier structure is less than that of the substrate; and / or, the elastic modulus of the barrier structure is greater than that of the substrate.

3. The semiconductor structure according to claim 1, characterized in that, The width of the bottom of the blocking structure is not less than the width of the gap. The width of the bottom of the blocking structure and the width of the gap are respectively the widths of the blocking structure and the gap along a first direction, wherein the first direction is a direction parallel to the substrate plane.

4. The semiconductor structure according to claim 3, characterized in that, The width of the gap increases along a second direction, wherein the second direction is perpendicular to the plane of the substrate and points from the lower surface of the substrate to the upper surface of the substrate.

5. The semiconductor structure according to claim 4, characterized in that, The gap includes a first gap near the upper surface of the substrate and a second gap near the lower surface of the substrate; The width of the first gap along the first direction is greater than the width of the second gap along the first direction.

6. The semiconductor structure according to any one of claims 4 or 5, characterized in that, The width of the first end of the gap that contacts the bottom of the blocking structure along the first direction is equal to the width of the bottom of the blocking structure along the first direction.

7. The semiconductor structure according to claim 5, characterized in that, Also includes: A circuit structure comprising a first portion located on the upper surface of the substrate and a second portion located within the substrate near the upper surface; The height of the second part is equal to the sum of the heights of the blocking structure and the first gap.

8. The semiconductor structure according to claim 1, characterized in that, Also includes: A protective layer covering the lower surface of the substrate, the protective layer sealing the opening at the second end of the void, which is positioned opposite the first end.

9. The semiconductor structure according to claim 8, characterized in that, The materials of the barrier structure and the protective layer have a high etching selectivity.

10. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including opposing upper and lower surfaces; Trenches are formed by etching the substrate from its upper surface, and a first material is filled into the trenches to form a barrier structure. Forming a through-hole structure that penetrates the substrate; The substrate is etched from the lower surface of the substrate to form a groove in the substrate outside the sidewall of the via structure. The barrier structure serves as an etching stop layer for etching the groove, such that the first end of the groove near the upper surface of the substrate stops at the bottom of the barrier structure near the lower surface of the substrate. A protective layer is formed covering the lower surface of the substrate, the protective layer covering the opening of the groove to form a void inside the substrate.

11. The method according to claim 10, characterized in that, Before forming the groove in the substrate outside the sidewall of the through-hole structure, the method further includes: A pre-protective layer is formed covering the lower surface of the substrate; Forming a groove in the substrate outside the sidewall of the through-hole structure includes: etching the pre-protective layer and the substrate from the lower surface of the pre-protective layer to form a groove in the pre-protective layer and the substrate; Forming a void inside the substrate includes: forming a secondary protective layer covering the lower surface of the pre-protective layer, the secondary protective layer covering the opening of the groove to form a void inside the substrate; wherein the pre-protective layer and the secondary protective layer together constitute a protective layer.

12. The method according to claim 11, characterized in that, The first material and the pre-protective layer have a high etching selectivity.

13. The method according to claim 10, characterized in that, The coefficient of thermal expansion of the barrier structure is less than that of the substrate; and / or, the elastic modulus of the barrier structure is greater than that of the substrate.

14. The method according to claim 10, characterized in that, The width of the bottom of the blocking structure is not less than the width of the gap. The width of the bottom of the blocking structure and the width of the gap are respectively the widths of the blocking structure and the gap along a first direction, wherein the first direction is a direction parallel to the substrate plane.

15. The method according to claim 14, characterized in that, The width of the gap increases along a second direction, wherein the second direction is perpendicular to the plane of the substrate and points from the lower surface of the substrate to the upper surface of the substrate.

16. The method according to claim 15, characterized in that, The gap includes a first gap near the upper surface of the substrate and a second gap near the lower surface of the substrate; The width of the first gap along the first direction is greater than the width of the second gap along the first direction.

17. The method according to any one of claims 15-16, characterized in that, The width of the first end of the gap that contacts the bottom of the blocking structure along the first direction is equal to the width of the bottom of the blocking structure along the first direction.

18. The method according to claim 16, characterized in that, After forming the barrier structure, the method further includes: A circuit structure is formed, the circuit structure including a first portion located on the upper surface of the substrate and a second portion located within the substrate near the upper surface; The height of the second part is equal to the sum of the heights of the blocking structure and the first gap.

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