Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure interposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed inside the second insulating layer and surrounded by at least one of the plurality of etch stop layers; and a through-electrode structure configured to pass through the semiconductor substrate, the first insulating layer, and at least one of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0060339, filed with the Korean Intellectual Property Office on May 10, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device. Background Technology

[0004] Semiconductor devices may include: a semiconductor substrate, comprising a separate device; wiring patterns connected to the separate device; and through-electrode structures extending through the semiconductor substrate. To enable high storage capacity in semiconductor devices, the semiconductor package comprising the semiconductor device must be thin and lightweight. Therefore, the shapes of wiring patterns included in semiconductor devices are becoming more complex, and the dimensions of wiring patterns and through-electrode structures are becoming thinner and smaller. For example, the dimensions of through-electrode structures and wiring patterns can be on the nanometer scale, potentially requiring appropriate structural configurations and finely tuned processes to ensure that the fabricated semiconductor devices and semiconductor packages have a reliable structure. Summary of the Invention

[0005] The present invention provides a semiconductor device with enhanced structural reliability.

[0006] The present invention also provides a thin and lightweight semiconductor device.

[0007] According to an embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure disposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed within the second insulating layer and surrounded by at least one of the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer and at least one of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

[0008] According to an embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure located between the first insulating layer and the second insulating layer and including a first etch stop layer disposed on a lower portion of the first insulating layer, a second etch stop layer disposed on a lower portion of the first etch stop layer, and a third etch stop layer disposed between the second etch stop layer and the second insulating layer; a contact wiring pattern disposed on the second etch stop layer and surrounded by the third etch stop layer and the second insulating layer; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer, the first etch stop layer, and the second etch stop layer and contact the contact wiring pattern, the through electrode structure having a width of approximately 10 nanometers to approximately 200 nanometers.

[0009] According to an embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate having a first surface adjacent to an active layer; a first insulating layer disposed on the first surface of the semiconductor substrate; a second insulating layer disposed on the first insulating layer; an etch stop structure disposed between the first insulating layer and the second insulating layer and including a plurality of etch stop layers; a contact wiring pattern disposed between the first insulating layer and the second insulating layer and surrounded by the plurality of etch stop layers; and a through electrode structure configured to pass through the semiconductor substrate, the first insulating layer and at least one of the plurality of etch stop layers in a vertical direction and contact the contact wiring pattern.

[0010] The semiconductor device may include an etch-stop structure disposed between the through-electrode structure and the second insulating layer and including a plurality of etch-stop layers. A semiconductor device according to an embodiment of the present invention may include the etch-stop structure, and therefore the etching degree of the semiconductor substrate and the first insulating layer can be finely adjusted during the operation of etching the semiconductor substrate and the first insulating layer to form the through-hole in which the through-electrode structure is disposed. Therefore, the structural reliability between the through-electrode structure of the semiconductor device and the contact wiring pattern connected to the through-electrode structure can be improved. Attached Figure Description

[0011] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0013] Figure 2 and Figure 3 yes Figure 1 A magnified view of region A in the image;

[0014] Figure 4 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0015] Figure 5 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0016] Figure 6 yes Figure 5 A magnified view of region B in the image;

[0017] Figure 7 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0018] Figure 8 This is a cross-sectional view of a semiconductor package according to an embodiment of the present invention;

[0019] Figures 9A to 9J This is a diagram illustrating the operation of a method for manufacturing a semiconductor device according to an embodiment of the present invention; and

[0020] Figures 10A to 10J This is a diagram illustrating the operation of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0021] because Figures 1 to 10 The accompanying drawings are intended for illustrative purposes, so the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0022] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention. Figure 2 and Figure 3 yes Figure 1 An enlarged view of region A in the image.

[0024] refer to Figures 1 to 3According to an embodiment of the present invention, the semiconductor device 10 may include a semiconductor substrate 110, a first insulating layer 210, a second insulating layer 230, a third insulating layer 250, an etch stop structure 300, a separator layer 410, a through electrode structure 500, a lower wiring pattern 600, a connection terminal 710, a terminal pad 750, a protective layer 780, an upper wiring structure 900, and a conductive pad 830.

[0025] The semiconductor device 10 according to an embodiment of the present invention may be, for example, a memory chip, a logic chip, or a combination thereof.

[0026] Semiconductor substrate 110 may be a wafer-level or chip-level substrate. In embodiments of the present invention, semiconductor substrate 110 may include silicon (Si). Alternatively, semiconductor substrate 110 may include semiconductor elements such as germanium (Ge), or compound semiconductors such as, for example, silicon carbide (SiC), silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide (GaAs), gallium antimony (GaSb), gallium phosphide (GaP), indium arsenide (InAs), indium phosphide (InP), indium antimony (InSb), lead telluride (PbTe) compounds, or indium gallium arsenide (InGaAs). However, the material of semiconductor substrate 110 is not limited to the above. Furthermore, semiconductor substrate 110 may include one or more semiconductor layers or structures and may include active or operable portions of semiconductor devices.

[0027] The semiconductor substrate 110 may have a first surface 110S1 and a second surface 110S2 facing each other. For example, the first surface 110S1 of the semiconductor substrate 110 may be a front surface adjacent to the active layer AL, while the second surface 110S2 may be a rear surface opposite to the first surface 110S1. The second surface 110S2 of the semiconductor substrate 110 may be parallel to the first surface 110S1 of the semiconductor substrate 110.

[0028] The semiconductor substrate 110 may include an active layer AL in a portion adjacent to the first surface 110S1. In embodiments of the present invention, the active layer AL may include multiple individual devices of various types. For example, the multiple individual devices may include various microelectronic devices such as complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), system-on-large-scale integration (LSI), image sensors such as CMOS imaging sensors (CIS), microelectromechanical systems (MEMS), active devices, passive devices, etc.

[0029] In an embodiment of the present invention, multiple individual devices in the active layer AL can be electrically connected to the lower wiring pattern 630 via the lower wiring path pattern 650.

[0030] The first insulating layer 210 may be disposed on the first surface 110S1 of the semiconductor substrate 110. In embodiments of the present invention, the first insulating layer 210 may comprise an oxide or a nitride. For example, the first insulating layer 210 may comprise, for example, silicon oxide (SiO2) or silicon nitride (Si3N4). However, the present invention is not limited thereto. For example, in embodiments of the present invention, the first insulating layer 210 may comprise, for example, silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon carbonitride (SiOC). The first insulating layer 210 may be a single layer or multiple layers.

[0031] In embodiments of the present invention, the first insulating layer 210 may comprise an insulating material of a photoimageable dielectric (PID) material to which photolithography processes can be performed. For example, the first insulating layer 210 may comprise photosensitive polyimide (PSPI).

[0032] The etch stop structure 300 may be disposed on the first insulating layer 210. In an embodiment of the present invention, the etch stop structure 300 may be located between the first insulating layer 210 and the second insulating layer 230.

[0033] In embodiments of the present invention, the etch stop structure 300 may include multiple etch stop layers. For example, the etch stop structure 300 may include three etch stop layers, such as a first etch stop layer 310, a second etch stop layer 330, and a third etch stop layer 350. That is, the etch stop structure 300 may include a first etch stop layer 310, a second etch stop layer 330, and a third etch stop layer 350. In embodiments of the present invention, the third etch stop layer 350, the second etch stop layer 330, and the first etch stop layer 310 may be sequentially stacked on the second insulating layer 230.

[0034] The number of etch stop layers included in the etch stop structure 300 is not limited to the three mentioned above. For example, the etch stop structure 300 may include more than three etch stop layers.

[0035] In embodiments of the present invention, the first etch stop layer 310, the second etch stop layer 330, and the third etch stop layer 350 may each have a thickness of approximately 1 nanometer to approximately 10 nanometers. Therefore, the etch stop structure 300 may have a thickness of approximately 3 nanometers to approximately 30 nanometers. That is, the sum of the thicknesses of the first etch stop layer 310, the second etch stop layer 330, and the third etch stop layer 350 may be approximately 3 nanometers to approximately 30 nanometers. Taking into account the measurement results discussed and the errors associated with the measurement results of a particular quantity (i.e., limitations of the measurement system), the term "approximately" as used herein includes the stated value and means within an acceptable deviation range of a particular value as determined by those skilled in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0036] In embodiments of the present invention, the etch stop structure 300 may have a structure in which two different types of materials are alternately stacked. For example, the etch stop structure 300 may have a structure in which two materials with different etch selectivity are alternately stacked.

[0037] In embodiments of the present invention, the first etch stop layer 310 may comprise a material having a relatively low etch rate or not being etched in a dry etching process. The material of the first etch stop layer 310 may differ from the material of the second etch stop layer 330. For example, in a dry etching process, the etch rate of the material of the first etch stop layer 310 may be lower than the etch rate of the material of the second etch stop layer 310. Furthermore, the material of the first etch stop layer 310 may be substantially the same as the material of the third etch stop layer 350.

[0038] The first etch stop layer 310 and the third etch stop layer 350 may be made of materials with relatively high etch rates in wet etching processes, and the second etch stop layer 330, which is located between the first etch stop layer 310 and the third etch stop layer 310, may be made of materials with relatively low etch rates or not etched in wet etching processes.

[0039] In embodiments of the present invention, the materials of the first etch stop layer 310 and the third etch stop layer 350 may include metallic materials, such as nickel (Ni), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), aluminum (Al), etc. In embodiments of the present invention, the materials of the first etch stop layer 310 and the third etch stop layer 350 may be dielectric materials containing metals.

[0040] The second etch stop layer 330 may comprise a material having a relatively high etch rate in a dry etching process. For example, the material of the second etch stop layer 330 may comprise, for example, silicon (Si), carbon (C), oxygen (O), nitrogen (N), and / or hydrogen (H). For example, the material of the second etch stop layer 330 may comprise at least one of silicon oxide (SiO2), silicon nitride (Si3N4), or silicon carbonitride (SiCN). In embodiments of the present invention, the material of the second etch stop layer 330 may be a silicon (Si)-containing dielectric material.

[0041] In embodiments of the present invention, a portion of the etch stop structure 300 may surround a portion of the side surface of the through electrode structure 500. For example, the first etch stop layer 310 and the second etch stop layer 330 of the etch stop structure 300 may surround a portion of the side surface of the through electrode structure 500.

[0042] A portion of the etch stop structure 300 may surround a portion of the side surface of the contact wiring pattern 635, as described below. For example, a third etch stop layer 350 of the etch stop structure 300 may surround a portion of the side surface of the contact wiring pattern 635.

[0043] The second insulating layer 230 may be disposed on the etch stop structure 300. In embodiments of the present invention, the second insulating layer 230 may comprise an oxide or a nitride. For example, the second insulating layer 230 may comprise, for example, silicon oxide (SiO2) or silicon nitride (Si3N4). However, the present invention is not limited thereto. For example, in embodiments of the present invention, the second insulating layer 230 may comprise, for example, silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon carbonitride (SiOC). The second insulating layer 230 may be a single layer or multiple layers.

[0044] The lower wiring pattern 600 may include: a lower wiring line pattern 630 extending horizontally in the first insulating layer 210 and the second insulating layer 230; and a lower wiring path pattern 650 extending vertically in the first insulating layer 210 and the second insulating layer 230 to interconnect the lower wiring line patterns 630 with each other, or extending vertically in the first insulating layer 210 and the second insulating layer 230 to connect individual devices in the active layer AL and the lower wiring line pattern 630 with each other.

[0045] The lower wiring pattern 630 may comprise multiple layers extending horizontally in the first insulating layer 210 and the second insulating layer 230, and may be electrically connected to each other via the lower wiring path pattern 650. In an embodiment of the present invention, when the lower wiring pattern 630 is viewed in a plan view, the width of the lower wiring pattern 630 may be approximately 10 nanometers to approximately 100 nanometers.

[0046] In an embodiment of the present invention, a portion of the lower wiring pattern 630 may be configured to transmit data signals and / or control signals, while another portion may be configured to transmit power signals.

[0047] In an embodiment of the present invention, the lower wiring pattern 630 that contacts the through electrode structure 500 can be defined as a contact wiring pattern 635. The side surface of the contact wiring pattern 635 can be surrounded by a portion of the second insulating layer 230 and a portion of the etch stop structure 300. For example, the side surface of the contact wiring pattern 635 can be surrounded by the second insulating layer 230 and the third etch stop layer 350, and the upper surface of the contact wiring pattern 635 can contact the through electrode structure 500 and the second etch stop layer 330. For example, the lower surface of the second etch stop layer 330 can be coplanar with the upper surface of the contact wiring pattern 635. The contact wiring pattern 635 can extend horizontally and have a relatively consistent spacing distance with the first surface 110S1 of the semiconductor substrate 110 in the vertical direction. In an embodiment of the present invention, when the contact wiring pattern 635 is viewed in a plan view, the width of the contact wiring pattern 635 can be approximately 10 nanometers to approximately 100 nanometers.

[0048] refer to Figure 2 and Figure 3 The contact wiring pattern 635 may include a barrier metal layer 635a, a seed metal layer 635b, and a metal pattern 635c.

[0049] In embodiments of the present invention, the barrier metal layer 635a may be located between the second insulating layer 230 and the seed metal layer 635b, and between the second etch stop layer 330 and the seed metal layer 635b. A portion of the barrier metal layer 635a may be surrounded by the third etch stop layer 350. Additionally, a portion of the barrier metal layer 635a may surround at least a portion of the through-electrode structure 500.

[0050] In embodiments of the present invention, the barrier metal layer 635a may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN). However, the present invention is not limited thereto.

[0051] In an embodiment of the present invention, the seed metal layer 635b may be located between the barrier metal layer 635a and the metal pattern 635c. For example... Figure 2 As shown, the seed metal layer 635b may not directly contact the through electrode structure 500. However, the inventive concept is not limited thereto, and as... Figure 3 As shown, the seed metal layer 635b may surround a portion of the side surface of the through electrode structure 500 and may directly contact the through electrode structure 500. For example, the through electrode structure 500 may be configured to pass through at least a portion of the contact wiring pattern 635 and may be surrounded by the contact wiring pattern 635.

[0052] In embodiments of the present invention, the seed metal layer 635b may include, for example, copper (Cu), manganese (Mn), titanium (Ti), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or alloys thereof. However, the present invention is not limited thereto.

[0053] In an embodiment of the present invention, the metal pattern 635c may be a pattern of conductive material filling the recessed space formed by the barrier metal layer 635a and the seed metal layer 635b. For example, the upper and side surfaces of the metal pattern 635c may be surrounded by the seed metal layer 635b. Additionally, a portion of the lower surface of the metal pattern 635c may contact the second insulating layer 230 and the lower wiring path pattern 650. The seed metal layer 635b does not cover the lower surface of the metal pattern 635c.

[0054] refer to Figure 2 The metal pattern 635c may not directly contact the through electrode structure 500. However, the inventive concept is not limited thereto, and references are made to... Figure 3 The metal pattern 635c may surround a portion of the through electrode structure 500 and may directly contact the through electrode structure 500. That is, the contact wiring pattern 635 may surround at least a portion of the side surface of the through electrode structure 500.

[0055] In embodiments of the present invention, the metal pattern 635c may include, for example, copper (Cu), nickel (Ni), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), and / or alloys thereof. However, the present invention is not limited thereto.

[0056] The separator layer 410 may be located between the semiconductor substrate 110 and the through-electrode structure 500, between the first insulating layer 210 and the through-electrode structure 500, and between a portion of the etch stop structure 300 and the through-electrode structure 500. For example, a portion of the etch stop structure 300 may be the first etch stop layer 310, and the separator layer 410 may be located between the first etch stop layer 310 and the through-electrode structure 500. The separator layer 410 can prevent leakage current generated by the through-electrode structure 500. For example, the separator layer 410 can electrically isolate the semiconductor substrate 110 and the through-electrode structure 500, thereby preventing and / or suppressing leakage current of the through-electrode structure 500.

[0057] In embodiments of the present invention, the separator layer 410 may include an insulating material. For example, the separator layer 410 may include, for example, silicon dioxide (SiO2) or silicon oxynitride (SiON). However, the material of the separator layer 410 is not limited to the above-mentioned items.

[0058] A portion of the separator layer 410 may contact the etch stop structure 300. For example, a portion of the separator layer 410 may contact the second etch stop layer 330 and may be surrounded by the first etch stop layer 310.

[0059] The through-electrode structure 500 can pass through a portion of the semiconductor substrate 110, the first insulating layer 210, and the etch stop structure 300 in a vertical direction to contact the contact wiring pattern 635. Hereinafter, the vertical direction can be defined as the direction perpendicular to the direction along which the first surface 110S of the semiconductor substrate 110 extends, and the horizontal direction can be defined as the direction parallel to the direction along which the first surface 110S of the semiconductor substrate 110 extends.

[0060] In an embodiment of the present invention, the through-electrode structure 500 can pass through the first etch stop layer 310 and the second etch stop layer 330 of the etch stop structure 300 in the vertical direction to contact the contact wiring pattern 635. Additionally, the lowermost portion of the through-electrode structure 500 can be surrounded by the second etch stop layer 330 and the contact wiring pattern 635.

[0061] In an embodiment of the present invention, a first etch stop layer 310 may be disposed on the lower portion of the first insulating layer 210, such as its lower surface, and configured to surround a portion of the side surface of the through electrode structure 500. A second etch stop layer 330 may be disposed on the lower portion of the first etch stop layer 310, such as its lower surface, configured to surround a portion of the side surface of the through electrode structure 500, and configured to contact the contact wiring pattern 635. A third etch stop layer 350 may be disposed between the second etch stop layer 330 and the second insulating layer 230 and configured to surround a portion of the side surface of the contact wiring pattern 635.

[0062] In embodiments of the present invention, the through-electrode structure 500 may have a tapered shape, wherein the cross-sectional area of ​​the through-electrode structure 500 in the horizontal direction decreases toward the contact wiring pattern 635. Furthermore, the length 500h (i.e., height) of the through-electrode structure 500 in the vertical direction may be approximately 0.1 micrometers to approximately 2 micrometers. Additionally, the length 500d (i.e., width) of the through-electrode structure 500 in the horizontal direction may be approximately 30 nanometers to approximately 200 nanometers. However, the height and width of the through-electrode structure 500 are not limited to the values ​​described above.

[0063] In an embodiment of the present invention, the bottom surface of the through-electrode structure 500 can be circular. For example, the bottom surface of the through-electrode structure 500 can protrude downwards. Since the bottom surface of the through-electrode structure 500 is circular, the contact area between the through-electrode structure 500 and the contact wiring pattern 635 can be increased. Therefore, the structural reliability between the through-electrode structure 500 and the contact wiring pattern 635 can be improved.

[0064] In an embodiment of the present invention, the through electrode structure 500 may include a blocking pattern 510, a seed pattern 530, and a conductive path 550.

[0065] In embodiments of the present invention, the blocking pattern 510 may be disposed along the side and bottom surfaces of the through electrode structure 500. The blocking pattern 510 may be located between the separator layer 410 and the seed pattern 530, between a portion of the etch stop structure 300 and the seed pattern 530, and between the contact wiring pattern 635 and the seed pattern 530. For example, the blocking pattern 510 may be disposed along the surface of the separator layer 410 and configured to contact the contact wiring pattern 635.

[0066] The through-electrode structure 500 and the contact wiring pattern 635 can be electrically connected. In an embodiment of the present invention, the through-electrode structure 500 can extend into the seed metal layer 635b, such that the blocking pattern 510 contacts and is electrically connected to the seed metal layer 635b. In an embodiment of the present invention, the through-electrode structure 500 can extend into the metal pattern 635c, such that the blocking pattern 510 contacts and is electrically connected to the metal pattern 635c.

[0067] The blocking pattern 510 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), tungsten (W), or alloys thereof.

[0068] The seed pattern 530 may extend along the inner surface of the barrier pattern 510 and may be located between the barrier pattern 510 and the conductive path 550. The seed pattern 530 may include a conductive material such as a metal. For example, the seed pattern 530 may include, for example, copper (Cu), manganese (Mn), titanium (Ti), cobalt (Co), tungsten (W), molybdenum (Mo), ruthenium (Ru), and / or alloys thereof.

[0069] Conductive pathways 550 may be disposed on the seed pattern 530 and may fill through holes (e.g., via holes) defined by the inner surface of the seed pattern 530. In embodiments of the inventive concept, conductive pathways 550 may comprise metals such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), and / or alloys thereof.

[0070] In embodiments of the present invention, the uppermost surfaces of the blocking pattern 510, the seed pattern 530, and the conductive path 550 may be substantially coplanar with each other.

[0071] A third insulating layer 250 may be disposed on the second surface 110S2 of the semiconductor substrate 110 to cover the second surface 110S2. Alternatively, the third insulating layer 250 may surround a portion of the side surface of the through-electrode structure 500 and expose the upper surface of the through-electrode structure 500. In embodiments of the inventive concept, the third insulating layer 250 may comprise a carbon-containing material, such as a spin-coated carbon hard mask (SOC) material. However, the inventive concept is not limited thereto, and the third insulating layer 250 may be omitted.

[0072] The upper wiring structure 900 may include: an upper wiring insulating layer 910; an upper wiring pattern 930 extending horizontally inside the upper wiring insulating layer 910 and connected to the through electrode structure 500; and an upper wiring path pattern 950 extending vertically inside the upper wiring insulating layer 910 to interconnect a plurality of upper wiring patterns 930 or to connect the upper wiring patterns 930 and conductive pads 830 to each other.

[0073] In the embodiments of this invention, since the through-electrode structure 500 is sized in nanometers, a stable electrical connection between the through-electrode structure 500 and the conductive pad 830 is required. Therefore, an upper wiring structure 900 can be positioned between the through-electrode structure 500 and the conductive pad 830. In other words, the upper wiring pattern 930 and the upper wiring path pattern 950 of the upper wiring structure 900 can provide a path for the movement of electrical signals between the through-electrode structure 500 and the conductive pad 830.

[0074] The upper wiring insulating layer 910 may be an insulating material layer disposed on the second surface 110S2 of the semiconductor substrate 110. In embodiments of the present invention, the upper wiring insulating layer 910 may include oxides or nitrides. For example, the upper wiring insulating layer 910 may include, for example, silicon oxide (SiO2) or silicon nitride (Si3N4).

[0075] In embodiments of the present invention, the upper wiring pattern 930 may include two or more layers extending in a horizontal direction. For example, the upper wiring pattern 930 may include three layers extending in a horizontal direction. However, the number of layers included in the upper wiring pattern 930 is not limited to those described above.

[0076] The conductive pad 830 can be disposed on the upper wiring structure 900 and can be electrically connected to the through electrode structure 500 via the upper wiring line pattern 930 and the upper wiring path pattern 950.

[0077] In an embodiment of the present invention, the conductive pad 830 may be disposed on the upper wiring structure 900 to overlap with the through electrode structure 500 in the vertical direction. However, the present invention is not limited thereto, and the conductive pad 830 may be disposed on the upper wiring structure 900 to not overlap with the through electrode structure 500 in the vertical direction. The conductive pad 830 may contact a portion of the upper wiring path pattern 950 and may be electrically connected to the through electrode structure 500 via the upper wiring path pattern 950 and the upper wiring line pattern 930.

[0078] In embodiments of the present invention, the conductive pad 830 can be electrically connected to the lower wiring pattern 600 via the through electrode structure 500. For example, the conductive pad 830 can be electrically connected to multiple individual devices in the active layer AL via the electrode structure 500 and the lower wiring pattern 600. Additionally, the conductive pad 830 can act as a terminal for electrical connection to external devices. For example, external devices may include, for example, semiconductor devices, passive devices, substrates, etc. The material of the conductive pad 830 may include metals such as copper (Cu), aluminum (Al), titanium (Ti), and / or alloys thereof.

[0079] Terminal pads 750 may be disposed in the lower portion of the second insulating layer 230 and may be electrically connected via a lower wiring pattern 600 to multiple individual devices in the through-electrode structure 500 and the active layer AL. For example, in an embodiment of the present invention, the bottom surface of the terminal pads 750 and the bottom surface of the second insulating layer 230 may be coplanar. In an embodiment of the present invention, the terminal pads 750 may comprise a metallic material such as copper (Cu), titanium (Ti), or aluminum (Al).

[0080] The connection terminal 710 may be attached to and electrically connected to the terminal pad 750. In embodiments of the present invention, the connection terminal 710 may include solder balls of a metallic material, including at least one of, for example, tin (Sn), silver (Ag), copper (Cu), or aluminum (Al).

[0081] A protective layer 780 may be disposed on the second insulating layer 230 to cover the bottom surface of the second insulating layer 230. The protective layer 780 may have openings exposing the terminal pads 750 and the connection terminals 710. In embodiments of the present invention, the material of the protective layer 780 may include an insulating polymer.

[0082] The dimensions of the through-electrode structure 500 and the contact wiring pattern 635 included in the semiconductor device 10 according to embodiments of the present invention can be in the nanometer unit. For example, the width 500d of the through-electrode structure 500 and the width and thickness of the contact wiring pattern 635 can be in the nanometer unit. For example, the width 500d of the through-electrode structure 500 in the horizontal direction can be from about 30 nanometers to about 200 nanometers, and the width of the contact wiring pattern 635 can be from about 10 nanometers to about 100 nanometers.

[0083] In the process of etching the semiconductor substrate 110 and the first insulating layer 210 and forming a through hole 500H in which the through electrode structure 500 is disposed, it is necessary to finely adjust the etching degree of the semiconductor substrate 110 and the first insulating layer 210.

[0084] When the etching degree of the semiconductor substrate 110 and the first insulating layer 210 is not finely adjusted, there is a risk that the contact wiring pattern 635 may be etched. As a result, the through electrode structure 500 and the contact wiring pattern 635 may not have a reliable connection structure.

[0085] The semiconductor device 10 according to an embodiment of the present invention may include an etch stop structure 300 disposed between a through electrode structure 500 and a contact wiring pattern 635, the etch stop structure 300 including a plurality of etch stop layers 310, 330, and 350. Furthermore, the etch stop structure 300 may have a structure in which two materials with different etch selectivity are alternately stacked. For example, the first etch stop layer 310 and the third etch stop layer 350 may have materials with relatively low etch rates in dry etching processes, and the second etch stop layer 330 between the first etch stop layer 310 and the third etch stop layer 350 may have materials with relatively high etch rates in dry etching processes.

[0086] The semiconductor device 10 according to an embodiment of the present invention may include an etch stop structure 300, and therefore, the etching degree of the semiconductor substrate 110 and the first insulating layer 210 can be finely adjusted during the operation of etching the semiconductor substrate 110 and the first insulating layer 210 and forming a through hole 500H in which the through electrode structure 500 is disposed. Therefore, the reliability of the connection structure between the through electrode structure 500 and the contact wiring pattern 635 of the semiconductor device 10 can be improved.

[0087] Figure 4 This is a cross-sectional view of a semiconductor device 20 according to an embodiment of the present invention.

[0088] In the following text, is omitted. Figure 1 Semiconductor device 10 and Figure 4 Redundancy between the semiconductor devices 20 is described, and the differences between them are described in detail.

[0089] The semiconductor device 20 according to an embodiment of the present invention may include a semiconductor substrate 110, a first insulating layer 210, a second insulating layer 230, a third insulating layer 250, an etch stop structure 300, a separator layer 410, a through electrode structure 500, a lower wiring pattern 600, a connection terminal 710, a terminal pad 750, a protective layer 780, an upper wiring structure 900, and a conductive pad 830.

[0090] In an embodiment of the present invention, the through-electrode structure 500 may include a first through-electrode portion 500a and a second through-electrode portion 500b. The first through-electrode portion 500a may be the portion of the through-electrode structure 500 that overlaps with the contact wiring pattern 635 in the vertical direction. Conversely, the second through-electrode portion 500 may be the portion of the through-electrode structure 500 disposed outside the side surface of the contact wiring pattern 635. That is, the second through-electrode portion 500 may be the portion of the through-electrode structure 500 that does not overlap with the contact wiring pattern 635 in the vertical direction.

[0091] In an embodiment of the present invention, the first through electrode portion 500a of the through electrode structure 500 can pass through the first etch stop layer 310 and the second etch stop layer 330 and is disposed on the upper part of the contact wiring pattern 635, while the second through electrode portion 500b can pass through the first etch stop layer 310, the second etch stop layer 330 and the third etch stop layer 350 and is disposed on the upper part of the second insulating layer 230.

[0092] In an embodiment of the present invention, the bottom surface of the first through electrode portion 500a of the through electrode structure 500 can contact the contact wiring pattern 635, and the bottom surface of the second through electrode portion 500b can contact a portion of the second insulating layer 230.

[0093] In an embodiment of the present invention, the second through electrode portion 500b may pass through the etch stop structure 300 to surround at least a portion of the side surface of the contact wiring pattern 635. For example, the second through electrode portion 500b may contact a portion of the side surface of the contact wiring pattern 635. Therefore, the through electrode structure 500 and the contact wiring pattern 635 may be electrically connected. Additionally, the bottom surface of the second through electrode portion 500b may be coplanar with the upper portion (i.e., the upper surface) of the second insulating layer 230.

[0094] The semiconductor device 20 according to an embodiment of the present invention may include an etch stop structure 300, and therefore, the etching degree of the semiconductor substrate 110 and the first insulating layer 210 can be finely adjusted during the operation of etching the semiconductor substrate 110 and the first insulating layer 210 to create the through electrode structure 500. Therefore, the reliability of the connection structure between the through electrode structure 500 and the contact wiring pattern 635 of the semiconductor device 20 can be improved.

[0095] Figure 5 This is a cross-sectional view of a semiconductor device 30 according to an embodiment of the present invention. Additionally, Figure 6 yes Figure 5 A magnified view of region B in the image.

[0096] In the following text, is omitted. Figure 1 Semiconductor device 10 and Figure 5 Redundancy descriptions among the semiconductor devices 30, and primarily descriptions of the differences between them.

[0097] Let's refer to each other. Figure 5 and Figure 6 According to an embodiment of the present invention, the semiconductor device 30 may include a semiconductor substrate 110, a first insulating layer 210, a second insulating layer 230, a third insulating layer 250, an etch stop structure 300, a separator layer 415, a through electrode structure 505, a lower wiring pattern 600, a connection terminal 710, a terminal pad 750, a protective layer 780, an upper wiring structure 900, and a conductive pad 830.

[0098] The lower wiring pattern 600 may include a contact wiring pattern 637 that contacts the through electrode structure 505. In embodiments of the present invention, the contact wiring pattern 637 may be surrounded by an etch stop structure 300. For example, the side surfaces of the contact wiring pattern 637 may be surrounded by a first etch stop layer 310, a second etch stop layer 330, and a third etch stop layer 350. Additionally, the upper surface of the contact wiring pattern 637 may be coplanar with the lower surface of the first insulating layer 210. For example, the upper surface of the contact wiring pattern 637 may be coplanar with the upper surface of the first etch stop layer 310.

[0099] In an embodiment of the present invention, the thickness of the contact wiring pattern 637 can be greater than the thickness of the etch stop structure 300. Therefore, when the upper surface of the contact wiring pattern 637 is coplanar with the lower surface of the first insulating layer 210, the side surface of the contact wiring pattern 637 can be surrounded by the etch stop structure 300 and a portion of the second insulating layer 230.

[0100] In an embodiment of the present invention, the contact wiring pattern 637 may include a barrier metal layer 637a, a seed metal layer 637b, and a metal pattern 637c.

[0101] In embodiments of the present invention, the barrier metal layer 637a may provide the side and top surfaces of the contact wiring pattern 637. For example, the barrier metal layer 637a may be located between the first insulating layer 210 and the seed metal layer 637b, between the second insulating layer 230 and the seed metal layer 637b, and between the etch stop structure 300 and the seed metal layer 637b.

[0102] In embodiments of the present invention, the barrier metal layer 637a may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN).

[0103] In an embodiment of the present invention, the seed metal layer 637b may be located between the barrier metal layer 637a and the metal pattern 637c. In another embodiment, a portion of the seed metal layer 637b may directly contact the through electrode structure 505. For example, the through electrode structure 505 may extend into the seed metal layer 637b to directly contact it. In yet another embodiment, a portion of the metal pattern 637c may directly contact the through electrode structure 505. For example, the through electrode structure 505 may extend into the metal pattern 637c to directly contact it.

[0104] In embodiments of the present invention, the seed metal layer 637b may include, for example, copper (Cu), manganese (Mn), titanium (Ti), or alloys thereof. However, the material of the seed metal layer 637b is not limited thereto.

[0105] In embodiments of the present invention, the metal pattern 637c may be a pattern of conductive material filling a recess formed by the barrier metal layer 637a and the seed metal layer 637b. For example, the upper and side surfaces of the metal pattern 637c may be surrounded by the seed metal layer 637b. Additionally, a portion of the lower surface of the metal pattern 637c may contact the second insulating layer 230 and the lower wiring path pattern 650.

[0106] In embodiments of the present invention, the metal pattern 637c may include, for example, copper (Cu), nickel (Ni), gold (Au), silver (Ag), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), and / or alloys thereof. However, the present invention is not limited thereto.

[0107] The separator layer 415 may be located between the semiconductor substrate 110 and the through electrode structure 505, and between a portion of the first insulating layer 210 and the through electrode structure 505. In embodiments of the present invention, the separator layer 415 may include an insulating material. For example, the separator layer 415 may include, for example, silicon oxide (SiO2) or silicon oxynitride (SiON).

[0108] In embodiments of the present invention, the length of the separator layer 415 in the vertical direction may be less than the length of the through-electrode structure 505 in the vertical direction. The separator layer 415 can electrically isolate the semiconductor substrate 110 from the through-electrode structure 505, thereby preventing and / or suppressing leakage current of the through-electrode structure 505. For example, the separator layer 415 may pass through the first surface 110S1 and the second surface 110S2 of the semiconductor substrate 110 and the upper surface of the first insulating layer 210. However, the separator layer 415 may not pass through the lower surface of the first insulating layer 210.

[0109] The third insulating layer 250 may be disposed on the second surface 110S2 of the semiconductor substrate 110 opposite to its first surface 110S1 and configured as part of the side surface surrounding the separator layer 415. The third insulating layer 250, the separator layer 415 and the uppermost surface of the through electrode structure 505 may be coplanar with each other.

[0110] The through electrode structure 505 may include a blocking pattern 515, a seed pattern 535, and a conductive path 555.

[0111] In embodiments of the present invention, the blocking pattern 515 may be disposed along the side and bottom surfaces of the through electrode structure 505. The blocking pattern 515 may be located between the separator layer 415 and the seed pattern 535, between the seed metal layer 637b and the seed pattern 535, between the second etch stop layer 330 and the seed pattern 535, and between the first etch stop layer 310 and the seed pattern 535. For example, the blocking pattern 515 may be disposed along the surface of the separator layer 415 and configured to contact the contact wiring pattern 637.

[0112] In an embodiment of the present invention, the seed pattern 535 may extend along the inner surface of the blocking pattern 515. The seed pattern 535 may be located between the blocking pattern 515 and the conductive passage 555. Furthermore, the conductive passage 555 may be disposed on the seed pattern 535 and may fill a through-hole (e.g., a via hole) defined by the inner surface of the seed pattern 535.

[0113] In an embodiment of the present invention, the through-electrode structure 505 may include a first through-electrode portion 505a and a second through-electrode portion 505b. The first through-electrode portion 505a may be the portion of the through-electrode structure 505 that overlaps with the contact wiring pattern 637 in the vertical direction. Conversely, the second through-electrode portion 505b may be the portion of the through-electrode structure 505 disposed outside the side surface of the contact wiring pattern 637. That is, the second through-electrode portion 505b may be the portion of the through-electrode structure 505 that does not overlap with the contact wiring pattern 637 in the vertical direction.

[0114] In an embodiment of the present invention, the length of the first through electrode portion 505a in the vertical direction may be less than the length of the second through electrode portion 505b in the vertical direction. Therefore, the through electrode structure 505 may have a stepped shape outside the contact wiring pattern 637.

[0115] In an embodiment of the present invention, the first through-electrode portion 505a of the through-electrode structure 505 can contact the upper surface of the contact wiring pattern 637. In an embodiment of the present invention, the blocking pattern 515 of the first through-electrode portion 505a can contact the seed metal layer 637b of the contact wiring pattern 637. However, the present invention is not limited thereto. For example, in an embodiment of the present invention, the blocking pattern 515 of the first through-electrode portion 505a can contact the metal pattern 637c of the contact wiring pattern 637. For example, in an embodiment of the present invention, the blocking pattern 515 of the first through-electrode portion 505a can contact the blocking metal layer 637a of the contact wiring pattern 637.

[0116] The second through-electrode portion 505b of the through-electrode structure 505 can pass through a portion of the etch stop structure 300. That is, the second through-electrode portion 505b can pass through the first etch stop layer 310 and can contact the second etch stop layer 330. Additionally, a portion of the second through-electrode portion 505b can surround a portion of the side surface of the contact wiring pattern 637. For example, the second through-electrode portion 505b can contact a portion of the side surface of the contact wiring pattern 637. Therefore, the through-electrode structure 505 and the contact wiring pattern 637 can be electrically connected.

[0117] The semiconductor device 30 according to an embodiment of the present invention may include an etch stop structure 300, and therefore, the etching degree of the semiconductor substrate 110 and the first insulating layer 210 can be finely adjusted during the operation of etching the semiconductor substrate 110 and the first insulating layer 210 to create the through electrode structure 505. Therefore, the reliability of the connection structure between the through electrode structure 505 and the contact wiring pattern 637 of the semiconductor device 30 can be improved.

[0118] Figure 7 This is a cross-sectional view of a semiconductor device 40 according to an embodiment of the present invention.

[0119] In the following text, is omitted. Figure 1 Semiconductor device 10 and Figure 7 Redundancy descriptions among the semiconductor devices 40, and primarily descriptions of the differences between them.

[0120] The etch stop structure 305 of the semiconductor device 40 according to an embodiment of the present invention may include a first etch stop layer 315, a second etch stop layer 335, a third etch stop layer 355, a fourth etch stop layer 375, and a fifth etch stop layer 395. Although Figure 7 The etch stop structure 305 is shown as including five etch stop layers, but the number of etch stop layers included in the etch stop structure 305 is not limited to this.

[0121] In embodiments of the present invention, the first etch stop layer 315, the second etch stop layer 335, the third etch stop layer 355, the fourth etch stop layer 375, and the fifth etch stop layer 395 may each have a thickness of approximately 1 nanometer to approximately 10 nanometers. Additionally, the etch stop structure 305 may have a structure in which two materials with different etch selectivity are alternately stacked.

[0122] The first etch stop layer 315, the third etch stop layer 355, and the fifth etch stop layer 395 may comprise materials that have a relatively high etch rate in wet etching processes but a relatively low etch rate in dry etching processes or are not etched at all. Furthermore, the materials of the first etch stop layer 315, the third etch stop layer 355, and the fifth etch stop layer 395 may be substantially the same as each other.

[0123] The second etch stop layer 335 and the fourth etch stop layer 375 may comprise materials that have a relatively high etch rate in dry etching processes but a relatively low etch rate in wet etching processes or are not etched at all. Furthermore, the materials of the second etch stop layer 335 and the fourth etch stop layer 375 may be substantially the same as each other.

[0124] In an embodiment of the present invention, the side surface of the contact wiring pattern 639 of the semiconductor device 40 may be surrounded by a fifth etch stop layer 395 and a second insulating layer 230, and the upper surface of the contact wiring pattern 639 may contact a fourth etch stop layer 375 and a through electrode structure 507.

[0125] The through-electrode structure 507 of the semiconductor device 40 can pass through the semiconductor substrate 110, the first insulating layer 210, and the first etch stop layer 315, the second etch stop layer 335, the third etch stop layer 355, and the fourth etch stop layer 375 of the etch stop structure 305 to contact the contact wiring pattern 639. A portion of the side surface of the through-electrode structure 507 may be surrounded by the first etch stop layer 315, the second etch stop layer 335, the third etch stop layer 355, and the fourth etch stop layer 375.

[0126] In embodiments of the present invention, the through-electrode structure 507 may include a blocking pattern 517, a seed pattern 537, and a conductive path 557. Additionally, a separator layer 417 may surround a portion of the side surface of the through-electrode structure 507. For example, the blocking pattern 517 may be disposed along the surface of the separator layer 417 and configured to contact the contact wiring pattern 639. Furthermore, the separator layer 417 may extend through the first etch stop layer 315, the second etch stop layer 335, and the third etch stop layer 355 to contact the fourth etch stop layer 375. The separator layer 417 can electrically isolate the semiconductor substrate 110 and the through-electrode structure 507, thereby preventing and / or suppressing leakage current in the through-electrode structure 507.

[0127] The semiconductor device 40 according to an embodiment of the present invention may include an etch stop structure 305, and therefore, the etching degree of the semiconductor substrate 110 and the first insulating layer 210 can be finely adjusted during the operation of etching the semiconductor substrate 110 and the first insulating layer 210 to create the through electrode structure 507. Therefore, the reliability of the connection structure between the through electrode structure 507 and the contact wiring pattern 639 of the semiconductor device 40 can be improved.

[0128] Figure 8 This is a cross-sectional view of a semiconductor package 1 according to an embodiment of the present invention.

[0129] refer to Figure 8 According to an embodiment of the present invention, the semiconductor package 1 may include a first semiconductor device 10a, a second semiconductor device 10b, a third semiconductor device 10c, a package substrate 1100, an external connection terminal 1200, and a molding layer 2100.

[0130] Although the semiconductor package 1 according to this embodiment is shown to include three semiconductor devices, such as a first semiconductor device 10a, a second semiconductor device 10b and a third semiconductor device 10c, the number of semiconductor devices included in the semiconductor package 1 is not limited to those described above.

[0131] The packaging substrate 1100 may be a substrate on which a first semiconductor device 10a, a second semiconductor device 10b, and a third semiconductor device 10c are mounted. For example, the packaging substrate 1100 may include a printed circuit board or a redistribution layer. In addition, external connection terminals 1200 may be disposed on the lower part of the packaging substrate 1100 to be electrically connected to the wiring pattern in the packaging substrate 1100.

[0132] The first semiconductor device 10a and the second semiconductor device 10b can be substantially similar to the reference. Figures 1 to 7 At least one of the described semiconductor devices 10, 20, 30, or 40 is identical. For example, the first semiconductor device 10a and the second semiconductor device 10b may include semiconductor substrates 110a and 110b, first insulating layers 210a and 210b, second insulating layers 230a and 230b, etch stop structures 300a and 300b, through electrode structures 500a1 and 500b2, lower wiring patterns 600a and 600b, connection terminals 710a and 710b, upper wiring structures 900a and 900b, and conductive pads 830a and 830b. The etch stop structure 300a of the first semiconductor device 10a and the etch stop structure 300b of the second semiconductor device 10b may each be substantially similar to the referenced one. Figures 1 to 6 The described etch stop structure 300 or reference Figure 7 The etch stop structure 305 described is the same. The through-electrode structure 500a1 of the first semiconductor device 10a and the through-electrode structure 500b2 of the second semiconductor device 10b can each be substantially the same as the reference. Figures 1 to 4 The described through-electrode structure 500, reference Figures 5 to 6 The described through-electrode structure 505, or referenced Figure 7 The through-electrode structure 507 described is the same. In addition, the third semiconductor device 10c may include a semiconductor substrate 110c, a first insulating layer 210c, a lower wiring pattern 600c, and a connection terminal 710c.

[0133] The first semiconductor device 10a can be mounted on the packaging substrate 1100. The connection terminal 710a of the first semiconductor device 10a can be located between the semiconductor substrate 110a and the packaging substrate 1100 to electrically connect the first semiconductor device 10a to the packaging substrate 1100.

[0134] The second semiconductor device 10b can be mounted on the first semiconductor device 10a. The connection terminal 710b of the second semiconductor device 10b can be located between the semiconductor substrate 110a of the first semiconductor device 10a and the semiconductor substrate 110b of the second semiconductor device 10b to electrically connect the first semiconductor device 10a to the second semiconductor device 10b.

[0135] The third semiconductor device 10c can be mounted on the second semiconductor device 10b. The connection terminal 710c of the third semiconductor device 10c can be located between the semiconductor substrate 110b of the second semiconductor device 10b and the semiconductor substrate 110c of the third semiconductor device 10c to electrically connect the second semiconductor device 10b to the third semiconductor device 10c.

[0136] The third semiconductor device 10c may not include a through-electrode structure and an etch stop structure.

[0137] The molding layer 2100 can cover the first semiconductor device 10a, the second semiconductor device 10b, and the third semiconductor device 10c on the packaging substrate 1100. In embodiments of the present invention, the molding layer 2100 may include an epoxy molding compound (EMC) material. However, the material of the molding layer 2100 is not limited to the aforementioned epoxy molding compound (EMC) and may include various materials, such as epoxy materials, thermosetting materials, thermoplastic materials, UV-treated materials, etc.

[0138] Since the first semiconductor device 10a and the second semiconductor device 10b may include etch stop structures 300a and 300b to form reliable connection structures for through electrode structures 500a1 and 500b2 and lower wiring patterns 600a and 600b respectively, the manufactured semiconductor package 1 can have a reliable structure.

[0139] In embodiments of the present invention, with Figure 8 As shown, the semiconductor package 1 may include only the first semiconductor device 10a. In other words, the semiconductor package 1 may include only one semiconductor device, such as the first semiconductor device 10a.

[0140] In an embodiment of the present invention, the semiconductor device 10a included in the semiconductor package 1 may include a lower wiring pattern 630, an upper wiring pattern 930, and a through electrode structure 500 connecting the lower wiring pattern 630 to the upper wiring pattern 930.

[0141] When the semiconductor package 1 includes a semiconductor device 10a, the lower wiring pattern 630 disposed on the lower part of the semiconductor device 10a can be configured to transmit data signals and / or control signals, and the upper wiring pattern 930 disposed on the upper part of the semiconductor device 10a can be configured to transmit power signals. However, the inventive concept is not limited thereto, and the lower wiring pattern 630 disposed on the lower part of the semiconductor device 10a can be configured to transmit power signals, and the upper wiring pattern 930 disposed on the upper part of the semiconductor device 10a can be configured to transmit data signals and / or control signals.

[0142] Figures 9A to 9J This is a diagram illustrating the operation of a method for manufacturing a semiconductor device 20 according to an embodiment of the present invention.

[0143] In the following text, reference will be made to Figures 9A to 9J A method for manufacturing a semiconductor device 20 according to an embodiment of the present invention is described. The method for manufacturing the semiconductor device 20 according to this embodiment may include manufacturing… Figure 4 Method for developing semiconductor device 20.

[0144] refer to Figure 9A A first insulating layer 210, an etch stop structure 300, and a second insulating layer 230 can be sequentially stacked on the first surface 110S1 of the semiconductor substrate 110.

[0145] The contact wiring pattern 635 can be formed in the second insulating layer 230 by photolithography and etching processes. For example, in the photolithography process, the mask pattern can be formed with openings for defining areas of the second insulating layer 230 to be etched. For example, in the etching process of forming the contact wiring pattern 635 in the second insulating layer 230, the third etch stop layer 350 of the etch stop structure 300 can act as a stop layer.

[0146] A portion of the second insulating layer 230 can be removed using a dry etching process until the third etch stop layer 350 is exposed. Alternatively, the third etch stop layer 350 can be removed using a wet etching process for cleaning the surface of the second insulating layer 230.

[0147] An etch stop structure 300 can be used in the process of forming the contact wiring pattern 635 so that the contact wiring pattern 635 can be formed with a separation distance of relatively consistent size with the first surface 110S1 of the semiconductor substrate 110 in the vertical direction.

[0148] The contact wiring pattern 635 can be formed by the following operations: forming a barrier metal layer 635a on the surface of the second insulating layer 230 and the second etch stop layer 330; forming a seed metal layer 635b on the barrier metal layer 635a; and forming a metal pattern 635c in the recess formed by the barrier metal layer 635a and the seed metal layer 635b. For example, a trench can be formed after removing a portion of the second insulating layer 230 by a dry etching process and removing the third etch stop layer 350 by a wet etching process. The barrier metal layer 635a can be formed in the trench to conformally cover the bottom and sidewalls of the trench. The seed metal layer 635b can be conformally formed on the barrier metal layer 635a. By performing an electroplating process using the seed metal layer 635b as an electrode, the metal pattern 635c can be formed on the seed metal layer 635b. Then an etching process or a planarization process can be performed to remove the barrier metal layer 635a, seed metal layer 635b and metal pattern 635c on top of the second insulating layer 230.

[0149] refer to Figure 9B The semiconductor substrate 110 can be flipped so that its second surface 110S2 faces upward. A portion of the semiconductor substrate 110 can then be removed, making the semiconductor substrate 110 thin. For example, thinning the semiconductor substrate 110 can include performing a planarization process on the second surface 110S2 of the semiconductor substrate 110. The planarization process can be a chemical mechanical polishing (CMP) process.

[0150] refer to Figure 9C A mask pattern MP can be formed on the second surface 110S2 of the semiconductor substrate 110. In embodiments of the present invention, the mask pattern MP may include a carbon-containing material such as a spin-coated carbon hard mask (SOC) material.

[0151] The mask pattern MP may include a mask opening MO formed by a photolithography process. The mask opening MO may expose the second surface 110S2 of the semiconductor substrate 110.

[0152] The operation of etching the semiconductor substrate 100 and forming a through-hole 500H can be performed. In an embodiment of the present invention, the through-hole 500H can be formed by etching the second surface 110S2 of the semiconductor substrate 110 exposed by the mask opening MO of the mask pattern MP. For example, the etching process can be a dry etching process using a fluorine-containing gas.

[0153] In embodiments of the present invention, the first etch stop layer 310 of the etch stop structure 300 may have a relatively low etch rate in a dry etching process or may not be etched at all. Therefore, after the etching processes of the semiconductor substrate 110 and the first insulating layer 210 are completed, the via 500H may expose the upper surface of the first etch stop layer 310. Depending on the etching conditions, the via 500H may or may not have vertical sidewalls perpendicular to the upper surface of the first etch stop layer 310. In embodiments of the present invention, the via 500H may have a tapered shape, wherein the cross-sectional area of ​​the via 500H in the horizontal direction decreases toward the contact wiring pattern 635.

[0154] refer to Figure 9D The surface of the through-hole 500H can be cleaned. In embodiments of the present invention, the inner surface of the semiconductor substrate 110 defining the through-hole 500H and the inner surface of the first insulating layer 210 can be cleaned by a wet etching process. For example, the etching process can be a wet etching process using an etchant such as an ammonium-containing material.

[0155] In the embodiments of the present invention, the first etch stop layer 310 of the etch stop structure 300 can have a relatively high etch rate in the wet etching process. Furthermore, the second etch stop layer 330 of the etch stop structure 300 can have a relatively low etch rate in the wet etching process or may not be etched at all. Therefore, during the cleaning operation of the semiconductor substrate 110 and the first insulating layer 210, the first etch stop layer 310 can be removed, and the through-hole 500H can expose the upper surface of the second etch stop layer 330.

[0156] The semiconductor device 20 according to an embodiment of the present invention may include an etch stop structure 300, and therefore, the etching degree of the semiconductor substrate 110 and the first insulating layer 210 can be finely adjusted during the operation of etching the semiconductor substrate 110 and the first insulating layer 210 to form the through-hole 500H. Therefore, the reliability of the connection structure of the through-electrode structure 500 and the contact wiring pattern 635 of the semiconductor device 10 can be improved.

[0157] refer to Figure 9E A separator layer 410 can be formed in the through-hole 500H. For example, the separator layer 410 can conformally cover the upper surface of the mask pattern MP and the bottom and side surfaces of the through-hole 500H. In addition, the separator layer 410 can cover the second etch stop layer 330 of the etch stop structure 300 exposed by the through-hole 500H.

[0158] refer to Figure 9FThe operation of exposing the contact wiring pattern 635 can be performed by an etching process. The etching process may include removing the separator layer 410 and the second etch stop layer 330 by a dry etching process and removing the third etch stop layer 350 by a wet etching process.

[0159] In the operation of removing the separator layer 410 and the second etch stop layer 330 exposed by the through-hole 500H using a dry etching process, the third etch stop layer 350 can act as a stop layer. Therefore, physical damage to the contact wiring pattern 635 can be prevented during the operation of exposing the contact wiring pattern 635 by etching. In this etching process, the separator layer 410 on top of the mask pattern MP can also be removed, or its thickness can be significantly reduced.

[0160] refer to Figure 9G The operation of forming a barrier pattern 510 and a seed pattern 530 can be performed. The barrier pattern 510 can be formed on the surface of the separator layer 410 and the bottom and side surfaces of the through hole 500H. For example, the barrier pattern 510 can be formed on the surface of the separator layer 410, the surface of the second etch stop layer 330 exposed by the through hole 500H, the surface of the third etch stop layer 350, and the surface of the contact wiring pattern 635.

[0161] In an embodiment of the present invention, the barrier pattern 510 can be formed by a deposition process and can conformally cover the bottom and side surfaces of the through-hole 500H. The barrier pattern 510 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable deposition process. The barrier pattern 510 can be horizontally spaced from the semiconductor substrate 110 by the aforementioned separating layer 410.

[0162] In embodiments of the present invention, the seed pattern 530 may be conformally formed on the surface of the barrier pattern 510. The seed pattern 530 may be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0163] refer to Figure 9H The operation of forming a conductive path 550 can be performed. The conductive path 550 can be formed by an electroplating process using a seed pattern 530 as an electrode. The conductive path 550 can be filled inside the through hole 500H by an electroplating process.

[0164] pass Figure 9G and Figure 9HThe manufacturing process can produce the through electrode structure 500 according to an embodiment of the present invention. Therefore, the through electrode structure 500 may include a blocking pattern 510, a seed pattern 530, and a conductive path 550.

[0165] refer to Figure 9I It can perform operations to remove the mask pattern MP, the separator layer 410, the blocking pattern 510, the seed pattern 530 and a portion of the conductive path 550 disposed on the second surface 110S2 of the semiconductor substrate 110.

[0166] In embodiments of the present invention, the mask pattern MP, separator layer 410, barrier pattern 510, seed pattern 530, and conductive path 550 can be removed by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process. Furthermore, the barrier pattern 510, seed pattern 530, and conductive path 550 removed by the planarization process can form a through-electrode structure 500. That is, the through-electrode structure 500 may include the barrier pattern 510, seed pattern 530, and conductive path 550 remaining after the planarization process.

[0167] The remaining mask pattern MP after the planarization process can form the aforementioned third insulating layer 250. However, the inventive concept is not limited thereto, and the planarization process can be performed until the second surface 110S2 of the semiconductor substrate 110 is exposed.

[0168] refer to Figure 9J The system can perform operations to form an upper wiring structure 900 on the upper surface of the third insulating layer 250 and the upper surface of the through electrode structure 500. For example, forming the upper wiring structure 900 may include forming an upper wiring insulating layer 910 on the third insulating layer 250 and patterning the upper wiring insulating layer 910 to form an upper wiring line pattern 930 and an upper wiring path pattern 950. The upper wiring line pattern 930 may include two or more layers extending in a horizontal direction. The upper wiring path pattern 950 may extend vertically within the upper wiring insulating layer 910 to interconnect multiple upper wiring line patterns 930.

[0169] The operation of forming conductive pads 830 on the upper wiring structure 900 can be additionally performed. The conductive pads 830 can be electrically connected to the through electrode structure 500 via the upper wiring structure 900. For example, the conductive pads 830 can contact a portion of the upper wiring path pattern 950 and can be electrically connected to the through electrode structure 500 via the upper wiring path pattern 950 and the upper wiring line pattern 930.

[0170] As described above, the semiconductor device 20 according to an embodiment of the present invention can be manufactured.

[0171] Figures 10A to 10J This is a diagram illustrating the operation of a method for manufacturing a semiconductor device 30 according to an embodiment of the present invention.

[0172] In the following text, reference will be made to Figures 10A to 10J A method for manufacturing a semiconductor device 30 according to an embodiment of the present invention is described. The method for manufacturing a semiconductor device 30 according to this embodiment may be... Figure 5 A method for manufacturing semiconductor device 30.

[0173] In the following text, the method and reference for manufacturing semiconductor device 30 are omitted. Figures 9A to 9J The description of the methods for manufacturing semiconductor device 20 is redundant, and the main focus is on the differences between them.

[0174] refer to Figure 10A A first insulating layer 210, an etch stop structure 300, and a second insulating layer 230 can be sequentially stacked on the first surface 110S1 of the semiconductor substrate 110.

[0175] The contact wiring pattern 637 can be formed in the second insulating layer 230 by photolithography and etching processes. For example, in the photolithography process, the mask pattern can be formed with openings for defining areas of the second insulating layer 230 to be etched. For example, in the etching process of the second insulating layer 230 for forming the contact wiring pattern 637, the first etch stop layer 310 of the etch stop structure 300 can act as a stop layer.

[0176] The second insulating layer 230, the third etch stop layer 350, and the second etch stop layer 330 can be removed by a dry etching process until the first etch stop layer 310 is exposed. Alternatively, the first etch stop layer 310 can be removed by a wet etching process used to clean the surface of the second insulating layer 230.

[0177] An etch stop structure 300 can be used in the process of forming the contact wiring pattern 637, so that the contact wiring pattern 637 can be formed with a separation distance of relatively consistent size with the first surface 110S1 of the semiconductor substrate 110 in the vertical direction.

[0178] The contact wiring pattern 637 can be formed by the following operations: forming a barrier metal layer 637a on the surface of the second insulating layer 230, the surface of the etch stop structure 300, and the surface of the first insulating layer 210; forming a seed metal layer 637b on the barrier metal layer 637a; and forming a metal pattern 637c in the recess formed by the barrier metal layer 637a and the seed metal layer 637b. For example, a trench can be formed after removing the second insulating layer 230, the third etch stop layer 350, the second etch stop layer 330, and the first etch stop layer 310 by alternately applying dry and wet etching processes. The barrier metal layer 637a can be formed in the trench to conformally cover the bottom and sidewalls of the trench. The seed metal layer 637b can be formed on the barrier metal layer 637a. By performing an electroplating process using the seed metal layer 637b as an electrode, the metal pattern 637c can be formed on the seed metal layer 637b. Then an etching process or a planarization process can be performed to remove the barrier metal layer 637a, seed metal layer 637b and metal pattern 637c on top of the second insulating layer 230.

[0179] refer to Figure 10B The semiconductor substrate 110 can be flipped so that its second surface 110S2 faces upward. Subsequently, a portion of the semiconductor substrate 110 can be removed, allowing the semiconductor substrate 110 to be thin.

[0180] refer to Figure 10C A mask pattern MP can be formed on the second surface 110S2 of the semiconductor substrate 110. In embodiments of the present invention, the mask pattern MP may include a carbon-containing material such as a SOC material.

[0181] The mask pattern MP may include a mask opening MO formed by a photolithography process. The mask opening MO may expose the second surface 110S2 of the semiconductor substrate 110.

[0182] The operation of etching the semiconductor substrate 110 and forming the through-hole 505H can be performed. In embodiments of the present invention, the through-hole 505H can be formed by etching the second surface 110S2 of the semiconductor substrate 110 exposed by the mask opening MO of the mask pattern MP. For example, the etching process can be a dry etching process using a fluorine-containing gas.

[0183] In an embodiment of the present invention, the etch stop structure 300 may not be etched during the etching process. In other words, the through-hole 505H generated by the etching process may not expose the etch stop structure 300. For example, the through-hole 505H may pass through the first surface 110S1 and the second surface 110S2 of the semiconductor substrate 110 and the upper surface of the first insulating layer 210. However, the through-hole 505H may not pass through the lower surface of the first insulating layer 210.

[0184] refer to Figure 10D A separator layer 415 can be formed in the through-hole 505H. For example, the separator layer 415 can conformally cover the top surface of the mask pattern MP and the bottom and side surfaces of the through-hole 505H. For example, the separator layer 415 can cover one surface of the first insulating layer 210 exposed through the through-hole 505H.

[0185] refer to Figure 10E The etching process can be performed to etch the first insulating layer 210 and expose the contact wiring pattern 637. Before etching the first insulating layer 210 below the through-hole 505H, the portion of the separator layer 415 exposed at the bottom of the through-hole 505H can be etched away first. For example, the etching process can be a dry etching process using a fluorine-containing gas.

[0186] In embodiments of the present invention, the first etch stop layer 310 of the etch stop structure 300 may have a relatively low etch rate or may not be etched at all during a dry etching process. Therefore, after the operation of etching the first insulating layer 210 and exposing the contact wiring pattern 637, the through-hole 505H may expose the upper surface of the first etch stop layer 310.

[0187] In an embodiment of the present invention, the etching process for exposing the contact wiring pattern 637 can be performed after the operation of forming the separator layer 415, so the length of the separator layer 415 in the vertical direction can be less than the length of the through hole 505H of the exposed contact wiring pattern 637 in the vertical direction.

[0188] refer to Figure 10F The surface of the through-hole 505H can be cleaned. In embodiments of the present invention, the inner surface of the semiconductor substrate 110 defining the through-hole 505H and the inner surface of the first insulating layer 210 can be cleaned by a wet etching process. For example, the etching process can be a wet etching process using an etchant such as an ammonium-containing material.

[0189] In embodiments of the present invention, the first etch stop layer 310 of the etch stop structure 300 can have a relatively high etch rate in a wet etching process. Conversely, the second etch stop layer 330 of the etch stop structure 300 can have a relatively low etch rate or may not be etched at all in a wet etching process.

[0190] During the cleaning of the semiconductor substrate 110 and the first insulating layer 210, the first etch stop layer 310 can be removed, and the through-hole 505H can expose the upper surface of the second etch stop layer 330. Therefore, a step can be created in the lower portion of the through-hole 505H adjacent to the contact wiring pattern 637.

[0191] refer to Figure 10G The operation of forming a barrier pattern 515 and a seed pattern 535 can be performed. The barrier pattern 515 can be conformally formed on the surface of the separator layer 415 and the bottom and side surfaces of the through hole 505H. For example, the barrier pattern 515 can be formed on the surface of the separator layer 415, the surface of the second etch stop layer 330 exposed by the through hole 505H, the surface of the first etch stop layer 310, the surface of the first insulating layer 210, and the surface of the contact wiring pattern 637.

[0192] In an embodiment of the present invention, the barrier pattern 515 can be formed by a deposition process and can conformally cover the bottom and side surfaces of the through-hole 505H. The barrier pattern 515 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable deposition process. The barrier pattern 515 can be horizontally spaced from the semiconductor substrate 110 by the aforementioned separating layer 415.

[0193] In embodiments of the present invention, the seed pattern 535 may be conformally formed on the surface of the barrier pattern 515. The seed pattern 535 may be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0194] refer to Figure 10H The operation of forming a conductive path 555 can be performed. The conductive path 555 can be formed by an electroplating process using a seed pattern 535 as an electrode. The conductive path 555 can be filled inside the through hole 505H by an electroplating process.

[0195] pass Figures 10A to 10H The manufacturing process can be used to manufacture the through electrode structure 505 according to an embodiment of the present invention. Therefore, the through electrode structure 505 may include a blocking pattern 515, a seed pattern 535, and a conductive path 555.

[0196] refer to Figure 10I It can remove the mask pattern MP, separator layer 415, blocking pattern 515, seed pattern 535 and a portion of conductive path 555 disposed on the second surface 110S2 of semiconductor substrate 110.

[0197] In embodiments of the present invention, the mask pattern MP, separator layer 415, barrier pattern 515, seed pattern 535, and conductive path 555 can be removed by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process. Furthermore, the barrier pattern 515, seed pattern 535, and conductive path 555 removed by the planarization process can form a through-electrode structure 505. That is, the through-electrode structure 505 may include the barrier pattern 515, seed pattern 535, and conductive path 555 remaining after the planarization process.

[0198] The remaining mask pattern MP after the planarization process can form the aforementioned third insulating layer 250. However, the inventive concept is not limited thereto, and the planarization process can be performed until the second surface 110S2 of the semiconductor substrate 110 is exposed.

[0199] refer to Figure 10J The system can perform operations to form an upper wiring structure 900 on the upper surface of the third insulating layer 250 and the upper surface of the through electrode structure 505. For example, forming the upper wiring structure 900 may include forming an upper wiring insulating layer 910 on the third insulating layer 250, and patterning the upper wiring insulating layer 910 to form an upper wiring line pattern 930 and an upper wiring path pattern 950. The upper wiring line pattern 930 may include two or more layers extending in a horizontal direction. The upper wiring path pattern 950 may extend vertically within the upper wiring insulating layer 910 to interconnect multiple upper wiring line patterns 930.

[0200] The operation of forming conductive pads 830 on the upper wiring structure 900 can be additionally performed. The conductive pads 830 can be electrically connected to the through electrode structure 505 via the upper wiring structure 900. For example, the conductive pads 830 can contact a portion of the upper wiring path pattern 950 and can be electrically connected to the through electrode structure 505 via the upper wiring path pattern 950 and the upper wiring line pattern 930.

[0201] As described above, the semiconductor device 30 according to an embodiment of the present invention can be manufactured.

[0202] In a method of manufacturing a semiconductor device 30 according to an embodiment of the present invention, an etch stop structure 300 including a plurality of etch stop layers 310, 330 and 350 can be used as a stop layer in the operation of etching the semiconductor substrate 110 and the first insulating layer 210.

[0203] The etch stop layers 310, 330, and 350 of the etch stop structure 300 can have a structure in which two materials with different etch selectivity are alternately stacked. The etch stop structure 300 can finely control the etching degree of the semiconductor substrate 110 and the first insulating layer 210. Therefore, physical damage to the contact wiring pattern 637 can be prevented in the process of manufacturing the semiconductor device 30, and the reliability of the connection structure between the contact wiring pattern 637 and the through electrode structure 505 can be improved.

[0204] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface adjacent to an active layer; A first insulating layer is disposed on the first surface of the semiconductor substrate; A second insulating layer is disposed on the first insulating layer; An etch stop structure, wherein the etch stop structure is located between the first insulating layer and the second insulating layer and includes a plurality of etch stop layers; A contact wiring pattern disposed within the second insulating layer and surrounded by at least one of the plurality of etch stop layers; as well as A through-electrode structure is configured to pass through the semiconductor substrate, the first insulating layer, and at least one of the plurality of etch stop layers in a vertical direction and to contact the contact wiring pattern.

2. The semiconductor device of claim 1, wherein, The etch stop structure includes: A first etch stop layer is disposed on the lower portion of the first insulating layer and is configured to surround a portion of the side surface of the through electrode structure; A second etch stop layer, disposed below the first etch stop layer, is configured to surround a portion of the side surface of the through-electrode structure and is configured to contact the contact wiring pattern; and A third etch stop layer is disposed between the second etch stop layer and the second insulating layer and is configured to be part of the side surface surrounding the contact wiring pattern.

3. The semiconductor device according to claim 2, wherein, The lower surface of the second etch stop layer is coplanar with the upper surface of the contact wiring pattern.

4. The semiconductor device according to claim 2, wherein, The material of the first etch stop layer is different from the material of the second etch stop layer, and The material of the first etch stop layer is the same as the material of the third etch stop layer.

5. The semiconductor device according to claim 4, wherein, The material of the first etch stop layer has a lower etch rate in the dry etching process than the material of the second etch stop layer in the dry etching process.

6. The semiconductor device according to claim 4, wherein, The material of the first etch stop layer includes at least one selected from nickel, copper, tungsten, titanium, tantalum, indium, molybdenum, manganese, cobalt, tin, magnesium, rhenium, beryllium, gallium, aluminum, or ruthenium. The material of the second etch stop layer includes at least one of silicon, carbon, oxygen, nitrogen, or hydrogen.

7. The semiconductor device according to claim 2, wherein, The first etch stop layer, the second etch stop layer, and the third etch stop layer all have a thickness of 1 nanometer to 10 nanometers.

8. The semiconductor device according to claim 2, further comprising: A separating layer is provided between the through-electrode structure and the semiconductor substrate, between the through-electrode structure and the first insulating layer, and between the through-electrode structure and the first etch stop layer.

9. The semiconductor device according to claim 8, wherein, The through-electrode structure includes: A blocking pattern is disposed along the surface of the separator layer and configured to contact the contact wiring pattern; Seed pattern, the seed pattern being disposed along the surface of the blocking pattern; and A conductive path is provided on the seed pattern and fills the path opening defined by the blocking pattern and the seed pattern. The uppermost surface of the blocking pattern, the uppermost surface of the seed pattern, and the uppermost surface of the conductive path are coplanar.

10. The semiconductor device according to claim 1, wherein, The width of the through-electrode structure is 30 nanometers to 200 nanometers.

11. The semiconductor device according to claim 1, wherein, The through-electrode structure includes: A first through-electrode portion, the first through-electrode portion being configured to overlap with the contact wiring pattern in the vertical direction; and The second through electrode portion is disposed outside the side surface of the contact wiring pattern.

12. A semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface adjacent to an active layer; A first insulating layer is disposed on the first surface of the semiconductor substrate; A second insulating layer is disposed on the first insulating layer; An etch stop structure is provided, which is located between a first insulating layer and a second insulating layer and includes a first etch stop layer disposed on the lower part of the first insulating layer, a second etch stop layer disposed on the lower part of the first etch stop layer, and a third etch stop layer disposed between the second etch stop layer and the second insulating layer. A contact wiring pattern is disposed on the second etch stop layer and surrounded by the third etch stop layer and the second insulating layer; as well as A through-electrode structure is configured to pass through the semiconductor substrate, the first insulating layer, the first etch stop layer and the second etch stop layer and contact the contact wiring pattern, the through-electrode structure having a width of 10 nanometers to 200 nanometers.

13. The semiconductor device according to claim 12, wherein, The material of the first etch stop layer is different from the material of the second etch stop layer, and The material of the first etch stop layer is the same as the material of the third etch stop layer.

14. The semiconductor device according to claim 12, wherein, The sum of the thickness of the first etch stop layer, the thickness of the second etch stop layer, and the thickness of the third etch stop layer is 3 nanometers to 30 nanometers.

15. The semiconductor device of claim 12, further comprising: A separating layer is provided between the through-electrode structure and the semiconductor substrate, between the through-electrode structure and the first insulating layer, and between the through-electrode structure and the first etch stop layer.

16. The semiconductor device according to claim 12, wherein, The bottom surface of the through electrode structure is circular.

17. A semiconductor device, the semiconductor device comprising: A semiconductor substrate having a first surface adjacent to an active layer; A first insulating layer is disposed on the first surface of the semiconductor substrate; A second insulating layer is disposed on the first insulating layer; An etch stop structure, wherein the etch stop structure is located between the first insulating layer and the second insulating layer and includes a plurality of etch stop layers; A contact wiring pattern disposed between the first insulating layer and the second insulating layer and surrounded by the plurality of etch stop layers; as well as A through-electrode structure is configured to pass through the semiconductor substrate, the first insulating layer, and at least one of the plurality of etch stop layers in a vertical direction and to contact the contact wiring pattern.

18. The semiconductor device according to claim 17, wherein, The through-electrode structure includes: A first through electrode portion, configured to overlap with and contact the upper surface of the contact wiring pattern in the vertical direction; and The second through electrode portion is configured to pass through at least one of the plurality of etch stop layers and contact the side surface of the contact wiring pattern. Wherein, the length of the first through electrode portion in the vertical direction is less than the length of the second through electrode portion in the vertical direction.

19. The semiconductor device according to claim 18, wherein, The etch stop structure includes: A first etch stop layer is disposed on the lower portion of the first insulating layer and is configured to surround at least a portion of the side surface of the second through electrode portion; A second etch stop layer is disposed below the first etch stop layer and configured to contact the lower surface of the second through electrode portion; and A third etch stop layer is disposed between the second etch stop layer and the second insulating layer.

20. The semiconductor device according to claim 19, wherein, The material of the first etch stop layer is different from the material of the second etch stop layer, and The material of the first etch stop layer is the same as the material of the third etch stop layer.

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