Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, and a capacitor structure located on the substrate and extending along a first direction, the first direction being parallel to the substrate; wherein the capacitor structure comprises a lower electrode layer, a capacitor dielectric layer and an upper electrode layer, the capacitor dielectric layer conformally covers at least part of the sidewall of the lower electrode layer extending along the first direction, the upper electrode layer covers the surface of the capacitor dielectric layer away from the lower electrode layer, and the lower electrode layer has a stepped topography, wherein the cross-sectional area of the lower electrode layer in at least part of the region perpendicular to the first direction decreases successively along the first direction. The embodiment of the present disclosure is at least beneficial to improving the capacitance of the capacitor structure while improving the integration density of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] As semiconductor structures continue to evolve and their critical dimensions shrink, limitations in lithography machines restrict further reduction. Therefore, achieving higher storage density chips on a single wafer remains a key research focus for many researchers and semiconductor professionals. In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Thus, the integration density of two-dimensional or planar semiconductor devices is determined by the area occupied by each memory cell. This integration density is significantly influenced by the technology used to form intricate patterns, limiting the potential for further increases in integration density. Consequently, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, with the increasing demand for capacitor structures with large capacitance, it is difficult to control the size of the capacitor structure while increasing the integration density of the semiconductor structure. As a result, it is difficult to achieve a balance between the layout space occupied by the capacitor structure in the semiconductor structure and the capacitance of the capacitor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to increase the capacitance of the capacitor structure while increasing the integration density of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate; a capacitor structure located on the substrate and extending along a first direction, the first direction being parallel to the substrate; wherein the capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer, the capacitor dielectric layer conformally covering at least a portion of the sidewalls of the lower electrode layer extending along the first direction, the upper electrode layer covering the surface of the capacitor dielectric layer away from the lower electrode layer, and the lower electrode layer having a stepped morphology, wherein along the first direction, at least a portion of the cross-sectional area of ​​the lower electrode layer perpendicular to the first direction decreases sequentially.

[0006] In some embodiments, the semiconductor structure further includes: active pillar structures arranged in an array along a second direction and a third direction; word lines and bit lines connected to the active pillar structures, the word lines surrounding a portion of the sidewalls of the active pillar structures extending in the first direction; wherein the word lines extend in the second direction and the bit lines extend in the third direction; or, the word lines extend in the third direction and the bit lines extend in the second direction; a plurality of capacitor structures arranged in an array along the second direction and the third direction, the capacitor structures being electrically connected to the active pillar structures one-to-one, the plurality of capacitor structures sharing the capacitor dielectric layer and the upper electrode layer, and the first direction, the second direction and the third direction intersecting each other.

[0007] In some embodiments, the semiconductor structure further includes: a support layer located on a portion of the sidewall of the lower electrode layer extending along the first direction; the lower electrode layer in contact with the support layer is a protrusion region; the cross-sectional area of ​​the protrusion region perpendicular to the first direction is a first area; and the cross-sectional area of ​​a step region in the lower electrode layer adjacent to the protrusion region perpendicular to the first direction is a second area, wherein the first area is larger than the second area.

[0008] In some embodiments, the support layer surrounds the sidewall of the protrusion region extending in the first direction, and the capacitor dielectric layer and the support layer together cover the sidewall of the lower electrode layer extending in the first direction.

[0009] In some embodiments, along the second direction, the protrusion region has opposing first and second sidewalls, and along the third direction, the protrusion region has opposing third and fourth sidewalls, the support layer is located on the first and second sidewalls, and the capacitor dielectric layer is located on the third and fourth sidewalls.

[0010] In some embodiments, the semiconductor structure further includes a transistor structure arranged along the first direction with the capacitor structure. The transistor structure includes a portion of an active pillar structure and a portion of a word line. The lower electrode layer includes a stepped region electrically connected to the transistor structure. The cross-sectional area of ​​the stepped region electrically connected to the transistor structure in the direction perpendicular to the first direction is equal to the first area.

[0011] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a capacitor structure extending along a first direction on the substrate, the first direction being parallel to the substrate; wherein the capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer, the capacitor dielectric layer conformally covering at least a portion of the sidewalls of the lower electrode layer extending along the first direction, the upper electrode layer covering the surface of the capacitor dielectric layer away from the lower electrode layer, and the lower electrode layer having a stepped morphology, wherein, along the first direction, at least a portion of the cross-sectional area of ​​the lower electrode layer decreases sequentially in the direction perpendicular to the first direction.

[0012] In some embodiments, the manufacturing method further includes: forming an active pillar structure arranged in an array along a second direction and a third direction; forming word lines and bit lines connected to the active pillar structure, the word lines surrounding a portion of the sidewalls of the active pillar structure extending in the first direction; the step of forming the capacitor structure includes: forming a plurality of capacitor structures arranged in an array along the second direction and the third direction, the capacitor structures being electrically connected to the active pillar structure one-to-one, the plurality of capacitor structures sharing the capacitor dielectric layer and the upper electrode layer, the first direction, the second direction and the third direction intersecting each other.

[0013] In some embodiments, the step of forming the lower electrode layer includes: forming a plurality of semiconductor pillars on the substrate, the plurality of semiconductor pillars being spaced apart along a second direction and extending along a first direction, the semiconductor pillars including a first semiconductor layer and a second semiconductor layer alternately stacked along a third direction upward; forming a dielectric layer, the dielectric layer at least filling the gap between adjacent semiconductor pillars; patterning the dielectric layer; etching a portion of the second semiconductor layer exposed by the dielectric layer to form a hole structure; forming an initial lower electrode layer in the hole structure, the initial lower electrode layer being spaced apart along the second direction and the third direction; removing a portion of the first semiconductor layer along the first direction using a first etching process; etching the exposed initial lower electrode layer using a second etching process; and alternately performing the first etching process and the second etching process multiple times to form the lower electrode layer.

[0014] In some embodiments, the step of forming the semiconductor pillars includes: forming a multilayer stacked structure on the substrate, the stacked structure including an initial first semiconductor layer and an initial second semiconductor layer alternately stacked upward along the third side; and patterning the stacked structure to form the plurality of semiconductor pillars.

[0015] In some embodiments, the semiconductor pillars include a first semiconductor pillar and a second semiconductor pillar adjacent to each other in the second direction; the step of patterning the dielectric layer includes: providing a first mask layer having a first opening extending along the first direction, and the first mask layer between adjacent first openings being opposite to the dielectric layer between the first semiconductor pillar and the second semiconductor pillar, the first opening being opposite to the dielectric layer located on the side of the first semiconductor pillar away from the second semiconductor pillar; etching the dielectric layer using the first mask layer as a mask, and the remaining dielectric layer being in contact with the first semiconductor layer.

[0016] In some embodiments, the step of patterning the dielectric layer includes: providing a second mask layer having a second opening extending along the second direction; and removing the dielectric layer opposite to the second opening.

[0017] In some embodiments, after patterning the dielectric layer and before forming the hole structure, the method further includes: etching the first semiconductor layer exposed by the dielectric layer and facing the second opening to form a first spacer; forming a support layer that at least fills the first spacer and surrounds a portion of the sidewall of the second semiconductor layer extending in the first direction; the step of forming the hole structure further includes: etching a portion of the remaining dielectric layer to expose a portion of the second semiconductor layer; in the step of forming the initial lower electrode layer, the support layer surrounds a portion of the sidewall of the initial lower electrode layer extending in the first direction.

[0018] In some embodiments, along the second direction, the semiconductor pillar includes opposing fifth and sixth sidewalls, and the step of patterning the dielectric layer includes: providing a third mask layer having a third opening spaced apart along the second direction and the first direction, and the third opening exposing a portion of the dielectric layer; removing the dielectric layer opposite to the third opening to form a second gap, the second gap exposing the fifth and sixth sidewalls.

[0019] In some embodiments, after patterning the dielectric layer and before forming the hole structure, the method further includes: forming a support layer that at least fills the second gap; the step of forming the hole structure further includes: etching a portion of the remaining dielectric layer to expose a portion of the second semiconductor layer; in the step of forming the initial lower electrode layer, the support layer is located on opposite sides of the initial lower electrode layer in the second direction.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] The lower electrode layer has a stepped morphology, and along the first direction, at least a portion of the lower electrode layer has a progressively decreasing cross-sectional area perpendicular to the first direction. Thus, the surface of the lower electrode layer extends not only along the first direction but also in a direction perpendicular to the first direction, which is beneficial for increasing the surface area of ​​the lower electrode layer without increasing its length along the first direction. Furthermore, since the capacitor dielectric layer conformally covers the lower electrode layer, the surface morphology of the capacitor dielectric layer is consistent with that of the lower electrode layer. Therefore, the facing area between the upper and lower electrode layers is mainly determined by the surface morphology of the lower electrode layer. Increasing the surface area of ​​the lower electrode layer is beneficial for increasing the facing area between the upper and lower electrode layers, thereby increasing the capacitance of the capacitor structure. Moreover, it is beneficial for increasing the capacitance of the capacitor structure without increasing its length in the first direction, which is beneficial for increasing the capacitance of the capacitor structure while simultaneously increasing the integration density of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A partial three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 2 Another partial three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 3 A top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0026] Figure 4 for Figure 3 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1.

[0027] Figure 5 Another top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0028] Figure 6 for Figure 5The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1.

[0029] Figure 7 A top view schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0030] Figure 8 for Figure 7 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1.

[0031] Figures 9 to 24 This is a partial cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0032] As can be seen from the background technology, the capacitance and integration density of capacitor structures in semiconductor structures need to be improved.

[0033] This disclosure provides a semiconductor structure and its manufacturing method. In the semiconductor structure, the lower electrode layer has a stepped morphology, and along a first direction, at least a portion of the lower electrode layer has a progressively decreasing cross-sectional area perpendicular to the first direction. Thus, the surface of the lower electrode layer extends not only along the first direction but also along a direction perpendicular to the first direction, which is beneficial for increasing the surface area of ​​the lower electrode layer without increasing its length along the first direction. Furthermore, the capacitor dielectric layer conformally covers the lower electrode layer, so the surface morphology of the capacitor dielectric layer is consistent with the surface morphology of the lower electrode layer. Therefore, the facing area between the upper and lower electrode layers is mainly determined by the surface morphology of the lower electrode layer. Increasing the surface area of ​​the lower electrode layer is beneficial for increasing the facing area between the upper and lower electrode layers, thereby increasing the capacitance of the capacitor structure. Moreover, it is beneficial for increasing the capacitance of the capacitor structure without increasing its length in the first direction, that is, it is beneficial for increasing the capacitance of the capacitor structure while simultaneously increasing the integration density of the semiconductor structure.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] This application provides a semiconductor structure according to one embodiment. The semiconductor structure provided by this application will be described in detail below with reference to the accompanying drawings. Figure 1A partial three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0036] Figure 2 Another partial three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 4 for Figure 3 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1. Figure 5 Another top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 6 for Figure 5 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1. Figure 7 A top view schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 8 for Figure 7 The diagram shows partial cross-sectional views of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1.

[0037] refer to Figures 1 to 8 The semiconductor structure includes: a substrate 100; a capacitor structure 101 located on the substrate 100 and extending along a first direction X, the first direction X being parallel to the substrate 100; wherein the capacitor structure 101 includes a lower electrode layer 111, a capacitor dielectric layer 121, and an upper electrode layer 131, the capacitor dielectric layer 121 conformally covering at least a portion of the sidewalls of the lower electrode layer 111 extending along the first direction X, the upper electrode layer 131 covering the surface of the capacitor dielectric layer 121 away from the lower electrode layer 111, and the lower electrode layer 111 having a stepped morphology, with at least a portion of the lower electrode layer 111 having a progressively decreasing cross-sectional area perpendicular to the first direction X along the first direction X.

[0038] It should be noted that conformal coverage refers to the same thickness of the film deposited on the covered structure. Therefore, if the capacitor dielectric layer 121 conformally covers at least part of the sidewalls of the lower electrode layer 111 extending along the first direction X, the surface morphology of the capacitor dielectric layer 121 is consistent with the surface morphology of the lower electrode layer 111 covered by the capacitor dielectric layer 121. Thus, the facing area between the upper electrode layer 131 and the lower electrode layer 111 is mainly determined by the surface morphology of the lower electrode layer 111.

[0039] The lower electrode layer 111 has a stepped morphology, and along the first direction X, at least a portion of the lower electrode layer 111 has a progressively smaller cross-sectional area perpendicular to the first direction X. Thus, the surface of the lower electrode layer 111 extends not only along the first direction X but also along a direction perpendicular to the first direction X. This is beneficial for increasing the surface area of ​​the lower electrode layer 111 without increasing its length along the first direction X, thereby increasing the facing area between the upper electrode layer 131 and the lower electrode layer 111. This allows for an increase in the capacitance of the capacitor structure 101 without increasing its length along the first direction X, which is beneficial for increasing the capacitance of the capacitor structure 101 while simultaneously increasing the integration density of the semiconductor structure.

[0040] It should be noted that the lower electrode layer 111 has a stepped morphology, and the embodiments in which the cross-sectional area of ​​at least a portion of the lower electrode layer 111 decreases sequentially in the direction perpendicular to the first direction X include at least the following two embodiments:

[0041] In some embodiments, reference Figures 1 to 4 Along the first direction X, the cross-sectional area of ​​the entire lower electrode layer 111 decreases sequentially in the direction perpendicular to the first direction X, that is, the change trend of the step morphology is consistent, so that the surface of the lower electrode layer 111 extends not only along the first direction X, but also in the direction perpendicular to the first direction X. This is beneficial to increase the surface area of ​​the lower electrode layer 111 without increasing the length of the lower electrode layer 111 along the first direction X, thereby increasing the facing area between the upper electrode layer 131 and the lower electrode layer 111.

[0042] It should be noted that, Figure 1 , Figure 2 as well as Figure 4 Taking the lower electrode layer 111 as an example, which is divided into three segments with successively decreasing cross-sectional areas in the first direction X, in practical applications, there is no restriction on the number of segments with different cross-sectional areas that the lower electrode layer 111 is divided into in the first direction X. It is only necessary to satisfy that the surface of the lower electrode layer 111 extends not only along the first direction X, but also along a direction perpendicular to the first direction X.

[0043] In other embodiments, reference is made to... Figures 5 to 8 In some regions, the cross-sectional area of ​​the lower electrode layer 111 in the direction perpendicular to the first direction X decreases sequentially. The cross-sectional area of ​​the lower electrode layer 111 in the direction perpendicular to the first direction X first decreases sequentially and then increases. This facilitates the formation of a lower electrode layer 111 with a stepped surface shape, which further increases the total area of ​​the lower electrode layer 111 extending in the direction perpendicular to the first direction X, thereby further increasing the surface area of ​​the lower electrode layer 111 and thus further increasing the facing area between the upper electrode layer 131 and the lower electrode layer 111. It should be noted that... Figure 3, Figure 5 and Figure 7 The uneven morphology of the lower electrode layer 111 is not visually shown, which is understandable. Figure 3 , Figure 5 and Figure 7 The surface morphology of the lower electrode layer 111 in contact with the support layer 105 shown is similar to that of the lower electrode layer 111 in the diagram. Figure 6 The surface morphology of the lower electrode layer 111, which is shown to be uneven, is basically consistent with that of the layer shown in the diagram. Further details will be provided later. Figures 2 to 8 The example shown will be explained in detail.

[0044] The following will combine Figures 1 to 8 The embodiments of this disclosure will be described in more detail.

[0045] In some embodiments, reference Figure 3 middle Figure 8 The upper electrode layer 131 can be a double-layer structure. Specifically, the upper electrode layer 131 may include a diffusion barrier layer 181 that conformally covers the surface of the capacitor dielectric layer 121 away from the lower electrode layer 111, and a conductive layer 191 that covers the surface of the diffusion barrier layer 181. The diffusion barrier layer 181 helps to prevent the diffusion of conductive material in the conductive layer 191 into the capacitor dielectric layer 121, thereby ensuring good insulation performance of the capacitor dielectric layer 121 and good conductivity performance of the conductive layer 191. In one example, the material of the diffusion barrier layer 181 can be titanium nitride, and the material of the conductive layer 191 can be polycrystalline silicon.

[0046] In some embodiments, reference Figure 1 and Figure 2 The semiconductor structure may further include: active pillar structures 102 arranged in an array along the second direction Y and the third direction Z; word lines 103 and bit lines 104 connected to the active pillar structures 102, the word lines 103 surrounding a portion of the sidewalls of the active pillar structures 102 extending along the first direction X. Multiple capacitor structures 101 (see reference) Figure 3 The capacitor structures 101 and active pillar structures 102 are arranged in an array along the second direction Y and the third direction Z, respectively. The capacitor structures 101 are electrically connected to each other in a one-to-one correspondence. Multiple capacitor structures 101 share a capacitor dielectric layer 121 and an upper electrode layer 131. The first direction X, the second direction Y and the third direction Z intersect each other.

[0047] The layout of the word line 103, bit line 104, and active column structure 102 includes at least the following two embodiments.

[0048] In some embodiments, reference Figure 1Word lines 103 extend along the second direction Y, and bit lines 104 extend along the third direction Z. It is understood that bit lines 104 can be spaced apart along the second direction Y; that is, multiple lower electrode layers 111 spaced apart along the second direction Y correspond to different bit lines 104, and multiple lower electrode layers 111 spaced apart along the second direction Y correspond to the same word line 103. This is beneficial for increasing the integration density of word lines 103, bit lines 104, and capacitor structures 101 in the semiconductor structure while reducing the control complexity of multiple memory cells in the semiconductor structure.

[0049] In other embodiments, reference is made to... Figure 2 Word lines 103 extend along the third direction Z, and bit lines 104 extend along the second direction Y. It is understood that bit lines 104 can be spaced apart along the third direction Z; that is, multiple lower electrode layers 111 spaced apart along the third direction Z correspond to different bit lines 104, and multiple lower electrode layers 111 spaced apart along the third direction Z correspond to the same word line 103. This is beneficial for increasing the integration density of word lines 103, bit lines 104, and capacitor structures 101 in the semiconductor structure while reducing the control complexity of multiple memory cells in the semiconductor structure.

[0050] In both embodiments described above, the active pillar structure 102 has two opposing ends in the first direction X, one end of which is in contact with the bit line 104, and the other end is in contact with the capacitor structure 101 (reference). Figure 3 The lower electrode layer 111 of the bit line 104 is contacted and connected. The bit line 104 has two opposite sides in the first direction X, and the two sides are respectively contacted and connected to different active pillar structures 102. Moreover, the word line 103 surrounds the active pillar structure 102. It can be understood that, along the first direction X, the active pillar structure 102 includes a first region, a channel region and a second region arranged in sequence. The word line 103 surrounds the sidewall of the channel region extending along the first direction X, and the word line 103 includes a gate dielectric layer and a gate surrounding the channel region. The gate dielectric layer may only surround the channel region, that is, the gate dielectric layer corresponds one-to-one with the active pillar structure 102. The gate extends along the second direction Y or the third direction Z, that is, the gate may correspond to multiple active pillar structures 102, so that the word line 103 extends as a whole along the second direction Y or the third direction Z.

[0051] It should be noted that, in order to clearly demonstrate the characteristics of the semiconductor structure provided in one embodiment of this disclosure, Figure 1 and Figure 2 Only capacitor structure 101 is shown in the diagram (reference). Figure 3 The lower electrode layer 111 in ) and Figure 1 and Figure 2 The dielectric layer separating adjacent identical structures is not shown in the diagram. Furthermore, Figures 1 to 8The example given is that the cross-sectional area of ​​the lower electrode layer 111 in the direction perpendicular to the first direction X of at least a portion of the active pillar structure 102 away from the bit line 104 decreases sequentially. In practical applications, it can also be that the cross-sectional area of ​​the lower electrode layer 111 in the direction perpendicular to the first direction X of at least a portion of the active pillar structure 102 close to the bit line 104 decreases sequentially.

[0052] In some embodiments, reference Figure 4 , Figure 6 and Figure 8 The number of capacitor structures 101 is determined by the number of lower electrode layers 111. Multiple capacitor structures 101 can share the capacitor dielectric layer 121 and the upper electrode layer 131. In practical applications, etching processes can also be used to make the capacitor dielectric layer 121 correspond one-to-one with the lower electrode layer 111, or the upper electrode layer 131 correspond one-to-one with the lower electrode layer 111.

[0053] It should be noted that, Figure 3 , Figure 5 and Figure 7 The upper electrode layer 131 covering the capacitor dielectric layer 121 and the lower electrode layer 111 are shown in perspective.

[0054] In some embodiments, reference Figures 5 to 8 The semiconductor structure may further include: a support layer 105, the support layer 105 being a portion of the sidewall of the lower electrode layer 111 extending along the first direction X, the lower electrode layer 111 being a raised region 141 in contact with the support layer 105, the cross-sectional area of ​​the raised region 141 perpendicular to the first direction X being a first area, and a portion of the stepped region 151 in the lower electrode layer 111 adjacent to the raised region 141 having a cross-sectional area perpendicular to the first direction X being a second area, the first area being larger than the second area.

[0055] It should be noted that, Figure 8 The morphology of the two sidewalls of the lower electrode layer 111 in the second direction Y is shown, and Figure 6 The surface morphology of the schematic lower electrode layer 111 is consistent. Furthermore, the portion of the stepped region 151 adjacent to the protrusion region 141 refers to the lower electrode layer 111 partially contacting and connected to the protrusion region 141, and the cross-sectional area of ​​this portion of the lower electrode layer 111 perpendicular to the first direction X is the second area. In practical applications, refer to... Figure 6When the number of support layers 105 is greater than one, the cross-sectional areas of some protruding areas 141 and the lower electrode layer 111 that is in contact with and connected to the protruding areas 141 are different in the direction perpendicular to the first direction X. The cross-sectional areas of other protruding areas 141 and the lower electrode layer 111 that is in contact with and connected to the protruding areas 141 can be the same in the direction perpendicular to the first direction X. The difference in the cross-sectional area of ​​the protruding areas 141 and the lower electrode layer 111 that is in contact with and connected to the protruding areas 141 can be designed according to the actual situation. That is, it is only necessary to satisfy that the cross-sectional area of ​​the protruding area 141 corresponding to one support layer 105 and a part of the step area 151 adjacent to the protruding area 141 are different in the direction perpendicular to the first direction X.

[0056] It is understandable that the raised region 141 and the stepped region 151 are adjacent in the first direction X, and the raised region 141 and the partially stepped region 151 have different cross-sectional areas in the direction perpendicular to the first direction X, thus forming a lower electrode layer 111 with an uneven surface morphology, thereby increasing the surface area of ​​the lower electrode layer 111. Furthermore, continuing to refer to... Figure 6 The lower electrode layer 111 may include two protruding regions 141 and three stepped regions 151, and the cross-sectional area of ​​some of the stepped regions 151 in the first direction X also varies. This is beneficial to further increase the total area of ​​the lower electrode layer 111 extending in the direction perpendicular to the first direction X, thereby further increasing the surface area of ​​the lower electrode layer 111. It can be understood that the division of the protruding regions 141 and the stepped regions 151 in the lower electrode layer 111 is related to the area of ​​the lower electrode layer 111 surrounded by the support layer 105. The protruding regions 141 are directly opposite to the support layer 105, that is, the part of the lower electrode layer 111 that is in contact with and connected to the support layer 105 is called the protruding region 141, and the remaining parts in the lower electrode layer 111 are all stepped regions 151.

[0057] Furthermore, due to the increased demand for capacitor structures 101 with large capacitance, the layout length of capacitor structures 101 in the first direction X is relatively large. A support layer 105 is added to the semiconductor structure so that the support layer 105 surrounds the lower electrode layer 111 extending along the first direction X to fix and support the long capacitor structure 101, prevent the capacitor structure 101 from collapsing, and improve the stability of the semiconductor structure.

[0058] It should be noted that, Figure 5 and Figure 6Taking a semiconductor structure including two support layers 105 as an example, in practical applications, the semiconductor structure may include only one support layer 105, which surrounds the sidewall of the lower electrode layer 111 in the middle part; or the semiconductor structure may include only three support layers 105, with multiple support layers 105 surrounding part of the sidewall of the lower electrode layer 111, and the multiple support layers 105 are evenly distributed along the layout length of the lower electrode layer 111 along the first direction X. That is, in one embodiment of this disclosure, the number and distribution of support layers 105 are not limited and can be adjusted according to actual needs.

[0059] The relative positional relationship between the support layer 105 and the lower electrode layer 111 includes at least the following two embodiments.

[0060] In some embodiments, reference Figure 5 and Figure 6 The support layer 105 surrounds the sidewall of the protrusion 141 extending along the first direction X, and the capacitor dielectric layer 121 and the support layer 105 together cover the sidewall of the lower electrode layer 111 extending along the first direction X.

[0061] It should be noted that, for ease of description, Figure 5 and Figure 6 Taking the lower electrode layer 111 as an example, which is a cuboid, in practical applications, the lower electrode layer 111 can also be a cylinder.

[0062] Understandable, Figure 5 and Figure 6 The lower electrode layer 111 shown in the diagram has four sidewalls extending along the first direction X. The sidewalls of the support layer 105 surrounding the protrusion 141 extending along the first direction X refer to the support layer 105 surrounding the protrusion 141 with four sidewalls extending along the first direction X.

[0063] It should be noted that the four sidewalls of the part of the protrusion 141 are all surrounded by the support layer 105, a certain section of the part of the protrusion 141 is surrounded by the support layer 105, and the remaining section of the protrusion 141 is surrounded by the capacitor dielectric layer 121.

[0064] In other embodiments, reference is made to... Figure 7 and Figure 8 Along the second direction Y, the width of the protrusion 141 remains constant, while along the third direction Z, the width of the protrusion 141 decreases. Along the second direction Y, the protrusion 141 has opposing first sidewalls a and second sidewalls b, and along the third direction Z, the protrusion 141 has opposing third sidewalls c and fourth sidewalls d. The support layer 105 is located on the first sidewalls a and second sidewalls b, and the capacitor dielectric layer 121 is located on the third sidewalls c and fourth sidewalls d.

[0065] It is understandable that the adjacent lower electrode layers 111 are electrically insulated from each other by the capacitor dielectric layer 121 and the support layer 105.

[0066] In both embodiments described above, adding a support layer 105 not only helps to further increase the surface area of ​​the lower electrode layer 111, thereby increasing the facing area between the upper electrode layer 131 and the lower electrode layer 111, but also helps to increase the proportion of the area with a larger cross-sectional area in the first direction X of the lower electrode layer 111. This helps to increase the overall volume of the lower electrode layer 111, thereby reducing the resistance of the lower electrode layer 111 itself, and thus helping to reduce the resistance between the lower electrode layer 111 and the active pillar structure 102 (see reference). Figure 1 The contact resistance between the two junctions is reduced to improve the electrical performance of the semiconductor junction.

[0067] In some embodiments, reference Figure 1 , Figure 2 and Figure 6 The semiconductor structure may further include: a transistor structure 106 arranged along the first direction X with the capacitor structure 101, the transistor structure 106 including a portion of the active pillar structure 102 and a portion of the word line 103, the lower electrode layer 111 including a step region 151 electrically connected to the transistor structure 106, the step region 151 electrically connected to the transistor structure 106 having a cross-sectional area in the direction perpendicular to the first direction X equal to the first area. It is understood that the stepped region 151 electrically connected to the transistor structure 106 refers to the stepped region 151 that is in contact with the active pillar structure 102 in the transistor structure 106. The cross-sectional area of ​​the stepped region 151 in the direction perpendicular to the first direction X is equal to the first area, which is beneficial to ensure that there is a large contact area between the transistor structure 106 and the lower electrode layer 111, and to reduce the contact resistance between the transistor structure 106 and the lower electrode layer 111. At the same time, by using the alternately arranged stepped regions 151 and the protrusion regions 141 to form the lower electrode layer 111, in order to increase the surface area of ​​the lower electrode layer 111, it is also beneficial to increase the overall volume of the lower electrode layer 111, so as to reduce the contact resistance of the lower electrode layer 111 itself.

[0068] It should be noted that, Figures 1 to 8 In the example where the lower electrode layer 111 is arranged at intervals along both the second direction Y and the third direction Z, in practical applications, the lower electrode layer 111 may be arranged at intervals only along the second direction Y or only along the third direction Z.

[0069] In summary, the lower electrode layer 111 has a stepped morphology, and along the first direction X, at least a portion of the lower electrode layer 111 has a progressively decreasing cross-sectional area perpendicular to the first direction X. Thus, the surface of the lower electrode layer 111 extends not only along the first direction X but also in a direction perpendicular to the first direction X, which is beneficial for increasing the surface area of ​​the lower electrode layer 111 without increasing its length along the first direction X. Furthermore, the capacitor dielectric layer 121 conformally covers the lower electrode layer 111, which is beneficial for increasing the facing area between the upper electrode layer 131 and the lower electrode layer 111, thereby increasing the capacitance of the capacitor structure 101. Moreover, it is beneficial for increasing the capacitance of the capacitor structure 101 without increasing its length in the first direction X, that is, it is beneficial for increasing the capacitance of the capacitor structure 101 while simultaneously increasing the integration density of the semiconductor structure.

[0070] Another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, used to prepare the semiconductor structure provided in the foregoing embodiments. The following will be combined with... Figures 1 to 24 A method for manufacturing a semiconductor structure according to another embodiment of this disclosure will be described in detail. Figures 9 to 24 This is a partial cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be described again here.

[0071] It should be noted that, Figures 9 to 24 Except Figure 12 , Figure 20 and Figure 23 The accompanying drawings are partial cross-sectional schematic diagrams of the semiconductor structure along the first cross-sectional direction AA1, the second cross-sectional direction BB1, and the third cross-sectional direction CC1. Figure 12 for Figure 11 A top view of the first mask layer in the semiconductor structure manufacturing method shown; Figure 20 for Figure 19 A top view of the second mask layer in the semiconductor structure manufacturing method shown; Figure 23 for Figure 22 A top view of the third mask layer in the semiconductor structure manufacturing method shown.

[0072] refer to Figures 9 to 24A method for manufacturing a semiconductor structure includes: providing a substrate 100; forming a capacitor structure 101 extending along a first direction X on the substrate 100, the first direction X being parallel to the substrate 100; wherein the capacitor structure 101 includes a lower electrode layer 111, a capacitor dielectric layer 121, and an upper electrode layer 131, the capacitor dielectric layer 121 conformally covering at least a portion of the sidewalls of the lower electrode layer 111 extending along the first direction X, the upper electrode layer 131 covering the surface of the capacitor dielectric layer 121 away from the lower electrode layer 111, and the lower electrode layer 111 having a stepped morphology, with at least a portion of the lower electrode layer 111 having a progressively decreasing cross-sectional area perpendicular to the first direction X along the first direction X. This allows for an increase in the surface area of ​​the lower electrode layer 111 without increasing its length along the first direction X.

[0073] In some embodiments, reference Figure 1 and Figure 2 The method for manufacturing a semiconductor structure may further include: forming an active pillar structure 102 arranged in an array along a second direction X and a third direction Y; forming a word line 103 and a bit line 104 connected to the active pillar structure 102, wherein the word line 103 surrounds a portion of the sidewall of the active pillar structure 102 extending along a first direction X.

[0074] It should be noted that the layout of the word line 103, bit line 104, and active column structure 102 includes at least the following two embodiments: In some embodiments, refer to Figure 1 Word line 103 extends along the second direction Y, and bit line 104 extends along the third direction Z; in other embodiments, reference is made to... Figure 2 The character line 103 extends along the third direction Z, and the bit line 104 extends along the second direction Y.

[0075] It should be noted that the present disclosure does not limit the formation order of the word line 103, the bit line 104, and the active pillar structure 102, nor the specific formation method of the three.

[0076] refer to Figures 3 to 24 The step of forming the capacitor structure 101 may include: forming a plurality of capacitor structures 101 arranged in an array along the second direction Y and the third direction Z, wherein each capacitor structure 101 is electrically connected to an active pillar structure 102 in a one-to-one correspondence, and the plurality of capacitor structures 101 share a capacitor dielectric layer 121 and an upper electrode layer 131, wherein the first direction X, the second direction Y, and the third direction Z intersect each other in pairs. In practical applications, an etching process can also be used to make the capacitor dielectric layer 121 correspond one-to-one with the lower electrode layer 111 and / or the upper electrode layer 131 correspond one-to-one with the lower electrode layer 111.

[0077] In some embodiments, forming the lower electrode layer 111 may include the following steps:

[0078] refer to Figures 9 to 10 A plurality of semiconductor pillars 107 are formed on a substrate 100. The semiconductor pillars 107 are spaced apart along a second direction Y and extend along a first direction X. Each semiconductor pillar 107 includes a first semiconductor layer 117 and a second semiconductor layer 127 alternately stacked along a third direction Z. In one example, the first semiconductor layer 117 may be made of silicon germanide, and the second semiconductor layer 127 may be made of silicon. The second semiconductor layer 127 may be doped with N-type ions or P-type ions. The N-type ions may be at least one of arsenic ions, phosphorus ions, or antimony ions, and the P-type ions may be at least one of boron ions, indium ions, or gallium ions.

[0079] In some embodiments, the step of forming the semiconductor pillar 107 may include: referencing Figure 9 A multilayer stacked structure 137 is formed on a substrate 100, the stacked structure 137 including an initial first semiconductor layer 147 and an initial second semiconductor layer 157 alternately stacked along the third direction Z; in conjunction with reference Figure 9 and Figure 10 A patterned stacked structure 137 is formed to create multiple semiconductor pillars 107.

[0080] In some embodiments, the step of graphically stacking structure 137 may include: referring to Figure 9 A fourth mask layer 179 with a fourth opening 169 is formed on the top surface of the stacked structure 137 away from the substrate 100. The fourth opening 169 extends along the first direction X and is spaced apart along the second direction Y. Using the fourth mask layer 179 as a mask, the stacked structure 137 is etched through the fourth opening 169 to form a plurality of semiconductor pillars 107 spaced apart along the second direction Y and extending along the first direction X. The spacing between the fourth opening 169 and the adjacent semiconductor pillars 107 corresponds.

[0081] It should be noted that the transistor structure 106 (reference) is formed Figure 1 The step of forming the semiconductor pillar 107 is performed after the semiconductor pillar 107 is formed. The manufacturing method provided in another embodiment of this disclosure does not limit the specific process for forming the transistor structure 106. In addition, the step of forming the bit line 104 can be performed after the semiconductor pillar 107 is formed or before the semiconductor pillar 107 is formed. The manufacturing method provided in another embodiment of this disclosure does not limit the order in which the bit line 104 is formed and the semiconductor pillar 107 is formed.

[0082] refer to Figure 11 A dielectric layer 108 is formed, which at least fills the gap between adjacent semiconductor pillars 107. Figure 11In one example, the dielectric layer 108 not only fills the gaps between adjacent semiconductor pillars 107, but also lies on the top surface of the semiconductor pillars 107 away from the substrate 100, meaning the top surface of the dielectric layer 108 away from the substrate 100 is higher than the top surface of the semiconductor pillars 107 away from the substrate 100. In practical applications, the dielectric layer 108 may only fill the gaps between adjacent semiconductor pillars 107, meaning the top surface of the dielectric layer 108 away from the substrate 100 is flush with the top surface of the semiconductor pillars 107 away from the substrate 100. In one example, the material of the dielectric layer 108 may be silicon oxide.

[0083] refer to Figures 11 to 13 as well as Figures 19 to 24 The patterned dielectric layer 108 serves several purposes. One is to expose at least a portion of the sidewalls of the semiconductor pillar 107 extending Z-direction, while simultaneously forming a support structure for the subsequent lower electrode layer 111. This support structure helps prevent the lower electrode layer 111 from collapsing during the subsequent formation of the capacitor structure 101. The specific steps of the patterned dielectric layer 108 will be explained in detail later.

[0084] refer to Figures 11 to 13 The portion of the second semiconductor layer 127 exposed by etching the dielectric layer 108 is used to form a hole structure 118.

[0085] Reference Figure 13 and Figure 14 An initial lower electrode layer 161 is formed in the hole structure 118, and the initial lower electrode layer 161 is arranged at intervals along the second direction Y and the third direction Z.

[0086] In some embodiments, after forming the initial lower electrode layer 161 and before etching the initial lower electrode layer 161, the method for manufacturing the semiconductor structure may further include: referencing Figure 14 An isolation layer 128 is formed, which fills the remaining void structure 118.

[0087] refer to Figure 15 The first semiconductor layer 117, a portion of its length in the first direction X, is removed using a first etching process.

[0088] It should be noted that both the dielectric layer 108 and the insulating layer 128 are located within a portion of the spacing between adjacent initial lower electrode layers 161, and Figure 5In the example shown, the dielectric layer 108 is also located on the top surface of the initial lower electrode layer 161 away from the substrate 100. During the step of removing a portion of the first semiconductor layer 117 using the first etching process, the dielectric layer 108 and the isolation layer 128 opposite to the removed first semiconductor layer 117 are also removed to expose all sidewalls of the initial lower electrode layer 161 extending along the first direction X. It is understood that the dielectric layer 108 and the isolation layer 128 opposite to the removed first semiconductor layer 117 refer to the dielectric layer 108 whose orthogonal projection on the substrate 100 coincides with the orthogonal projection of the removed first semiconductor layer 117 on the substrate 100, and the isolation layer 128 whose orthogonal projection on the substrate 100 coincides with the orthogonal projection of the removed first semiconductor layer 117 on the substrate 100.

[0089] Reference Figure 15 and Figure 16 The exposed initial lower electrode layer 161 is etched using a second etching process to form an initial lower electrode layer 161 with a smaller cross-sectional area in a portion of the region perpendicular to the first direction X.

[0090] refer to Figure 15 refer to Figure 18 The first and second etching processes are alternately performed multiple times to form the lower electrode layer 111.

[0091] It should be noted that in each step of the first etching process that removes a portion of the first semiconductor layer 117 along the first direction X, the dielectric layer 108 and the isolation layer 128 opposite to the removed first semiconductor layer 117 are also removed simultaneously. It can be understood that one function of the first etching process is to expose all sidewalls of a portion of the initial lower electrode layer 161 extending along the first direction X, facilitating subsequent etching of this exposed portion of the initial lower electrode layer 161 in the second etching process. Each second etching process etches the sidewalls of the initial lower electrode layer 161 exposed by the corresponding first etching process, thereby reducing the cross-sectional area of ​​this portion of the initial lower electrode layer 161 perpendicular to the first direction X. This facilitates the formation of a lower electrode layer 111 with a stepped morphology, and along the first direction X, at least a portion of the lower electrode layer 111 has a progressively decreasing cross-sectional area perpendicular to the first direction X.

[0092] In addition, refer to Figure 15 The first etching process is performed to remove a portion of the first semiconductor layer 117 along the first direction X; (Refer to...) Figure 16 The first second etching process is performed to etch the exposed initial lower electrode layer 161, forming an initial lower electrode layer 161 with a smaller cross-sectional area in a portion of the region perpendicular to the first direction X; Reference Figure 17 Perform a second first etching process and a second second second etching process; refer to Figure 18A third first etching process is performed to form the lower electrode layer 111, exposing the entire sidewall of the lower electrode layer 111 extending along the first direction X, facilitating the subsequent formation of the capacitor dielectric layer and the upper electrode layer on the entire sidewall of the lower electrode layer 111 extending along the first direction X. It is understood that... Figures 15 to 18 The manufacturing method of the lower electrode layer 111 shown involves three first etching processes and two second etching processes to form the lower electrode layer 111. In practical applications, there is no limit to the number of first etching processes and the number of second etching processes. It is only necessary that the final lower electrode layer 111 has a stepped morphology and that the cross-sectional area of ​​at least a portion of the lower electrode layer 111 decreases sequentially along the first direction X in the direction perpendicular to the first direction X.

[0093] It should be noted that after the first etching process and the first second etching process, the initial lower electrode layer 161 exposed by the second first etching process can also be etched by the second first etching process and / or the second second etching process. Similarly, each subsequent first etching process and / or subsequent second etching process can further etch the initial lower electrode layer 161 exposed by the previous first etching process.

[0094] The steps of the graphical medium layer 108 are described in detail below through three embodiments.

[0095] In some embodiments, reference Figure 11 and Figure 12 The semiconductor pillars 107 may include a first semiconductor pillar 167 and a second semiconductor pillar 177 that are adjacent to each other in the second direction X; the step of patterning the dielectric layer 108 may include: providing a first mask layer 119 having a first opening 109 extending along the first direction X, and the first mask layer 119 between adjacent first openings 109 being directly opposite to the dielectric layer 108 between the first semiconductor pillars 167 and the second semiconductor pillars 177, and the first opening 109 being directly opposite to the dielectric layer 108 located on the side of the first semiconductor pillar 167 away from the second semiconductor pillar 177.

[0096] It should be noted that the alignment of the first mask layer 119 between adjacent first openings 109 with the dielectric layer 108 between the first semiconductor pillar 167 and the second semiconductor pillar 177 means that the orthogonal projection of the dielectric layer 108 between the first semiconductor pillar 167 and the second semiconductor pillar 177 onto the substrate 100 lies within the orthogonal projection of the first mask layer 119 between adjacent first openings 109 onto the substrate 100. Similarly, the alignment of the first opening 109 with the dielectric layer 108 located on the side of the first semiconductor pillar 167 away from the second semiconductor pillar 177 means that the orthogonal projection of the dielectric layer 108 on the side of the first semiconductor pillar 167 away from the second semiconductor pillar 177 onto the substrate 100 lies within the orthogonal projection of the first opening 109 onto the substrate 100. Furthermore, one first opening 109 is aligned with the dielectric layer 108 located on the side of the first semiconductor pillar 167 away from the second semiconductor pillar 177, and another first opening 109 is aligned with the dielectric layer 108 located on the side of the second semiconductor pillar 177 away from the first semiconductor pillar 167.

[0097] It is understood that there are two semiconductor pillars 107, namely the first semiconductor pillar 167 and the second semiconductor pillar 177, between adjacent first openings 109. The dielectric layer 108 located between the first semiconductor pillar 167 and the second semiconductor pillar 177 will be retained as a support structure that supports the initial lower electrode layer 161 in the step of etching the initial lower electrode layer 161 to form the lower electrode layer 111.

[0098] Reference Figure 11 and Figure 13 The dielectric layer 108 is etched using the first mask layer 119 as a mask, and the remaining dielectric layer 108 is in contact with the first semiconductor layer 117. It is understood that, in one example, during the step of etching the dielectric layer 108 using the first mask layer 119 as a mask, the second semiconductor layer 127 in the semiconductor pillar 107 is also removed. To prevent the collapse of the first semiconductor layer 117, the remaining dielectric layer 108 can serve as a support structure for the first semiconductor layer 117, and also facilitates support for the initial lower electrode layer in the subsequent step of etching the initial lower electrode layer to form the lower electrode layer, as well as for the formed lower electrode layer. In another example, the second semiconductor layer 127 exposed by the remaining dielectric layer 108 can be etched after etching the dielectric layer 108 using the first mask layer 119 as a mask.

[0099] In other embodiments, reference is made to... Figures 19 to 21 The graphical media layer 108 may include the following steps:

[0100] refer to Figure 19 and Figure 20 A second mask layer 139 is provided having a second opening 129 extending along a second direction Y; in conjunction with a reference Figure 19 and Figure 21 Remove the dielectric layer 108 that is directly opposite the second opening 129. It should be noted that the dielectric layer 108 that is directly opposite the second opening 129 refers to the dielectric layer 108 whose orthogonal projection on the substrate 100 coincides with the orthogonal projection of the second opening 129 on the substrate 100.

[0101] In some embodiments, after the patterned medium layer 108, the hole structure 118 (reference) is formed. Figure 13 Previously, semiconductor structure manufacturing methods could also include: (continued reference) Figure 19 and Figure 21 The dielectric layer 108 is etched to expose the first semiconductor layer 117, which is directly opposite the second opening 129, to form a first spacer. A support layer 105 is formed, which at least fills the first spacer and surrounds a portion of the sidewall of the second semiconductor layer 127 extending in the first direction X. It should be noted that the first semiconductor layer 117 directly opposite the second opening 129 refers to the first semiconductor layer 117 whose orthogonal projection on the substrate 100 coincides with the orthogonal projection of the second opening 129 on the substrate 100.

[0102] Understandably, reference Figure 21 A support layer 105 surrounds four sidewalls of a portion of the second semiconductor layer 127 extending along the first direction X, and a support layer 105 surrounds a portion of the sidewalls of a plurality of second semiconductor layers 127 arranged in an array along the first direction X and the second direction Y.

[0103] Reference Figure 21 , Figure 5 and Figure 6 This forms a cavity structure 118 (reference) Figure 13 The steps may further include: etching a portion of the remaining dielectric layer 108 to expose a portion of the second semiconductor layer 127. It is understood that etching the remaining dielectric layer 108 may involve removing all of the dielectric layer 108 using the support layer 105 as a mask, followed by removing the second semiconductor layer 127 to form a hole structure 118; forming an initial lower electrode layer 161 (see reference). Figure 14 In the step of removing the second semiconductor layer 127 to form the hole structure 118, the support layer 105 surrounds a portion of the sidewall of the initial lower electrode layer 161 extending in the first direction X. It can be understood that in the step of removing the second semiconductor layer 127 to form the hole structure 118, the support layer 105 is used to support the first semiconductor layer 117 to prevent the collapse of the first semiconductor layer 117, and also to support the initial lower electrode layer 161 in the subsequent step of etching the initial lower electrode layer 161 to form the lower electrode layer 111, as well as to support the formed lower electrode layer 111.

[0104] It should be noted that the step of etching the initial lower electrode layer 161 to form the lower electrode layer 111 is basically the same as in the previous embodiment, and will not be described in detail here. The difference is that the support layer 105 is not removed in the first and second etching processes. That is, in the step of etching the exposed initial lower electrode layer 161 using the second etching process, the initial lower electrode layer 161 surrounded by the support layer 105 will not be etched, which is beneficial for forming such a lower electrode layer 111. Figure 6 The lower electrode layer 111 has an uneven surface morphology.

[0105] In some other embodiments, reference is made to Figures 22 to 24 Along the second direction Y, the semiconductor pillar 107 includes opposing fifth sidewalls e and sixth sidewalls f. The step of patterning the dielectric layer 108 may include: providing a third mask layer 159 having a third opening 149 spaced apart along the second direction Y and the first direction X, with the third opening 149 exposing a portion of the dielectric layer 108; removing the dielectric layer 108 directly opposite the third opening 149 to form a second gap, the second gap exposing the fifth sidewalls e and the sixth sidewalls f. It should be noted that the dielectric layer 108 directly opposite the third opening 149 refers to the dielectric layer 108 whose orthogonal projection on the substrate 100 coincides with the orthogonal projection of the third opening 149 on the substrate 100. Thus, the first semiconductor layer 117 spaced apart along the third direction Z is not removed.

[0106] In some embodiments, after the patterned medium layer 108, the hole structure 118 (reference) is formed. Figure 13 Previously, semiconductor structure manufacturing methods could also include: (continued reference) Figures 22 to 24 A support layer 105 is formed, which at least fills the second spacer. It is understood that the support layer 105 is located on the fifth sidewall e and the sixth sidewall f. The support layer 105 separates the second semiconductor layer 127 arranged along the second direction Y. The first semiconductor layer 117 separates the second semiconductor layer 127 arranged along the third direction Z.

[0107] Reference Figure 24 , Figure 5 and Figure 6 This forms a cavity structure 118 (reference) Figure 13 It may also include: etching a portion of the remaining dielectric layer 108 to expose a portion of the second semiconductor layer 127. It is understood that etching the remaining dielectric layer 108 may involve removing all of the dielectric layer 108 using the support layer 105 as a mask, followed by removing the second semiconductor layer 127 to form a hole structure 118; forming an initial lower electrode layer 161 (see reference). Figure 14In the step of removing the second semiconductor layer 127 to form the hole structure 118, the support layer 105 is located on opposite sides of the initial lower electrode layer 161 in the second direction Y. It is understood that in the step of removing the second semiconductor layer 127 to form the hole structure 118, the support layer 105 is used to support the first semiconductor layer 117 to prevent the collapse of the first semiconductor layer 117, and also to support the initial lower electrode layer 161 in the subsequent step of etching the initial lower electrode layer 161 to form the lower electrode layer 111, as well as to support the formed lower electrode layer 111.

[0108] It should be noted that the steps of etching the initial lower electrode layer 161 to form the lower electrode layer 111 are basically the same as those in the previous embodiment, and will not be repeated here. The difference is that the support layer 105 will not be removed in the first etching process and the second etching process. That is, when the first etching process is performed, the two opposite sides of the initial lower electrode layer 161 in the second direction Y will be protected from etching by the support layer 105, and the two opposite sides of the initial lower electrode layer 161 in the third direction Z will be exposed. When the second etching is performed, the two opposite sides of the initial lower electrode layer 161 in the third direction Z will be etched to reduce the cross-sectional area of ​​the initial lower electrode layer 161 in the direction perpendicular to the first direction X.

[0109] In summary, in the semiconductor structure manufacturing method provided by another embodiment of this disclosure, it is advantageous to form a lower electrode layer 111 with a stepped morphology, and along the first direction X, at least a portion of the lower electrode layer 111 has a progressively decreasing cross-sectional area perpendicular to the first direction X. This is advantageous in increasing the surface area of ​​the lower electrode layer 111 without increasing the length of the lower electrode layer 111 along the first direction X. Furthermore, the capacitor dielectric layer 121 conformally covers the lower electrode layer 111, which is advantageous in increasing the facing area between the upper electrode layer 131 and the lower electrode layer 111. This is advantageous in increasing the capacitance of the capacitor structure 101, and also advantageous in increasing the capacitance of the capacitor structure 101 without increasing the length of the capacitor structure 101 in the first direction X. In other words, it is advantageous in increasing the capacitance of the capacitor structure 101 while increasing the integration density of the semiconductor structure.

[0110] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A capacitor structure located on the substrate and extending along a first direction, the first direction being parallel to the substrate; The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer. The capacitor dielectric layer conformally covers at least a portion of the sidewalls of the lower electrode layer extending along the first direction. The upper electrode layer covers the surface of the capacitor dielectric layer away from the lower electrode layer. The lower electrode layer has a stepped morphology. The lower electrode layer is formed by performing multiple etching processes on an initial lower electrode layer so that the cross-sectional area of ​​the lower electrode layer perpendicular to the first direction decreases sequentially along the first direction.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: Active column structures arranged in an array along the second and third directions; Word lines and bit lines connected to the active pillar structure, wherein the word lines surround a portion of the sidewall of the active pillar structure extending in the first direction; Wherein, the word line extends along the second direction and the bit line extends along the third direction; or, the word line extends along the third direction and the bit line extends along the second direction. Multiple capacitor structures are arranged in an array along the second direction and the third direction. Each capacitor structure is electrically connected to an active pillar structure. The multiple capacitor structures share the capacitor dielectric layer and the upper electrode layer. The first direction, the second direction, and the third direction intersect each other.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, Also includes: A support layer is located on a portion of the sidewall of the lower electrode layer extending along the first direction. The lower electrode layer that is in contact with the support layer is a raised area. The cross-sectional area of ​​the raised area perpendicular to the first direction is a first area. A portion of the stepped area in the lower electrode layer adjacent to the raised area has a cross-sectional area perpendicular to the first direction, which is a second area. The first area is larger than the second area.

4. The semiconductor structure as described in claim 3, characterized in that, The support layer surrounds the sidewall of the protruding area extending in the first direction, and the capacitor dielectric layer and the support layer together cover the sidewall of the lower electrode layer extending in the first direction.

5. The semiconductor structure as described in claim 3, characterized in that, Along the second direction, the protruding area has opposing first and second sidewalls, and along the third direction, the protruding area has opposing third and fourth sidewalls, the support layer is located on the first and second sidewalls, and the capacitor dielectric layer is located on the third and fourth sidewalls.

6. The semiconductor structure as described in claim 3, characterized in that, The semiconductor structure further includes: a transistor structure arranged along the first direction with the capacitor structure, the transistor structure including a portion of an active pillar structure and a portion of a word line, the lower electrode layer including the step region electrically connected to the transistor structure, and the cross-sectional area of ​​the step region electrically connected to the transistor structure in the direction perpendicular to the first direction being equal to the first area.

7. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base; A capacitor structure extending along a first direction is formed on the substrate, the first direction being parallel to the substrate; The capacitor structure includes a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer. The capacitor dielectric layer conformally covers at least a portion of the sidewalls of the lower electrode layer extending along the first direction. The upper electrode layer covers the surface of the capacitor dielectric layer away from the lower electrode layer, and the lower electrode layer has a stepped morphology. The steps for forming the lower electrode layer include: Forming the initial lower electrode layer; The initial lower electrode layer is formed by multiple etching processes, so that the cross-sectional area of ​​the lower electrode layer perpendicular to the first direction decreases sequentially along the first direction.

8. The manufacturing method as described in claim 7, characterized in that, Also includes: An active column structure is formed by arranging columns along the second and third directions. A word line and a bit line are formed to connect with the active pillar structure, the word line surrounding a portion of the sidewall of the active pillar structure extending in the first direction; The steps for forming the capacitor structure include: Multiple capacitor structures are formed and arranged in an array along the second direction and the third direction. Each capacitor structure is electrically connected to an active pillar structure. The multiple capacitor structures share the capacitor dielectric layer and the upper electrode layer. The first direction, the second direction and the third direction intersect each other.

9. The manufacturing method as described in claim 8, characterized in that, The steps for forming the lower electrode layer include: A plurality of semiconductor pillars are formed on the substrate, the plurality of semiconductor pillars are spaced apart along the second direction and extend along the first direction, and the semiconductor pillars include a first semiconductor layer and a second semiconductor layer that are alternately stacked upward along the third direction; A dielectric layer is formed, wherein the dielectric layer at least fills the space between adjacent semiconductor pillars; Graphicalize the medium layer; The portion of the second semiconductor layer exposed by the dielectric layer is etched to form a hole structure; The initial lower electrode layer is formed in the cavity structure, and the initial lower electrode layer is arranged at intervals along the second direction and the third direction; The first semiconductor layer is removed along a portion of its length in the first direction using a first etching process; The exposed initial lower electrode layer is etched using a second etching process; The first etching process and the second etching process are performed alternately multiple times to form the lower electrode layer.

10. The manufacturing method as described in claim 9, characterized in that, The step of forming the semiconductor pillars includes: forming a multilayer stacked structure on the substrate, the stacked structure including an initial first semiconductor layer and an initial second semiconductor layer alternately stacked upward along the third side; and patterning the stacked structure to form the plurality of semiconductor pillars.

11. The manufacturing method as described in claim 9, characterized in that, The semiconductor pillars include a first semiconductor pillar and a second semiconductor pillar that are adjacent to each other in the second direction; The steps of graphically representing the dielectric layer include: A first mask layer is provided having a first opening extending along the first direction, and the first mask layer between adjacent first openings is opposite to the dielectric layer between the first semiconductor pillar and the second semiconductor pillar, wherein the first opening is opposite to the dielectric layer located on the side of the first semiconductor pillar away from the second semiconductor pillar; The dielectric layer is etched using the first mask layer as a mask, and the remaining dielectric layer is in contact with the first semiconductor layer.

12. The manufacturing method as described in claim 9, characterized in that, The steps of graphically representing the dielectric layer include: A second mask layer is provided having a second opening extending along the second direction; Remove the medium layer that is directly opposite the second opening.

13. The manufacturing method as described in claim 12, characterized in that, After the dielectric layer is patterned, but before the hole structure is formed, the method further includes: The first semiconductor layer, which is exposed by etching the dielectric layer and is directly opposite the second opening, is used to form a first gap; A support layer is formed, the support layer at least filling the first gap, and the support layer surrounds a portion of the sidewall of the second semiconductor layer extending in the first direction; The step of forming the hole structure further includes: etching a portion of the remaining dielectric layer to expose a portion of the second semiconductor layer; In the step of forming the initial lower electrode layer, the support layer surrounds a portion of the sidewall of the initial lower electrode layer extending in the first direction.

14. The manufacturing method as described in claim 9, characterized in that, Along the second direction, the semiconductor pillar includes opposing fifth and sixth sidewalls, and the step of patterning the dielectric layer includes: A third mask layer is provided, the third opening being spaced apart along the second direction and the first direction, and the third opening exposing a portion of the dielectric layer; The medium layer opposite the third opening is removed to form a second gap, which exposes the fifth and sixth sidewalls.

15. The manufacturing method as described in claim 14, characterized in that, After the dielectric layer is patterned and before the cavity structure is formed, the method further includes: forming a support layer that at least fills the second gap; The step of forming the hole structure further includes: etching a portion of the remaining dielectric layer to expose a portion of the second semiconductor layer; In the step of forming the initial lower electrode layer, the support layer is located on both sides of the initial lower electrode layer opposite to each other in the second direction.

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