Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

This disclosure relates to a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes: a substrate; a first semiconductor pillar having a first channel region, a source region, and a drain region; the first semiconductor pillar in the first channel region surrounding the side of a first word line; a first bit line electrically connected to the source region of the first semiconductor pillar; two second semiconductor pillars and a gate located between the two second semiconductor pillars, each second semiconductor pillar having at least one source / drain region and a second channel region, the second channel region being disposed towards the gate, one end of the gate being electrically connected to the drain region of the first semiconductor pillar, the first semiconductor pillar, the gate, and the second semiconductor pillars being parallel to the substrate; a second word line and a second bit line being electrically connected to the source / drain region of at least one of the two second semiconductor pillars, respectively, the first word line, the second word line, and the second bit line being perpendicular to the substrate, and the first bit line being parallel to the substrate. This disclosure is beneficial for reducing the size of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] As the integration density of dynamic memory continues to increase, higher requirements are being placed on the arrangement and size of transistors in the dynamic memory array structure.

[0003] To further improve the integration density of semiconductor structures, 2TOC type DRAM (Dynamic Random Access Memory) cells are being researched. A 2TOC DRAM cell consists of two transistors and does not include a capacitor; instead, the gate of one of the two transistors replaces the storage function of the memory cell.

[0004] However, current semiconductor structures used to form 2T0C DRAM cells suffer from the problem of large semiconductor structure size. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure, which at least helps to reduce the size of the semiconductor structure.

[0006] This disclosure provides a semiconductor structure, including: a substrate; a first semiconductor pillar located on the substrate, the first semiconductor pillar having a first channel region and source and drain regions located on both sides of the first channel region; a first word line, the first semiconductor pillar in the first channel region being disposed around the side of the first word line; a first bit line, the first bit line being electrically connected to the source region of the first semiconductor pillar; two second semiconductor pillars located on the substrate and a gate located between the two second semiconductor pillars, the second semiconductor pillars having at least one source / drain region and a second channel region, the second channel region being disposed towards the gate, one end of the gate being electrically connected to the drain region of the first semiconductor pillar, wherein the first semiconductor pillar, the gate, and the second semiconductor pillars are disposed parallel to the substrate; a second word line and a second bit line, the second word line and the second bit line being electrically connected to the source / drain region of at least one of the two second semiconductor pillars, wherein the first word line, the second word line, and the second bit line are perpendicular to the substrate, and the first bit line is disposed parallel to the substrate.

[0007] In some embodiments, the substrate surface is provided with a plurality of first semiconductor pillars and second semiconductor pillars stacked in a direction away from the substrate, wherein the first channel regions of the plurality of stacked first semiconductor pillars surround the side of the same first word line, and the second word line and the second bit line are electrically connected to the source and drain regions of at least one of the two columns of stacked second semiconductor pillars.

[0008] In some embodiments, the second semiconductor pillar has one source / drain region, the source / drain region and the second channel region are arranged along a first direction, the second word line and the second bit line are electrically connected to the source / drain regions of the two second semiconductor pillars respectively, and the first direction is the direction in which the second semiconductor pillar points to the gate.

[0009] In some embodiments, the second semiconductor pillar has two source / drain regions, and the two source / drain regions are located on opposite sides of the second channel region in a second direction. The second word line and the second bit line are electrically connected to the two source / drain regions of the same second semiconductor pillar, and the second direction is the extension direction of the second semiconductor pillar.

[0010] In some embodiments, the first semiconductor pillar is made of silicon, and the second semiconductor pillar is made of an amorphous material.

[0011] In some embodiments, the substrate surface is provided with a plurality of first semiconductor pillars spaced apart along a third direction, the third direction being parallel to the substrate surface, and the first bit line covers the side surface of the first semiconductor pillar of each source region in the first semiconductor pillars arranged along the third direction.

[0012] In some embodiments, the gate includes a metal silicide layer and a metal layer, the metal silicide layer being disposed toward the first semiconductor pillar and electrically connected to the drain region of the first semiconductor pillar.

[0013] Accordingly, this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a first semiconductor pillar on the substrate, the first semiconductor pillar having a first channel region and a source region and a drain region located on both sides of the first channel region; forming a first word line, the first semiconductor pillar in the first channel region being disposed around the side of the first word line; forming a first bit line, the first bit line being electrically connected to the source region of the first semiconductor pillar; forming two second semiconductor pillars and a gate located between the two second semiconductor pillars on the substrate, the second semiconductor pillar having at least one source / drain region and a second channel region, the second channel region being disposed toward the gate, one end of the gate being electrically connected to the drain region of the first semiconductor pillar, wherein the first semiconductor pillar, the gate, and the second semiconductor pillars are disposed parallel to the substrate; forming a second word line and a second bit line, the second word line and the second bit line being electrically connected to the source / drain region of at least one of the two second semiconductor pillars, wherein the first word line, the second word line, and the second bit line are perpendicular to the substrate, and the first bit line is disposed parallel to the substrate.

[0014] In some embodiments, the number of first semiconductor pillars is multiple, and the multiple first semiconductor pillars are stacked. The method for forming the first word line includes: forming stacked initial semiconductor pillars on the substrate, a portion of the initial semiconductor pillars having a first channel region and a source region and a drain region located on both sides of the first channel region; performing an etching process on the initial semiconductor pillars in the first channel region to form a first via, the first via penetrating a portion of the first channel region of the multiple stacked initial semiconductor pillars and exposing the substrate, the remaining first channel region, the drain region and the source region constituting the first semiconductor pillar; and forming the first word line in the first via.

[0015] In some embodiments, the method of forming the gate and the second semiconductor pillar includes: forming a first sacrificial layer before forming the first semiconductor pillar, the first sacrificial layer being spaced apart from the initial semiconductor layer; removing a portion of the initial semiconductor pillar other than the first semiconductor pillar after forming the first semiconductor pillar to form a gap layer, the gap layer exposing the end of the first semiconductor pillar of the drain region; forming a gate in a portion of the gap layer, one end of the gate being electrically connected to the drain region of the first semiconductor pillar; and forming the second semiconductor pillar located on both sides of the gate in the remaining portion of the gap layer.

[0016] In some embodiments, the method of forming the second word line and the second bit line includes: removing a first sacrificial layer that contacts the second semiconductor pillar and the gate, forming a second sacrificial layer, the second sacrificial layer covering the sidewall of the second semiconductor pillar and the sidewall of the gate; performing an etching process on the second sacrificial layer to form a second via and a third via, the second via and the third via respectively exposing the source / drain regions of at least one of the two second semiconductor pillars disposed in the same layer and the substrate; forming a second word line in the second via and forming a second bit line in the third via.

[0017] In some embodiments, there is one source / drain region of the second semiconductor pillar, the source / drain region and the channel region are arranged along a first direction, and the second via and the third via expose the source / drain regions of the two second semiconductor pillars disposed in the same layer, the first direction being the direction in which the second semiconductor pillar points to the gate.

[0018] In some embodiments, the second semiconductor pillar has two source / drain regions, and the two source / drain regions are located on opposite sides of the channel region in a second direction, the second direction being the extension direction of the second semiconductor pillar, and the second via and the third via expose the two source / drain regions in the same second semiconductor pillar.

[0019] In some embodiments, a plurality of first semiconductor pillars are formed on the substrate surface at intervals along a third direction, the third direction being parallel to the substrate surface. The method of forming the first bit line includes: forming the first bit line on the top surface of the first semiconductor pillar in the source region, the bottom surface of the first semiconductor pillar in the source region, and both sides of the first semiconductor pillar in the source region along the third direction, the formed first bit line covering the side surface of the first semiconductor pillar in the source region of each of the first semiconductor pillars arranged along the third direction.

[0020] In some embodiments, in the first semiconductor pillars arranged along the third direction, the distance between adjacent first semiconductor pillars is a first distance, and in the first semiconductor pillars stacked together, the distance between adjacent first semiconductor pillars is a second distance, wherein the first distance is less than the second distance.

[0021] In some embodiments, the ratio of the second distance to the first distance is greater than 4.

[0022] The technical solutions provided in this disclosure have at least the following advantages:

[0023] In the semiconductor structure provided in this disclosure, a first semiconductor pillar with a first channel region is disposed around the side of a first word line and is used to control a write transistor formed by the first semiconductor pillar. The first bit line is electrically connected to the source region of the first semiconductor pillar, and the write transistor is used to write data. A gate is provided between two second semiconductor pillars, and the gate is electrically connected to the channel region of one of the two second semiconductor pillars, used to control a read transistor formed by the two second semiconductor pillars. Furthermore, one end of the gate is electrically connected to the drain region of the first semiconductor pillar and is used to receive signals written by the write transistor. The gate directly contacts the drain region of the first semiconductor pillar, thus eliminating the need for an additional metal layer for electrically connecting the drain region of the first semiconductor pillar and the gate, reducing the size of the semiconductor structure. A second word line and a second bit line are electrically connected to the source and drain regions of at least one of the two semiconductor pillars and are used to read data from the read transistor. The first word line, second word line, and second bit line are perpendicular to the substrate, and the first bit line is parallel to the substrate, making the horizontal dimension occupied by the first word line, second word line, and second bit line in the semiconductor structure relatively small, thereby reducing the size of the semiconductor structure. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 2 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 3 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0028] Figure 4 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0029] Figure 5 for Figure 1 The equivalent circuit diagram corresponding to the semiconductor structure in the diagram;

[0030] Figures 6 to 29A schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure provided in another embodiment of this disclosure. Detailed Implementation

[0031] As can be seen from the background technology, current semiconductor structures suffer from the problem of large size.

[0032] Analysis reveals that one reason for the large size of semiconductor structures is that current semiconductor structures used to construct 2TOC DRAM cells require at least two semiconductor pillars, one for the write transistor and the other for the read transistor. In current semiconductor structures, at least two of the word lines and bit lines of the read transistor, as well as the word lines and bit lines of the write transistor, are parallel to the substrate. This results in an excessively large horizontal size for the semiconductor structure, especially when there are many stacked semiconductor pillars. Because the word lines and bit lines are parallel to the substrate, the stacked semiconductor pillars cannot share the same bit line and word line, leading to a large overall size of the semiconductor structure.

[0033] This disclosure provides a semiconductor structure in which a first semiconductor pillar with a first channel region is disposed around the side of a first word line for controlling a write transistor formed by the first semiconductor pillar. A first bit line is electrically connected to the source region of the first semiconductor pillar, and the write transistor is used to write data. A gate is provided between two second semiconductor pillars, and the gate is electrically connected to the channel region of one of the two second semiconductor pillars for controlling a read transistor formed by the two second semiconductor pillars. One end of the gate is electrically connected to the drain region of the first semiconductor pillar for receiving signals written by the write transistor, and the gate directly contacts the drain region of the first semiconductor pillar, thus eliminating the need for an additional metal layer for electrically connecting the drain region of the first semiconductor pillar and the gate, reducing the size of the semiconductor structure. A second word line and a second bit line are electrically connected to the source and drain regions of at least one of the two semiconductor pillars for reading data from the read transistor. The first word line, second word line, and second bit line are perpendicular to the substrate, and the first word line is parallel to the substrate, resulting in a smaller horizontal dimension occupied by the first word line, further reducing the size of the semiconductor structure.

[0034] In this embodiment, two second semiconductor pillars are positioned on either side of the gate, allowing the second bit line and second word line to be perpendicular to the substrate while the gate, first semiconductor pillar, and second semiconductor pillar are parallel to the substrate, thus forming a 2TOC memory cell. In other words, this embodiment provides a novel semiconductor structure. By rearranging the positional relationships between the first semiconductor pillar, second semiconductor pillar, first word line, first word line, second word line, and second bit line, the size of the semiconductor structure is reduced while maintaining its performance, thereby improving the integration density of the semiconductor structure.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 1 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a cross-sectional schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0037] refer to Figures 1 to 4 The semiconductor structure includes: a substrate 100; a first semiconductor pillar 101 located on the substrate 100, the first semiconductor pillar 101 having a first channel region and source and drain regions located on both sides of the first channel region; a first word line 102, the first semiconductor pillar 101 of the first channel region being disposed around the side of the first word line 102; a first bit line 103, the first bit line 103 being electrically connected to the source region of the first semiconductor pillar 101; two second semiconductor pillars 104 located on the substrate 100 and a gate 105 located between the two second semiconductor pillars 104, the second semiconductor pillars 104 having at least one source and drain region 12 and The second channel region 11 is disposed facing the gate 105, one end of which is electrically connected to the drain region of the first semiconductor pillar 101. The first semiconductor pillar 101, the gate 105, and the second semiconductor pillar 104 are disposed parallel to the substrate 100. The second word line 106 and the second bit line 107 are electrically connected to the source and drain regions 12 of at least one of the two second semiconductor pillars 104. The first word line 102, the second word line 106, and the second bit line 107 are perpendicular to the substrate 100, and the first bit line 103 is disposed parallel to the substrate 100.

[0038] In this embodiment, two second semiconductor pillars 104 are positioned on either side of a gate 105. The gate 105 controls a read transistor composed of the two second semiconductor pillars 104. One end of the gate 105 is electrically connected to the drain region of the first semiconductor pillar 101 to receive signals written from the write transistor. The second semiconductor pillars 104 and the gate 105 are both parallel to the substrate 100, thus enabling the formation of a stacked DRAM structure. Furthermore, since the two second semiconductor pillars 104 are positioned on either side of the gate 105, the second bit line 107 and the second word line 106 are perpendicular to the substrate 100 when the gate 105, the first semiconductor pillar 101, and the second semiconductor pillars 104 are all parallel to the substrate 100. This results in a smaller horizontal dimension occupied by the second word line 106 and the second bit line 107 in the semiconductor structure, reducing the overall size of the semiconductor structure. It is understood that the first semiconductor pillar 101, the second semiconductor pillar 104, the gate 105, and the first bit line 103 being arranged parallel to the substrate 100 refers to being arranged parallel to the surface of the substrate 100.

[0039] The substrate 100 is made of a semiconductor material. In some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, or a silicon substrate on an insulator.

[0040] The first channel region, source region, and drain region of the first semiconductor pillar 101 are used to form a write transistor. The first channel region serves as the channel of the write transistor. The first word line 102 contacts the first semiconductor pillar 101 in the first channel region and serves as the word line of the write transistor. It is used to conduct the first channel region based on a control signal, realizing charge transfer between the source and drain in the write transistor, thereby achieving data writing. The first bit line 103 is electrically connected to the first semiconductor pillar 101 in the source region and is used to input a data voltage to the write transistor. Specifically, the first word line 102 can serve as a write word line, and the first bit line 103 can serve as a write bit line. Specifically, the first semiconductor pillar 101 is arranged parallel to the substrate 100, and the first semiconductor pillar 101 in the first channel region is arranged around the side of the first word line 102, thereby achieving a configuration where the first semiconductor pillar 101 is perpendicular to the substrate 100. Furthermore, the entire side of the first word line 102 is surrounded by the first semiconductor pillar 101 of the first channel region. Therefore, the contact area between the first word line 102 and the first semiconductor pillar 101 of the first channel region is large, resulting in a larger channel region area for the written transistor. This is beneficial to enhance the control capability of the first word line 102 over the written transistor and can reduce leakage current.

[0041] In some embodiments, the dopant ion type in the first channel region may be different from the dopant ion type in the source and drain regions, thereby forming a junction transistor. For example, the dopant ion type in the first channel region may be P-type, and the dopant ion type in the source and drain regions may be N-type, thus forming an NMOS transistor.

[0042] In other embodiments, the dopant ion type of the first channel region may also be the same as the dopant ion type of the source and drain regions to form a junctionless transistor.

[0043] The second channel region 11 of the second semiconductor pillar 104 and the source / drain regions 12 located in the two second semiconductor pillars 104 constitute a read transistor, wherein the second channel region 11 serves as the channel of the read transistor, and the source / drain regions 12 in the second semiconductor pillars 104 serve as either the source or the drain of the read transistor. One end of the gate 105 is electrically connected to the drain region of the first semiconductor pillar 101, specifically, it can contact the end of the first semiconductor pillar 101, thereby electrically connecting the gate 105 of the read transistor to the drain of the write transistor, so that the gate 105 can be used to receive the data voltage written from the write transistor. The second bit line 107 is electrically connected to the source / drain region 12 of one of the second semiconductor pillars 104, wherein the second bit line 107 can serve as a read bit line, and the second word line 106 can serve as a read word line. Specifically, the second word line 106 can be electrically connected to the source of the read transistor, and the second bit line 107 can be electrically connected to the drain of the read transistor. The second word line 106 can be used to apply a fixed voltage to the read transistor, and the second bit line 107 can be used to read the voltage change of the read transistor, thereby realizing data reading. The read transistor and the write transistor together constitute a 2T0C DRAM cell.

[0044] In some embodiments, the dopant ion type of the second channel region 11 may be different from the dopant ion type of the source / drain region 12, thereby forming a junction transistor. For example, the dopant ion type in the second channel region 11 may be P-type, and the dopant ion type in the source / drain region 12 may be N-type, thus forming an NMOS transistor.

[0045] In other embodiments, the doped ion type of the second channel region 11 may also be the same as the doped ion type of the source / drain region 12, forming a junctionless transistor.

[0046] refer to Figure 1 In some embodiments, the second semiconductor pillar 104 has a dielectric layer 112 on the side facing the first semiconductor pillar 101, the dielectric layer 112 being used to isolate the first semiconductor pillar 101 and the second semiconductor pillar 104.

[0047] Figure 5 for Figure 1The equivalent circuit diagram corresponding to the semiconductor structure in the diagram is shown in the reference diagram. Figure 5 The storage circuit includes a write transistor and a read transistor. The source of the write transistor is electrically connected to the first word line WBL, and the gate 105 of the write transistor is electrically connected to the first word line WWL. The gate of the read transistor is electrically connected to the drain of the write transistor, forming storage node A. The drain of the read transistor is electrically connected to the second word line RWL, and the source of the read transistor is electrically connected to the second bit line RBL. By changing the charge of the gate node of the read transistor through the write transistor, the resistance state between the source and drain of the read transistor is changed, thereby achieving the distinction between "0" and "1". In some embodiments, the working principle of the storage circuit is as follows:

[0048] The process of writing "1" to the write transistor involves applying a positive voltage (greater than the threshold voltage Vth) to the gate 105 of the write transistor to turn it on. A positive voltage is then written to the source of the write transistor through the first bit line WBL, and charge is injected into the gate of the read transistor, i.e., charge is injected into the memory node, making the logic level of the memory node "1".

[0049] The process of reading "1" from the read transistor involves applying a read voltage to the drain of the read transistor through the second word line RWL. Since there is charge stored in the storage node, the read transistor is in a conducting state, that is, the read transistor is in a low resistance state, which allows the second bit line RBL to read a large current. After being amplified by the external circuit, the process of reading "1" is completed.

[0050] The process of writing "0" to the write transistor involves applying a positive voltage (greater than the threshold voltage Vth) to the gate of the write transistor to turn it on. Then, a negative voltage is written to the source of the write transistor through the first bit line WBL to consume the charge of the storage node, and the logic level of the storage node becomes "0".

[0051] The process of reading "0" from the read transistor involves applying a read voltage to the drain of the read transistor through the second word line RWL. Since there is no charge in the storage node, the read transistor is in the cutoff state, i.e., the read transistor is in a high-resistance state. As a result, the current read by the second word line RBL is relatively small, and then amplified by the external circuit to complete the process of reading "0".

[0052] Continue to refer to Figures 1 to 4In some embodiments, a plurality of first semiconductor pillars 101 and second semiconductor pillars 104 stacked along a direction away from the substrate 100 are disposed on the surface of the substrate 100. The first channel regions of the plurality of stacked first semiconductor pillars 101 surround the side of the same first word line 102, and the second word line 106 and second bit line 107 are electrically connected to the source / drain regions 12 of at least one of the two columns of stacked second semiconductor pillars 104. That is, the plurality of stacked first semiconductor pillars 101 share the same first word line 102, and the plurality of stacked second semiconductor pillars 104 share the same second word line 106 and the same second bit line 107. Since the first semiconductor pillars 101 and second semiconductor pillars 104 are both disposed parallel to the substrate 100, a plurality of first semiconductor pillars 101 and a plurality of second semiconductor pillars 104 can be stacked to form a stacked 2TOC DRAM cell, thereby improving the integration density of memory cells in the semiconductor structure. Furthermore, since the first word line 102, the second word line 106, and the second bit line 107 are all perpendicular to the substrate 100, that is, the extension direction of the first word line 102, the second word line 106, and the second bit line 107 is perpendicular to the extension direction of the first semiconductor pillar 101 and the second semiconductor pillar 104, multiple stacked first semiconductor pillars 101 only need to share one first word line 102, and multiple stacked second semiconductor pillars 104 only need to share one second bit line 107 and the second word line 106, thereby greatly reducing the number of first word lines 102, second bit lines 107, and second word lines 106 in the semiconductor structure, thereby improving the integration of the semiconductor structure.

[0053] As can be seen from the above analysis, in this embodiment of the present disclosure, when the semiconductor structure is used to form a stacked 2T0C DRAM cell, since the first word line 102, the second bit line 107 and the second word line 106 are all set perpendicular to the substrate 100, the number of the first word line 102, the second bit line 107 and the second word line 106 can be greatly reduced, thereby greatly improving the integration of the semiconductor structure.

[0054] refer to Figure 1In some embodiments, the second semiconductor pillar 104 has one source / drain region 12, which is arranged along a first direction X with the second channel region 11. The second word line 106 and the second bit line 107 are electrically connected to the source / drain regions 12 of the two second semiconductor pillars 104, respectively. The first direction X is the direction in which the second semiconductor pillar 104 points towards the gate 105. The two second semiconductor pillars 104 together constitute a read transistor. The source / drain region 12 of one second semiconductor pillar 104 is used as either the source or the drain of the read transistor, and the source / drain region 12 of the other second semiconductor pillar 104 is used as the other of the source or the drain of the read transistor. The second word line 106 and the second bit line 107 are located on the side of the second semiconductor pillar 104 away from the gate 105. The second word line 106 is electrically connected to the source / drain region 12 of one semiconductor pillar to write a fixed voltage to the read transistor, and the second bit line 107 is electrically connected to the source / drain region 12 of the other semiconductor pillar to obtain the current change of the read transistor. The gate 105 is located between the two second semiconductor pillars 104, and along the first direction X, both sides of the gate 105 are electrically connected to the second channel regions 11 of the two second semiconductor pillars 104, respectively, for receiving data from the write transistor to turn on or off the read transistor. In other words, the channel regions of the two second semiconductor pillars 104 are electrically connected through the gate 105, so that the two second semiconductor pillars 104 can together form a read transistor.

[0055] refer to Figure 4 In other embodiments, the second semiconductor pillar 104 has two source / drain regions 12, located on opposite sides of the second channel region 11 in the second direction Y. The second word line 106 and the second bit line 107 are electrically connected to the two source / drain regions 12 of the same second semiconductor pillar 104, respectively. The second direction Y is the extension direction of the second semiconductor pillar 104. That is, one second semiconductor pillar 104 is used to form a read transistor. The second word line 106 and the second bit line 107 are located on the same side of the second semiconductor pillar 104, and the second word line 106 and the second bit line 107 are located on opposite sides of the gate 105 of the second semiconductor pillar 104. The second word line 106 is electrically connected to one of the source / drain regions 12 of the same second semiconductor pillar 104 to write a fixed voltage to the read transistor; the second bit line 107 is electrically connected to the other source / drain region 12 of the same second semiconductor pillar 104 to obtain the current change of the read transistor. Thus, when there are two second semiconductor pillars 104 on both sides of the gate 105, the two second semiconductor pillars 104 can each form a read transistor, and the two read transistors share the same gate 105. Compared to the two second semiconductor pillars 104 forming one read transistor, the number of memory cells formed in the semiconductor structure can be increased, thereby improving the integration density.

[0056] In some embodiments, a plurality of first semiconductor pillars 101 are spaced apart along a third direction Z on the surface of the substrate 100. The third direction Z is parallel to the surface of the substrate 100. A first line 103 covers the side surface of each source region of the first semiconductor pillar 101 among the first semiconductor pillars 101 arranged along the third direction Z. That is, the plurality of first semiconductor pillars 101 spaced apart along the third direction Z are disposed in the same layer. Since the first line 103 is parallel to the substrate 100, when a plurality of first semiconductor pillars 101 are disposed parallel to the substrate 100 and in the same layer are provided, the plurality of first semiconductor pillars 101 disposed in the same layer can be configured to share the same first line 103. This can increase the number of memory cells in the semiconductor structure while reducing the number of first lines 103 in the semiconductor structure, thereby further improving the integration density of the semiconductor structure. In some embodiments, the third direction Z can be parallel to the first direction X.

[0057] In some embodiments, the first semiconductor pillar 101 can be made of silicon, and the second semiconductor pillar 104 can be made of an amorphous material. Amorphous silicon has a high carrier mobility, which increases the carrier migration rate in the source and drain of the second semiconductor pillar 104 after the source and drain are turned on, thereby reducing the off-state current of the read transistor. Specifically, the second semiconductor pillar 104 can be made of indium gallium zinc oxide (IGZO). IGZO, as an amorphous material, has extremely high carrier mobility, allowing the read transistor formed by the second semiconductor pillar 104 to drive a larger current, resulting in faster read speeds and lower off-state currents.

[0058] Meanwhile, setting the material of the first semiconductor pillar 101 to silicon simplifies the actual semiconductor structure fabrication process. This is because the annealing step of indium gallium zinc oxide is more complex than that of silicon. Therefore, setting the material of the first semiconductor pillar 101 to silicon simplifies the fabrication process, thereby preventing the overall semiconductor structure fabrication process from becoming overly complex.

[0059] In some other embodiments, the materials of the first semiconductor pillar 101 and the second semiconductor pillar 104 may both be silicon, or in yet another embodiment, the materials of the first semiconductor pillar 101 and the second semiconductor pillar 104 may both be amorphous materials.

[0060] In some embodiments, the gate 105 includes a metal silicide layer and a metal layer. The metal silicide layer is disposed facing the first semiconductor pillar 101 and electrically connected to the drain region of the first semiconductor pillar 101. The metal layer acts as a conductor for data transmission. The metal silicide layer can serve as a connection structure between the metal layer and the first semiconductor pillar 101, specifically as a storage node in a storage circuit for storing charge. Since the metal silicide layer and the first semiconductor pillar 101 have the same elements, their material properties are similar. Compared to directly placing the metal layer in contact with the drain region of the first semiconductor pillar 101, placing the metal silicide layer between the metal layer and the drain region of the first semiconductor pillar 101 results in a lower contact resistance between them, thereby reducing RC delay and improving the performance of the semiconductor structure.

[0061] In some embodiments, the material of the metal silicide layer may include at least one of tungsten silicide, cobalt silicide, or titanium silicide. The material of the metal layer may include at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold.

[0062] In some embodiments, the materials of the first word line 102 and the second word line 106 may be the same, specifically including metallic materials, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. In other embodiments, the materials of the first word line 102 and the second word line 106 may also be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0063] In some embodiments, the first bit line 103 and the second bit line 107 may be made of the same material, specifically including a metallic material, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. In other embodiments, the first bit line 103 and the second bit line 107 may also be made of polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0064] In some embodiments, a first gate dielectric layer 110 and a second gate dielectric layer may be included. The first gate dielectric layer 110 is located between the first word line 102 and the first semiconductor pillar 101, and is used to isolate the second channel region 11 of the first word line 102 and the first semiconductor pillar 101. The second dielectric layer is located between the gate 105 and the second semiconductor pillar 104, and is used to isolate the second channel region 11 of the gate 105 and the second semiconductor pillar 104. The provision of the first gate dielectric layer 110 and the second gate dielectric layer can reduce the on-state voltage of the write transistor and the read transistor.

[0065] In the semiconductor structure provided in the above embodiments, two second semiconductor pillars 104 are located on both sides of the gate 105. This allows the second bit line 107 and the second word line 106 to be perpendicular to the substrate 100 when the gate 105, the first semiconductor pillar 101, and the second semiconductor pillar 104 are parallel to the substrate 100, thereby forming a 2T0C memory cell. In other words, this disclosure provides a novel semiconductor structure. By rearranging the positional relationships between the first semiconductor pillar 101, the second semiconductor pillar 104, the first word line 102, the first bit line 103, the second word line 106, and the second bit line 107, the size of the semiconductor structure is reduced while maintaining its performance, thereby improving the integration density of the semiconductor structure.

[0066] Accordingly, this disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0067] Methods for fabricating semiconductor structures include:

[0068] refer to Figures 6 to 12 A substrate 100 is provided, and a first semiconductor pillar 101 is formed on the substrate 100. The first semiconductor pillar 101 has a first channel region and source and drain regions located on both sides of the first channel region. A first word line 102 is formed, and the first semiconductor pillar 101 of the first channel region is disposed around the side of the first word line 102. The first channel region, source region, and drain region of the first semiconductor pillar 101 are used to form a write transistor. The first channel region serves as the channel of the write transistor, and the side of the first word line 102 is surrounded by the first semiconductor pillar 101 of the first channel region, serving as the word line of the write transistor. Based on a control signal, the first channel region is turned on to realize charge transfer between the source and drain in the write transistor, thereby realizing data writing.

[0069] The first semiconductor pillar 101 is disposed parallel to the substrate 100. Since the first semiconductor in the first channel region surrounds the side of the first word line 102, the first word line 102 is disposed perpendicular to the first semiconductor pillar 101, i.e., perpendicular to the substrate 100. This helps to reduce the size occupied by the first word line 102 in the horizontal direction of the semiconductor structure. Furthermore, since the first word line 102 is perpendicular to the substrate 100, when multiple stacked transistors are formed in the semiconductor structure, i.e., multiple stacked first semiconductor pillars 101 are formed, the multiple stacked first semiconductor pillars 101 can share the same first word line 102, thereby reducing the number of first word lines 102 and further reducing the size of the semiconductor structure.

[0070] In some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate 100, a germanium-silicon substrate 100, a silicon carbide substrate 100, or a silicon-on-insulator substrate 100.

[0071] In some embodiments, the number of first semiconductor pillars 101 is multiple, and the multiple first semiconductor pillars 101 are stacked to form a first word line 102.

[0072] refer to Figure 6 Stacked initial semiconductor pillars 20 are formed on the substrate 100. Some of the initial semiconductor pillars 20 have a first channel region and source and drain regions located on both sides of the first channel region. That is, each initial semiconductor pillar 20 is used to form a write transistor, thereby improving the integration density of the semiconductor structure.

[0073] In some embodiments, the material of the initial semiconductor pillar 20 may be the same as the material of the substrate 100.

[0074] Specifically, in some embodiments, the step of forming the stacked initial semiconductor pillars 20 further includes: forming a first sacrificial layer 21, which is located between adjacent initial semiconductor pillars 20, serving both to support the initial semiconductor pillars 20 and to isolate adjacent initial semiconductor pillars 20. The first sacrificial layer 21 is also located between the initial sacrificial layer and the substrate 100, separating the substrate 100 from the initial semiconductor pillars 20. In some embodiments, the substrate 100 and the initial semiconductor pillars 20 are made of silicon, and the first sacrificial layer 21 can be made of silicon germanide. This ensures that the first sacrificial layer 21 and the substrate 100 have the same silicon element, matching the lattice constants of the silicon substrate 100 and the first sacrificial layer 21. Based on this, the formation of the initial semiconductor pillars 20 and the method thereof may include an epitaxial process. Since the lattice constants of the silicon substrate 100 and the first sacrificial layer 21 are matched, when the initial semiconductor pillar 20 of the spacer colloid and the first sacrificial layer 21 are formed on the substrate 100 using an epitaxial process, silicon germanide can be grown more easily using silicon in the silicon substrate 100. This not only simplifies the fabrication process, but also makes the boundary between the first sacrificial layer 21 and the initial semiconductor pillar 20 clear, which is beneficial for the subsequent complete removal of the first sacrificial layer 21 located on the surface of the initial semiconductor.

[0075] In some embodiments, the dopant ion type in the first channel region may be different from the dopant ion type in the source and drain regions, thereby forming a junction transistor. For example, the dopant ion type in the first channel region may be P-type, and the dopant ion type in the source and drain regions may be N-type, constituting an NMOS transistor. In some embodiments, the initial semiconductor pillar 20 may be doped before forming the first semiconductor pillar 101, so that after etching the initial semiconductor pillar 20 to form a plurality of spaced-apart first semiconductor pillars 101, each first semiconductor pillar 101 has a first channel region, a source region, and a drain region. In other embodiments, the first semiconductor pillar 101 may be doped after forming the first semiconductor pillar 101 to form the first channel region and the source and drain regions located on both sides of the first channel region. The doping process may be either ion implantation or thermal diffusion.

[0076] refer to Figure 7 as well as Figure 8 The initial semiconductor pillar 20 of the first channel region is etched to form a first via 22. The first via 22 penetrates part of the first channel region of multiple stacked initial semiconductor pillars 20 and exposes the substrate 100. The remaining first channel region, drain region and source region constitute the first semiconductor pillar 101. The first via 22 is used to subsequently form the first word line 102. Since the first via 22 penetrates multiple stacked initial semiconductor pillars 20, after the first word line 102 is subsequently formed in the first via 22, the first word line 102 can be surrounded by the channel regions of multiple stacked first semiconductor pillars 101. On the one hand, this makes the contact area between the first word line 102 and the first semiconductor pillars 101 in the first hook area larger, resulting in a larger channel region for the write transistor formed by the first semiconductor pillars 101. This is beneficial for enhancing the control capability of the first word line 102 over the write transistor and reducing leakage current. On the other hand, it allows multiple stacked first semiconductor pillars 101 to share the same first word line 102, thereby increasing the integration density of the semiconductor structure while greatly reducing the number of first word lines 102 in the semiconductor structure, and thus greatly reducing the size of the semiconductor structure.

[0077] Specifically, in some embodiments, the process for forming the first via 22 includes: patterning a first sacrificial layer 21 located on the top surface to define the opening of the first via 22; and etching the patterned first sacrificial layer 21 to form the first via 22. In some embodiments, the first sacrificial layer 21 may be patterned using self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0078] refer to Figures 9 to 12 A first word line 102 is formed in the first via 22. In some embodiments, before forming the first word line 102, the method further includes: forming a first gate dielectric layer 110 on the inner wall and bottom of the first via 22 using a deposition process; forming the first word line 102 on the surface of the first gate dielectric layer 110 using a deposition process, wherein the first word line 102 fills the remaining space of the first via 22. In some embodiments, the material of the first gate dielectric layer 110 may be at least one of silicon oxide, silicon nitride, or silicon oxynitride. The material of the first word line 102 may be a metallic material, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, or gold; in other embodiments, the material of the first word line 102 may also be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0079] refer to Figure 11 as well as Figure 12 When the semiconductor structure also has multiple first semiconductor pillars 101 spaced apart along the third direction Z, multiple first vias 22 spaced apart along the third direction Z can be formed in the initial semiconductor pillars 20, thereby forming a first word line 102 in each via. After forming the spaced first word lines 102, a patterning process is performed on the initial semiconductor pillars 20, and an etching process is used to remove the initial semiconductor pillars 20 between adjacent first word lines 102 to form a first trench, and the first semiconductor pillars 101 spaced apart along the third direction Z separated by the first trench. In this way, only one process step of forming the initial semiconductor pillars 20 is required to form multiple spaced and stacked first semiconductor pillars 101, which helps to simplify the process flow.

[0080] refer to Figures 13 to 22Two second semiconductor pillars 104 and a gate 105 located between the two second semiconductor pillars 104 are formed on the substrate 100. The second semiconductor pillars 104 have at least one source / drain region 12 and a second channel region 11. The second channel region 11 is disposed toward the gate 105. One end of the gate 105 is electrically connected to the drain region of the first semiconductor pillar 101. The gate 105 of the first semiconductor pillar 101 and the second semiconductor pillars 104 are disposed parallel to the substrate 100.

[0081] The second channel region 11 of the second semiconductor pillar 104 and the source / drain regions 12 located in the two second semiconductor pillars 104 constitute a read transistor. The second channel region 11 serves as the channel of the read transistor, and the source / drain regions 12 in the second semiconductor pillars 104 serve as either the source or drain of the read transistor. One end of the gate 105 is electrically connected to the drain region of the first semiconductor pillar 101, specifically, it can contact the end of the first semiconductor pillar 101, thereby electrically connecting the gate 105 of the read transistor to the drain of the write transistor, allowing the gate 105 to receive the data voltage written from the write transistor. The second bit line 107 is electrically connected to the source / drain region 12 of one of the second semiconductor pillars 104, wherein the second bit line 107 can serve as a read bit line, and the second word line 106 can serve as a read word line. The read transistor and the write transistor together constitute a 2T0C DRAM cell.

[0082] In some embodiments, a portion of the initial semiconductor pillars 20 is used to form the first semiconductor pillar 101, and the remaining portion of the initial semiconductor pillars 20 is used to form the second semiconductor pillar 104. In this way, the process flow for forming the second semiconductor pillar 104 can be saved, that is, there is no need to use an additional deposition process to form the second semiconductor pillar 104, only the initial semiconductor pillars 20 need to be etched.

[0083] Based on this, in some embodiments, the method of forming the gate 105 and the second semiconductor pillar 104 includes:

[0084] refer to Figure 6 Before forming the first semiconductor pillar 101, a first sacrificial layer 21 is formed, which is spaced apart from the initial semiconductor layer. The first sacrificial layer 21 is used to define the region for forming the second semiconductor pillar 104 after the portion of the initial semiconductor pillar 20 other than the first semiconductor pillar 101 is subsequently removed.

[0085] refer to Figures 13 to 18After forming the first semiconductor pillar 101, the portion of the initial semiconductor pillar 20 other than the first semiconductor pillar 101 is removed to form a gap layer 24, which exposes the end of the drain region of the first semiconductor pillar 101. The gap layer 24 is used for the subsequent formation of the gate 105 and the second semiconductor pillar 104. Since the formed second semiconductor pillar 104 contacts the drain region of the first semiconductor pillar 101, for example, it can contact the end of the first semiconductor pillar 101, thus allowing the initial semiconductor pillar 20 to be formed first, and a portion of the initial semiconductor pillar 20 to be converted into the first semiconductor pillar 101. After removing the remaining portion of the initial semiconductor pillar 20, sufficient space can be provided for the formation of the gate 105 and the second semiconductor pillar 104. The formed gate 105 will inevitably contact the end of the first semiconductor pillar 101, allowing the gate 105 to directly contact the end of the first semiconductor pillar 101, fully utilizing the space of the semiconductor structure and reducing the size of the formed semiconductor structure.

[0086] Specifically, in some embodiments, the method of forming the gap layer 24 may include:

[0087] refer to Figures 13 to 14 A mask layer 23 is formed between the initial semiconductor pillars 20 and the first sacrificial layer 21 spaced along the third direction Z and on the sidewalls of the initial semiconductor pillars 20 and the first sacrificial layer 21 spaced along the third direction Z. The top surface of the mask layer 23 is flush with the top surface of the first sacrificial layer 21. The mask layer 23 is located on the sidewall of the initial semiconductor pillars 20 and is used to protect the sidewalls of the first semiconductor pillars 101 in the subsequent step of exposing the initial semiconductor pillars 20 corresponding to the area where the second semiconductor pillars 104 are to be formed, preventing the mask layer 23 from causing process damage to the first semiconductor pillars 101.

[0088] refer to Figures 15 to 16 The mask layer 23 is etched to expose the sidewalls of the initial semiconductor pillars 20 other than the first semiconductor pillar 101, for subsequent etching of the exposed sidewalls of the initial semiconductor pillars 20 to form a gap layer 24. Specifically, in some embodiments, the method of etching the mask layer 23 may include: patterning the top surface of the mask layer 23; and etching the patterned mask layer 23 to remove the portion of the mask layer 23 corresponding to the portion of the initial semiconductor pillars 20 other than the first semiconductor pillar 101, exposing the sidewalls of the initial semiconductor pillars 20 other than the first semiconductor pillar 101. Specifically, in some embodiments, SAQP or SADP may be used to pattern the mask layer 23.

[0089] refer to Figures 17 to 18An etching process is performed on the sidewalls of the initial semiconductor pillar 20 exposed by the mask layer 23 to remove the portion of the initial semiconductor pillar 20 other than the first semiconductor pillar 101, forming a gap layer 24. Since the remaining portion of the mask layer 23 is still located on the sidewalls of the first semiconductor pillar 101, the etching process will not cause process damage to the first semiconductor pillar 101. Specifically, in some embodiments, either dry etching or wet etching can be used to etch the sidewalls of the initial semiconductor pillar 20 exposed by the mask layer 23.

[0090] refer to Figure 19 A gate 105 is formed in a portion of the gap layer 24, and one end of the gate 105 is electrically connected to the drain region of the first semiconductor pillar 101. Since the gap layer 24 exposes the end of the first semiconductor pillar 101, when the gate 105 is formed in the portion of the gap layer 24, the gate 105 can contact the end of the first semiconductor pillar 101, thereby realizing the electrical connection between the gate 105 and the drain region of the first semiconductor pillar 101.

[0091] In some embodiments, the gate 105 includes a metal silicide layer 108 and a metal layer 109. The metal silicide layer 108 is disposed facing the first semiconductor pillar 101 and electrically connected to the drain region of the first semiconductor pillar 101. Since the metal silicide layer 108 and the first semiconductor pillar 101 have the same elements, their material properties are similar. Compared to directly placing the metal layer 109 in contact with the first semiconductor pillar 101 in the drain region, placing the metal silicide layer 108 between the metal layer 109 and the first semiconductor pillar 101 in the drain region allows for a lower contact resistance between the first semiconductor pillar 101 in the drain region and the metal silicide layer 108, thereby reducing RC delay and improving the performance of the semiconductor structure.

[0092] Specifically, in some embodiments, the method of forming the gate 105 may include: forming an initial metal layer (not shown) in a portion of the interstitial layer 24 using a deposition process, such as either atomic layer deposition or chemical vapor deposition; the material of the initial metal layer may include either titanium, cobalt, or nickel; subsequently, the initial metal layer undergoes a first RTA (Rapid Thermal Acrylution) treatment. The rapid thermal annealing (RTA) process involves a first RTA at a relatively low annealing temperature (compared to the second RTA). The first RTA allows the initial metal layer to react with silicon to form a high-resistivity metal silicide. After the first RTA, selective wet etching is performed to remove the unreacted initial metal layer, followed by a second RTA at a relatively high annealing temperature (compared to the first RTA). This second RTA converts the high-resistivity metal silicide into a low-resistivity metal silicide, which forms a metal silicide layer 108. The material of the metal silicide layer 108 can include any one of tungsten silicide, cobalt silicide, or titanium silicide. A metal layer 109 is formed on the side of the metal silicide layer 108 away from the first semiconductor pillar 101 using a deposition process. The material of the metal layer 109 can include at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold.

[0093] refer to Figures 20 to 22 Second semiconductor pillars 104 are formed on both sides of the gate 105 in the remaining gap layer 24. In some embodiments, before forming the second semiconductor pillars 104 on both sides of the gate 105, a second gate dielectric layer 25 is formed on both sides of the gate 105 using a deposition process. The material of the second gate dielectric layer 25 can be at least one of silicon oxide, silicon nitride, or silicon oxynitride. After forming the second gate dielectric layer 25, the second semiconductor pillars 104 are formed on the side of the second gate dielectric layer 25 away from the gate 105 using a deposition process.

[0094] In some embodiments, since the second semiconductor pillar 104 is deposited separately after the first semiconductor pillar 101 is formed, the material of the second semiconductor pillar 104 can be different from the material of the first semiconductor pillar 101. For example, the material of the first semiconductor pillar 101 can be silicon, and the material of the second semiconductor pillar 104 can be an amorphous material. Amorphous silicon has a higher carrier mobility, which increases the carrier migration rate in the source and drain of the second semiconductor pillar 104 after the source and drain are turned on, thereby reducing the off-state current of the readout transistor. Specifically, the material of the second semiconductor pillar 104 can be indium gallium zinc oxide.

[0095] In some embodiments, when the material of the second semiconductor pillar 104 is an amorphous material, the method of forming the second semiconductor pillar 104 may include: depositing the amorphous material in the interstitial layer 24 using a deposition process; annealing the amorphous material in an oxygen atmosphere to form the second semiconductor pillar 104. In this way, defects in the amorphous material caused by oxygen can be repaired, thereby improving the carrier mobility of the formed second semiconductor pillar 104.

[0096] It is understood that in other embodiments, the material of the second semiconductor pillar 104 may also be the same as the material of the first semiconductor pillar 101.

[0097] In some embodiments, the dopant ion type of the second channel region 11 in the second semiconductor pillar 104 may be different from the dopant ion type of the source / drain region 12, thereby forming a junction transistor. For example, the dopant ion type of the second channel region 11 may be P-type, and the dopant ion type of the source / drain region 12 may be N-type, constituting an NMOS transistor. In other embodiments, the dopant ion type of the second channel region 11 may be the same as the dopant ion type of the source / drain region 12, forming a junctionless transistor. Specifically, in some embodiments, after forming the second semiconductor pillar 104, a doping process may be performed on the second semiconductor pillar 104 to form the second channel region 11 and the source / drain region 12. The doping process may be either ion implantation or thermal diffusion.

[0098] refer to Figures 23 to 27 A second word line 106 and a second bit line 107 are formed, and the second word line 106 and the second bit line 107 are electrically connected to the source and drain regions 12 of at least one of the two second semiconductor pillars 104, wherein the first word line 102, the second word line 106, and the second bit line 107 are perpendicular to the substrate 100. Since the two formed second semiconductor pillars 104 are located on both sides of the gate 105, it is possible to achieve that when the gate 105, the first semiconductor pillar 101, and the second semiconductor pillar 104 are arranged parallel to the substrate 100, the second bit line 107 and the second word line 106 are arranged perpendicular to the substrate 100, thereby forming a 2T0C memory cell. In other words, by rearranging the positional relationship between the first semiconductor pillar 101, the second semiconductor pillar 104, the first word line 102, the first bit line 103, the second word line 106, and the second bit line 107, the size of the semiconductor structure can be reduced while maintaining the semiconductor structure performance, thereby improving the integration density of the semiconductor structure.

[0099] The second bit line 107 is electrically connected to the source / drain region 12 of one of the second semiconductor pillars 104. The second bit line 107 can serve as a read bit line, and the second word line 106 can serve as a read word line. Specifically, the second word line 106 can be electrically connected to the source of the read transistor, and the second bit line 107 can be electrically connected to the drain of the read transistor. The second word line 106 can be used to apply a fixed voltage to the read transistor, and the second bit line 107 can be used to read the voltage changes of the read transistor, thereby realizing data reading.

[0100] In some embodiments, the method of forming the second word line 106 and the second bit line 107 includes:

[0101] refer to Figures 23 to 24 The first sacrificial layer 21, which contacts the second semiconductor pillar 104 and the gate 105, is removed to form a second sacrificial layer 26. The second sacrificial layer 26 covers the sidewalls of the second semiconductor pillar 104 and the gate 105. The second sacrificial layer 26 serves as the basis for the subsequent formation of the second via. Specifically, in some embodiments, the method for forming the second sacrificial layer 26 includes: patterning the top surface of the first sacrificial layer 21 to define the opening for forming the second sacrificial layer 26. In some embodiments, SAQP or SADP can be used to pattern the first sacrificial layer 21. After removing the first sacrificial layer 21, the second sacrificial layer 26 is formed on the sidewalls of the second semiconductor pillar 104 and the gate 105 using a deposition process. In some embodiments, the material of the second sacrificial layer 26 can be silicon oxide. Silicon oxide has high hardness, which allows the second sacrificial layer 26 to also isolate adjacent second semiconductor pillars 104.

[0102] refer to Figures 25 to 27 The second sacrificial layer 26 is etched to form a second via and a third via. The second and third vias expose the source / drain regions 12 of at least one of the two second semiconductor pillars 104 disposed on the same layer and the substrate 100, respectively. The second via is used to subsequently form a second word line 106, and the third via is used to subsequently form a second bit line 107. Since the second and third vias penetrate multiple stacked second semiconductor pillars 104, after the second word line 106 is formed in the second via and the second bit line 107 is formed in the third via, the second word line 106 and the second bit line 107 can contact the source / drain regions 12 of the multiple stacked second semiconductor pillars 104. That is, the multiple stacked second semiconductor pillars 104 can share the same second word line 106 and the same second bit line 107.

[0103] In some embodiments, the process for forming the second via includes: patterning a second sacrificial layer 26 located on the top surface to define the opening of the second via; and etching the patterned second sacrificial layer 26 to form the second via. In some embodiments, the first sacrificial layer 21 may be patterned using self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0104] In some embodiments, the second semiconductor pillar 104 has one source / drain region 12, which is arranged along a first direction X with the channel region. A second via and a third via expose the source / drain regions 12 of the two second semiconductor pillars 104 disposed on the same layer. The first direction X is the direction in which the second semiconductor pillar 104 points towards the gate 105. The two second semiconductor pillars 104 together constitute a read transistor. The source / drain region 12 of one second semiconductor pillar 104 is used as either the source or drain of the read transistor, and the source / drain region 12 of the other second semiconductor pillar 104 is used as the other of the source or drain of the read transistor. The second via and the third via are located on the side of the second semiconductor pillar 104 away from the gate 105, such that the formed second word line 106 is electrically connected to the source / drain region 12 of one semiconductor pillar to write a fixed voltage to the read transistor, and the second bit line 107 is electrically connected to the source / drain region 12 of the other semiconductor pillar to obtain the current change of the read transistor.

[0105] In some embodiments, when a plurality of gates 105 arranged in the same layer and spaced apart are also formed on the substrate 100, a plurality of read transistors arranged in the same layer can be formed. Adjacent read transistors can also share the same second bit line 107 or second word line 106. That is, the formed second bit line 107 or second word line 106 is electrically connected to the source / drain regions 12 of the second semiconductor pillars 104 belonging to two different read transistors, respectively. This can further reduce the number of second bit lines 107 or second word lines 106 in the semiconductor structure and improve the integration density of the semiconductor structure.

[0106] In other embodiments, the second semiconductor pillar 104 has two source / drain regions 12, located on opposite sides of the channel region in the second direction Y, where Y is the extension direction of the second semiconductor pillar 104. A second via and a third via expose the two source / drain regions 12 within the same second semiconductor pillar 104. That is, one second semiconductor pillar 104 is used to form one read transistor. Specifically, the second via and the third via are located on the same side of the second semiconductor pillar 104, such that the formed second word line 106 and second bit line 107 are located on the same side of the second semiconductor pillar 104. Thus, when there are two second semiconductor pillars 104 on both sides of the gate 105, each second semiconductor pillar 104 can form a read transistor, and the two read transistors share the same gate 105. Compared to two second semiconductor pillars 104 forming one read transistor, this increases the number of memory cells formed in the semiconductor structure, thereby improving integration density.

[0107] A second letter line 106 is formed in the second through-hole, and a second bit line 107 is formed in the third through-hole. Specifically, in some embodiments, the second letter line 106 can be formed on the inner wall of the second through-hole using a deposition process, and the second letter line 106 fills the second through-hole. The second bit line 107 is formed in the third through-hole using a deposition process, and the second bit line 107 fills the third through-hole. In some embodiments, the material of the second bit line 107 may include a metallic material, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. The material of the second letter line 106 may include a metallic material, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. In other embodiments, the material of the second bit line 107 may also be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide, and the material of the second word line 106 may also be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0108] refer to Figure 28 , Figure 29 , Figure 2 as well as Figure 3 A first line 103 is formed, which is electrically connected to the source region of the first semiconductor pillar 101. The first line 103 is arranged parallel to the substrate 100. Thus, when multiple first semiconductor pillars 101 are formed at intervals along the third direction Z on the surface of the substrate 100, the first line 103 is parallel to the substrate 100, allowing the multiple spaced first semiconductor pillars 101 to share the same first line 103. This enables the semiconductor structure to be reduced in size and its integration density to be increased while increasing the number of memory cells in the semiconductor structure.

[0109] Specifically, in some embodiments, a plurality of first semiconductor pillars 101 are formed on the surface of the substrate 100 at intervals along a third direction Z, the third direction Z being parallel to the surface of the substrate 100. The method for forming the first first line 103 includes:

[0110] refer to Figure 28 as well as Figure 29 A first line 103 is formed on the top surface of the first semiconductor pillar 101 in the source region, the bottom surface of the first semiconductor pillar 101 in the source region, and both sides of the first semiconductor pillar 101 in the third direction Z. The first line 103 formed covers the side surface of the first semiconductor pillar 101 in the source region of each semiconductor pillar 101 arranged along the third direction Z.

[0111] Specifically, in some embodiments, an etching process can be used to remove the first sacrificial layer 21 and the mask layer 23 on the surface of the first semiconductor pillar 101 covering the source region, so as to expose the surface of the first semiconductor pillar 101 in the source region. The etching process can be either a dry etching process or a wet etching process.

[0112] refer to Figure 2 as well as Figure 3 Before forming the first line 103, a barrier layer 111 can be formed on the surface of the first semiconductor pillar 101 exposing the source region using a deposition process. The barrier layer 111 is used to prevent the interdiffusion between the elements in the first line 103 and the doped ions in the first semiconductor. In some embodiments, the material of the barrier layer 111 can be titanium nitride.

[0113] After forming the barrier layer 111, a first line 103 is formed on the surface of the barrier layer 111 away from the first semiconductor pillar 101 using a deposition process. The deposition process can be atomic layer deposition. The material of the first line 103 can be a metallic material, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. In other embodiments, the material of the first line 103 can also be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0114] In some embodiments, a plurality of first semiconductor pillars 101 are also formed in the semiconductor structure and stacked along a direction away from the substrate 100. To prevent electrical interference between the first semiconductor pillars 101 stacked together in a direction perpendicular to the substrate 100, in some embodiments, after forming the first first line 103, an isolation structure 27 is also formed. The isolation structure 27 is located on adjacent first first lines 103 in a direction perpendicular to the surface of the substrate 100, thereby preventing electrical interference between adjacent first first lines 103. The material of the isolation structure 27 can be silicon oxide.

[0115] In some embodiments, in the first semiconductor pillars 101 arranged along the third direction Z, the distance between adjacent first semiconductor pillars 101 is a first distance, and in the stacked first semiconductor pillars 101, the distance between adjacent first semiconductor pillars 101 is a second distance, where the first distance is less than the second distance. Setting the distance between adjacent first semiconductor pillars 101 arranged along the third direction Z to be small avoids the problem of breakage of the first first line 103 between adjacent first semiconductor pillars 101 due to excessively large distances during the formation of the first first line 103. This ensures that the formed first first line 103 is a continuous film layer, which can better connect the source regions of each first semiconductor pillar 101 spaced along the third direction Z, improving the electrical transport performance of the first first line 103.

[0116] In the stacked first semiconductor pillars 101, each first semiconductor pillar 101 is electrically connected to a different first first line 103. To prevent electrical interference between the first first lines 103 corresponding to adjacent first semiconductor pillars 101 along the stacking direction, the distance between adjacent first semiconductor pillars 101 is relatively large. This helps ensure that after the first first lines 103 are formed, adjacent first first lines 103 along the stacking direction will not contact each other. Furthermore, after the isolation structure 27 is subsequently formed between adjacent first first lines 103 along the stacking direction, the larger distance results in a larger thickness for the formed isolation structure 27, thus providing better isolation for adjacent first first lines 103.

[0117] Specifically, in some embodiments, the ratio of the second distance to the first distance is greater than 4. Within this range, the distance between adjacent first semiconductor pillars 101 along the stacking direction is relatively large, thereby ensuring that after the first first line 103 is formed, adjacent first first lines 103 along the stacking direction will not contact each other, avoiding the problem of electrical interference between the first first lines 103 corresponding to adjacent first semiconductor pillars 101 along the stacking direction.

[0118] In the semiconductor structure fabrication method provided in the above embodiments, the two second semiconductor pillars 104 are located on both sides of the gate 105. This allows the gate 105, the first semiconductor pillar 101, and the second semiconductor pillar 104 to be arranged parallel to the substrate 100, while the second bit line 107 and the second word line 106 are arranged perpendicular to the substrate 100, thereby forming a 2T0C memory cell. In other words, by rearranging the positional relationships between the first semiconductor pillar 101, the second semiconductor pillar 104, the first word line 102, the first bit line 103, the second word line 106, and the second bit line 107, the size of the semiconductor structure can be reduced while maintaining its performance, thereby improving the integration density of the semiconductor structure.

[0119] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first semiconductor pillar located on the substrate, the first semiconductor pillar having a first channel region and source and drain regions located on both sides of the first channel region; The first word line, wherein the first semiconductor pillar of the first channel region is disposed around the side of the first word line; The first bit line is electrically connected to the source region of the first semiconductor pillar; Two second semiconductor pillars are located on the substrate and a gate is located between the two second semiconductor pillars. The second semiconductor pillars have at least one source / drain region and a second channel region. The second channel region is disposed toward the gate. One end of the gate is electrically connected to the drain region of the first semiconductor pillar. The first semiconductor pillar, the gate, and the second semiconductor pillars are disposed parallel to the substrate. The second word line and the second bit line are electrically connected to the source and drain regions of at least one of the two second semiconductor pillars, respectively. The first word line, the second word line, and the second bit line are perpendicular to the substrate, and the first bit line is parallel to the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The substrate surface is provided with a plurality of first semiconductor pillars and second semiconductor pillars stacked in a direction away from the substrate, wherein the first channel region of the plurality of stacked first semiconductor pillars surrounds the side of the same first word line, and the second word line and the second bit line are respectively electrically connected to the source and drain regions of at least one of the two columns of stacked second semiconductor pillars.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The second semiconductor pillar has one source / drain region, which is arranged along the second channel region in a first direction. The second word line and the second bit line are electrically connected to the source / drain regions of the two second semiconductor pillars, respectively. The first direction is the direction in which the second semiconductor pillar points to the gate.

4. The semiconductor structure according to claim 1 or 2, characterized in that, The second semiconductor pillar has two source / drain regions, and the two source / drain regions are located on opposite sides of the second channel region in the second direction. The second word line and the second bit line are electrically connected to the two source / drain regions of the same second semiconductor pillar, respectively. The second direction is the extension direction of the second semiconductor pillar.

5. The semiconductor structure according to claim 1, characterized in that, The first semiconductor pillar is made of silicon, and the second semiconductor pillar is made of an amorphous material.

6. The semiconductor structure according to claim 2, characterized in that, The substrate surface is provided with a plurality of first semiconductor pillars arranged at intervals along a third direction, the third direction being parallel to the substrate surface, and the first bit line covering the side surface of the first semiconductor pillar of the source region of each of the first semiconductor pillars arranged along the third direction.

7. The semiconductor structure according to claim 1, characterized in that, The gate includes a metal silicide layer and a metal layer, the metal silicide layer being disposed facing the first semiconductor pillar and electrically connected to the drain region of the first semiconductor pillar.

8. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A first semiconductor pillar is formed on the substrate, the first semiconductor pillar having a first channel region and a source region and a drain region located on both sides of the first channel region; A first word line is formed, and the first semiconductor pillar of the first channel region is disposed around the side of the first word line; A first bit line is formed, and the first bit line is electrically connected to the source region of the first semiconductor pillar; Two second semiconductor pillars and a gate located between the two second semiconductor pillars are formed on the substrate. The second semiconductor pillars have at least one source / drain region and a second channel region. The second channel region is disposed toward the gate. One end of the gate is electrically connected to the drain region of the first semiconductor pillar. The first semiconductor pillar, the gate, and the second semiconductor pillars are disposed parallel to the substrate. A second word line and a second bit line are formed, and the second word line and the second bit line are electrically connected to the source and drain regions of at least one of the two second semiconductor pillars, wherein the first word line, the second word line and the second bit line are perpendicular to the substrate, and the first bit line is disposed parallel to the substrate.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The number of the first semiconductor pillars is multiple, and the multiple first semiconductor pillars are stacked to form the first word line. Stacked initial semiconductor pillars are formed on the substrate, and a portion of the initial semiconductor pillars have a first channel region and source and drain regions located on both sides of the first channel region; An etching process is performed on the initial semiconductor pillar in the first channel region to form a first via. The first via penetrates a portion of the first channel region of the multiple stacked initial semiconductor pillars and exposes the substrate. The remaining first channel region, the drain region, and the source region constitute the first semiconductor pillar. The first letter is formed in the first through hole.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The method of forming the gate and the second semiconductor pillar includes: Prior to the step of forming the first semiconductor pillar, a first sacrificial layer is formed, the first sacrificial layer being spaced apart from the initial semiconductor pillar; After the step of forming the first semiconductor pillar, the portion of the initial semiconductor pillar other than the first semiconductor pillar is removed to form a gap layer, the gap layer exposing the end of the first semiconductor pillar in the drain region; A gate is formed in a portion of the gap layer, one end of which is electrically connected to the drain region of the first semiconductor pillar; The second semiconductor pillars are formed on both sides of the gate in the remaining portion of the gap layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The method for forming the second word line and the second bit line includes: The first sacrificial layer that is in contact with the second semiconductor pillar and the gate is removed to form a second sacrificial layer, the second sacrificial layer covering the sidewall of the second semiconductor pillar and the sidewall of the gate; The second sacrificial layer is etched to form a second via and a third via, the second via and the third via exposing the source and drain regions of at least one of the two second semiconductor pillars disposed on the same layer and the substrate, respectively. A second word line is formed in the second through hole, and a second bit line is formed in the third through hole.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The second semiconductor pillar has one source / drain region, which is arranged along the first direction with the channel region. The second via and the third via expose the source / drain regions of the two second semiconductor pillars disposed in the same layer. The first direction is the direction in which the second semiconductor pillar points to the gate.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, The second semiconductor pillar has two source / drain regions, and the two source / drain regions are located on opposite sides of the channel region in a second direction, which is the extension direction of the second semiconductor pillar. The second via and the third via expose the two source / drain regions in the same second semiconductor pillar.

14. The method for preparing a semiconductor structure according to claim 9, characterized in that, The substrate surface has a plurality of first semiconductor pillars spaced apart along a third direction, the third direction being parallel to the substrate surface. The method for forming the first bit line includes: The first bit line is formed on the top surface of the first semiconductor pillar in the source region, the bottom surface of the first semiconductor pillar in the source region, and both sides of the first semiconductor pillar in the source region in the third direction. The formed first bit line covers the side surface of the first semiconductor pillar in the source region of each of the first semiconductor pillars arranged in the third direction.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, In the first semiconductor pillars arranged along the third direction, the distance between adjacent first semiconductor pillars is a first distance, and in the first semiconductor pillars stacked together, the distance between adjacent first semiconductor pillars is a second distance, wherein the first distance is less than the second distance.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The ratio of the second distance to the first distance is greater than 4.

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