Semiconductor structure, method of making the same, and memory array structure

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof and a memory array structure, the structure comprising: a substrate and a plurality of semiconductor pillars formed on the substrate, the semiconductor pillars extending along a first direction and arranged along a second direction and a third direction, the semiconductor pillars comprising a channel region, a source and a drain, the source and the drain being located on opposite sides of the channel region; a word line surrounding the channel region of the semiconductor pillar, the word line extending along the third direction, and along the third direction, a plurality of semiconductor pillars being connected to the same word line; a bit line connected to one of the source or the drain of the semiconductor pillar, the bit line extending along the second direction, and along the second direction, a plurality of semiconductor pillars being connected to the same bit line; a capacitor structure connected to the other one of the source or the drain of the semiconductor pillar, the capacitor structure extending along the first direction; wherein the number of semiconductor pillars connected by at least two word lines is different, so as to reduce the parasitic capacitance in the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to a semiconductor structure, a method for fabricating the same, and a memory array structure. Background Technology

[0002] As the integration density of dynamic memory continues to increase, higher requirements are being placed on the arrangement of transistors in the dynamic memory array structure.

[0003] To further improve the integration density of semiconductor structures, three-dimensional semiconductor structures are being researched. A three-dimensional semiconductor structure refers to a three-dimensional stacked semiconductor structure, where the transistors are arranged in a stacked configuration. Three-dimensional stacked semiconductor structures are characterized by high density, large capacity, and high speed.

[0004] However, for three-dimensional semiconductor structures, how to reduce the parasitic capacitance between transistor structures has become an urgent problem to be solved. Summary of the Invention

[0005] This disclosure provides a semiconductor structure, a method for fabricating the same, and a memory array structure to reduce parasitic capacitance in the semiconductor structure.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate and a plurality of semiconductor pillars formed on the substrate, the semiconductor pillars extending along a first direction and arranged upward along a second direction and a third direction, each semiconductor pillar including a channel region, a source, and a drain, the source and drain being located on opposite sides of the channel region; a word line surrounding the channel region of the semiconductor pillars, the word line extending along a third direction and upward along the third direction, the plurality of semiconductor pillars connecting to the same word line; a bit line connecting one of the source or drain of the semiconductor pillars, the bit line extending along a second direction, the plurality of semiconductor pillars connecting to the same bit line along the second direction; and a capacitor structure connecting the other of the source or drain of the semiconductor pillars, the capacitor structure extending along the first direction; wherein at least two word lines are connected to a different number of semiconductor pillars.

[0007] In some embodiments, the maximum number of semiconductor pillars arranged along the second direction is A, and the maximum number of semiconductor pillars arranged along the third direction is B, wherein A≥B>1.

[0008] In some embodiments, along the second direction, the number of semiconductor pillars connected to a portion of the word line increases sequentially.

[0009] In some embodiments, along the second direction, the number of semiconductor pillars connected to a portion of the word lines increases sequentially and then decreases sequentially.

[0010] In some embodiments, along the second direction, the capacitor structure connected to the other of the source or drain of the semiconductor pillar is arranged in a stepped manner.

[0011] In some embodiments, the semiconductor structure further includes: a plurality of bit line extensions, which extend along a third direction and are arranged along a second direction, wherein different bit line extensions are connected to different bit lines at their bottoms along the second direction.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory array structure, including a semiconductor structure as described in any of the above embodiments, wherein the semiconductor structures are arranged along a first direction, and adjacent semiconductor structures are symmetrically arranged along bit lines along the first direction, and semiconductor pillars located in the same layer of adjacent semiconductor structures share the same bit line.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate and forming a plurality of semiconductor pillars on the substrate, the semiconductor pillars extending along a first direction and arranged along a second direction and a third direction, each semiconductor pillar including a channel region, a source, and a drain, the source and drain being located on opposite sides of the channel region; forming a word line connecting the channel region of the semiconductor pillars, the word line extending along a third direction and upward along the third direction, the plurality of semiconductor pillars being connected to the same word line, wherein at least two word lines are connected to different numbers of semiconductor pillars; forming a bit line connecting either the source or the drain of the semiconductor pillars, the bit line extending along a second direction, the plurality of semiconductor pillars being connected to the same bit line along the second direction; and forming a capacitor structure connecting either the source or the drain of the semiconductor pillars, the capacitor structure extending along the first direction.

[0014] In some embodiments, forming a plurality of semiconductor pillars includes: forming alternating layers of sacrificial layers and semiconductor layers on a substrate; forming a plurality of first insulating layers within the sacrificial layers and semiconductor layers, the first insulating layers extending along a first direction and spaced apart along a second direction; removing a portion of the sacrificial layers and semiconductor layers, at least a portion of the remaining sacrificial layers and semiconductor layers having a stepped structure; forming a second insulating layer that covers and fills the gaps between the first insulating layers, the remaining semiconductor layers serving as semiconductor pillars, the maximum number of semiconductor pillars arranged along the second direction being A, and the maximum number of semiconductor pillars arranged along the third direction being B, wherein A≥B>1.

[0015] In some embodiments, the thickness of both the sacrificial layer and the semiconductor layer is 20 nm to 60 nm.

[0016] In some embodiments, forming a word line includes: forming a first isolation layer along a second direction, a semiconductor pillar penetrating the first isolation layer, and a channel region of the semiconductor pillar located between the first isolation layers; and forming a word line on the surface of the semiconductor pillar between the first isolation layers.

[0017] In some embodiments, after forming the first isolation layer but before forming the word line, the method further includes forming a second isolation layer between the first isolation layers along a first direction, the second isolation layer being located between adjacent semiconductor pillars.

[0018] In some embodiments, after forming the first isolation layer and before forming the word line, the method further includes: forming an insulating layer that fills the gap between the source of the semiconductor pillar and the first isolation layer, and fills the gap between the drain of the semiconductor pillar and the first isolation layer.

[0019] In some embodiments, forming bit lines includes: removing one end of the source or drain of a portion of a semiconductor pillar along a second direction and forming multiple bit lines, wherein the bit lines have a stepped structure along the second direction.

[0020] In some embodiments, forming a bit line further includes forming a plurality of bit line extensions, the bit line extensions extending along a third direction and arranged along a second direction, wherein different bit line extensions are connected to different bit lines at their bottoms along the second direction.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: By extending the semiconductor pillars along a first direction and arranging them upwards along a second and third direction, the transistors formed corresponding to the semiconductor pillars can extend along the first direction and be arranged along the second and third directions, thereby increasing the transistor density; wherein, multiple semiconductor pillars connected to the same word line along the third direction and multiple semiconductor pillars connected to the same bit line along the second direction can reduce the control terminals of word lines and bit lines in the semiconductor structure; the capacitor structure connected to the source or drain of the semiconductor pillars extends along the first direction, which can help increase the aspect ratio of the capacitor structure, that is, the ratio of length to width or diameter, thereby increasing the distance between capacitor structures of adjacent transistors, avoiding the generation of parasitic capacitance between capacitor structures, and compared with the vertical transistor structure, it can avoid tilting when the aspect ratio of the capacitor structure is large, thus avoiding damage to the semiconductor structure; wherein, the number of semiconductor pillars connected to at least two word lines is different, which can appropriately reduce the number of semiconductor pillars arranged, and correspondingly increase the spacing between the transistor structure and the capacitor structure formed by the semiconductor pillars, thereby avoiding the generation of parasitic capacitance in the high-density stacked structure that affects the performance of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figures 2 to 12 This is a schematic diagram of the various steps corresponding to a method for fabricating a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0025] As is known from the background art, parasitic capacitance exists in three-dimensional semiconductor structures.

[0026] Analysis reveals that Dynamic Random Access Memory (DRAM) utilizes capacitors to store a certain amount of charge. Some DRAM capacitor structures include cup-shaped or cylindrical capacitors, where one electrode is formed as a container, and the dielectric material and the other electrode are formed inside the container-shaped electrode (e.g., a single-sided via capacitor structure); or only outside the container-shaped electrode (e.g., a single-sided pillar capacitor structure); or both inside and outside the container-shaped electrode (e.g., a double-sided capacitor structure). To increase the integration density of semiconductor structures, transistors are arranged in a stacked configuration, which increases the stacking density between the corresponding capacitor structures, resulting in a decrease in the distance between adjacent capacitor structures and an increase in parasitic capacitance.

[0027] According to some embodiments of the present disclosure, one embodiment of the present disclosure provides a semiconductor structure to reduce parasitic capacitance in the semiconductor structure.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0030] refer to Figure 1 The semiconductor structure includes: a substrate (not shown) and a plurality of semiconductor pillars 100 formed on the substrate. The semiconductor pillars 100 extend along a first direction X and are arranged along a second direction Y and a third direction Z. Each semiconductor pillar 100 includes a channel region, a source, and a drain, with the source and drain located on opposite sides of the channel region; a word line 101 surrounds the channel region of the semiconductor pillars 100 and extends along a third direction Z and is arranged upwards along the third direction Z. The plurality of semiconductor pillars 100 are connected to the same word line 101; a bit line 102 connects to either the source or the drain of the semiconductor pillars 100 and extends along a second direction Y and is arranged upwards along the second direction Y. The plurality of semiconductor pillars 100 are connected to the same bit line 102; and a capacitor structure 103 connects to the other of the source or the drain of the semiconductor pillars 100 and extends along the first direction X. At least two word lines 101 are connected to a different number of semiconductor pillars 100.

[0031] By extending the semiconductor pillars 100 along the first direction X and arranging them along the second direction Y and the third direction Z, the transistors formed corresponding to the semiconductor pillars 100 can extend along the first direction X and be arranged along the second direction Y and the third direction Z, thereby increasing the transistor density. Multiple semiconductor pillars 100 connected along the third direction Z are connected to the same word line 101, and multiple semiconductor pillars 100 connected along the second direction Y are connected to the same bit line 102, which reduces the number of control terminals for the word line 101 and bit line 102 in the semiconductor structure. The capacitor structure 103, connected to the source or drain of the semiconductor pillars 100, extends along the first direction X, which helps to increase the number of capacitor junctions. The aspect ratio of structure 103, i.e., the ratio of length to width or diameter, increases the distance between capacitor structures 103 of adjacent transistors, avoiding parasitic capacitance between capacitor structures 103. Compared with vertical transistor structures, it can prevent tilting when the aspect ratio of capacitor structure 103 is large, thus avoiding damage to the semiconductor structure. In particular, the number of semiconductor pillars 100 connected by at least two word lines 101 is different, which can appropriately reduce the number of semiconductor pillars 100 arranged, increasing the spacing between the transistors formed by semiconductor pillars 100 and the capacitor structures 103, thereby avoiding parasitic capacitance in high-density stacked structures from affecting the performance of the semiconductor structure.

[0032] It should be noted that in this embodiment, the angle between the first direction X and the second direction Y is 90°, and the plane containing the first direction X and the second direction Y is parallel to the surface of the substrate, while the third direction Z is perpendicular to the surface of the substrate. That is, the angle between the plane containing the first direction and the second direction and the third direction is 90°. In other embodiments, the angle between the first direction X and the second direction Y can be 30°, 45°, or 60°, and the angle between the plane containing the first direction and the second direction and the surface of the substrate can be 30°, 45°, or 90°. In this embodiment, the angle between the third direction and the surface of the substrate can be 30°, 45°, or 60°, and the angle between the plane containing the first direction and the second direction and the third direction can be 30°, 45°, or 60°. This embodiment does not constitute a limitation on the angle between the first direction, the second direction, and the third direction.

[0033] For the semiconductor pillar 100, the material of the semiconductor pillar 100 includes elemental semiconductor materials or crystalline inorganic compound semiconductor materials. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium ionide. The material of the semiconductor pillar 100 can also be IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), or ITO (indium tin oxide).

[0034] In this embodiment, the semiconductor pillar 100 is a square prism; in other embodiments, the semiconductor pillar can also be a polygonal prism, a cylinder, or an elliptical cylinder. This embodiment does not constitute a limitation on the shape of the semiconductor pillar. It is understood that when the semiconductor pillar is a cylinder or an elliptical cylinder, the surface of the semiconductor pillar can be smoothly transitioned to avoid point discharge or leakage in the transistor structure formed by the semiconductor pillar during operation; when the semiconductor pillar is a square prism or a polygonal prism, the edges of the semiconductor pillar can be chamfered to make the edges of the semiconductor pillar transition smoothly, which can also avoid the formation of sharp points that could lead to leakage or discharge.

[0035] It should be noted that, in this embodiment, the source of the semiconductor pillar is used to connect to the bit line, and the drain of the semiconductor pillar is used to connect to the capacitor structure. The specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection methods of "drain" replacing "source" and "source" replacing "drain" can be used. The accompanying drawings provided in this embodiment only show a schematic diagram of the arrangement structure of some semiconductor pillars in the semiconductor structure and do not constitute a limitation on the number of semiconductor pillars arranged.

[0036] In some embodiments, the maximum number of semiconductor pillars arranged along the second direction is A, and the maximum number of semiconductor pillars arranged along the third direction is B, where A ≥ B > 1. Since the number of semiconductor pillars connected by at least two word lines is different, by setting the maximum number of semiconductor pillars arranged along the second direction to A and the maximum number arranged along the third direction to B, where A ≥ B > 1, that is, the number of semiconductor pillars arranged laterally is greater than the number stacked vertically, the arrangement of semiconductor pillars can form a stepped structure, thereby appropriately reducing the arrangement density of semiconductor pillars, and thus increasing the spacing between the corresponding capacitor structures of the transistors formed by the semiconductor pillars, reducing the parasitic capacitance between the transistor structures.

[0037] Continue to refer to Figure 1 In some embodiments, along the second direction Y, the number of semiconductor pillars 100 connected to some word lines 101 increases sequentially. By gradually increasing the number of semiconductor pillars in a sequential manner, the corresponding transistor structures can be arranged in a stepped structure, thereby appropriately reducing the arrangement density of transistor structures and reducing the parasitic capacitance between transistor structures.

[0038] In other embodiments, along the second direction, the number of semiconductor pillars connected to some word lines increases sequentially and then decreases sequentially. By gradually increasing and then decreasing the number of semiconductor pillars, the resulting transistor structure can be arranged in a pyramid structure, thereby appropriately reducing the transistor density and lowering the parasitic capacitance between transistor structures.

[0039] Furthermore, in some embodiments, along the second direction, the capacitor structures connected to the source or drain of the semiconductor pillar are arranged in a stepped manner. It is understood that the capacitor structures extend in the same direction as the semiconductor pillars. When the semiconductor pillars are arranged in a stepped or pyramidal shape, the capacitor structures connected to the drain of the semiconductor pillars are correspondingly arranged in a stepped or pyramidal shape, thereby increasing the spacing between the capacitor structures and reducing the parasitic capacitance between them.

[0040] For word line 101, the material of word line 101 includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper or tungsten.

[0041] In this embodiment, the word line 101 is disposed around the semiconductor pillar 100; in other embodiments, the word line may also pass through the interior of the semiconductor pillar, i.e., the channel region wraps around the word line. This forms a transistor with a fully encircling gate structure, increases the area of ​​the channel region to improve the transistor's current control capability, overcomes the short-channel effect, and thus improves the performance of the semiconductor structure.

[0042] In some embodiments, the surface of the word lines surrounding the semiconductor pillar may further include a dielectric layer. The dielectric layer covers the surface of the channel region of the semiconductor pillar, and the word lines surround the surface of the dielectric layer of the semiconductor pillar. The dielectric layer can prevent the word lines from reacting with the semiconductor pillar during subsequent processes, thereby avoiding damage to the semiconductor structure.

[0043] Further, refer to Figure 1 The semiconductor structure also includes an isolation layer 111, which extends along the second direction Y. Word lines 101 are located between adjacent isolation layers 111. Semiconductor pillars 100 pass through the isolation layer 111 along the first direction. The isolation layer 111 can separate word lines 101 from the source and drain of semiconductor pillars 100, thereby preventing leakage between the source or drain and the channel region in the transistor structure formed by semiconductor pillars 100, thus preventing the performance of the semiconductor structure from being affected.

[0044] For bit line 102, the material of bit line 102 can be a single metal, a metal compound, or an alloy. The single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. Setting the material of bit line 102 to a metallic material can give bit line 102 a lower resistivity, which is beneficial for reducing the resistance of bit line 102, increasing the transmission rate of electrical signals in bit line 102, reducing the parasitic capacitance of bit line 102, and reducing heat loss to reduce power consumption.

[0045] In some embodiments, reference Figure 1 The semiconductor structure also includes multiple bit line extensions 104, which extend along a third direction Z and are arranged along a second direction Y. Along the second direction Y, different bit line extensions 104 are connected to different bit lines 102 at their bottoms. It can be understood that as the number of stacked semiconductor pillars 100 is gradually increased in an incremental manner, the number of semiconductor pillars 100 connected to the bit lines 102 from bottom to top gradually decreases. Correspondingly, the length of the bit lines 102 can be gradually shortened from bottom to top, i.e., the bit lines 104 can form a stepped structure. Furthermore, the extension direction of the bit lines 102 can be changed from the second direction Y to the third direction Z through the bit line extensions 104. The control terminals of the corresponding bit lines 102 and word lines 101 can be located in the same direction to facilitate the connection of the corresponding control ports of the bit lines 102. In addition, the stepped structure formed by the bit lines 104 can be set within the memory area without occupying space in the peripheral area, further improving the integration of the semiconductor structure.

[0046] For bit line extension 104, the material of bit line extension 104 can be a single metal, a metal compound, or an alloy. Among them, the single metal can be copper, aluminum, tungsten, gold, or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver.

[0047] In this embodiment, the bit line extension 104 is made of the same material as the bit line 102 and is characterized by the same features, thereby reducing the contact resistance between the bit line and the bit line contact line; in other embodiments, the bit line extension may be made of a different material than the bit line.

[0048] The semiconductor structure provided in this disclosure, by extending the semiconductor pillars 100 along a first direction X and arranging them along a second direction Y and a third direction Z, allows the transistors formed corresponding to the semiconductor pillars 100 to extend along the first direction X and be arranged along the second direction Y and the third direction Z, thereby increasing the transistor density. Wherein, multiple semiconductor pillars 100 along the third direction Z are connected to the same word line 101, and multiple semiconductor pillars 100 along the second direction Y are connected to the same bit line 102, the control terminals of the word line 101 and bit line 102 in the semiconductor structure can be reduced. The capacitor structure 103, connected to the source or drain of the semiconductor pillars 100, extends along the first direction X, and can... This design facilitates an increase in the aspect ratio of the capacitor structure 103, i.e., the ratio of its length to its width or diameter, thereby increasing the distance between adjacent transistors and preventing parasitic capacitance between the capacitor structures 103. Compared to a vertical transistor structure, this design also prevents tilting when the aspect ratio of the capacitor structure 103 is large, thus avoiding damage to the semiconductor structure. Furthermore, the different numbers of semiconductor pillars 100 connected to at least two word lines 101 can appropriately reduce the number of semiconductor pillars 100, increasing the spacing between the transistors formed by the semiconductor pillars 100 and the corresponding capacitor structures. This prevents parasitic capacitance from affecting the performance of the semiconductor structure in a high-density stacked structure.

[0049] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory array structure, including any of the semiconductor structures described in the above embodiments, to reduce parasitic capacitance in the semiconductor structure.

[0050] The memory array structure includes semiconductor structures arranged along a first direction, wherein adjacent semiconductor structures are symmetrically arranged along bit lines along the first direction, and semiconductor pillars in the same layer of adjacent semiconductor structures share the same bit line. By continuing to arrange the semiconductor structures in the above embodiment along the first direction, and having adjacent semiconductor structures in the same layer share the same bit line, the arrangement density of the semiconductor structures can be appropriately increased, while the control capability of the bit lines can be increased, thereby improving the performance of the semiconductor structures.

[0051] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure to reduce parasitic capacitance in the semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0052] Figures 2 to 12 This is a schematic diagram of the structural steps corresponding to the method for fabricating a semiconductor structure provided in another embodiment of the present disclosure, wherein, Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the AA1 direction. Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure along the BB1 ​​direction. Figure 8 for Figure 6 Top view of a semiconductor structure. Figure 9 for Figure 6 A schematic diagram of the cross-sectional structure along the BB1 ​​direction. Figure 10 and Figure 11 All Figure 6 The left view of the semiconductor structure is shown below. The fabrication method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0053] A substrate is provided, and a plurality of semiconductor pillars are formed on the substrate. The semiconductor pillars extend along a first direction and are arranged along a second direction and a third direction. The semiconductor pillars include a channel region, a source, and a drain, with the source and drain located on opposite sides of the channel region.

[0054] Specifically, refer to Figures 2 to 6 Multiple semiconductor pillars are formed, including: reference Figure 2 An alternating layer of sacrificial layer 201 and semiconductor layer 202 is formed on substrate 200; Reference Figure 3 A plurality of first insulating layers 203 are formed within the sacrificial layer 201 and the semiconductor layer 202. The first insulating layers 203 extend along a first direction X and are spaced apart along a second direction Y. (Reference) Figure 4 Remove part of the sacrificial layer 201 and semiconductor layer 202, refer to Figure 5 At least a portion of the remaining sacrificial layer 201 and semiconductor layer 202 have a stepped structure; Reference Figure 6 A second insulating layer 204 is formed, which covers and fills the gaps between the first insulating layers 203. The remaining semiconductor layer 202 serves as semiconductor pillars 212. The maximum number of semiconductor pillars 212 arranged along the second direction Y is A, and the maximum number of semiconductor pillars 212 arranged along the third direction Z is B, where A≥B>1.

[0055] By setting the maximum number of semiconductor pillars arranged along the second direction as A and the maximum number arranged along the third direction as B, where A≥B>1, that is, the number of semiconductor pillars arranged laterally is greater than the number of pillars stacked vertically, the arrangement of semiconductor pillars can form a stepped structure, thereby appropriately reducing the arrangement density of semiconductor pillars, and thus increasing the spacing between the corresponding capacitor structures of the transistors formed by the semiconductor pillars, reducing the parasitic capacitance between the transistor structures.

[0056] It should be noted that in this embodiment, the number of alternating layers of sacrificial layer 201 and semiconductor layer 202 is 3, that is, the number of layers of sacrificial layer 201 is 3 and the number of layers of semiconductor layer 202 is 3. In other embodiments, the number of alternating layers of sacrificial layer 201 and semiconductor layer 202 can also be 4, 6, 10 or 20, that is, the number of layers of sacrificial layer 201 and semiconductor layer 202 are both 4, 6, 10 or 20. This embodiment does not constitute a limitation on the number of alternating layers of sacrificial layer 201 and semiconductor layer 202.

[0057] For the substrate 200, the material forming the substrate 200 includes elemental semiconductor materials or crystalline inorganic compound semiconductor materials. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0058] For semiconductor layer 202, the material forming the semiconductor layer includes elemental semiconductor materials or crystalline inorganic compound semiconductor materials. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0059] For the sacrificial layer 201, the material forming the sacrificial layer 201 includes silicon germanide.

[0060] For the first insulating layer 203 and the second insulating layer 204, the materials forming the first insulating layer 203 and the second insulating layer 204 include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0061] In this embodiment, the material 203 forming the first insulating layer is the same as the material forming the second insulating layer 204, and is represented by the same features; in other embodiments, the material forming the first insulating layer may be different from the material forming the second insulating layer.

[0062] In some embodiments, the thickness of both the sacrificial layer and the semiconductor layer is 20nm to 60nm. It is understood that the semiconductor layer is used to form semiconductor pillars. A larger semiconductor layer thickness results in a larger diameter of the semiconductor pillars, reducing the number of stacked semiconductor pillars per unit space; conversely, a thinner semiconductor layer thickness results in a smaller diameter of the semiconductor pillars, increasing the density of the pillars and reducing the distance between capacitor structures. This can lead to parasitic capacitance between capacitor structures, affecting the performance of the semiconductor structure. Therefore, the thickness of the semiconductor layer needs to be adjusted within a certain range to maximize the density of the semiconductor pillars while minimizing parasitic capacitance between capacitor structures, thus improving the reliability of the semiconductor structure. Similarly, the sacrificial layer is located between the semiconductor layers, and its thickness corresponds to the distance between the semiconductor pillars. The distance between these pillars needs to be adjusted within a certain range according to the arrangement requirements of the semiconductor pillars to avoid the semiconductor structure performance being affected by excessively close spacing, while also preventing the semiconductor structure's integration density from decreasing due to excessively large spacing.

[0063] Furthermore, word lines are formed, which connect to the channel regions of semiconductor pillars. The word lines extend in a third direction and upward in a third direction. Multiple semiconductor pillars are connected to the same word line, wherein at least two word lines are connected to a different number of semiconductor pillars.

[0064] Specifically, refer to Figure 7 The word line is formed by: forming a first isolation layer 205 along the second direction Y, semiconductor pillars 212 penetrating the first isolation layer 205, and the channel region of the semiconductor pillars 212 being located between the first isolation layers 205; and forming word lines 206 on the surface of the semiconductor pillars 212 between the first isolation layers 205.

[0065] In some embodiments, a dielectric layer 216 is formed before forming the word line 206. The dielectric layer 216 covers the surface of the channel region of the semiconductor pillar 212. The word line 206 surrounds the surface of the dielectric layer 216 of the semiconductor pillar 212. The dielectric layer 216 can prevent the word line 206 from reacting with the semiconductor pillar 212 during subsequent processes, thereby avoiding damage to the semiconductor structure.

[0066] For word line 206, the material forming word line 206 includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, tantalum, copper, aluminum, lanthanum, copper or tungsten.

[0067] For the first isolation layer 205, the material forming the first isolation layer 205 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0068] For dielectric layer 216, the material forming dielectric layer 216 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0069] In this embodiment, the material forming the dielectric layer 216 is the same as the material forming the first insulating layer 203 and is represented by the same features; in other embodiments, the material forming the dielectric layer may be different from the material forming the first insulating layer.

[0070] refer to Figure 8 In some embodiments, after forming the first isolation layer 205 and before forming the word lines 206, the method further includes forming a second isolation layer 207 between the first isolation layers 205 along a first direction X, wherein the second isolation layer 207 is located between adjacent semiconductor pillars 212. The first isolation layer 205 and the second isolation layer 207 can isolate different word lines 206, preventing interconnection between adjacent word lines 206 from affecting the performance of the semiconductor structure and improving the stability of the semiconductor structure.

[0071] For the second isolation layer 207, the materials forming the second isolation layer 207 include silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0072] In this embodiment, the material forming the first isolation layer 205 is the same as the material forming the second isolation layer 207, and is represented by the same features; in other embodiments, the material forming the first isolation layer may be different from the material forming the second isolation layer.

[0073] refer to Figure 9 In some embodiments, after forming the first isolation layer 205 and before forming the word line 206, the method further includes forming an insulating layer 208. The insulating layer 208 fills the gap between the source of the semiconductor pillar 212 and the first isolation layer 205, and also fills the gap between the drain of the semiconductor pillar 212 and the first isolation layer 205. Filling the gaps between the semiconductor pillars with the insulating layer can isolate transistor structures formed by different semiconductor pillars, preventing interconnection between adjacent transistor structures and improving the reliability of the semiconductor structure.

[0074] A bit line is formed, which connects to either the source or drain of a semiconductor pillar. The bit line extends along a second direction, and multiple semiconductor pillars are connected to the same bit line along the second direction.

[0075] Specifically, refer to Figure 10 The formation of bit line 209 includes: removing one end of the source or drain of a portion of the semiconductor pillar 212 along the second direction Y, and forming multiple bit lines 209, wherein the bit lines 209 have a stepped structure along the second direction Y.

[0076] Further, refer to Figure 11In some embodiments, forming the bit line 209 further includes forming a plurality of bit line extension lines 219. The bit line extension lines 219 extend along a third direction Z and are arranged along a second direction Y. Along the second direction Y, the bottoms of different bit line extension lines 219 are connected to different bit lines 209. The extension direction of the bit line can be changed from the second direction to the third direction through the bit line extension lines. The control terminal of the corresponding bit line and the control terminal of the word line can be located in the same direction to facilitate the connection of the corresponding control ports.

[0077] refer to Figure 12 A capacitor structure 300 is formed, which is connected to the source or drain of the semiconductor pillar 212. The capacitor structure 300 extends along the first direction X.

[0078] Specifically, the capacitor structure 300 includes a lower electrode layer 301, a capacitor dielectric layer 302, and an upper electrode layer 303. The lower electrode layer 301 covers the surface of the source or drain of the semiconductor pillar 212, the capacitor dielectric layer 302 covers the surface of the lower electrode layer 301, and the upper electrode layer 303 covers the surface of the capacitor dielectric layer 302.

[0079] For the lower electrode layer 301 and the upper electrode layer 303, the materials forming the lower electrode layer 301 and the upper electrode layer 303 can be at least one of platinum nickelide, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. For the capacitor dielectric layer 302, the materials forming the capacitor dielectric layer 302 include high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0080] In this embodiment, the material forming the upper electrode layer 303 is the same as the material forming the lower electrode layer 301, and is represented by the same features; in other embodiments, the material forming the upper electrode layer and the material forming the lower electrode layer may be different.

[0081] The semiconductor structure fabrication method provided in this disclosure, by forming semiconductor pillars 212 extending along a first direction X and arranged along a second direction Y and a third direction Z, allows the transistor structures corresponding to the semiconductor pillars 212 to extend along the first direction X and be arranged along the second direction Y and the third direction Z, thereby increasing the arrangement density of the transistor structures. Multiple semiconductor pillars 212 along the third direction Z are connected to the same word line 206, and multiple semiconductor pillars 212 along the second direction Y are connected to the same bit line 209, which can reduce the number of control terminals of the word line 206 and bit line 209 in the semiconductor structure. The capacitor structure 300 connected to the source or drain of the semiconductor pillars 212 extends along the first direction X. The X-extension can help increase the aspect ratio of the capacitor structure 300, that is, the ratio of length to width or diameter, thereby increasing the distance between capacitor structures 300 of adjacent transistors, avoiding the generation of parasitic capacitance between capacitor structures 300, and compared with the vertical transistor structure, it can avoid tilting when the aspect ratio of the capacitor structure 300 is large, thus avoiding damage to the semiconductor structure. In particular, the number of semiconductor pillars 212 connected by at least two word lines 206 is different, which can appropriately reduce the number of semiconductor pillars 212, increasing the spacing between the transistors formed by the semiconductor pillars 212 and the corresponding capacitor structures, thereby avoiding the generation of parasitic capacitance in the high-density stacked structure that affects the performance of the semiconductor structure.

[0082] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a plurality of semiconductor pillars formed on the substrate, the semiconductor pillars extending along a first direction and arranged upward along a second direction and a third direction, each semiconductor pillar including a channel region, a source and a drain, the source and the drain being located on opposite sides of the channel region, the first direction intersecting the second direction, the plane containing the first direction and the second direction being parallel to the surface of the substrate, and the third direction intersecting the surface of the substrate; A word line surrounds the channel region of the semiconductor pillar, the word line extends in a third direction and upward in the third direction, and multiple semiconductor pillars are connected to the same word line; Bit lines are connected to either the source or drain of the semiconductor pillars, the bit lines extend along the second direction, and along the second direction, a plurality of semiconductor pillars are connected to the same bit line; A capacitor structure is connected to the source or drain of the semiconductor pillar, and the capacitor structure extends along the first direction; At least two of the word lines are connected to a different number of semiconductor pillars.

2. The semiconductor structure as described in claim 1, characterized in that, Along the second direction, the maximum number of semiconductor pillars is A, and along the third direction, the maximum number of semiconductor pillars is B, where A ≥ B > 1.

3. The semiconductor structure as described in claim 2, characterized in that, Along the second direction, the number of semiconductor pillars connected to a portion of the word lines increases sequentially.

4. The semiconductor structure as described in claim 2, characterized in that, Along the second direction, the number of semiconductor pillars connected to a portion of the word lines first increases and then decreases sequentially.

5. The semiconductor structure as described in any one of claims 3 or 4, characterized in that, Along the second direction, the capacitor structure connected to the source or drain of the semiconductor pillar is arranged in a stepped manner.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: Multiple bit line extension lines extend along the third direction and are arranged along the second direction, with different bit lines connected to different bit lines at their bottoms along the second direction.

7. A memory array structure comprising the semiconductor structure as described in any one of claims 1 to 6, characterized in that, The semiconductor structures are arranged along the first direction, and adjacent semiconductor structures are symmetrically arranged along the bit line along the first direction. The semiconductor pillars located in the same layer of adjacent semiconductor structures share the same bit line.

8. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a plurality of semiconductor pillars are formed on the substrate. The semiconductor pillars extend along a first direction and are arranged upward along a second direction and a third direction. Each semiconductor pillar includes a channel region, a source, and a drain. The source and the drain are located on opposite sides of the channel region. The first direction intersects the second direction. The plane containing the first direction and the second direction is parallel to the surface of the substrate. The third direction intersects the surface of the substrate. A word line is formed, the word line surrounds the channel region of the semiconductor pillar, the word line extends in a third direction and upward in the third direction, and a plurality of semiconductor pillars are connected to the same word line, wherein at least two word lines are connected to a different number of semiconductor pillars; A bit line is formed, the bit line being connected to either the source or the drain of the semiconductor pillar, the bit line extending along a second direction, and along the second direction, a plurality of semiconductor pillars being connected to the same bit line; A capacitor structure is formed, the capacitor structure being connected to the source or drain of the semiconductor pillar, the capacitor structure extending along the first direction.

9. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The formation of multiple semiconductor pillars includes: Alternating layers of sacrificial and semiconductor layers are formed on the substrate; A plurality of first insulating layers are formed within the sacrificial layer and the semiconductor layer, the first insulating layers extending along the first direction and spaced apart along the second direction; The sacrificial layer and the semiconductor layer are partially removed, leaving at least a portion of the remaining sacrificial layer and semiconductor layer in a stepped structure; A second insulating layer is formed, which covers and fills the gaps between the first insulating layers. The remaining semiconductor layer serves as the semiconductor pillars. The maximum number of semiconductor pillars arranged along the second direction is A, and the maximum number of semiconductor pillars arranged along the third direction is B, where A ≥ B > 1.

10. The method for fabricating a semiconductor structure as described in claim 9, characterized in that, The thickness of both the sacrificial layer and the semiconductor layer is 20nm~60nm.

11. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, Forming the word line includes: A first isolation layer is formed along the second direction, the semiconductor pillar penetrates the first isolation layer, and the channel region of the semiconductor pillar is located between the first isolation layers; The word lines are formed on the surface of the semiconductor pillars between the first isolation layers.

12. The method for fabricating a semiconductor structure as described in claim 11, characterized in that, After forming the first isolation layer and before forming the word line, the method further includes: forming a second isolation layer between the first isolation layers along the first direction, the second isolation layer being located between adjacent semiconductor pillars.

13. The method for fabricating a semiconductor structure as described in claim 11, characterized in that, After forming the first isolation layer and before forming the word line, the method further includes: forming an insulating layer that fills the gap between the source of the semiconductor pillar and the first isolation layer, and fills the gap between the drain of the semiconductor pillar and the first isolation layer.

14. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, Forming the bit lines includes: removing one end of the source or drain of a portion of the semiconductor pillar along the second direction, and forming a plurality of the bit lines, wherein the bit lines have a stepped structure along the second direction.

15. The method for fabricating a semiconductor structure as described in claim 14, characterized in that, Forming the bit line further includes: forming a plurality of bit line extension lines, the bit line extension lines extending along the third direction and arranged along the second direction, wherein the bottom of different bit line extension lines are connected to different bit lines along the second direction.

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