An LDMOSFET device and a method of fabricating the same

Abstract

This application belongs to the field of semiconductor technology and provides an LDMOSFET device and its fabrication method. The LDMOSFET device includes: an N-type substrate, an insulating layer, a P-type well region, a source region, a P-type base region, a drain region, a drift region, a passivation layer, a source electrode, a drain electrode, a gate electrode, and a gate extension region. By setting a gate extension region between the gate electrode and the drain electrode, a low-resistance, high-concentration electron channel from the drain region to the source region can be formed above the drift region, reducing the on-resistance of the LDMOSFET device. Furthermore, by making the distance between the P-type base region and the N-type substrate layer smaller than the thickness of the insulating layer, the potential lines are dispersed, resulting in a uniform electric field distribution within the drift region. This avoids electric field concentration near the drain region, thereby increasing the device's breakdown voltage. This solves the problem of existing LDMOSFET devices failing to balance breakdown voltage and on-resistance.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to an LDMOSFET device and its fabrication method. Background Technology

[0002] With the increasing integration density of integrated circuits, laterally diffused metal-oxide-semiconductor (LDMOSFET) is frequently used in the design of high-voltage power integrated circuits due to its outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. It is particularly prevalent in high-voltage power amplifiers. One important parameter of LDMOSFET is its on-resistance. In practical applications, on-resistance is a crucial parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOSFET.

[0003] For high-performance power devices, in addition to high breakdown voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between breakdown voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between breakdown voltage and on-resistance, minimizing on-resistance while maintaining a certain breakdown voltage to obtain the maximum possible output power. Some literature has studied the on-resistance of conventionally doped LDMOSFETs and yielded many results, but it has not fundamentally resolved the contradiction between on-resistance and breakdown voltage. The demand for high-performance devices has led to a research focus on simultaneously achieving high breakdown voltage and low on-resistance for LDMOSFETs.

[0004] This shows that existing LDMOSFET devices cannot achieve a balance between breakdown voltage and on-resistance. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides an LDMOSFET device and its fabrication method, which can solve the problem that existing LDMOSFET devices cannot achieve a balance between breakdown voltage and on-resistance.

[0006] This application provides an LDMOSFET device, the LDMOSFET device comprising:

[0007] Insulating layer;

[0008] An N-type substrate layer is disposed on the back side of the insulating layer;

[0009] A P-type well region is disposed on the front side of the insulating layer, and the P-type well region is L-shaped.

[0010] A P-type base region is disposed on the front side of the insulating layer; wherein the distance between the P-type base region and the N-type substrate layer is less than the thickness of the insulating layer;

[0011] The source region is located on the horizontal portion of the P-type well region and is in contact with the P-type base region;

[0012] A drift region is located on the front side of the insulating layer and is in contact with the P-type well region;

[0013] The drain region is located on the drift region;

[0014] A passivation layer is disposed on the source region, the P-type well region, the drift region, and the drain region; wherein the passivation layer is L-shaped.

[0015] The source electrode is located on the P-type base region and the source region;

[0016] A gate electrode is disposed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is located between the gate electrode and the source electrode;

[0017] The drain electrode is in contact with the drain region;

[0018] A gate extension region is disposed on the horizontal portion of the passivation layer and located between the gate electrode and the drain electrode.

[0019] In one embodiment, the gate extension region includes:

[0020] A first P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the gate electrode;

[0021] The second P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the first P-type doped region;

[0022] The first N-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the second P-type doped region;

[0023] The third P-type doped region is located on the horizontal portion of the passivation layer and is in contact with the first N-type doped region.

[0024] In one embodiment, the doping concentration of the first P-type doped region is greater than the doping concentration of the second P-type doped region.

[0025] In one embodiment, the width of the second P-type doped region is greater than the width of the first P-type doped region.

[0026] In one embodiment, the doping concentration of the drift region gradually decreases from the central region to the left and right sides.

[0027] In one embodiment, the drift region is alternately arranged with the N-type substrate layer, and the P-type base region and the P-type well region are arranged opposite to the N-type substrate layer.

[0028] In one embodiment, the insulating layer has a stepped structure.

[0029] In one embodiment, the width of the gate electrode is greater than the width of the vertical portion of the P-type well region.

[0030] In one embodiment, the thickness of the P-type base region is equal to the sum of the thickness of the source region and the thickness of the horizontal portion of the P-type well region.

[0031] A second aspect of this application provides a method for fabricating an LDMOSFET device, comprising:

[0032] An insulating layer is formed by oxidizing the N-type substrate layer, such that the N-type substrate layer is located on the back side of the insulating layer;

[0033] A P-type well region, a P-type base region, and a drift region are sequentially formed on the front side of the insulating layer; wherein, the P-type well region is L-shaped, the distance between the P-type base region and the N-type substrate layer is less than the thickness of the insulating layer, and the drift region is in contact with the P-type well region;

[0034] A source region is formed on the horizontal portion of the P-type well region, and a drain region is formed on the drift region; wherein the source region is in contact with the P-type base region;

[0035] A passivation layer is formed on the source region, the P-type well region, the drift region, and the drain region; wherein the passivation layer is L-shaped.

[0036] A gate extension region is formed on the horizontal portion of the passivation layer;

[0037] A source electrode is formed on the source region and the P-type base region, a drain electrode is formed on the drain region, and a gate electrode is formed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is located between the gate electrode and the source electrode, and the gate extension region is located between the gate electrode and the drain electrode.

[0038] The beneficial effects of this application embodiment compared with the prior art are as follows: by setting a gate extension region between the gate electrode and the drain electrode, a low-resistance, high-concentration electron channel from the drain region to the source region can be formed above the drift region, thereby reducing the on-resistance of the LDMOSFET device. Furthermore, by making the distance between the P-type base region and the N-type substrate layer smaller than the thickness of the insulating layer, the thickness of the insulating layer below the drain electrode is made larger, thus dispersing the potential lines and making the electric field in the drift region uniformly distributed, avoiding the concentration of the electric field near the drain region, thereby improving the breakdown voltage of the device. This improves the breakdown voltage of the LDMOSFET device while reducing the on-resistance of the LDMOSFET device, solving the problem that existing LDMOSFET devices cannot achieve a balance between breakdown voltage and on-resistance. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of an LDMOSFET device provided in one embodiment of this application. Figure 1 ;

[0040] Figure 2 This is a schematic diagram of the structure of an LDMOSFET device provided in one embodiment of this application. Figure 2 ;

[0041] Figure 3 This is a schematic diagram of the structure of an LDMOSFET device provided in one embodiment of this application. Figure 3 ;

[0042] Figure 4 This is a schematic diagram of the structure of an LDMOSFET device provided in one embodiment of this application. Figure 4 ;

[0043] Figure 5 This is a schematic diagram of the structure of an LDMOSFET device provided in one embodiment of this application. Figure 5 ;

[0044] Figure 6 This is a schematic diagram of the structure of an LDMOSFET device provided in one embodiment of this application. Figure 6 ;

[0045] Figure 7 This is a schematic diagram of the fabrication steps of an LDMOSFET device provided in one embodiment of this application;

[0046] Figure 8 This is a schematic diagram of the insulating layer after formation according to an embodiment of this application;

[0047] Figure 9 This is a schematic diagram of the formation of a P-type well region, a P-type base region, and a drift region according to an embodiment of this application;

[0048] Figure 10 This is a schematic diagram of the formation of the source and drain regions provided in one embodiment of this application;

[0049] Figure 11 This is a schematic diagram of the passivation layer after formation according to an embodiment of this application;

[0050] Figure 12 This is a schematic diagram of forming a gate extension region provided in one embodiment of this application;

[0051] Figure 13 This is a schematic diagram of the formation of a gate electrode, a drain electrode, and a source electrode provided in one embodiment of this application. Detailed Implementation

[0052] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0053] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0054] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0056] With the increasing integration density of integrated circuits, laterally diffused metal-oxide-semiconductor (LDMOSFET) is frequently used in the design of high-voltage power integrated circuits due to its outstanding advantages such as high voltage resistance, large drive current, high output power, and good switching characteristics. It is particularly prevalent in high-voltage power amplifiers. One important parameter of LDMOSFET is its on-resistance. In practical applications, on-resistance is a crucial parameter closely related to performance, and its magnitude is closely related to the maximum output power of the LDMOSFET.

[0057] For high-performance power devices, in addition to high breakdown voltage, the lowest possible on-resistance is also required. On-resistance always decreases with increasing drift region doping concentration, while the relationship between breakdown voltage and drift region doping concentration is often complex. Therefore, we need to optimize the relationship between breakdown voltage and on-resistance, minimizing on-resistance while maintaining a certain breakdown voltage to obtain the maximum possible output power. Some literature has studied the on-resistance of conventionally doped LDMOSFETs and yielded many results, but it has not fundamentally resolved the contradiction between on-resistance and breakdown voltage. The demand for high-performance devices has made the research focus of LDMOSFETs on simultaneously achieving high breakdown voltage and low on-resistance. The breakdown voltage of an LDMOSFET in the off-state and its on-state on-resistance are both inversely proportional to the drift region concentration. Early LDMOSFETs had low breakdown voltages due to excessively high drift region concentration. Subsequent RESURF LDMOSFETs improved the breakdown voltage by reducing the drift region concentration, but this significantly increased the on-resistance.

[0058] This shows that existing LDMOSFET devices cannot achieve a balance between breakdown voltage and on-resistance.

[0059] To address the aforementioned technical problems, this application provides an LDMOSFET device, as shown in the following embodiment. Figure 1 As shown, the LDMOSFET device includes: an N-type substrate layer 10, an insulating layer 20, a P-type well region 50, a source region 60, a P-type base region 70, a drain region 40, a drift region 30, a passivation layer 80, a source electrode S, a drain electrode D, a gate electrode G, and a gate extension region 90.

[0060] Specifically, the N-type substrate layer 10 is disposed on the back side of the insulating layer 20; the P-type well region 50 is disposed on the front side of the insulating layer 20, and the P-type well region 50 is L-shaped; the P-type base region 70 is disposed on the front side of the insulating layer 20; wherein, the distance between the P-type base region 70 and the N-type substrate layer 10 is less than the thickness of the insulating layer 20; the source region 60 is disposed on the horizontal portion of the P-type well region 50, and the source region 60 is in contact with the P-type base region 70; the drift region 30 is disposed on the front side of the insulating layer 20, and the drift region 30 is in contact with the P-type well region 50; the drain region 40 is disposed on the drift region 50. The passivation layer 80 is disposed on the source region 60, the P-type well region 50, the drift region 30, and the drain region 40. The passivation layer 80 is L-shaped. The source electrode S is located on the P-type base region 70 and the source region 60. The gate electrode G is disposed on the horizontal portion of the passivation layer 80. The vertical portion of the passivation layer 80 is located between the gate electrode G and the source electrode S. The drain electrode D is in contact with the drain region 40. The gate extension region 90 is disposed on the horizontal portion of the passivation layer 80 and is located between the gate electrode G and the drain electrode D.

[0061] In this embodiment, the distance between the P-type base region 70 and the N-type substrate layer 10 is less than the thickness of the insulating layer 20. Specifically, refer to... Figure 1 As shown, the P-type base region 70 and the P-type well region 50 are both located on the front side of the insulating layer 20. The distance between the P-type base region 70 and the P-type well region 50 and the N-type substrate layer 10 is less than the thickness of the insulating layer 20. It can be understood that the thickness of the insulating layer 20 located under the P-type base region 70 and the P-type well region 50 is different from the thickness of the insulating layer 20 located under the drift region 30. Moreover, the thickness of the insulating layer 20 located under the P-type base region 70 and the P-type well region 50 is less than the thickness of the insulating layer 20 located under the drift region 30. In this way, the area of ​​the equipotential can be reduced, thereby dispersing the equipotential lines, making the equipotential lines uniformly distributed, and the electric field uniform, thereby weakening the electric field near the drain region 40, and thus increasing the breakdown voltage.

[0062] In this embodiment, the P-type well region 50, the P-type base region 70, and the drift region 30 are all disposed on the front side of the insulating layer 20. The P-type well region 50 is L-shaped, with a horizontal portion and a vertical portion. The source region 60 is disposed on the horizontal portion of the P-type well region 50. In a specific application embodiment, the upper surface of the source region 60 is flush with the upper surface of the vertical portion of the P-type well region 50, and the width of the source region 60 is equal to the width of the horizontal portion of the P-type well region 50. At this time, the source region 60 and the P-type well region 50 form a cuboid.

[0063] In this embodiment, the drift region 30 is L-shaped, with a horizontal portion and a vertical portion. The drain region 40 is disposed on the horizontal portion of the drift region 30, and the upper surface of the drain region 40 is flush with the upper surface of the vertical portion of the drift region 30. The width of the drain region 40 is the same as the width of the horizontal portion of the drift region 30. At this time, the drain region 40 and the drift region 30 form a cuboid.

[0064] In this embodiment, the passivation layer 80 is L-shaped, with a horizontal portion and a vertical portion. The gate electrode G and the gate extension region 90 are both disposed on the horizontal portion of the passivation layer 80, with the gate electrode G in contact with the vertical portion of the passivation layer 80, and the gate extension region 90 in contact with the gate electrode G. In a specific application embodiment, the upper surfaces of the gate electrode G and the gate extension region 90 are flush with the upper surface of the passivation layer 80, and the sum of the widths of the gate electrode G and the gate extension region 90 is equal to the sum of the widths of the horizontal portion of the passivation layer 80. In this case, the gate electrode G, the gate extension region 90, and the passivation layer 80 together form a cuboid. In this embodiment, by providing the gate extension region 90, a low-resistance, high-concentration electron channel from the drain region 40 to the source region 60 can be formed above the drift region 30, thereby reducing the on-resistance of the device.

[0065] In this embodiment, the source electrode S, drain electrode D, and gate electrode G are located on the same plane, which allows the source electrode S, drain electrode D, and gate electrode G to be formed in a single process, simplifying the electrode fabrication process and reducing electrode fabrication costs.

[0066] In this embodiment, a low-resistance, high-concentration electron channel from the drain region 40 to the source region 60 is formed above the drift region 30 by setting the gate extension region 90, thereby reducing the on-resistance of the device. By setting the thickness of the insulating layer 20 located under the P-type base region 70 and the P-type well region 50 to be less than the thickness of the insulating layer 20 under the drift region 30, the area of ​​the equipotential is reduced, thereby dispersing the equipotential lines, making the equipotential lines uniformly distributed, and the electric field uniform, thereby weakening the electric field near the drain region 40, thereby increasing the breakdown voltage. This provides a method that reduces the on-resistance while increasing the breakdown voltage of the device, solving the problem that existing LDMOSFET devices cannot achieve a balance between breakdown voltage and on-resistance.

[0067] In one embodiment, for the material of the insulating layer 20, silicon oxide is a commonly used material with mature technology. Alternatively, a low-K dielectric with a dielectric constant lower than that of silicon oxide can be used to improve the longitudinal withstand voltage and reduce the thickness of the insulating layer 20.

[0068] In one embodiment, reference Figure 2 As shown, the gate extension region 90 includes: a first P-type doped region 91, a second P-type doped region 92, a first N-type doped region 93, and a third P-type doped region 94.

[0069] Specifically, a first P-type doped region 91 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the gate electrode G; a second P-type doped region 92 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the first P-type doped region 91; a first N-type doped region 93 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the second P-type doped region 92; and a third P-type doped region 94 is disposed on the horizontal portion of the passivation layer 80 and is in contact with the first N-type doped region 93.

[0070] In this embodiment, the first P-type doped region 91 and the second P-type doped region 92 are doped with P-type dopant ions, and the doping concentration of the first P-type doped region 91 is greater than that of the second P-type doped region 92. The first N-type doped region 93 can be doped with N-type dopant ions, such as nitrogen ions or phosphorus ions. The third P-type doped region 94 can be doped with P-type dopant ions, such as aluminum ions. By doping with different elements, the first N-type doped region 93 and the third P-type doped region 94 form a PN junction, which can enhance the electric field above the passivation layer 80, thereby forming a low-resistance electron channel above the drift region 30 and reducing the on-resistance.

[0071] In one embodiment, the second P-type doped region 92 has the same doped ions as the first P-type doped region 91, but with a different doping concentration. It is different from the doped ions of the first N-type doped region 93. This can avoid the adverse effect on the longitudinal electric field strength of the drift region 30 after the second P-type doped region 92 is depleted in the device off-voltage state, and can improve the device's voltage withstand capability.

[0072] In one embodiment, reference Figure 2 As shown, the width of the second P-type doped region 92 is greater than the width of the first P-type doped region 91.

[0073] In this embodiment, the doping concentration of the second P-type doped region 92 is less than that of the first P-type doped region 91. By setting the width of the first P-type doped region 91 to be less than the width of the second P-type doped region 92, more low-resistance electron channels can be formed above the drift region 30, reducing the on-resistance and thus lowering the on-resistance of the device.

[0074] In one embodiment, reference Figure 3 As shown, the doping concentration of the drift region 30 gradually decreases from the central region to the left and right sides.

[0075] In this embodiment, the middle region of the drift region 30 has a higher doping concentration, while the drift region 30 near the drain region 40 and near the P-type well region 50 has a lower doping concentration. Since the electric field strength near the drain region 40 is relatively high, setting the drift region 30 near the drain region 40 to have a lower doping concentration can appropriately improve the breakdown voltage of the device. The drift region 30 near the P-type well region 50 has a lower doping concentration, which can appropriately weaken the electron channel induced by the gate electrode G in the drift region 30, thereby increasing the threshold voltage.

[0076] In one embodiment, reference Figure 3 As shown, the drift region 30 includes: a first drift unit 31, a second drift unit 32, and a third drift unit 33.

[0077] Specifically, the first drift unit 31 is L-shaped, and the drain region 40 is located on the horizontal part of the first drift unit 31; the second drift unit 32 is in contact with the first drift unit 31; the third drift unit 33 is in contact with the second drift unit 32, and the third drift unit 33 is in contact with the P-type well region 50; wherein, the doping concentration of the first drift unit 31 is less than the doping concentration of the second drift unit 32, and the doping concentration of the third drift unit 33 is less than the doping concentration of the second drift unit 32.

[0078] In this embodiment, the drift region 30 can be doped with N-type dopant ions. By using different doping concentrations in the drift region 30, the performance of the device can be improved. For example, if the doping concentration of the first drift unit 31 is set to be lower than that of the second drift unit 32, since the first drift unit 31 is closer to the drain region 40, the electric field strength near the drain region 40 is relatively large. By setting the doping concentration of the first drift unit 31 to be smaller, the electric field strength near the drain region 40 can be reduced, thereby increasing the breakdown voltage of the device. If the doping concentration of the third drift unit 33 is set to be lower than that of the second drift unit 32, since the third drift unit 33 is closer to the source region 60, the voltage required by the source region 60 is generally relatively large. By setting the doping concentration of the third drift unit 33 to be smaller, the electron channel induced by the gate electrode G in the drift region 30 can be appropriately weakened, thereby increasing the threshold voltage and improving the performance of the device.

[0079] In one embodiment, reference Figure 3 As shown, the doping concentration of the first drift unit 31 is equal to the doping concentration of the third drift unit 33.

[0080] In this embodiment, the doping concentration of the first drift unit 31 is equal to that of the third drift unit 33, and both are less than the doping concentration of the second drift unit 32. In this way, not only can the electric field strength near the drain region 40 be reduced and the breakdown voltage of the device be increased, but the voltage of the source region 60 can also be increased, thereby improving the overall performance of the device.

[0081] In one embodiment, reference Figure 3 As shown, the drift region 30 is staggered with the N-type substrate layer 10, and the P-type base region 70 and the P-type well region 50 are arranged opposite to the N-type substrate layer 10.

[0082] In this embodiment, the N-type substrate 10 is rectangular, and the insulating layer 20 has an "L"-shaped structure. Specifically, the lower surface of the N-type substrate 10 is flush with the lower surface of the vertical portion of the insulating layer 20, and the width of the N-type substrate 10 is the same as the width of the horizontal portion of the insulating layer 20. At this time, the N-type substrate 10 and the insulating layer 20 form a rectangle. By setting the drift region 30 and the N-type substrate 10 to be staggered, the area of ​​the equipotential can be reduced, thereby dispersing the equipotential lines, making the equipotential lines uniformly distributed, the electric field uniform, and reducing the electric field concentration at the drain region 40, thereby improving the breakdown voltage.

[0083] In one embodiment, reference Figure 4 As shown, the insulating layer 20 has a stepped structure.

[0084] In this embodiment, the insulating layer 20 has a stepped structure, and the N-type substrate layer 10 also has a stepped structure. The stepped structure of the N-type substrate layer 10 is complementary to the stepped structure of the insulating layer 20. For example, the thickness of the stepped structure of the N-type substrate layer 10 gradually decreases from the source electrode S to the drain electrode D. Conversely, the thickness of the stepped structure of the insulating layer 20 gradually increases from the source electrode S to the drain electrode D. By providing a thicker insulating layer 20 below the drain region 40, the area of ​​the equipotential can be reduced, the equipotential lines can be evenly distributed, and the electric field is evenly distributed inside the drift region 30, avoiding the concentration of the electric field at the drain, thereby improving the breakdown voltage of the device.

[0085] In one embodiment, reference Figure 5 As shown, the N-type substrate 10 has a trapezoidal structure, and the insulating layer 20 has a "slide" structure. Specifically, the trapezoidal structure of the N-type substrate 10 has a first inclined surface, and the "slide" structure of the insulating layer 20 has a second inclined surface. The first and second inclined surfaces are in contact, so that the N-type substrate 10 and the insulating layer 20 form a rectangle. The thickness of the second inclined surface of the insulating layer 20 gradually increases from the P-type well region 50 to the drain region 40, and the thickness of the first inclined surface of the N-type substrate 10 gradually increases and decreases from the P-type well region 50 to the drain region 40. The lower surface of the trapezoidal structure of the N-type substrate 10 is flush with the bottom surface of the "slide" structure of the insulating layer 20. At this time, the N-type substrate 10 and the insulating layer 20 form a rectangle. By increasing the thickness of the insulating layer 20 near the drain region 40, the potential lines can be dispersed, making the equipotential lines evenly distributed. The electric field is evenly distributed inside the drift region 30, avoiding the electric field concentration at the drain, thereby improving the breakdown voltage of the device.

[0086] In this embodiment, by oxidizing the N-type substrate layer 10 to different degrees, the area of ​​the insulating layer 20 is increased, thereby dispersing the potential lines and making the equipotential lines uniformly distributed. The electric field uniformly distributed inside the drift region 30 avoids the electric field concentration at the drain electrode, thereby improving the breakdown voltage of the device.

[0087] In one embodiment, the width of the gate electrode G is greater than the width of the vertical portion of the P-type well region 50.

[0088] In this embodiment, the gate electrode G is made of a metal material, such as copper, gold, or silver. By setting the width of the gate electrode G to be greater than the width of the vertical portion of the P-type well region 50, a high-concentration electron channel can be induced in the drift region 30 when the device is working, thereby reducing the on-resistance of the device.

[0089] In one embodiment, the thickness of the P-type base region 70 is equal to the sum of the thickness of the source region 60 and the thickness of the horizontal portion of the P-type well region 50.

[0090] In this embodiment, the thickness of the P-type base region 70 is greater than the thickness of the source region 60 because the P-type base region 70 is the voltage access point of the LDMOSFET device. By setting the thickness of the P-type base region 70 to be the sum of the thicknesses of the source region 60 and the horizontal portion of the P-type well region 50, the voltage can be better accessed, maintaining the stability of the LDMOSFET device and improving its performance.

[0091] In one embodiment, reference Figure 6 As shown, the LDMOSFET device also includes: multiple shallow trench isolation regions 100.

[0092] Specifically, multiple shallow trench isolation regions 100 are disposed within the second P-type doped region 92. The depth of the multiple shallow trench isolation regions 100 gradually increases from the source region 60 to the drain region 40. Specifically, the depth of the shallow trench isolation region 100 near the source region 60 is less than the depth of the shallow trench isolation region 100 near the drain region 40. The multiple shallow trench isolation regions 100 are formed by depositing, patterning, and etching silicon using a silicon nitride mask to form trenches, and then filling the trenches with deposited oxide. By setting multiple shallow trench isolation regions 100 within the second P-type doped region 92, a high electric field can be generated at the multiple shallow trench isolation regions 100, which can modulate the electric field distribution of the LDMOSFET device and improve the breakdown voltage of the LDMOSFET device.

[0093] In one embodiment, the passivation layer 80 is made of a high-K dielectric material. By using a high-K dielectric, the concentration of electron channels formed above the drift region 30 can be increased and the resistance can be reduced. In this way, the on-resistance of the LDMOSFET device can be reduced more effectively.

[0094] In one embodiment, the insulating layer 20 may be silicon oxide.

[0095] In one embodiment, the gate electrode G can be at least one of copper, gold, and silver.

[0096] In one embodiment, the drain electrode D can be at least one of copper, gold, and silver.

[0097] In one embodiment, the source electrode S can be at least one of copper, gold, and silver.

[0098] In one embodiment, the source region 60 and the drain region 40 can be used as pad materials for the corresponding electrodes, such as gallium nitride materials, or metal material layers.

[0099] This application also provides a method for fabricating an LDMOSFET device, see reference. Figure 7 As shown, it includes steps S100 to S600.

[0100] In step S100, refer to Figure 8 As shown, the N-type substrate 10 is oxidized to form an insulating layer 20, such that the N-type substrate 10 is located on the back side of the insulating layer 20.

[0101] In one specific application, a first oxide layer is first formed on the back side of the N-type substrate 10, and a portion of the front side of the N-type substrate 10 is oxidized to form a second oxide layer. Then, the first oxide layer and the second oxide layer constitute the insulating layer 20.

[0102] In step S200, refer to Figure 9 As shown, a P-type well region 50, a P-type base region 70, and a drift region 30 are sequentially formed on the front side of the insulating layer 20.

[0103] Specifically, the P-type well region 50 is L-shaped, the distance between the P-type base region 70 and the N-type substrate layer 10 is less than the thickness of the insulating layer 20, and the drift region 30 is in contact with the P-type well region 50.

[0104] In this embodiment, a P-type well region 50, a P-type base region 70, and a drift region 30 can be sequentially formed in a predetermined area on the front side of the insulating layer 20 by depositing semiconductor or metal materials.

[0105] In one embodiment, the insulating layer 20 is selectively etched to form regions of P-type well region 50, P-type base region 70 and drift region 30, respectively. Then, corresponding ionic materials are deposited to form the corresponding regions. For example, drift region 30 is formed by depositing N-type ions, and P-type well region 50 and P-type base region 70 are formed by depositing P-type ions.

[0106] In step S300, refer to Figure 10 As shown, a source region 60 is formed on the horizontal portion of the P-type well region 50, and a drain region 40 is formed on the drift region 30; wherein, the source region 60 is in contact with the P-type base region 70, and the drift region 30 has an "L" shaped structure.

[0107] In this embodiment, N-type ions are deposited on the horizontal portion of the P-type well region 50 to form the source region 60, and N-type ions are deposited on the horizontal portion of the drift region 30 to form the drain region 40. Furthermore, the drain region 40 and the source region 60 are heavily doped with N-type ions.

[0108] In step S400, refer to Figure 11 As shown, a passivation layer 80 is formed on the source region 60, the P-type well region 50, the drift region 30, and the drain region 40; wherein, the passivation layer 80 is L-shaped.

[0109] In this embodiment, selective etching is performed on the source region 60, the P-type well region 50, the drift region 30, and the drain region 40 to form a passivation layer 80.

[0110] In one embodiment, the passivation layer 80 is made of a high-K dielectric material. By using a high-K dielectric, the concentration of electron channels formed above the drift region 30 can be increased and the resistance can be reduced. In this way, the on-resistance of the LDMOSFET device can be reduced more effectively.

[0111] In step S500, refer to Figure 12 As shown, a gate extension region 90 is formed on the horizontal portion of the passivation layer 80.

[0112] In this embodiment, the gate extension region 90 can be formed by etching on the passivation layer 80, and then P-type ions can be doped in the trench to form the gate extension region 90.

[0113] In step S600, refer to Figure 13 As shown, a source electrode S is formed on the source region 60 and the P-type base region 70, a drain electrode D is formed on the drain region 40, and a gate electrode G is formed on the horizontal portion of the passivation layer 80.

[0114] Specifically, the vertical portion of the passivation layer 80 is located between the gate electrode G and the source electrode S, and the gate extension region 90 is located between the gate electrode G and the drain electrode D.

[0115] In a specific application, a mask is used to determine the shape of the source electrode S, the gate electrode G, and the drain electrode D, and metal is deposited on the mask to form the source electrode S, the gate electrode G, and the drain electrode D.

[0116] In this embodiment, a mask is used to define the shapes of the source electrode S, the gate electrode G, and the drain electrode D, thereby depositing metal material on the mask to form the source electrode S, the gate electrode G, and the drain electrode D, and then removing the mask.

[0117] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0118] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An LDMOSFET device, characterized in that, The LDMOSFET device includes: Insulating layer; An N-type substrate layer is disposed on the back side of the insulating layer; A P-type well region is disposed on the front side of the insulating layer, and the P-type well region is L-shaped. A P-type base region is disposed on the front side of the insulating layer; wherein the distance between the P-type base region and the N-type substrate layer is less than the thickness of the insulating layer; The source region is located on the horizontal portion of the P-type well region and is in contact with the P-type base region; A drift region is provided on the front side of the insulating layer and in contact with the P-type well region; the thickness of the insulating layer located below the P-type base region and the P-type well region is less than the thickness of the insulating layer located below the drift region; The drain region is located on the drift region; A passivation layer is disposed on the source region, the P-type well region, the drift region, and the drain region; wherein the passivation layer is L-shaped. The source electrode is located on the P-type base region and the source region; A gate electrode is disposed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is located between the gate electrode and the source electrode; The drain electrode is in contact with the drain region; A gate extension region is disposed on the horizontal portion of the passivation layer and located between the gate electrode and the drain electrode; The gate extension region includes: A first P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the gate electrode; The second P-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the first P-type doped region; The first N-type doped region is disposed on the horizontal portion of the passivation layer and is in contact with the second P-type doped region; The third P-type doped region is located on the horizontal portion of the passivation layer and is in contact with the first N-type doped region; Multiple shallow trench isolation regions are disposed within the second P-type doped region. The depth of the multiple shallow trench isolation regions gradually increases from the source region to the drain region. The depth of the shallow trench isolation region near the source region is less than the depth of the shallow trench isolation region near the drain region. The multiple shallow trench isolation regions are formed by depositing, patterning, and etching silicon using a silicon nitride mask to form trenches, and then filling the trenches with deposited oxide.

2. The LDMOSFET device of claim 1, wherein, The doping concentration of the first P-type doped region is greater than that of the second P-type doped region.

3. The LDMOSFET device of claim 1, wherein, The width of the second P-type doped region is greater than the width of the first P-type doped region.

4. The LDMOSFET device of claim 1, wherein, The doping concentration in the drift region gradually decreases from the central region to the left and right sides.

5. The LDMOSFET device of claim 1, wherein, The drift region is staggered with the N-type substrate layer, and the P-type base region and the P-type well region are arranged opposite to the N-type substrate layer.

6. The LDMOSFET device of claim 2, wherein, The width of the gate electrode is greater than the width of the vertical portion of the P-type well region.

7. The LDMOSFET device of claim 1, wherein, The thickness of the P-type base region is equal to the sum of the thickness of the source region and the thickness of the horizontal portion of the P-type well region.

8. A method for fabricating an LDMOSFET device as described in any one of claims 1-7, characterized in that, include: An insulating layer is formed by oxidizing the N-type substrate layer, such that the N-type substrate layer is located on the back side of the insulating layer; A P-type well region, a P-type base region, and a drift region are sequentially formed on the front side of the insulating layer; wherein, the P-type well region is L-shaped, the distance between the P-type base region and the N-type substrate layer is less than the thickness of the insulating layer, and the drift region is in contact with the P-type well region; A source region is formed on the horizontal portion of the P-type well region, and a drain region is formed on the drift region; wherein the source region is in contact with the P-type base region; A passivation layer is formed on the source region, the P-type well region, the drift region, and the drain region; wherein the passivation layer is L-shaped. A gate extension region is formed on the horizontal portion of the passivation layer; A source electrode is formed on the source region and the P-type base region, a drain electrode is formed on the drain region, and a gate electrode is formed on the horizontal portion of the passivation layer; wherein, the vertical portion of the passivation layer is located between the gate electrode and the source electrode, and the gate extension region is located between the gate electrode and the drain electrode.

Images