Semiconductor structure and its formation method

Abstract

This disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a plurality of spaced-apart semiconductor pillars on the substrate, each semiconductor pillar including a first doped region, a channel region, and a second doped region sequentially distributed along a first direction, each semiconductor pillar having a hollow region, and at least a portion of the channel region surrounding the hollow region; a bit line extending along a second direction, the bit line contacting the first doped region of the plurality of semiconductor pillars arranged along the second direction; and a word line extending along a third direction, the word line surrounding the channel region of the plurality of semiconductor pillars arranged along the third direction. This disclosure at least improves the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor structures and methods of forming them. Background Technology

[0002] As the integration density of dynamic memory (DRAM) continues to increase, higher demands are being placed on the arrangement and size of transistors in DRAM array structures. When used as transistors in DRAM, all-around gate transistors (AGBs) can achieve smaller pattern sizes under given process conditions, which is beneficial for increasing the integration density of DRAM.

[0003] While researching the arrangement of dynamic memory structures and how to reduce their size, it is also necessary to improve the electrical performance of small-sized dynamic memory. Specifically, during the conduction of word line drive transistors in dynamic memory, the driving capability of the word line to the channel region farther away from the word line is poor, which in turn affects the performance of the semiconductor structure. Summary of the Invention

[0004] The semiconductor structure and its formation method provided in this disclosure are at least beneficial to improving the electrical performance of the semiconductor structure.

[0005] This disclosure provides a semiconductor structure, comprising: a substrate; a plurality of spaced semiconductor pillars on the substrate, each semiconductor pillar including a first doped region, a channel region, and a second doped region sequentially distributed along a first direction, each semiconductor pillar having one or more hollow regions, and at least a portion of the channel region surrounding the hollow region; a bit line extending along a second direction, the bit line contacting the first doped region of the plurality of semiconductor pillars arranged along the second direction; and a word line extending along a third direction, the word line surrounding the channel region of the plurality of semiconductor pillars arranged along the third direction.

[0006] In some embodiments, the inner wall of the semiconductor pillar facing the hollow region is arc-shaped.

[0007] In some embodiments, along a first direction, the hollow region penetrates the channel region of the semiconductor pillar, and a portion of the first doped region adjacent to the channel region surrounds the hollow region.

[0008] In some embodiments, the second doped region surrounds the hollow region, and along the first direction, the hollow region penetrates the second doped region of the semiconductor pillar.

[0009] In some embodiments, a portion of the second doped region adjacent to the channel region surrounds the hollow region.

[0010] In some embodiments, the system further includes: a functional layer that fills the hollow region; or, a functional layer located within a portion of the hollow region, and the functional layer and the semiconductor pillar forming a first air gap.

[0011] In some embodiments, it further includes: a functional layer, which at least blocks the end region of the hollow region adjacent to the second doped region.

[0012] In some embodiments, the material of the functional layer includes at least one of a semiconductor material or an insulating material.

[0013] In some embodiments, the first direction is a direction perpendicular to the substrate surface.

[0014] In some embodiments, the system further includes: a semiconductor layer located on the substrate surface and extending along a second direction, the semiconductor layer being connected to an outer wall of a plurality of semiconductor pillars arranged along the second direction adjacent to the substrate surface.

[0015] In some embodiments, the semiconductor pillar and the semiconductor layer are integrally formed.

[0016] In some embodiments, the bit line is also located on the surface of the semiconductor layer and surrounds a portion of the first doped region of the semiconductor pillar.

[0017] In some embodiments, a second air gap is provided in the portion of the substrate opposite the end of the first doped region that is away from the second doped region.

[0018] Accordingly, another aspect of this disclosure provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of spaced semiconductor pillars on the substrate, each semiconductor pillar including a first doped region, a channel region, and a second doped region sequentially distributed along a first direction, each semiconductor pillar having a hollow region, and at least a portion of the channel region surrounding the hollow region; forming a bit line extending along a second direction, the bit line contacting the first doped region of the plurality of semiconductor pillars arranged along the second direction; and forming a word line extending along a third direction, the word line surrounding the channel region of the plurality of semiconductor pillars arranged along the third direction.

[0019] In some embodiments, the first direction is a direction perpendicular to the substrate surface, and forming a semiconductor pillar includes: forming a plurality of spaced-apart sacrificial structures on the substrate and extending along the first direction; forming a first semiconductor film on the surface of the sacrificial structures; removing the first semiconductor film from the top surface of the sacrificial structures away from the substrate; removing the sacrificial structures to form an etch hole; forming a second semiconductor film in a portion of the etch hole, the second semiconductor film and the first semiconductor film forming a hollow region, and the second semiconductor film and the first semiconductor film serving as a semiconductor pillar.

[0020] In some embodiments, forming bit lines includes: forming a bit line layer located between the sidewalls of a portion of the first doped region of a semiconductor pillar; removing a portion of the bit line layer to form a plurality of independent bit lines extending along a second direction.

[0021] In some embodiments, forming a first semiconductor film on the surface of the sacrificial structure further includes: forming a first semiconductor film on a substrate other than the sacrificial structure, wherein the first semiconductor film on the substrate other than the sacrificial structure serves as an initial semiconductor layer; the bit line layer is also located on the initial semiconductor layer, and removing a portion of the bit line layer further includes: removing the initial semiconductor layer at the bottom of a portion of the bit line layer to form a semiconductor layer extending along a second direction, wherein the semiconductor layer is connected to the outer wall of a plurality of semiconductor pillars arranged along the second direction adjacent to the surface of the substrate.

[0022] In some embodiments, the method further includes: forming a functional layer within the hollow region, the functional layer at least sealing the top region of the hollow region away from the substrate, the functional layer being located within a portion of the hollow region, and the hollow region outside the functional layer being a first air gap.

[0023] In some embodiments, while removing the sacrificial structure, a portion of the substrate in contact with the bottom of the sacrificial structure is also removed to form a second air gap within the substrate.

[0024] The technical solutions provided in this disclosure have at least the following advantages:

[0025] In the above technical solution, the semiconductor pillar on the substrate is used to form the semiconductor channel of the transistor. The semiconductor pillar includes a first doped region, a channel region, and a second doped region distributed sequentially in a direction away from the substrate surface. The channel region of the semiconductor pillar is used to form a conductive channel in the transistor semiconductor channel. A word line extending in a third direction surrounds the channel region of the semiconductor pillar and is used to drive the channel region of the transistor to form a conductive channel. The semiconductor pillar has a hollow region, and at least a portion of the channel region is arranged around the hollow region. In this way, the distance between the portion of the channel region surrounding the hollow region and the word line is controlled within a small range, avoiding the portion of the channel region far from the word line from being uncontrolled by the word line. This is beneficial to promoting the formation of the depletion layer during the conduction process of the word line-controlled channel region, thereby improving the electrical performance of the semiconductor structure. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 A cross-sectional view of a semiconductor structure in a first direction provided in an embodiment of this disclosure;

[0028] Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0029] Figure 3 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0030] Figure 4 A cross-sectional view of yet another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0031] Figure 5 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0032] Figure 6 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0033] Figure 7 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0034] Figure 8 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0035] Figure 9 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0036] Figure 10 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0037] Figures 11 to 18 A schematic diagram illustrating the steps of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0038] Figure 19 A schematic diagram illustrating the steps of a method for forming a second air gap in a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0039] As is known from the background technology, during the conduction of the word line driving transistor in dynamic memory, the driving capability of the word line to the channel region that is far from the word line is poor, which in turn affects the performance of the semiconductor structure.

[0040] Analysis revealed that by reducing the size of the semiconductor pillars that form the semiconductor channel, the problem of some channel regions being far from the word line can be avoided. However, forming smaller semiconductor pillars not only increases the difficulty of the process, but may also cause changes in the electrical performance of the transistor.

[0041] To address the aforementioned problems, this disclosure provides a semiconductor structure and its formation method. The semiconductor structure includes a first doped region, a channel region, and a second doped region sequentially distributed along a direction away from the substrate surface. The channel region of the semiconductor pillar is used to form a conductive channel in a transistor semiconductor channel. A word line extending along a third direction surrounds the channel region of the semiconductor pillar, driving the channel region of the transistor to form a conductive channel. The semiconductor pillar has a hollow region, and at least a portion of the channel region surrounds the hollow region. This approach, on the one hand, helps to control the distance between the portion of the channel region surrounding the hollow region and the word line within a small range, preventing the portion of the channel region farther from the word line from being uncontrolled by the word line, promoting the formation of a depletion layer during the conduction process of the word line-controlled channel region, increasing the transistor's switching current ratio, and improving the electrical performance of the semiconductor structure. On the other hand, by providing a semiconductor pillar with a hollow region, the problem of poor word line driving channel region capability can be avoided by reducing the size of the semiconductor pillar, thus reducing the manufacturing difficulty of the semiconductor structure.

[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0043] Figure 1 A cross-sectional view of a semiconductor structure in a first direction provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction; Figure 4 A cross-sectional view of yet another semiconductor structure provided in an embodiment of this disclosure in a first direction;

[0044] Figure 5 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction; Figure 6 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction; Figure 7 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction; Figure 8 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction; Figure 9 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction; Figure 10 A cross-sectional view of another semiconductor structure provided in an embodiment of this disclosure in a first direction.

[0045] refer to Figure 1 The semiconductor structure includes: a substrate 100; a plurality of spaced semiconductor pillars 110 on the substrate 100, each semiconductor pillar 110 including a first doped region I, a channel region II, and a second doped region III sequentially distributed along a first direction Z, each semiconductor pillar 110 having a hollow region 111, and at least a portion of the channel region II surrounding the hollow region 111; a bit line 120 extending along a second direction X, the bit line 120 contacting the first doped region I of the plurality of semiconductor pillars 110 arranged along the second direction X; and a word line 130 extending along a third direction Y, the word line 130 surrounding the channel region II of the plurality of semiconductor pillars 110 arranged along the third direction Y. In this design, the channel region II of the semiconductor pillar 110 is used to form a conductive channel in the semiconductor channel. The word line 130, extending along the third direction Y, surrounds the semiconductor pillar 110 of the channel region II and is used to drive the channel region II of the transistor to form a conductive channel. The semiconductor pillar 110 has a hollow region 111, and at least a portion of the channel region II is arranged around the hollow region 111. In this way, not only is the distance between the portion of the channel region II surrounding the hollow region 111 and the word line 130 controlled within a small range, which promotes the formation of the depletion layer during the conduction process of the channel region II controlled by the word line 130, increases the switching current ratio of the transistor, and improves the electrical performance of the semiconductor structure, but also avoids solving the problem of poor driving capability of the channel region II by reducing the size of the semiconductor pillar 110, and reduces the manufacturing difficulty of the semiconductor pillar 110.

[0046] In this embodiment, the substrate 100 is made of a semiconductor material; in some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0047] In some embodiments, the substrate 100 may include a first substrate layer 104 and a second substrate layer 103 stacked sequentially in a first direction Z. The first substrate layer 104 may be made of silicon, and the second substrate layer 103 may be made of silicon oxide or silicon nitride.

[0048] Semiconductor pillar 110 is the semiconductor channel of the transistor. In some embodiments, the transistor can be a gate-all-around transistor, which can achieve the smallest pattern size under given process conditions, thus improving the integration density of the semiconductor structure.

[0049] In some embodiments, the semiconductor pillar 110 may be made of silicon. In other embodiments, the semiconductor pillar 110 may also be made of other semiconductor channel materials, such as IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide), or ITO (indium tin oxide). When the semiconductor channel is composed of the above materials, it is beneficial to improve the mobility of charge carriers in the semiconductor channel, thereby facilitating the efficient transmission of electrical signals by the semiconductor channel.

[0050] In some embodiments, reference Figure 2 The semiconductor pillar 110 has a cylindrical structure, which helps to avoid tip discharge on the outer wall of the semiconductor pillar 110, thereby improving the performance of the semiconductor structure.

[0051] In some embodiments, the first direction Z is perpendicular to the surface of the substrate 100. That is, the extension direction of the semiconductor pillar 110 can be perpendicular to the surface of the substrate 100. Setting the extension direction of the semiconductor pillar 110 used to form the semiconductor channel to be perpendicular to the surface of the substrate 100 facilitates the simple fabrication of the semiconductor pillar 110 through a patterned method, thereby reducing the manufacturing difficulty of the semiconductor structure. It is understood that in other embodiments, the first direction Z can also be other directions, such as a direction parallel to the surface of the substrate 100.

[0052] refer to Figure 2 In the semiconductor pillar 110, a first doped region I, a channel region II, and a second doped region III are sequentially distributed along a first direction Z. The first doped region I and the second doped region III are used to form the source and drain of the transistor, and the channel region II of the semiconductor pillar 110 is used to form the conductive channel of the transistor. The first doped region I and the second doped region III are doped regions. In some embodiments, the type of dopant ions in the doped regions may be different from the type of dopant ions in the channel region II. Specifically, in one example, the dopant ions in the doped regions may be N-type ions, and the dopant ions in the channel region II may be P-type ions. The P-type ions may be at least one of boron ions, indium ions, or gallium ions, and the N-type ions may be at least one of arsenic ions, phosphorus ions, or antimony ions. In another example, the dopant ions in the doped regions may be P-type ions, and the dopant ions in the channel region II may be N-type ions. In other embodiments, the type of dopant ions in the doped regions may also be the same as the type of dopant ions in the channel region II, that is, the semiconductor pillar 110 may be used to form a junctionless field-effect transistor.

[0053] Furthermore, taking the first direction Z as the direction perpendicular to the surface of the substrate 100 as an example, the semiconductor pillars 110 on the substrate 100 can be arranged in an array. The arrangement direction of the rows in the semiconductor pillars 110 is the second direction X, and the arrangement direction of the columns is the third direction Y. The second direction X is different from the third direction Y. It should be noted that the definitions of "row" and "column" are relative, that is, the arrangement direction of the columns can also be defined as the second direction X, and the arrangement direction of the rows can be defined as the third direction Y.

[0054] refer to Figure 2 Word lines 130 extend along a third direction Y and surround the channel region II of semiconductor pillars 110. Specifically, each word line 130 may surround the channel region II of a row of semiconductor pillars 110 arranged along a third direction Y. Word lines 130 serve as the gate of transistors, used to conduct channel region II based on a control signal, thereby enabling carrier transport between the source and drain. The material of word lines 130 is a conductive material; in some examples, the material of word lines 130 may include at least one of polysilicon, tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0055] refer to Figure 2 The semiconductor structure further includes a gate dielectric layer 140, which surrounds the channel region II of the semiconductor pillar 110 and is located between the word line 130 and the semiconductor pillar 110. The gate dielectric layer 140 is used to enable the word line 130 to drive the source and drain of the transistor to conduct. In some embodiments, the gate dielectric layer 140 may be made of silicon oxide. The process of forming silicon oxide on the silicon-based semiconductor pillar 110 using a thermal oxidation process is mature and helps to reduce the fabrication difficulty of the gate dielectric layer 140. In other embodiments, the gate dielectric layer 140 may also be made of silicon nitride or silicon oxynitride.

[0056] In some embodiments, reference Figure 1 The inner wall of the semiconductor pillar 110 facing the hollow region 111 is arc-shaped. This ensures that the inner wall of the semiconductor pillar 110 facing the hollow region 111 is a smooth surface, which helps to avoid the phenomenon of tip discharge on the inner wall of the semiconductor pillar 110 facing the hollow region 111, and thus helps to improve the performance of the semiconductor structure.

[0057] In some embodiments, the semiconductor pillar is a cylindrical structure. In a cross-section perpendicular to the first direction Z, the hollow region 111 can have a circular cross-sectional shape. At the same height in the first direction Z, the channel region II outside the hollow region 111 has the same thickness. This helps ensure that the channel region II driven by the word line 130 has a more uniform morphology, which is beneficial for improving the electrical performance of the semiconductor structure. In other embodiments, in a cross-section perpendicular to the first direction Z, the hollow region 111 can also have an elliptical or other irregular shape.

[0058] In some embodiments, the cross-sectional shape of the hollow region 111 in the first direction Z is elliptical. In this way, the inner walls of the semiconductor pillar 110 facing the hollow region 111 are all smooth surfaces, which helps to avoid the occurrence of tip discharge phenomenon on the inner walls of the semiconductor pillar 110 facing the hollow region 111.

[0059] In some embodiments, reference Figure 3 Along the first direction Z, the hollow region 111 penetrates the channel region II of the semiconductor pillar 110, and a portion of the first doped region I adjacent to the channel region II surrounds the hollow region 111. In the first direction Z, the longer hollow region 111 can further promote the formation of the depletion layer during the control of the word line 130 to conduct the channel region II. Therefore, the hollow region 111 extending to the first doped region I is beneficial to improving the electrical performance of the semiconductor structure. Furthermore, in the direction perpendicular to the first direction Z, the difference between the thickness of the first doped region I adjacent to the channel region II and the thickness of the channel region II surrounding the hollow region 111 is smaller, which is beneficial to promoting carrier transport between the first doped region I and the channel region II.

[0060] In some embodiments, reference Figure 4 or Figure 5 The second doped region III surrounds the hollow region 111 and extends along the first direction Z, penetrating the second doped region III of the semiconductor pillar 110. Thus, in the direction perpendicular to the first direction Z, the difference between the thickness of the second doped region III adjacent to the channel region II and the thickness of the channel region II surrounding the hollow region 111 is small, which facilitates carrier transport between the second doped region III and the channel region II, thereby improving the electrical performance of the semiconductor structure. Furthermore, the end of the hollow region 111 away from the substrate 100 is exposed on the top surface of the semiconductor pillar 110 away from the substrate, which helps reduce the difficulty of forming the hollow region 111.

[0061] In some embodiments, a portion of the second doped region III adjacent to the channel region II surrounds the hollow region 111. (Reference) Figure 6 Thus, in the direction perpendicular to the first direction Z, the difference between the thickness of the second doped region III adjacent to the channel region II and the thickness of the channel region II surrounding the hollow region 111 is small, which is conducive to promoting the transport of charge carriers between the second doped region III and the channel region II.

[0062] In some embodiments, reference Figure 7A portion of the second doped region III adjacent to channel region II surrounds the hollow region 111, and a portion of the first doped region I adjacent to channel region II surrounds the hollow region 111. Thus, perpendicular to the first direction Z, the difference between the thickness of the second doped region III adjacent to channel region II and the thickness of channel region II surrounding the hollow region 111 is small, and the difference between the thickness of the first doped region I adjacent to channel region II and the thickness of channel region II surrounding the hollow region 111 is also small. This is beneficial for promoting carrier transport between the first doped region I and channel region II, and also beneficial for promoting carrier transport between the second doped region III and channel region II, thereby further promoting carrier transport between the first doped region I and the second doped region III.

[0063] In some embodiments, reference Figure 8 The semiconductor structure also includes a functional layer 113, which fills the hollow region 111. This prevents the semiconductor pillar 110 with the hollow region 111 from deforming under external force, thus improving the structural stability of the semiconductor structure.

[0064] In some embodiments, reference Figure 9 The functional layer 113 is located within the partially hollow region 111, and the functional layer 113 and the semiconductor pillar 110 form a first air gap 114. The functional layer 113 helps ensure the high structural stability of the semiconductor pillar 110, while the first air gap 114 facilitates heat dissipation from the semiconductor structure. Furthermore, the low dielectric constant of the first air gap 114 helps reduce the parasitic capacitance of the semiconductor structure, thereby improving its electrical performance.

[0065] In some embodiments, reference Figure 10 The functional layer 113 at least blocks the end region of the hollow region 111 adjacent to the second doped region III. This provides more stable support for the structure located at the end of the second doped region III and helps to prevent impurities from entering the hollow region 111.

[0066] In some embodiments, the material of functional layer 113 includes at least one of semiconductor materials or insulating materials. For example, the material of functional layer 113 can be at least one of polysilicon, silicon oxide, silicon oxynitride, or high-k dielectric materials. It should be noted that if the material of functional layer 113 is a semiconductor material, the type of dopant ions in the semiconductor material of functional layer 113 is different from the type of dopant ions in channel region II. If channel region II is an N-type semiconductor material, then functional layer 113 is a P-type semiconductor material.

[0067] refer to Figures 1 to 10The semiconductor structure also includes multiple bit lines 120 extending along a second direction X. Each bit line 120 is located between portions of the first doped regions I of a plurality of semiconductor pillars 110 arranged along the second direction X, and is electrically connected to the first doped regions I. These bit lines are used to lead out the source or drain of a transistor and to provide electrical signals to the source or drain of the transistor. The bit lines 120 are made of a conductive material. In some embodiments, the material of the bit lines 120 may include at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0068] In some embodiments, the semiconductor structure further includes a semiconductor layer 112, which is located on the surface of the substrate 100 and extends along a second direction X. The semiconductor layer 112 is connected to the outer wall of a plurality of semiconductor pillars 110 arranged along the second direction X adjacent to the surface of the substrate 100. The semiconductor layer 112 interconnects the first doped regions I of the semiconductor pillars 110 arranged along the second direction X, which is beneficial to the contact resistance between the subsequent dropout line 120 and the first doped region I, thereby improving the electrical performance of the semiconductor structure.

[0069] In some embodiments, the semiconductor pillar 110 and the semiconductor layer 112 are integrally formed. Forming the semiconductor layer 112 integrally with the semiconductor pillar 110 at the same time as forming the semiconductor pillar 110 helps to reduce the manufacturing difficulty of the semiconductor layer 112. Furthermore, compared to separate semiconductor pillar 110 and semiconductor layer 112, the integrally formed semiconductor pillar 110 and semiconductor layer 112 have less obstruction to the transport of charge carriers.

[0070] In some embodiments, the bit line 120 is also located on the surface of the semiconductor layer 112, and the bit line 120 surrounds a portion of the first doped region I of the semiconductor pillar 110. This increases the contact area between the bit line 120 and the first doped region I, which is beneficial for enhancing the ability of the bit line 120 to transmit control signals to the first doped region I, thereby improving the electrical performance of the semiconductor structure.

[0071] In some embodiments, a second air gap 117 is provided in the portion of the substrate 100 opposite the end of the first doped region I away from the second doped region III. The second air gap 117 is beneficial to improving the heat dissipation capability of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0072] In some embodiments, the semiconductor structure further includes a dielectric layer 150, which fills the regions between adjacent semiconductor pillars 110, the regions between adjacent word lines 130, and the regions between adjacent bit lines 120. The dielectric layer 150 is made of an insulating material; in some embodiments, the material of the dielectric layer 150 may be at least one of silicon oxide or silicon nitride.

[0073] The semiconductor structure provided in the above embodiment includes: a first doped region I, a channel region II, and a second doped region III sequentially distributed along a direction away from the surface of the substrate 100. The channel region II of the semiconductor pillar 110 is used to form the channel region of a transistor. A word line 130 extending along a third direction Y surrounds the channel region II of the semiconductor pillar 110, driving the channel region II of the transistor to form a conductive channel. The semiconductor pillar 110 has a hollow region 111, and at least the channel region II of the semiconductor pillar 110 is arranged around the hollow region 111. Thus, on the one hand, the distance between the portion of the channel region II surrounding the hollow region 111 and the word line 130 is controlled within a small range, preventing the central portion of the channel region II farther from the word line 130 from being uncontrolled by the word line 130, promoting the formation of a depletion layer during the conduction process of the channel region II controlled by the word line 130, and increasing the switching current ratio of the transistor. On the other hand, it avoids solving the problem of poor driving capability of the word line 130 for the channel region II by reducing the size of the semiconductor pillar 110, which helps to reduce the manufacturing difficulty of the semiconductor structure.

[0074] This disclosure also provides a method for forming a semiconductor structure for forming the semiconductor structure described in the above embodiments. The method for forming the semiconductor structure provided in this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the detailed description of the foregoing embodiments, and will not be repeated hereafter.

[0075] Figures 11 to 18 A schematic diagram illustrating the steps of a method for forming a semiconductor structure according to an embodiment of this disclosure; Figure 19 A schematic diagram illustrating the steps of a method for forming a second air gap in a semiconductor structure provided in an embodiment of this disclosure.

[0076] refer to Figures 11 to 14 The method for forming a semiconductor structure includes: providing a substrate 100; forming a plurality of spaced semiconductor pillars 110 on the substrate 100, each semiconductor pillar 110 including a first doped region I, a channel region II, and a second doped region III sequentially distributed along a first direction Z, each semiconductor pillar 110 having a hollow region 111, and at least a portion of the channel region II surrounding the hollow region 111. The hollow region 111 prevents portions of the channel region II located far from the word line 130 from being uncontrolled by the word line 130, promotes the formation of a depletion layer during the conduction process of the channel region II controlled by the word line 130, increases the switching current ratio of the transistor, and improves the electrical performance of the semiconductor structure.

[0077] In some embodiments, the first direction Z is a direction perpendicular to the surface of the substrate 100, as referenced. Figure 11 and Figure 12The formation of the semiconductor pillar 110 includes forming a plurality of sacrificial structures 101 spaced apart and extending along a first direction Z on the substrate 100. The sacrificial structures 101 serve as supports for the formation of the semiconductor pillar 110, assisting in the formation of the semiconductor pillar 110 and helping to reduce the process difficulty of forming the semiconductor pillar 110.

[0078] Specifically, the steps for forming the sacrificial structure 101 may include: (Refer to...) Figures 11 to 12 An initial substrate 200 is provided. The initial substrate 200 may include an initial first substrate layer 201 and an initial second substrate layer 202 stacked in a first direction Z. In some embodiments, the initial first substrate layer 201 may be a silicon layer, and the initial second substrate layer 202 may be a silicon oxide layer or a nitride layer. A mask layer with an etching window is formed on the initial second substrate layer 202. The portion of the initial second substrate layer 202 exposed by the mask layer is etched to form the sacrificial structure 101, and then the mask layer is removed. The method of patterning the initial second substrate layer 202 to form the sacrificial structure 101 simplifies the process flow for forming the sacrificial structure 101 and helps to save fabrication costs.

[0079] It is understandable that the material of the sacrificial structure 101 formed using the initial second base layer 202 is the same as the material of the initial second base layer 202.

[0080] In some embodiments, the initial substrate 200 can be patterned using SADP (Self-aligned Double Patterning) or SAQP (Self-aligned Quadruple Patterning) processes. SADP or SAQP processes can form smaller patterns, which is beneficial for improving the precision of the patterning process of the initial substrate 200 and for forming smaller sacrificial structures 101, thereby helping to reduce the size of the semiconductor structure.

[0081] refer to Figures 13 to 14 The formation of the semiconductor pillar 110 further includes: forming a first semiconductor film 115 on the surface of the sacrificial structure 101, wherein the first semiconductor film 115 located on the sidewall of the sacrificial structure 101 is used to form the semiconductor pillar 110. (See reference) Figure 14The process involves removing the first semiconductor film 115 from the top surface of the sacrificial structure 101, which is away from the substrate 100; removing the sacrificial structure 101 to form an etched hole; and forming a second semiconductor film within a portion of the etched hole. The second semiconductor film and the first semiconductor film 115 together form a hollow region 111, which serves as the semiconductor pillar 110. Specifically, the first semiconductor film 115 from the top surface of the sacrificial structure 101, which is away from the substrate 100, is removed to expose the top surface of the sacrificial structure 101. Then, an etching process with high selectivity for the sacrificial structure 101 is used to remove the sacrificial structure 101 to form an etched hole, and a second semiconductor film is formed within a portion of the etched hole. In this way, a semiconductor pillar 110 with a hollow region 111 can be easily prepared, which simplifies the process flow for preparing the semiconductor pillar 110 with a hollow region 111.

[0082] In some embodiments, forming a first semiconductor film 115 on the surface of the sacrificial structure 101 further includes forming a first semiconductor film on a substrate 100 other than the sacrificial structure 101, wherein the first semiconductor film on the substrate 100 other than the sacrificial structure 101 serves as an initial semiconductor layer. The initial semiconductor layer is used to form a semiconductor layer connected to a portion of the first doped region I of the semiconductor pillar 110. Forming the initial semiconductor layer simultaneously with forming the semiconductor pillar 110 simplifies the process flow and reduces fabrication costs.

[0083] In some embodiments, after forming the semiconductor pillar 110, a doping process is further performed on the semiconductor pillar 110 to form a channel region II and doped regions located on both sides of the channel region II, i.e., to form the channel region II, the first doped region I, and the second doped region III. The doped regions located on both sides of the channel region II constitute the source and drain of the semiconductor structure. Specifically, in some embodiments, either ion implantation or thermal diffusion can be used to dope the semiconductor pillar 110 to form the channel region II, the first doped region I, and the second doped region III of the semiconductor pillar 110.

[0084] refer to Figures 15 to 16 A bit line 120 extending along the second direction X is formed. The bit line 120 contacts the first doped region I of a plurality of semiconductor pillars 110 arranged along the second direction X to be electrically connected to the first doped region I, for leading out the source or drain of the transistor, and for providing electrical signals to the source or drain of the transistor.

[0085] In some implementations, forming bit line 120 includes: reference Figures 15 to 16A bit line layer 102 is formed between the sidewalls of a portion of the first doped region I of the semiconductor pillar 110. The bit line layer 102 can also be located on the initial semiconductor layer 112. Specifically, a deposition process can be used to first deposit bit line layer material over the entire surface, and then remove excess bit line layer material to form the bit line layer 102. Alternatively, a mask layer covering the semiconductor pillar 110 can be formed first, and then a deposition process can be used to deposit bit line layer material over the entire surface. After removing the mask layer covering the semiconductor pillar 110, the bit line layer 102 between the sidewalls of a portion of the first doped region I of the semiconductor pillar 110 can be obtained. After forming the bit line layer 102, the bit line layer 102 is patterned to remove a portion of the bit line 120 layer, forming multiple independent bit lines 120 extending along the second direction X.

[0086] In some embodiments, reference Figures 16 to 17 The removal of a portion of the bit line layer 102 further includes removing the initial semiconductor layer at the bottom of the bit line layer 102 to form a semiconductor layer 112 extending along the second direction X. The semiconductor layer 112 is connected to the outer wall of a plurality of semiconductor pillars 110 arranged along the second direction X adjacent to the surface of the substrate 100. Removing the portion of the bit line layer 102 simultaneously with removing the initial semiconductor layer at the bottom of the bit line layer 102 allows for the formation of independent bit lines 120 along with the formation of independent semiconductor layers 112 at the bottom of the bit lines 120. This simplifies the process flow for forming the semiconductor layer 112 and reduces the fabrication cost of the semiconductor structure. Furthermore, forming a semiconductor layer 112 that contacts the bottom surface of the substrate 100 adjacent to the bit lines 120 increases the contact area between the bit lines 120 and the first doped region I, thereby promoting carrier transport between the bit lines 120 and the first doped region I and improving the electrical performance of the semiconductor structure.

[0087] In some embodiments, reference Figure 16 While removing part of the initial semiconductor layer at the bottom of the bit line layer 102, a portion of the substrate 100 at the bottom of the initial semiconductor layer is also removed. This helps to avoid the formation of connections between semiconductor layers 112 due to the residue of the initial semiconductor layer, thereby helping to avoid semiconductor structure failure.

[0088] refer to Figure 17Word lines 130 extending in the third direction Y are formed, surrounding channel regions II of a plurality of semiconductor pillars 110 arranged in the third direction Y. Specifically, after forming the bit lines 120, a first dielectric layer can be formed to fill the space between the sidewalls of the first doped regions I of adjacent semiconductor pillars 110. The first dielectric layer exposes the sidewalls of the channel regions II of the semiconductor pillars 110. A word line layer filling the space between the sidewalls of the channel regions II of adjacent semiconductor pillars 110 is formed on the first dielectric layer. The word line layer is patterned to remove a portion of the word line layer, forming independent word lines 130 extending in the third direction Y. The processes for forming the first dielectric layer and the word line layer can be deposition processes. The material of the first dielectric layer can be an insulating material, such as silicon oxide.

[0089] refer to Figure 17 Before forming the word line layer, the process may further include forming a gate dielectric layer 140, which surrounds the channel region II of the semiconductor pillar 110. Specifically, after forming the first dielectric layer, the semiconductor pillar 110 can be directly oxidized using a thermal oxidation process to form the gate dielectric layer 140 on the side of the channel region II of the semiconductor pillar 110. In some embodiments, a gate dielectric layer 140 is also formed on the side of the second doped region III of the semiconductor pillar 110.

[0090] refer to Figure 17 After forming word lines 130 and gate dielectric layer 140, the process may further include forming a second dielectric layer between the sidewalls of adjacent word lines 130 and between the sidewalls of the second doped region III of adjacent semiconductor pillars 110 using a deposition process. The second dielectric layer and the first dielectric layer constitute dielectric layer 150. Dielectric layer 150 fills the regions between adjacent semiconductors, the regions between adjacent word lines 130, and the regions between adjacent bit lines 120, for forming isolation between adjacent bit lines 120, isolation between adjacent word lines 130, and isolation between adjacent semiconductor pillars 110.

[0091] In some embodiments, reference Figure 19 In the step of forming the semiconductor pillar 110, while removing the sacrificial structure 101, a portion of the substrate 100 in contact with the bottom of the sacrificial structure 101 is also removed to form a second air gap 117 within the substrate 100. The second air gap 117 facilitates heat dissipation of the semiconductor structure. In addition, forming the second air gap 117 while removing the sacrificial structure 101 helps reduce the difficulty of forming the second air gap 117.

[0092] In some embodiments, reference Figure 10The method for forming the semiconductor structure further includes: forming a functional layer 113 within the hollow region 111, wherein the functional layer 113 at least seals the top region of the hollow region 111 away from the substrate 100, the functional layer 113 is located within a portion of the hollow region 111, and the hollow region 111 outside the functional layer 113 forms a first air gap 114. The functional layer 113 provides support for the structure located at the end of the second doped region III away from the substrate 100, preventing the structure at the end of the second doped region III from losing support and detaching due to an excessively large opening in the hollow region 111, thus ensuring high structural stability of the semiconductor pillar 110. The first air gap 114 facilitates heat dissipation of the semiconductor structure, and its low dielectric constant helps reduce the parasitic capacitance of the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.

[0093] Specifically, a deposition process can be used to form a functional layer 113 in the hollow region 111. When the length of the hollow region 111 in the first direction Z is large and the width perpendicular to the first direction Z is small, due to the limitations of the deposition process itself, the deposition process will only form the functional layer 113 in the top region of the hollow region 111 away from the substrate 100, while ensuring that the hollow region 111 outside the functional layer 113 is the first air gap 114.

[0094] In the semiconductor structure formation method provided in the above embodiments, a semiconductor pillar 110 with a hollow region 111 is formed. The setting of the hollow region 111 avoids the central part of the channel region II that is far from the word line 130 from being uncontrolled by the word line 130, promotes the formation of the depletion layer during the conduction process of the channel region II controlled by the word line 130, increases the switching current ratio of the transistor, and is beneficial to improving the electrical performance of the semiconductor structure.

[0095] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A plurality of spaced semiconductor pillars are located on the substrate. Each semiconductor pillar includes a first doped region, a channel region, and a second doped region distributed sequentially along a first direction. Each semiconductor pillar has one or more hollow regions, and at least a portion of the channel region surrounds the hollow region. A bit line extending along a second direction, the bit line contacting the first doped region of the plurality of semiconductor pillars arranged along the second direction; Word lines extending along a third direction, the word lines surrounding the channel region of a plurality of semiconductor pillars arranged along the third direction; A functional layer is located within a portion of the hollow region, and the functional layer and the semiconductor pillar form a first air gap.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor pillar is arc-shaped, facing the inner wall of the hollow region.

3. The semiconductor structure as described in claim 1, characterized in that, Along the first direction, the hollow region penetrates the channel region of the semiconductor pillar, and a portion of the first doped region adjacent to the channel region surrounds the hollow region.

4. The semiconductor structure as described in claim 1 or 3, characterized in that, The second doped region surrounds the hollow region, and along the first direction, the hollow region penetrates the second doped region of the semiconductor pillar.

5. The semiconductor structure as described in claim 1 or 3, characterized in that, A portion of the second doped region adjacent to the channel region surrounds the hollow region.

6. The semiconductor structure as described in claim 4, characterized in that, The functional layer at least blocks the end region of the hollow region adjacent to the second doped region.

7. The semiconductor structure as described in claim 1 or 6, characterized in that, The material of the functional layer includes at least one of semiconductor materials or insulating materials.

8. The semiconductor structure as described in claim 1, characterized in that, The first direction is perpendicular to the surface of the substrate.

9. The semiconductor structure as described in claim 8, characterized in that, Also includes: A semiconductor layer is located on the surface of the substrate and extends along the second direction, and the semiconductor layer is connected to the outer wall of a plurality of semiconductor pillars arranged along the second direction adjacent to the surface of the substrate.

10. The semiconductor structure as described in claim 9, characterized in that, The semiconductor pillar and the semiconductor layer are integrally formed.

11. The semiconductor structure as described in claim 9, characterized in that, The bit line is also located on the surface of the semiconductor layer, and the bit line surrounds a portion of the first doped region of the semiconductor pillar.

12. The semiconductor structure as described in claim 11, characterized in that, The portion of the substrate opposite the end of the first doped region away from the second doped region has a second air gap.

13. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A plurality of spaced semiconductor pillars are formed on the substrate. Each semiconductor pillar includes a first doped region, a channel region, and a second doped region distributed sequentially along a first direction. Each semiconductor pillar has a hollow region, and at least a portion of the channel region surrounds the hollow region. A bit line is formed extending along a second direction, the bit line being in contact with the first doped region of a plurality of semiconductor pillars arranged along the second direction; A word line is formed extending along a third direction, the word line surrounding the channel region of a plurality of semiconductor pillars arranged along the third direction; Wherein, the first direction is a direction perpendicular to the surface of the substrate, and forming the semiconductor pillar includes: Multiple sacrificial structures are formed on the substrate at intervals and extending along the first direction; A first semiconductor film is formed on the surface of the sacrificial structure; Remove the first semiconductor film from the top surface of the sacrificial structure, which is away from the substrate; Remove the sacrificial structure to form an etched hole; A second semiconductor film is formed within a portion of the etched hole, the second semiconductor film and the first semiconductor film enclosing the hollow region, and the second semiconductor film and the first semiconductor film serving as the semiconductor pillar.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, Forming the bit line includes: A bit line layer is formed between the sidewalls of a portion of the first doped region of the semiconductor pillar; Remove part of the bit line layer to form multiple independent bit lines extending along the second direction.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, Forming the first semiconductor film on the surface of the sacrificial structure further includes: A first semiconductor film is formed on the substrate outside the sacrificial structure, and the first semiconductor film on the substrate outside the sacrificial structure serves as an initial semiconductor layer; The bit line layer is also located on the initial semiconductor layer, and removing a portion of the bit line layer further includes: The initial semiconductor layer at the bottom of a portion of the bit line layer is removed to form a semiconductor layer extending along the second direction, the semiconductor layer being connected to the outer wall of a plurality of semiconductor pillars arranged along the second direction adjacent to the surface of the substrate.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, Also includes: A functional layer is formed within the hollow region, the functional layer at least sealing the top region of the hollow region away from the substrate, the functional layer being located within a portion of the hollow region, and the hollow region outside the functional layer forming a first air gap.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, While removing the sacrificial structure, the portion of the substrate in contact with the bottom of the sacrificial structure is also removed to form a second air gap within the substrate.

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