Semiconductor structure and method of fabrication

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a preparation method. The semiconductor structure comprises: a substrate; active pillars located on the substrate and arranged in an array along a first direction and a second direction, the active pillars comprising channel regions; word lines extending along the second direction, the word lines surrounding the active pillars of the channel regions, the word lines comprising stacked first conductive layers and second conductive layers, the spacing between the first conductive layers adjacent along the first direction being greater than the spacing between the first conductive layers adjacent along the second direction; the first direction being one of a direction perpendicular to the surface of the substrate or a direction parallel to the surface of the substrate, and the second direction being the other of the direction perpendicular to the surface of the substrate or the direction parallel to the surface of the substrate. The semiconductor structure and the preparation method provided by the embodiment of the present disclosure can at least improve the storage density while improving the electrical performance of the word lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration density of integrated circuits while increasing the operating speed of memory and reducing its power consumption, the feature size of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices is constantly shrinking. MOSFET devices face a series of challenges. For example, in order to reduce the linewidth of the device, semiconductor structures have begun to evolve from buried word line structures to Gate-All-Around (GAA) structures. However, the integration density of memory devices is mainly determined by the area occupied by a unit memory cell, meaning that the storage capacity is also limited by size.

[0003] How to reduce device linewidth and further increase storage density has become an important problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and fabrication method that at least improves storage density while enhancing the electrical performance of word lines.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate; active pillars located on the substrate and arranged in an array along a first direction and a second direction, each active pillar including a channel region; word lines extending along the second direction, the word lines surrounding the active pillars in the channel region, each word line including a stacked first conductive layer and a second conductive layer, the spacing between adjacent first conductive layers along the first direction being greater than the spacing between adjacent first conductive layers along the second direction; the first direction being one of a direction perpendicular to the substrate surface or a direction parallel to the substrate surface, and the second direction being the other of a direction perpendicular to the substrate surface or a direction parallel to the substrate surface.

[0006] In some embodiments, an air gap is provided between adjacent word lines along a first direction, and the air gap extends along a second direction.

[0007] In some embodiments, a first conductive layer surrounds the channel region of the active pillars, and a second conductive layer is formed on the surface of the first conductive layer and connects to a plurality of active pillars arranged in a second direction.

[0008] In some embodiments, the difference between the spacing of adjacent first conductive layers along the first direction and the spacing of adjacent first conductive layers along the second direction ranges from 5 nm to 20 nm; the thickness of the air gap along the first direction ranges from 5 nm to 15 nm.

[0009] In some embodiments, the first direction is a direction perpendicular to the substrate surface, and the spacing between adjacent active posts along the direction perpendicular to the substrate surface is greater than the spacing between adjacent active posts along the direction parallel to the substrate surface.

[0010] In some embodiments, the first direction is a direction parallel to the substrate surface, and the spacing between adjacent active posts along the direction perpendicular to the substrate surface is smaller than the spacing between adjacent active posts along the direction parallel to the substrate surface.

[0011] In some embodiments, the active pillar further includes a first source / drain region and a second source / drain region located on both sides of the channel region, and the semiconductor structure further includes: a bit line extending along a first direction, the bit line being connected to the active pillar of the first source / drain region; a capacitor structure located on a substrate, the capacitor structure being connected to the active pillar of the second source / drain region; a first metal contact layer and a second metal contact layer, the first metal contact layer being located between the active pillar and the bit line, and the second metal contact layer being located between the active pillar and the capacitor structure.

[0012] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming active pillars arranged in an array along a first direction and a second direction on the substrate, the active pillars including a channel region; forming word lines extending along the second direction, the word lines surrounding the active pillars of the channel region, the word lines including stacked first conductive layers and second conductive layers, the spacing between adjacent first conductive layers along the first direction being greater than the spacing between adjacent first conductive layers along the second direction; the first direction being one of a direction perpendicular to the substrate surface or a direction parallel to the substrate surface, and the second direction being the other of a direction perpendicular to the substrate surface or a direction parallel to the substrate surface.

[0013] In some embodiments, the first direction is a direction perpendicular to the substrate surface; the method further includes: forming an isolation layer, the isolation layer being located on the substrate surface and between adjacent active pillars, the spacing between adjacent active pillars in the direction perpendicular to the substrate surface being greater than the spacing between adjacent active pillars in the direction parallel to the substrate surface; the process step of forming word lines includes: forming a first conductive layer on the surface of the active pillars, the first conductive layer surrounding the channel region of the active pillars; selectively growing a second conductive layer on the surface of the first conductive layer, the second conductive layer connecting a plurality of active pillars arranged in a second direction, and an air gap being formed between adjacent second conductive layers in the direction perpendicular to the substrate surface.

[0014] In some embodiments, the active post further includes a first source / drain region and a second source / drain region located on both sides of the channel region. The process steps for forming the first conductive layer include: removing a portion-width isolation layer to expose the surface of the channel region of the active post; forming a conductive film on the surface of the active post and the side of the isolation layer; forming a filler layer located between adjacent conductive films; patterning a portion-width isolation layer to expose the side of the conductive film; etching the conductive film located on the side of the isolation layer until the side of the filler layer is exposed, with the remaining conductive film serving as the first conductive layer.

[0015] In some embodiments, the isolation layer includes a first isolation layer and a second isolation layer, the second isolation layer being located between adjacent first isolation layers, and the etching rates of the first isolation layer and the second isolation layer being different under the same process; the isolation layer with a patterned portion width includes: removing the first isolation layer located on the side of the conductive film.

[0016] In some embodiments, after forming the word line, the method further includes: removing the first isolation layer; forming a first metal contact layer and a second metal contact layer, wherein the first metal contact layer is located between the active post and the bit line, and the second metal contact layer is located on the side of the active post in the second source / drain region.

[0017] In some embodiments, a second metal contact layer is formed simultaneously with the formation of a first metal contact layer.

[0018] In some embodiments, the process steps for forming an active pillar include: sequentially forming a first sacrificial layer and a semiconductor layer arranged at intervals on a substrate surface; patterning a portion of the first sacrificial layer and the semiconductor layer to form a first groove, the bottom of the first groove exposing the substrate, and the width of the first groove being less than the thickness of the first sacrificial layer; forming a second sacrificial layer in the first groove; removing the first sacrificial layer, with the remaining semiconductor layer serving as the active pillar.

[0019] In some embodiments, the material of the first conductive layer is titanium nitride, and the material of the second conductive layer is molybdenum.

[0020] In some embodiments, an atomic layer deposition technique is used to form a second conductive layer. The process conditions for forming the second conductive layer include: using molybdenum dioxide (MoO2Cl2) or molybdenum pentachloride (MoCl5) as a precursor material, using ammonia or hydrogen as an auxiliary reaction gas, and a reaction temperature of 450°C-600°C.

[0021] The technical solutions provided in this disclosure have at least the following advantages:

[0022] In the technical solution provided by the embodiments of this disclosure, the spacing between adjacent first conductive layers along the first direction is greater than the spacing between adjacent first conductive layers along the second direction. During the formation of the second conductive layer, under the same reaction conditions, the region with smaller spacing can quickly form word lines extending along the second direction, and the word lines between adjacent transistors are well connected, reducing the process complexity of word lines while avoiding excessively large defects in word lines due to excessively fast deposition growth rate, thereby affecting the electrical performance of word lines. The region with larger spacing forms an air gap or an isolation layer between adjacent word lines, reducing the impact of parasitic capacitance between adjacent word lines. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 2 A schematic cross-sectional view of a semiconductor structure along the A-A' section, provided in an embodiment of this disclosure;

[0026] Figure 3 A schematic cross-sectional view of a semiconductor structure along the B-B' section, provided in an embodiment of this disclosure;

[0027] Figures 4 to 24 This is a schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of this disclosure. Detailed Implementation

[0028] This disclosure provides a semiconductor structure and fabrication method in which the spacing between adjacent first conductive layers along a first direction is greater than the spacing between adjacent first conductive layers along a second direction. During the formation of the second conductive layer, under the same reaction conditions, the region with smaller spacing can quickly form word lines extending along the second direction, resulting in good word line connection between adjacent transistors. This reduces the process complexity of word lines while avoiding excessively fast deposition growth rates that could lead to excessively large defects within the word lines, thereby affecting the electrical performance of the word lines. The region with larger spacing forms an air gap or an isolation layer between adjacent word lines, reducing the impact of parasitic capacitance between adjacent word lines.

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Figure 1 A three-dimensional structural schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 A schematic cross-sectional view of a semiconductor structure along the A-A' section, provided in an embodiment of this disclosure; Figure 3 This is a schematic cross-sectional view of a semiconductor structure along the B-B' section, provided as an embodiment of the present disclosure.

[0031] According to some embodiments of this disclosure, reference is made to Figures 1-3 This disclosure provides a semiconductor structure, including: a substrate 100; active pillars 110 located on the substrate 100 and arranged in an array along a first direction and a second direction, the active pillars 110 including a channel region 112; word lines 120 extending along the second direction, the word lines 120 surrounding the active pillars 110 of the channel region 112, the word lines 120 including a stacked first conductive layer 121 and a second conductive layer 122, the spacing between adjacent first conductive layers 121 along the first direction being greater than the spacing between adjacent first conductive layers 121 along the second direction; the first direction is either a direction Z perpendicular to the surface of the substrate 100 or a direction Y parallel to the surface of the substrate 100, and the second direction is either a direction Z perpendicular to the surface of the substrate 100 or a direction Y parallel to the surface of the substrate 100.

[0032] In some embodiments, the first direction is a direction Z perpendicular to the surface of the substrate 100, and the second direction is a direction Y parallel to the surface of the substrate 100. That is, the word lines 120 extend along the direction Y parallel to the surface of the substrate 100, and the spacing L1 along the direction Z perpendicular to the surface of the substrate 100 is greater than the spacing L2 along the direction Y parallel to the surface of the substrate 100. The material of the substrate 100 can be a semiconductor material. Specifically, the semiconductor material can be any one of silicon, germanium, silicon germanium, or silicon carbide.

[0033] In some embodiments, the active pillar 110 further includes a first source / drain region 111 and a second source / drain region 113 located on both sides of the channel region 112. The active pillar 110 extends along a third direction X and includes the first source / drain region 111, the channel region 112, and the second source / drain region 113. The material of the active pillar 110 includes an amorphous material. The amorphous material has gaps inside and has a higher carrier mobility, which can reduce the thickness of the active pillar 110, reduce the linewidth of the semiconductor structure within a limited cell area, and further improve the storage density of the semiconductor structure. The amorphous material includes at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), or indium tungsten oxide (IWO). In other embodiments, the material of the active pillar 110 can be doped polycrystalline silicon or monocrystalline silicon, undoped polycrystalline silicon, amorphous silicon, or monocrystalline silicon. The doped elements can be N-type or P-type elements. N-type elements can be group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while P-type elements can be group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0034] In some embodiments, the spacing between adjacent active pillars 110 along the direction Z perpendicular to the surface of the substrate 100 is greater than the spacing between adjacent active pillars along the direction Y parallel to the surface of the substrate 100. The larger spacing between adjacent active pillars 110 along the direction Z perpendicular to the surface of the substrate 100 ensures that a certain interval is formed between adjacent word lines 120 to form an air gap 123 or isolation layer. On the one hand, this ensures electrical isolation between adjacent word lines 120, avoiding the risk of short circuits between adjacent word lines 120; on the other hand, increasing the spacing between adjacent word lines 120 reduces interference from the parasitic capacitance of adjacent word lines, thereby improving the electrical performance of the word lines 120. The small spacing between adjacent active pillars 110 along the direction Y parallel to the surface of the substrate 100 ensures that the second conductive layer subsequently formed on the surface of the adjacent active pillars 100 can form a continuous film layer. That is, along the direction Y parallel to the surface of the substrate 100, the word line 120 can surround multiple active pillars, improving the control capability of the word line 120 and reducing the linewidth occupied by the word line 120, thereby increasing the storage area of ​​the capacitor structure 140 and thus increasing the storage density of the semiconductor structure.

[0035] In some embodiments, word line 120 serves as the gate of a semiconductor structure. Word line 120 surrounds the active pillar 110 of channel region 112, i.e., the semiconductor structure is a GAA structure. The GAA structure can realize that the gate surrounds the channel region of the semiconductor on all four sides, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size. It also reduces the area occupied by word line 120 in the vertical direction, which is beneficial to enhance gate control performance and improve the integration of semiconductor structure.

[0036] In some embodiments, a first conductive layer 121 surrounds the channel region 112 of the active pillars 110, and a second conductive layer 122 is formed on the surface of the first conductive layer 121 and connects to a plurality of active pillars 110 arranged in a direction Y parallel to the surface of the substrate 100. The material of the first conductive layer 121 is titanium nitride, and the material of the second conductive layer 122 is molybdenum. Since the precursor material for forming molybdenum has a high deposition rate on titanium nitride, the formed second conductive layer 122 has fewer defects, thereby exhibiting good electrical and structural properties. Furthermore, compared with conventional processes for forming the second conductive layer 122, using molybdenum as the material of the second conductive layer 122 and titanium nitride as the material of the first conductive layer 121 can reduce the process difficulty of forming the second conductive layer 122. Moreover, since the second conductive layer 122 is formed on the first conductive layer 121, it is not necessary to define the position of the second conductive layer 122 to avoid electrical connection problems between adjacent second conductive layers 122, thus reducing the process steps and process difficulty of forming the word line 120.

[0037] In some embodiments, the difference between the spacing L1 of adjacent first conductive layers 121 along the direction Z perpendicular to the surface of the substrate 100 and the spacing L2 of adjacent first conductive layers 121 along the direction Y parallel to the surface of the substrate 100 ranges from 5 nm to 20 nm. Optionally, the difference range can be from 8 nm to 15 nm; specifically, the difference can be 8 nm, 9.6 nm, 10.6 nm, 13.1 nm, or 14.86 nm. The technical function and effect of the difference range between spacing L1 and spacing L2 are the same as or similar to the technical function and effect of the spacing between adjacent active pillars 110 along the direction Z perpendicular to the surface of the substrate 100 being greater than the spacing between adjacent active pillars 110 along the direction Y parallel to the surface of the substrate 100, and will not be elaborated further here.

[0038] In some embodiments, such as Figure 15As shown, an air gap 123 is provided between adjacent word lines 120 along the direction Z perpendicular to the surface of the substrate 100. The air gap 123 extends along the direction Y parallel to the surface of the substrate 100, that is, the extension direction of the air gap 123 is the same as the extension direction of the word lines 120. The air gap 123 can reduce the parasitic capacitance between adjacent word lines 120, which helps to avoid problems such as leakage current of word lines 120. In some embodiments, a low-dielectric-constant dielectric layer is provided between adjacent word lines. The low-dielectric-constant dielectric layer is used to reduce the parasitic capacitance between adjacent word lines. The material of the dielectric layer can be silicon oxide, silicon oxycarbide, or a porous material.

[0039] In some embodiments, the air gap 123 is formed because, at the same deposition rate, second conductive layers 122 formed at a spacing L2 between adjacent first conductive layers 121 in the direction Y parallel to the surface of the substrate 100 come into contact to form a continuous film. The larger spacing naturally forms the air gap 123. Therefore, the thickness range of the air gap 123 depends on the difference between the spacing L1 between adjacent first conductive layers 121 in the direction Z perpendicular to the surface of the substrate 100 and the spacing L2 between adjacent first conductive layers 121 in the direction Y parallel to the surface of the substrate 100. Along the direction Z perpendicular to the surface of the substrate 100, the thickness range of the air gap 123 is 5 nm to 15 nm, optionally, it is 8 nm to 13 nm; specifically, the thickness of the air gap 123 can be 8 nm, 8.9 nm, 10.7 nm, 11.2 nm, or 12.8 nm.

[0040] In some embodiments, the semiconductor structure further includes: a bit line 130 extending in a direction Z perpendicular to the surface of the substrate 100, the bit line 130 being connected to the active pillar 110 of the first source / drain region 111; a capacitor structure 140 located on the substrate 100, the capacitor structure 140 being connected to the active pillar 110 of the second source / drain region 113; a first metal contact layer 131 and a second metal contact layer 141, the first metal contact layer 131 being located between the active pillar 110 and the bit line 130, and the second metal contact layer 141 being located between the active pillar 110 and the capacitor structure 140.

[0041] In some embodiments, the bit line 130 extends along the direction Z perpendicular to the surface of the substrate 100. The bit line 130 is a metallic bit line, and its material can be metals such as tungsten, copper, molybdenum, and silver. Metals have low resistance, which is beneficial for improving the conductivity between the bit line 130 and the active pillar 110. In other embodiments, the bit line can be a semiconductor bit line, and its material can be silicon, germanium, germanium-silicon, silicon carbide, or polycrystalline silicon. Furthermore, the semiconductor bit line is doped with the same type of dopant element as the active pillar. The dopant element can act as a charge carrier, improving the migration and diffusion of charge carriers between the bit line and the active pillar, thus enhancing the conductivity between the bit line and the active pillar.

[0042] In some embodiments, word line 120 and active pillar 110 of channel region 112, and active pillar 110 of first source-drain region 111 and second source-drain region 113 located at both ends of channel region 112 constitute a transistor structure; along a third direction X, there are at least two transistor structures, the two transistor structures are electrically connected to the same bit line 130, so that the two transistors share bit line 130, and form a capacitor structure 140 parallel to the substrate and located on both sides of bit line 130. This allows the embodiments of the present disclosure to achieve three-dimensional stacking while reducing the size of key devices by sharing bit line 130, thereby improving the performance of semiconductor devices and the stability of semiconductor structures.

[0043] In some embodiments, the capacitor structure 140 has a semiconductor layer 102 made of the same material as the active pillar 110. The semiconductor layer 102 can serve as a support pillar for the capacitor structure 140. The semiconductor structure can form one transistor corresponding to one capacitor structure (1T-1C). The capacitor structure 140 includes a first electrode, a first dielectric layer, and a second electrode. The material of the first dielectric layer can include any one or more of silicon oxide, silicon nitride, and high-k materials. The high-k materials can include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate.

[0044] In some embodiments, the first metal contact layer 131 and the second metal contact layer 141 are used to reduce the contact resistance between the bit line 130 and the active pillar 110 and between the capacitor structure 140 and the active pillar 110, respectively, to form a good ohmic contact. The materials of the first metal contact layer 131 and the second metal contact layer 141 are metal silicides. The metal silicide layer can serve as a connection bridge between the semiconductor and the conductive material, reducing the contact resistance between the bit line 130 and the active pillar 110 and between the capacitor structure 140 and the active pillar 110, thereby helping to reduce the series resistance of the semiconductor structure, reduce RC delay, and improve the circuit speed. The material of the metal silicide layer can be titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, palladium silicide, platinum silicide, or cobalt silicide.

[0045] In some embodiments, the semiconductor structure further includes a second isolation layer 108 and an insulating layer 125, wherein the second isolation layer 108 and the insulating layer 125 are located between the word line 120 and the bit line 130, and are also located between the word line and the capacitor structure 140, serving as insulation. The material of the second isolation layer 108 may be silicon nitride, silicon oxide, or other materials with a high dielectric constant K. The material of the insulating layer 125 may be silicon oxide, silicon carbide, or silicon nitride. The semiconductor structure further includes a dielectric layer 126, wherein the dielectric layer 126 is located between adjacent first metal contact layers 131 and adjacent second metal contact layers 141, and is also located on the top surface of the second isolation layer 108, the insulating layer 125, and the word line 120. The material of the dielectric layer 126 may be silicon oxide, silicon nitride, or silicon oxynitride.

[0046] In some embodiments, the semiconductor structure further includes a gate dielectric layer 124 located between the word line 120 and the active pillar 110 of the channel region 112. The gate dielectric layer 124 may be made of silicon oxide, silicon carbide, silicon nitride, or other materials with high dielectric constants to suppress short-channel effects, thereby suppressing tunneling leakage current and other issues.

[0047] The above embodiments are described with the first direction being Z, which is perpendicular to the substrate surface, and the second direction being Y, which is parallel to the substrate surface. Another embodiment of this disclosure provides a semiconductor structure that is substantially the same as the semiconductor structure provided in the foregoing embodiments. The main difference is that the first direction is Y, which is parallel to the substrate surface, and the second direction is Z, which is perpendicular to the substrate surface. Specifically, the bit lines extend in a direction parallel to the substrate surface, and the word lines extend in a direction perpendicular to the substrate surface. Elements that are the same as or corresponding to those in the above embodiments will not be described in detail.

[0048] In some embodiments, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface. Bit lines extend in the direction parallel to the substrate surface, and word lines extend in the direction perpendicular to the substrate surface. The spacing between adjacent active pillars in the direction perpendicular to the substrate surface is smaller than the spacing between adjacent active pillars in the direction parallel to the substrate surface. The difference between the spacing of adjacent first conductive layers in the direction parallel to the substrate surface and the spacing of adjacent first conductive layers in the direction perpendicular to the substrate surface ranges from 5 nm to 20 nm. An air gap exists between adjacent word lines in the direction parallel to the substrate surface, the air gap extends in the direction perpendicular to the substrate surface, and the thickness of the air gap ranges from 5 nm to 15 nm.

[0049] In the technical solution provided by this disclosure embodiment, the spacing between adjacent first conductive layers 121 along the first direction is greater than the spacing between adjacent first conductive layers 121 along the second direction. During the formation of the second conductive layer 122, under the same reaction conditions, the region with smaller spacing can quickly form word lines 120 extending along the second direction. The word lines 120 between adjacent transistors are well connected, reducing the process complexity of word lines 120 while avoiding excessively large defects in word lines 120 due to excessively fast deposition growth rate, thereby affecting the electrical performance of word lines 120. The region with larger spacing forms an air gap 123 or an isolation layer between adjacent word lines 120, reducing the impact of parasitic capacitance between adjacent word lines 120.

[0050] Accordingly, one embodiment of this disclosure provides a method for fabricating a semiconductor structure, which can be used to form the above-mentioned... Figures 1 to 3 The semiconductor structure shown is identical or corresponding to those in the above embodiments and will not be described in detail below.

[0051] Figures 4 to 24 This is a schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to an embodiment of this disclosure.

[0052] in, Figures 4 to 17 This is a schematic cross-sectional view of each step in the fabrication method of the semiconductor structure provided in an embodiment of the present disclosure, corresponding to the cross-section along A-A'. Figures 18 to 24 This is a cross-sectional view of each step in the method for fabricating a semiconductor structure according to an embodiment of the present disclosure, along the B-B' section. The method for fabricating a semiconductor structure according to this embodiment will be described in detail below with reference to the accompanying drawings.

[0053] According to some embodiments of this disclosure, reference is made to Figures 1 to 24 Another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate 100; forming active pillars 110 arranged in an array along a first direction and a second direction on the substrate 100, the active pillars 110 including a channel region 112; forming word lines 120 extending along the second direction, the word lines 120 surrounding the active pillars 110 of the channel region 112, the word lines 120 including a first conductive layer 121 and a second conductive layer 122 stacked together, the spacing L1 between adjacent first conductive layers 121 along the first direction being greater than the spacing L2 between adjacent first conductive layers 121 along the second direction; the first direction being either a direction Z perpendicular to the surface of the substrate 100 or a direction Y parallel to the surface of the substrate 100, and the second direction being either a direction Z perpendicular to the surface of the substrate 100 or a direction Y parallel to the surface of the substrate 100.

[0054] In some embodiments, reference Figure 4The first direction is Z, which is perpendicular to the surface of the substrate 100, and the second direction is Y, which is parallel to the surface of the substrate 100. An alternating first sacrificial layer 101 and a semiconductor layer 102 are sequentially formed on the surface of the substrate 100; a first oxide layer 103 and a protective layer 104 are formed on the top surface of the outermost semiconductor layer 102, which is away from the substrate 100.

[0055] In some embodiments, the material of the first sacrificial layer 101 has a different etching ratio than the material of the semiconductor layer 102. The material of the first sacrificial layer 101 includes silicon nitride, titanium nitride, aluminum nitride, gallium nitride, or indium nitride, and the material of the first oxide layer 103 is silicon oxide. The material of the protective layer 104 includes silicon nitride, titanium nitride, aluminum nitride, gallium nitride, or indium nitride. The semiconductor layer 102 is used as an active pillar in subsequent applications. The material of the semiconductor layer 102 can be doped polycrystalline silicon or monocrystalline silicon, undoped polycrystalline silicon, amorphous silicon or monocrystalline silicon, or amorphous materials.

[0056] refer to Figure 18 The first sacrificial layer 101, semiconductor layer 102, first oxide layer 103, and protective layer 104 are patterned to form a first groove 105, the bottom of which exposes the substrate 100. The first groove 105 can be used as an isolation region for transistors adjacent in a direction Y parallel to the surface of the substrate 100.

[0057] Specifically, along B-B' (reference) Figure 1 A first groove 105 is formed by cross-sectional etching of a first sacrificial layer 101, a semiconductor layer 102, a first oxide layer 103, a protective layer 104, and a portion of the thickness of a substrate 100. Along the direction Y parallel to the surface of the substrate 100, the width of the first groove 105 is smaller than the spacing between adjacent semiconductor layers 102 along the direction Z perpendicular to the surface of the substrate 100, or the width of the first groove 105 is smaller than the thickness of the first sacrificial layer 101. This ensures that the spacing of the first conductive layer subsequently formed on the surfaces of adjacent semiconductor layers 102 differs between the direction Z perpendicular to the surface of the substrate 100 and the direction Y parallel to the surface of the substrate 100.

[0058] refer to Figure 19 A second sacrificial layer 106 is formed, which fills the first groove 105 (reference). Figure 18 The second sacrificial layer 106 material includes oxide or polycrystalline silicon, and the oxide may include silicon oxide, aluminum oxide or titanium oxide.

[0059] refer to Figure 5The first sacrificial layer 101, the second sacrificial layer 106, the first oxide layer 103, and the protective layer 104 are etched to form a second groove that exposes the substrate 100. The extension direction of the second groove intersects the extension direction of the first groove, and the extension direction of the second groove and the extension direction of the first groove 105 are both parallel to the substrate surface.

[0060] Specifically, the second groove extends in a direction Y parallel to the surface of the substrate 100, while the first groove 105 extends in a direction X. Furthermore, the extension direction of the second groove is perpendicular to the extension direction of the first groove 105.

[0061] Continue to refer to Figure 5 A first isolation layer 107 and a second isolation layer 108 are formed, with the second isolation layer 108 located between adjacent first isolation layers 107. Under the same process, the etching rate of the first isolation layer 107 is different from that of the second isolation layer 108; the first oxide layer 103 and the protective layer 104 are removed.

[0062] refer to Figure 6 as well as Figure 20 The first sacrificial layer 101 and the second sacrificial layer 106 are removed to form semiconductor layers 102 spaced apart along a direction Z perpendicular to the surface of the substrate 100 and a direction Y parallel to the surface of the substrate 100. The remaining semiconductor layers 102 serve as active pillars. The spacing between adjacent semiconductor layers 102 along the direction Z perpendicular to the surface of the substrate 100 is greater than the spacing between adjacent semiconductor layers 102 along the direction Y parallel to the surface of the substrate 100.

[0063] In some embodiments, a wet etching process can be used to remove the first sacrificial layer 101, and the etching solution in the wet etching process is a phosphoric acid solution. Specifically, the phosphoric acid concentration is 20-98%, the reaction time is 1-3600s, and the reaction temperature is 25-200℃.

[0064] refer to Figure 7 as well as Figure 21 A second oxide layer 109 is formed, located on the exposed surfaces of the substrate 100, semiconductor layer 102, first isolation layer 107, and second isolation layer 108. The first isolation layer 107, second isolation layer 108, and second oxide layer 109 together constitute isolation layer 114, which is located on the surface of the substrate 100 and between adjacent semiconductor layers 102. The material of the second oxide layer 109 can be silicon oxide.

[0065] refer to Figures 8 to 14 as well as Figures 22-24The process steps for forming word lines include: forming a first conductive layer 121 on the surface of semiconductor layer 102, the first conductive layer 121 surrounding a portion of semiconductor layer 102; selectively growing a second conductive layer 122 on the surface of the first conductive layer 121, the second conductive layer 122 connecting a plurality of semiconductor layers 102 arranged in a direction Y parallel to the surface of substrate 100, and forming an air gap 123 between adjacent second conductive layers 122 in a direction Z perpendicular to the surface of substrate 100.

[0066] refer to Figure 8 A portion of the width of the isolation layer 114 is removed to expose the surface of the channel region of the active pillar. Specifically, the second oxide layer 109 located between adjacent first isolation layers 107 is removed to expose the semiconductor layer 102.

[0067] In some embodiments, smoothing the exposed semiconductor layer 102 to make the active pillars elliptical or near-elliptical in shape along the B-B' cross-section can reduce surface damage and defects in the active pillars, thereby reducing the impedance between the active pillars and subsequently formed word lines. In other embodiments, the active pillars may not be smoothed.

[0068] refer to Figure 9 as well as Figure 22 A conductive film 116 is formed on the surface of the active pillar and the side of the isolation layer 114. A stacked gate dielectric layer 124 and conductive film 116 are formed on the surface of the semiconductor layer 102 and the first isolation layer 107.

[0069] refer to Figure 10 as well as Figure 23 A filling layer 117 is formed, which is located between adjacent conductive films 116. The material of the filling layer 117 can be silicon oxide.

[0070] refer to Figure 11 A patterned portion-width isolation layer 114 exposes the sides of the conductive film 116. The patterned portion-width isolation layer 114 includes: removing a first isolation layer 107 located on the sides of the conductive film 116.

[0071] refer to Figures 11-13 as well as Figure 24 The conductive film 116 located on the side of the isolation layer 114 is etched until the side of the filling layer 117 is exposed, and the remaining conductive film 116 serves as the first conductive layer 121; the filling layer 117 is removed.

[0072] refer to Figure 15 and Figure 3A second conductive layer 122 and an air gap 123 are formed. The second conductive layer 122 is located on the surface of the first conductive layer 121. The first conductive layer 121 and the second conductive layer 122 together constitute the word line 120. The air gap 123 is formed between adjacent word lines 120.

[0073] In some embodiments, the first conductive layer 121 is made of titanium nitride, and the second conductive layer 122 is made of molybdenum. The second conductive layer 122 is formed using atomic layer deposition (ALD). The process conditions for forming the second conductive layer 122 include: using molybdenum dichloride (MoO2Cl2) or molybdenum pentachloride (MoCl5) as a precursor material, using ammonia or hydrogen as an auxiliary reaction gas, and a reaction temperature of 450℃-600℃. Molybdenum dichloride (MoO2Cl2) or molybdenum pentachloride (MoCl5) has a high deposition rate on the surface of titanium nitride, but a lower deposition rate on the surfaces of silicon dioxide and silicon. That is, using molybdenum dichloride (MoO2Cl2) or molybdenum pentachloride (MoCl5) as a precursor material results in highly selective deposition on the surface of titanium nitride, leading to a second conductive layer 122 with fewer defects, thus exhibiting good electrical and structural properties. Furthermore, compared with the conventional process of forming the second conductive layer 122, using molybdenum as the material for the second conductive layer 122 and titanium nitride as the material for the first conductive layer 121 can reduce the process difficulty of forming the second conductive layer 122. Moreover, since the second conductive layer 122 is formed with the first conductive layer 121, there is no need to define the position of the second conductive layer to avoid the problem of electrical connection between adjacent second conductive layers, thus reducing the process steps and process difficulty of forming the word line 120.

[0074] refer to Figure 16 Remove the remaining first isolation layer 107 to expose the surface of the semiconductor layer 102.

[0075] refer to Figure 17 A first metal contact layer 131 and a second metal contact layer 141 are formed. The semiconductor layer 102 located between the first metal contact layer 131 and the second metal contact layer 141 serves as an active pillar 110. The region in contact with the first metal contact layer 131 is defined as the first source / drain region 111 of the active pillar 110. The semiconductor layer 102 surrounding the word line 120 is defined as the channel region 112 of the active pillar 110. The region in contact with the second metal contact layer 141 is defined as the second source / drain region 113 of the active pillar 110.

[0076] In some embodiments, a second metal contact layer 141 is formed simultaneously with the formation of a first metal contact layer 131. Forming both the first and second metal contact layers 131 using the same fabrication process simplifies the semiconductor structure fabrication process and reduces production costs. The first metal contact layer 131 can be formed by first forming a metal layer and then annealing it at high temperature to convert a portion of the semiconductor layer into the first metal contact layer 131; or by performing an ion implantation process on a portion of the semiconductor layer and then annealing it at high temperature to form the first metal contact layer 131.

[0077] Continue to refer to Figure 17 A dielectric layer 126 is formed, which is located in the direction Z perpendicular to the surface of the substrate 100, between adjacent first metal contact layers 131 and adjacent second metal contact layers 141. The dielectric layer 126 is also located on the top surface of the second isolation layer 108, the insulating layer 125 and the word line 120.

[0078] refer to Figures 1-3 A bit line 130 extending along a first direction, Z, perpendicular to the surface of the substrate 100, is formed. The bit line 130 is electrically connected to the active pillars 110 of the first source / drain region 111 through a first metal contact layer 131. Specifically, the bit line 130 is formed by removing the second oxide layer 109 and the semiconductor layer 102 located on one side of the dielectric layer 126 to form a third groove. A conductive material is deposited in the third groove, and a portion of the conductive material is etched away, forming the bit line 130 perpendicular to the surface of the substrate 100 in the third groove. Simultaneously, a third isolation layer is formed within the remaining third groove, located between adjacent bit lines. The conductive material can be metals such as tungsten, copper, molybdenum, and silver, or polycrystalline silicon.

[0079] Continue to refer to Figures 1-3 A capacitor structure 140 is formed, which is electrically connected to the active pillar 110 of the second source / drain region 113 through a second metal contact layer 141. The capacitor structure 140 surrounds the semiconductor layer 102. The capacitor structure 140 corresponds one-to-one with the active pillar 110, that is, the memory cell may include a three-dimensional (3D) DRAM memory cell with a 1T-1C (1 transistor-1 capacitor) structure. A fourth isolation layer is provided between adjacent capacitor structures 140.

[0080] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; An active column is located on the substrate and arranged in an array along a first direction and a second direction. The active column includes a channel region. The spacing between adjacent active columns along the first direction is greater than the spacing between adjacent active columns along the second direction. A word line extending along a second direction, the word line surrounding an active post in a channel region, the word line comprising a stacked first conductive layer and a second conductive layer, wherein the spacing between adjacent first conductive layers along the first direction is greater than the spacing between adjacent first conductive layers along the second direction. The first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, An air gap exists between adjacent word lines along the first direction, and the air gap extends along the second direction.

3. The semiconductor structure according to claim 1, characterized in that, The first conductive layer surrounds the channel region of the active pillar, and the second conductive layer is formed on the surface of the first conductive layer and connects the plurality of active pillars arranged in a second direction.

4. The semiconductor structure according to claim 2, characterized in that, The difference between the spacing of adjacent first conductive layers along the first direction and the spacing of adjacent first conductive layers along the second direction ranges from 5nm to 20nm; the thickness of the air gap along the first direction ranges from 5nm to 15nm.

5. The semiconductor structure according to claim 1, characterized in that, The active pillar further includes a first source / drain region and a second source / drain region located on both sides of the channel region, and the semiconductor structure further includes: A bit line extending along the first direction, the bit line being connected to the active post of the first source / drain region; A capacitor structure is located on the substrate and is connected to the active pillar of the second source / drain region; A first metal contact layer and a second metal contact layer, wherein the first metal contact layer is located between the active post and the bit line, and the second metal contact layer is located between the active post and the capacitor structure.

6. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; Active pillars are formed on the substrate in an array arranged along a first direction and a second direction. Each active pillar includes a channel region. The spacing between adjacent active pillars along the first direction is greater than the spacing between adjacent active pillars along the second direction. A word line extending along a second direction is formed, the word line surrounds the active pillar of the channel region, the word line includes a stacked first conductive layer and a second conductive layer, and the spacing between adjacent first conductive layers along the first direction is greater than the spacing between adjacent first conductive layers along the second direction. The first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The method further includes: forming an isolation layer located on the substrate surface and between adjacent active pillars; The process steps for forming the word lines include: forming a first conductive layer on the surface of the active pillar, the first conductive layer surrounding the channel region of the active pillar; selectively growing a second conductive layer on the surface of the first conductive layer, the second conductive layer connecting a plurality of active pillars arranged in a second direction, and forming an air gap between adjacent second conductive layers in a direction perpendicular to the surface of the substrate.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The active pillar further includes a first source / drain region and a second source / drain region located on both sides of the channel region, and the process steps for forming the first conductive layer include: Remove a portion of the isolation layer to expose the surface of the channel region of the active post; A conductive film is formed on the surface of the active pillar and on the side of the isolation layer; A filling layer is formed between adjacent conductive films; A patterned portion of the isolation layer exposes the sides of the conductive film; The conductive film located on the side of the isolation layer is etched until the side of the filling layer is exposed, and the remaining conductive film serves as the first conductive layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The isolation layer includes a first isolation layer and a second isolation layer, the second isolation layer being located between adjacent first isolation layers. Under the same process, the etching rate of the first isolation layer is different from that of the second isolation layer. The isolation layer with the patterned portion width includes: removing the first isolation layer located on the side of the conductive film.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, After forming the word lines, the process also includes: Remove the first isolation layer; A first metal contact layer and a second metal contact layer are formed. The first metal contact layer is located between the active post and the bit line, and the second metal contact layer is located on the side of the active post in the second source / drain region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The second metal contact layer is formed simultaneously with the formation of the first metal contact layer.

12. The method for preparing a semiconductor structure according to claim 7, characterized in that, The process steps for forming the active column include: A first sacrificial layer and a semiconductor layer are sequentially formed at intervals on the surface of the substrate; The first sacrificial layer and semiconductor layer in the patterned portion form a first groove, the bottom of the first groove exposing the substrate, and the width of the first groove is less than the thickness of the first sacrificial layer; A second sacrificial layer is formed in the first groove; The first sacrificial layer is removed, and the remaining semiconductor layer serves as the active pillar.

13. The method for preparing a semiconductor structure according to claim 6 or 7, characterized in that, The first conductive layer is made of titanium nitride, and the second conductive layer is made of molybdenum.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The second conductive layer is formed using atomic layer deposition technology. The process conditions for forming the second conductive layer include: using molybdenum dioxide (MoO2Cl2) or molybdenum pentachloride (MoCl5) as the precursor material, using ammonia or hydrogen as the auxiliary reaction gas, and the reaction temperature is 450℃-600℃.

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