DC-dc step-down SMPS

Abstract

Embodiments of the present disclosure relate to DC-DC buck SMPS. The present disclosure relates to a switched mode power supply buck converter comprising a switch coupled between a node receiving a supply potential and an internal node, another switch coupled between the internal node and a node receiving a reference potential, an inductive element coupling the internal node to an output node, and a control circuit controlling the switches such that a current pulse in the inductive element has a maximum value selected from at least a first value and a second value based on an average current drawn at the output node by the control circuit.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to French application number 2104945, filed on May 10, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to electronic circuits, and in certain embodiments, to a switch-mode power buck converter. Background Technology

[0004] Among known switch-mode power supply (SMPS) buck converters, those that operate using pulse frequency modulation (PFM) are different.

[0005] In a known pulse frequency modulation converter, as the converter's output voltage decreases and moves away from the set value, energy is supplied to the inductor during an energy accumulation phase and recovered by the inductor at the converter output during an energy recovery phase. Each successive energy accumulation and energy recovery phase corresponds to a current pulse in the inductor.

[0006] In this known PFM converter, the current pulses in the inductor all have the same maximum value. The converter's output voltage is then regulated by modifying the current pulse frequency. Furthermore, the maximum current pulse value determines the maximum average current the converter can deliver (i.e., the maximum average current the load can draw from the converter output). This maximum average current that the converter can deliver represents the high end of the range of current values ​​on which the converter operates, while the low end corresponds to zero or near-zero average current.

[0007] It is necessary to overcome some or all of the known drawbacks of PFM converters.

[0008] For example, it is necessary to increase the range of average current values ​​that a known PFM converter can deliver without increasing the startup time of these converters or the ripple amplitude of the output voltage provided by these converters. Summary of the Invention

[0009] One embodiment addresses all or some of the drawbacks of known PFM converters.

[0010] The embodiments allow for an increase in the maximum average current that the PFM converter can deliver without increasing its startup time or the ripple amplitude of the output voltage provided by the converter.

[0011] One embodiment provides a switch-mode power buck converter having a first switch and a second switch. The first switch is configured to be connected between a node receiving a power supply potential and an internal node; the second switch is connected between the internal node and a node configured to receive a reference potential; an inductor couples the internal node to the output node of the converter; and control circuitry is configured to control the first and second switches such that a current pulse in the inductor has a maximum value, the maximum value being selected from at least a first value and a second value based on the average current drawn at the output node.

[0012] One embodiment provides a control method comprising: using control circuitry to select, from at least a first value and a second value, a maximum value of a current pulse in an inductor that couples an internal node of a switch-mode power buck converter to an output node of the converter, the selection being based on an average current drawn at the output node; and using control circuitry to control a first switch connected between a node receiving a power supply potential and an internal node, and a second switch connected between an internal node and a node receiving a reference potential, such that the maximum value of the current pulse is equal to the selected value.

[0013] According to one embodiment, the control circuit is configured to select at least a maximum value from a first value and a second value, such that the maximum value increases when the average current increases and decreases when the average current decreases.

[0014] According to one embodiment, the first value is less than the second value; when the average current is greater than the first threshold, the control circuit selects the second value; and when the average current is less than the second threshold, less than or equal to the first threshold, the control circuit selects the first value.

[0015] According to one embodiment, the second threshold is less than the first threshold.

[0016] According to one embodiment, when a first value is selected at the end of each current pulse, the control circuit triggers a first temporization (i.e., a timing period) representing a first threshold; and if the start of the next current pulse occurs during the first temporization, the control circuit selects a second value, wherein when the second value is selected, at the end of each current pulse, the control circuit triggers a second temporization representing a second threshold; and if the start of the next current pulse occurs after the second temporization, the control circuit selects the first value.

[0017] According to one embodiment, the duration of each first timescale is less than the duration of each second timescale.

[0018] According to one embodiment, the maximum value is selected from at least a first value, a second value, and a third value greater than the second value.

[0019] According to one embodiment, when the average current is greater than a third threshold and greater than a first threshold, the control circuit selects a third value; and when the average current is less than a fourth threshold, greater than the first threshold, and less than or equal to the third threshold (preferably less than the third threshold), the control circuit selects a second value.

[0020] According to one embodiment, when the second value is selected: at the end of each current pulse, the control circuit also triggers a third time-sharing representing a third threshold; and if the start of the next current pulse occurs during the third time-sharing, the control circuit selects the third value, and wherein when the third value is selected, at the end of each current pulse, the control circuit triggers a fourth time-sharing representing a fourth threshold; and if the start of the next current pulse occurs after the fourth time-sharing, the control circuit selects the second value.

[0021] According to one embodiment, the end of each current pulse corresponds to the opening of the second switch when the first switch is open, and the beginning of each current pulse corresponds to the closing of the first switch when the second switch is open.

[0022] According to one embodiment, the average current is determined from the control signals of the first switch and the second switch.

[0023] According to one embodiment, the average current is determined by the delay between every two consecutive current pulses.

[0024] According to one embodiment, the first switch and the second switch are controlled in a pulse frequency modulation PFM.

[0025] According to one embodiment, at each current pulse, the duration of the on state of the first switch is determined by comparing a first voltage ramp with a first potential, the first potential being determined by a set value of the output potential of the converter; the duration of the on state of the second switch is determined by comparing a second voltage ramp with a second potential, the second potential being determined by a set value; and the slopes of the first voltage ramp and the second voltage ramp vary depending on the value selected as the maximum value. Attached Figure Description

[0026] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0027] Figure 1 This is a schematic diagram of an embodiment of a pulse frequency modulation (PFM) modulator;

[0028] Figure 2 This is a timing diagram corresponding to the control method in the embodiment;

[0029] Figure 3 This is a flowchart of the method in the embodiment;

[0030] Figure 4It is a graph corresponding to the method of the embodiment;

[0031] Figure 5 This is a flowchart of the method in the embodiment;

[0032] Figure 6 This is a flowchart of the method in the embodiment;

[0033] Figure 7 This is a timing diagram corresponding to the method in the embodiment;

[0034] Figure 8 This is a block diagram of the circuit in the embodiment;

[0035] Figure 9 This is a block diagram of the converter in the embodiment;

[0036] Figure 10 This is a block diagram of an embodiment of the converter, specifically a ramp generator; and

[0037] Figure 11 This is a flowchart of the implementation method. Detailed Implementation

[0038] In the various figures, similar features are designated by similar reference numerals. Specifically, structural or functional features common to various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0039] For clarity, only operations and components useful for understanding the embodiments described herein are illustrated and described in detail. Specifically, conventional electronic systems and applications including PFM converters are not described, and the described embodiments, implementation modes, and variations are compatible with such conventional electronic systems and applications. Furthermore, not all conventional conditions for generating current pulses in the inductive elements of a PFM converter are described, and the described embodiments are compatible with such conventional conditions and implementation methods used to verify them.

[0040] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0041] In the following disclosure, unless otherwise indicated, when referring to absolute positional qualifiers (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or relative positional qualifiers (such as the terms "above", "below", "higher", "lower", etc.) or orientational qualifiers (such as "horizontal", "vertical", etc.), the orientation shown in the accompanying drawings shall be used.

[0042] Unless otherwise specified, the expressions “around,” “approximately,” “substantially,” and “about” indicate within 10%, preferably within 5%.

[0043] Figure 1 An embodiment of PFM converter 1 is shown schematically. Converter 1 is configured to provide a DC output potential Vout from a DC power supply potential Vsupply. Both potentials are referenced to a reference potential GND (such as ground). The value of potential Vout is lower than the value of potential Vsupply.

[0044] Converter 1 is configured to provide a potential Vout such that it is equal to a set value. Converter 1 receives this set value as a potential Vref representing the set value. Potential Vref is referenced to potential GND.

[0045] In the remainder of the description, by way of example, the value of potential Vref is considered equal to the set value of potential Vout. Therefore, by comparing this potential with potential Vref, a direct comparison of the value of a given potential with the set value can be performed. However, those skilled in the art can apply the following description to cases where the value of potential Vref is lower than the set value of potential Vout. In this case, the value of the given potential can be compared with the set value by dividing the potential using a voltage divider bridge, for example, to obtain an intermediate potential representing the value of the given potential. This intermediate potential is then compared with potential Vref, which is equivalent to comparing the value of potential Vout with its set value.

[0046] The converter 1 includes a switch IT1 connected between node 104, which is configured to receive a potential Vsupply, and an internal node 106. In an embodiment, switch IT1 is implemented using a metal-oxide-semiconductor (MOS) transistor, such as a P-channel MOS transistor.

[0047] The converter 1 also includes a switch IT2 connected between node 106 and node 102 configured to receive a GND potential. In an embodiment, switch IT2 is implemented by a MOS transistor such as an N-channel MOS transistor.

[0048] Converter 1 includes an inductor L connected between node 106 and output node 108 of converter 1. Converter 1 is configured to provide a potential Vout at node 108.

[0049] Capacitor C is connected between nodes 108 and 102. According to one example, capacitor C is entirely part of converter 1. According to another example, capacitor C corresponds to the equivalent capacitance of the output capacitor of converter 1 and the input capacitor of load 110, and is connected between nodes 108 and 102 and powered by converter 1. Figure 1In the diagram, current source 111 shows the current drawn by load 110 at node 108, and current source 111 is connected in parallel to capacitor C between node 108 and node 102.

[0050] Typically, in a PFM converter, during the energy accumulation phase in inductor L, switch IT1 is on and switch IT2 is off. Conversely, during the energy recovery phase of element L at node 108, switch IT1 is off and switch IT2 is on. Each successive energy accumulation and energy recovery phase corresponds to a pulse of current IL in inductor L.

[0051] Converter 1 includes a control circuit CTRL. The CTRL circuit is configured to control switches IT1 and IT2. More specifically, the CTRL circuit is configured to modulate the control of switches IT1 and IT2 at a pulse frequency. The CTRL circuit provides a control signal cmd1 to switch IT1 and a control signal cmd2 to switch IT2. In an embodiment, signal cmd1 is a binary signal that turns on switch IT1 when "low" and turns off switch IT1 when "high," and signal cmd2 is a binary signal that turns on switch IT2 when "high" and turns off switch IT2 when "low." However, this description is not limited to these examples of control signals.

[0052] For example, as a case study, the circuit CTRL is configured to control the start of a current pulse IL in element L when the value of potential Vout becomes less than a threshold Vout_th, where the threshold Vout_th is determined to be a set value of potential Vout. Therefore, the circuit CTRL is configured to receive potential Vout and Vref.

[0053] Preferably, when the value of potential Vout becomes less than the threshold Vout_th, circuit CTRL is configured to initiate current pulse IL because the current IL in element L is zero. Circuit CTRL is only configured to control the start of a pulse if potential Vout is below the threshold Vout_th and current IL is zero. In other words, for each current pulse in the inductor element, if potential Vout is below the threshold Vout_th and current IL is zero, circuit CTRL controls the start of the pulse. For example, when potential Vout is below the threshold Vout_th, circuit CTRL does not control the start of a new pulse IL as long as current IL is not zero. Then converter 1 always operates in discontinuous conduction mode (DCM), and circuit control switches IT1 and IT2 cause converter 1 to operate in DCM mode in this case, as... Figure 1As illustrated, the circuit CTRL is configured to receive an EOC signal indicating when the current IL is zero. As an example, the EOC signal is provided by circuit 112 of converter 1, for example, circuit 112 is connected to node 106.

[0054] In this description, the circuit CTRL is configured to control switches IT1 and IT2 such that the current pulse IL in element L has a maximum value Valmax, which is selected from two values ​​val1 and val2 based on the average current Im drawn by load 110 at node 108.

[0055] The circuit CTRL is configured to select either value val1 or val2 based on the value of the current Im, and then control switches IT1 and IT2 such that each current pulse IL has a maximum value Valmax equal to the selected value val1 or val2.

[0056] The circuit CTRL allows the maximum value valmax of the current pulse IL to be adapted to the current value Im. Preferably, this adaptation of the value valmax of the pulse IL is discrete and depends on the value of the current Im (i.e., the value valmax cannot change continuously), or in other words, the value valmax can only have discrete values.

[0057] The fact that the current pulse IL can have two maximum values, val1 and val2, differs from the fact known in conventional PFM converters, where the maximum current pulse value in the inductive element of these converters remains the same regardless of the value of the average current drawn by the load connected to its output.

[0058] According to one embodiment, the control circuit is configured to select the maximum value valmax from values ​​val1 and val2, such that the maximum value valmax of the current pulse IL increases when the average current increases and decreases when the average current decreases.

[0059] Given that value val2 is greater than value val1, when the pulse value valmax equals value val1 (i.e., the selected value val1 or val2 is value val1) and the current Im increases, the circuit CTRL is configured to select value val2, causing value valmax to increase. Conversely, when value valmax equals val2 and current Im decreases, the circuit CTRL is configured to select value val1, causing value valmax to decrease.

[0060] Therefore, for the low value of current Im relative to the high value of current Im, the current pulse IL has a low maximum amplitude valmax relative to the high value of current Im.

[0061] Therefore, when load 110 draws a low average current Im, the maximum amplitude of the current pulse IL is lower, which reduces the ripple amplitude of the potential Vout compared to a constant and higher maximum amplitude of the current pulse IL. Furthermore, when the maximum amplitude of the current pulse IL is high, the maximum value of the current Im that load 110 can draw from node 108 without losing regulation of the potential Vout at its setpoint is higher compared to a constant and lower maximum amplitude of the current pulse IL. In fact, the maximum value of the current Im that load 110 can draw from node 108 without losing regulation of the voltage Vout at its setpoint is equal to half the maximum value of the current pulse IL amplitude.

[0062] To increase the maximum value of the current Im in a PFM converter with a constant maximum amplitude current pulse IL, increasing the constant maximum amplitude of the IL current pulse can be considered. However, in this case, if the current Im drawn by the load 110 is small, for example, at least twice the maximum current Im, this will result in a large fluctuation in the voltage Vout, which is undesirable. To reduce the amplitude of these voltage ripples in Vout, increasing the value of the capacitor C can be considered. However, this will significantly increase the startup time of converter 1, because the time required to charge capacitor C until the potential Vout equals its set value will be longer. Additionally, this will result in an increase in the total occupied area of ​​converter 1 and capacitor C, which is also undesirable.

[0063] According to one embodiment where the value val1 is less than the value val2, the circuit CTRL is configured to select the value val2 when the current Im is greater than the threshold th1, and to select the value val1 when the current Im is less than the threshold th2, wherein the threshold th2 is less than or equal to the threshold th1.

[0064] According to one embodiment, the threshold th2 is lower than (i.e., strictly lower than) the threshold th1, thus suppressing possible instabilities in the maximum value valmax of the current pulse IL that occurs when the thresholds th1 and th2 are equal and the value valmax switches between the values ​​val1 and val2.

[0065] Figure 2 The illustration shows Figure 1 A timing diagram of an embodiment of the control method implemented in converter 1, more specifically a timing diagram of a method for controlling switches IT1 and IT2, implemented by circuit CTRL.

[0066] Figure 2 The current IL ( is shown) Figure 2 (top of the middle) and average current Im ( Figure 2 The bottom of the equation (in the equation) depends on the evolution at time t.

[0067] exist Figure 2In the example shown, threshold th2 is lower than threshold th1, although in other examples not shown these thresholds may be equal.

[0068] exist Figure 2 In the example, the current Im is less than the thresholds th1 and th2 at time t0, so the current pulse IL has a maximum value valmax equal to the value val1.

[0069] At time t1 after time t0, the current Im becomes greater than the threshold th2. However, since the threshold th2 is lower than the threshold th1 here, and since the current Im at time t1 is still lower than the threshold th1, the maximum value valmax of the current pulse IL remains equal to the value val1.

[0070] At time t2, after time t1, the current Im becomes equal to the threshold th1 and then greater than the threshold th1. Then the value val2 is selected, and starting from time t2, the maximum value valmax of the current pulse IL is equal to val2.

[0071] exist Figure 2 In the example, the current Im increases from time t0 to time t3 after time t2. Therefore, the frequency of the current pulse IL increases between time t0 and time t2. Furthermore, this frequency changes or decreases, for example, when the maximum value valmax of the current pulse IL switches from value val1 to value val2. From time t2 to time t3, the frequency of the current pulse IL increases.

[0072] At time t4, after time t3, the current Im becomes lower than the threshold th1. However, since the threshold th2 is lower than the threshold th1 at this time, and at time t3, the current Im is still higher than the threshold th2, the maximum value valmax of the current pulse IL remains equal to the value val2.

[0073] At time t5, after time t4, the current Im becomes lower than the threshold th2. Then the value val1 is selected, and starting from time t4, the maximum value valmax of the current pulse IL is equal to val1.

[0074] exist Figure 2 In the example, the current Im decreases from time t3 until time t6, which follows time t5. Therefore, the frequency of the current pulse IL decreases between time t3 and time t5. Furthermore, this frequency changes or increases, for example, when the maximum value valmax of the current pulse IL switches from value val2 to value val1. From time t5 to time t6, the frequency of the current pulse IL decreases.

[0075] Although not described in detail above, each current pulse IL starts with switch IT1 being closed and switch IT2 being open. The current IL then increases until it reaches the selected value valmax (val1 between times t0 and t2 and between times t5 and t6; val2 between times t2 and t5). The moment when the current IL reaches the selected value valmax corresponds to the moment when switch IT1 is opened and switch IT2 is turned on. The current IL then decreases until it cancels out. The moment when the current cancels out corresponds to the moment when switch IT2 is switched to the open state.

[0076] Figure 3 illustrated in the form of a flow chart the method illustrated by the timing diagram of Figure 2 .

[0077] In step 300 (the block "valmax=val1"), valmax is equal to val1, or in other words, the circuit CTRL ( Figure 1 ) has selected val1 as the maximum value valmax of the current pulse IL.

[0078] Step 300 is followed by step 302 (the block "Im>th1"), in which the circuit CTRL compares the current Im with a threshold th1.

[0079] If the current Im is smaller than the threshold th1 (output N of step 302), the method continues in step 300 and valmax remains equal to val1.

[0080] If the current Im is greater than the threshold th1 (output Y of step 302), the method continues in step 304 (the block "valmax=val2").

[0081] In step 304, valmax becomes equal to the value val2, or in other words, the circuit CTRL selects val2 as the maximum value valmax.

[0082] Step 304 is followed by step 306 (the block "Im<th2"), in which the circuit CTRL compares the current Im with a threshold th2.

[0083] If the current Im is greater than the threshold th2 (output N of step 306), the method continues in step 304 and valmax remains equal to val2.

[0084] If the current Im is smaller than the threshold th2 (output Y of step 306), the method continues in step 300, where the value valmax becomes equal to the value val1, or the circuit CTRL selects the value val1 as the maximum value valmax.

[0085] Although the case where threshold th2 is less than threshold th1 has been combined Figure 2 However, those skilled in the art can apply the above method to the case where thresholds th1 and th2 are equal.

[0086] Figure 4 It is illustrated as a curve of 400. Figure 2 and 3 An example implementation of the method. More specifically, in the example where threshold th2 is lower than threshold th1, Figure 4 The diagram illustrates the evolution of the maximum value valmax of the current pulse IL depending on the value of the average current Im.

[0087] As the current Im increases from values ​​below the thresholds th1 and th2 (point 402 on curve 400), valmax remains equal to val1 until the current value Im reaches the threshold th1 (point 404 on curve 400). When the current value Im continues to increase above the threshold th2, valmax becomes equal to the value val2 (point 406 on curve 400).

[0088] Conversely, as the current Im decreases from values ​​above the thresholds th1 and th2 (point 408 on curve 400), valmax remains equal to val2 until the current value Im reaches the threshold th2 (point 410 on curve). When the current value Im continues to decrease below the threshold th2, valmax becomes equal to val1 (point 412 on curve 400).

[0089] Therefore, since the threshold th2 is strictly less than the threshold th1, there is a lag in the change of the value valmax between the values ​​val1 and val2, which allows for a reduction in the instability of the value valmax compared to when the thresholds th1 and th2 are equal.

[0090] To implement the above method, converter 1 ( Figure 1 This includes circuitry, for example, configured to measure the evolution of the current IL over time and provide a signal representing the value of the average current Im drawn by the load 110 at node 108. However, such circuitry can be cumbersome and may degrade converter performance, for example, when the current IL is measured through a resistor connected in series with element L between nodes 104 and 108.

[0091] It is suggested here that the frequency of the current pulse IL, and more specifically the difference between the end of one current pulse IL and the beginning of the next, is information representing the value of the current Im. In fact, for a given value valmax, this frequency increases or decreases as the corresponding current Im increases or decreases. Therefore, when the corresponding current Im increases or decreases, the gap between two consecutive current pulses IL increases or decreases.

[0092] Figure 5 It is shown in the form of a flowchart Figure 3 One embodiment of step 302 of the method. In this embodiment, the start and end times of the current pulse IL are used to estimate or determine the current Im, or to obtain information representing the value of the current Im. In this embodiment, step 302 is performed by the circuit CTRL ( Figure 1 ) Implementation.

[0093] Step 302 begins at step 500 (“End Pulse?” box). Step 500 involves waiting for the current pulse IL to end. Step 500 is repeated (output N of step 500) until the current pulse IL ends, or more precisely, until the moment the pulse ends.

[0094] When the current pulse IL ends (output Y of step 500), the method continues to step 502 (box “Start temp1”), where timed temp1 begins.

[0095] The method continues in step 504 (box “Start Pulse and temp1 ≠ 0?”). Step 504 involves waiting for the start of a subsequent current pulse IL, more specifically waiting for the start of a current pulse IL after the current pulse IL following the current pulse IL, the end of which causes the timer temp1 to start. Furthermore, when the next current pulse IL begins, if the timer temp1 has already ended (… Figure 3 The outputs N of steps 504 and 302 cause the current Im to be lower than the threshold th1. Conversely, if the timed temp1 has not ended when the next current pulse IL begins (the outputs Y of steps 504 and 302), the current Im is greater than the threshold th1. Therefore, in combination Figure 5 In the embodiment of step 302 described, the duration or time-varying temp1 represents the threshold th1.

[0096] Figure 6 It is shown in the form of a flowchart Figure 3 One embodiment of step 306 of the method. In this embodiment, the start and end times of the current pulse IL are used to estimate the current Im. Step 306 begins at step 600 (“End Pulse” box). With step 500 ( Figure 5 Similar to step 600, step 600 includes waiting for the current pulse IL to end. Step 600 is repeated (output N of step 600) until the current pulse IL ends, more precisely, until the moment the pulse ends. When the current pulse IL ends (output Y of step 600), the method continues to step 602 (“Start temp2” box), where timed temp2 begins.

[0097] The method continues in step 604 (box “Start pulse and temp2 = 0?”). Step 604 includes waiting for the start of a subsequent current pulse IL, more precisely waiting for the start of a current pulse IL after the current pulse IL, the end of which causes the start of timed temp2. ​​Furthermore, if timed temp2 has ended when the next current pulse IL begins (output Y of steps 604 and 306), the current Im is below the threshold th2. On the other hand, if timed temp2 has not yet ended when the next current pulse IL begins (output N of steps 604 and 306), the current Im is greater than the threshold th2. Therefore, in combination with... Figure 6 In the embodiment of step 306 described, the duration or time-varying temp2 represents the threshold th2.

[0098] Figure 7 The timing diagram is shown. Figure 3 The implementation method has the following characteristics: Figure 5 and 6 The steps described. More specifically, Figure 7 The diagram illustrates the evolution of the current IL, the control signals cmd1 and cmd2 used for switching IT1 and IT2, the time-varying signals temp and Sel depending on time t.

[0099] The signal Sel is a digital signal whose state indicates the current value val1 or val2 of the maximum value valmax of the current pulse. In this embodiment, the signal Sel is a binary signal with a first state. Figure 7 In the example, it is in a low state, where the indicator value val1 is selected as the maximum value valmax of the current pulse IL, and it has a second state, in Figure 7 In the example, the state is high, and the indicator value val2 is selected as the maximum value valmax of the current pulse IL.

[0100] In addition, Figure 7 In the example, when the corresponding signal cmd1 is low or high, switch IT1 ( Figure 1 ) are respectively considered to be on or off. When the corresponding signal cmd2 is high or low, switch IT2 ( Figure 1 These are respectively considered as being on or off.

[0101] Those skilled in the art can provide other examples in which the high and low levels of signal cmd1, signal cmd2, or signal Sel differ from those indicated herein as examples.

[0102] At time t10, signal Sel is low, indicating that the maximum value valmax of the current pulse IL is equal to the value val1. Time t10 corresponds to the end of the current pulse IL (step 500). Figure 5 Advantageously, in Figure 7 In this example, the end of the current pulse IL is detected by turning off the signal cmd2, which controls the switching of the command switch IT2; that is, in this example, the signal cmd2 is switched to a low level. Furthermore, time t10 corresponds to the start of the timed temp1 (step 502). Figure 5 In this example, this corresponds to switching the signal temp to a high state.

[0103] At a subsequent time t11, the next current pulse IL begins (step 504). Figure 5 Advantageously, in Figure 7 In the example, the end of the current pulse IL is detected by turning on the signal cmd1, which controls the switching of switch IT1 (i.e., switching signal cmd1 low in this example). Furthermore, at time t11, time-diminished temp1 has ended, and in this example, signal temp is low. Therefore, the value valmax remains equal to val1. Figure 5 Step 504 and Figure 3 The output N in step 302.

[0104] At time t12, following time t11, the current pulse IL ends, which in this example is detected by switching the signal cmd2 low. Since the value valmax equals the value val1, this causes the timed temp1 to begin.

[0105] At a subsequent time t13, the next current pulse IL begins. In this example, the start of the next current pulse IL is detected by switching the signal cmd1 low. Since temp1 has not yet ended at time t13 (when the signal temp is high), this causes the value val2 to be selected as the new maximum value valmax of the current pulse IL. Figure 5 Step 504 and Figure 3 The output of step 302 is Y3). Therefore, in this example, signal Sel switches to the high state at time t13.

[0106] Starting from time t13, switches IT1 and IT2 are controlled such that the maximum value of the current pulse valmax (specifically, the current pulse starting from time t13) is equal to the value val2.

[0107] At time t14, which follows time t13, the current pulse IL that started at time t12 ends (step 600). Figure 6 The end of this current pulse corresponds to the signal cmd2 switching to a low level in this example. Since the value valmax is now equal to the value val2 (Sel high signal), this causes the timed temp2 to begin (step 602, Figure 2 ).

[0108] At a subsequent time t15, the next current pulse IL begins (step 604). Figure 6 In this example, the start of the current pulse IL corresponds to switching the signal cmd1 low. Since timer temp2 has not yet ended at time t15, the value valmax remains unchanged and is equal to the value val2. Figure 6 Step 604 and Figure 3 The output N in step 306.

[0109] At time t16, after time t15, when the value valmax is still equal to the value val2, the current pulse IL ends and the timer temp2 begins.

[0110] When time temp2 has ended, the next current pulse IL begins at time t17, after time t15. This makes the value val1 the new maximum value valmax of the current pulse IL. Figure 6 Step 604 and Figure 3 The output Y in step 306. Therefore, in this example, signal Sel switches to a low state at time t17.

[0111] In an embodiment, such as Figure 7 As shown, the duration of timed temp1 is shorter than the duration of timed temp2.

[0112] Figure 8 An example embodiment of circuit 800 is shown, which is configured to implement Figure 5 and 6 The steps (i.e., implementation) Figure 7 (The method illustrated). In an embodiment, in Figure 8 In the signal, the corresponding high or low state of signal cmd1 controls the corresponding off or on state of switch IT1, the corresponding high or low state of signal cmd2 controls the corresponding off or open state of switch IT2, the high or low state indication value valmax of signal Sel is equal to the corresponding value val2 or val1, and depending on the value of signal Sel, the timer temp1 or temp2 starts from switching signal temp to high level and ends by switching signal temp to low level.

[0113] As an example, circuit 800 is circuit CTRL( Figure 1 Part of the circuit 800. Circuit 800 receives signals cmd1 and cmd2 and provides signal Sel. In addition, circuit 800 uses signal Sel to determine which value val1 or val2 is selected as the maximum current value valmax of the current pulse IL.

[0114] Circuit 800 includes circuit 802, which is configured to receive signal cmd2 and indicate a selected value val1 or val2 (i.e., signal Sel in this example). Circuit 800 is also configured to provide timed temp1 and temp2, which are signals temp in this example.

[0115] More specifically, in this example, when signal cmd2 switches to "low level", if signal Sel is low level, circuit 802 switches temp signal to "high level" for a duration corresponding to the duration of timed temp1, and if signal Sel is high level, it switches temp signal to "high level" for a duration corresponding to the duration of timed temp2.

[0116] Circuit 800 also includes a D flip-flop 804. Flip-flop 804 has a data input D configured to receive a signal temp. Flip-flop 804 also includes a timing input CK and an output Q. The state of input D is copied to output Q on each edge (rising edge in this example) of the signal received through its input CK, and the output level is maintained (stored) on its input CK until the next edge, rising edge in this example. More specifically, in this example, input CK of flip-flop 804 is configured to receive a signal Ncmd1 complementary to signal cmd1, which is low or high when signal cmd1 is in a corresponding high or low state. Therefore, each falling edge of signal cmd1 results in an update of output Q of flip-flop 804. Thus, circuit 800 provides a combination of... Figure 7 The signal Sel is described.

[0117] Depending on the signal Sel, the circuit CTRL( Figure 1 Then, the duration of the "on" state of switches IT1 and IT2 is adapted such that the maximum value valmax of the current pulse IL is equal to the selected value val1 or val2 (i.e., the value va1 or val2 indicated by the signal Sel). Those skilled in the art can provide methods for implementation. Figure 5 and 6 Other embodiments of the circuit for the steps.

[0118] Figure 9 It shows Figure 1 A more detailed example of an embodiment of converter 1, wherein only the circuit CTRL of converter 1 is as follows: Figure 9As shown. The circuit CTRL receives potential Vout, potential Vref, and preferably an EOC signal. The circuit CTRL includes circuit 900, which is configured to receive potentials Vref and Vout, and preferably an EOC signal. Circuit 900 is configured to provide a start signal whose state (such as switching from a low state to a high state) instructs the circuit CTRL to control element L ( Figure 1 The current pulse IL in ).

[0119] The circuit CTRL includes a digital circuit 902, such as a state machine, that receives a start signal and provides signals cmd1 and cmd2.

[0120] Circuit 902 is configured to provide a signal, such as a signal Sel, indicating which value val1 or val2 is selected as the current value valmax of the current pulse IL. In an embodiment, circuit 902 includes a function for generating the signal Sel. Figure 8 The circuit is 800.

[0121] In this embodiment, the duration of the “on” state of switches IT1 and IT2 is determined by comparing a voltage ramp with one or more potentials determined by a potential setpoint Vout.

[0122] In an embodiment, the circuit CTRL includes circuit 904 configured to provide voltage ramp Ramp1 and circuit 906 configured to provide voltage ramp Ramp2.

[0123] When circuit 902, and more generally circuit CTRL, wants to control the current pulse IL in element L, circuit 902 uses, for example, the signal start1 it provides to generator 904 of voltage ramp Ramp1 to control the start of voltage ramp Ramp1.

[0124] Circuit 908 of circuit CTRL compares the voltage ramp Ramp1 with a potential such as potential Vref determined by the set value of potential Vout. Circuit 908 provides the result of this comparison to circuit 902 in the form of, for example, signal Comp1.

[0125] In this embodiment, the ramp Ramp1 increases from zero, and the signal Comp1 is at a "low level" as long as the ramp Ramp1 is below the potential Vref, and then switches to a "high level" when the ramp Ramp1 becomes above the potential Vref.

[0126] In this embodiment, circuit 902 switches signal cmd1 at the start of ramp Ramp1 and switches it again when ramp Ramp1 becomes greater than potential Vref.

[0127] Therefore, the slope of ramp Ramp1, together with the potential Vref, determines the duration of the “on” state of switch IT1, and thus determines the maximum value valmax of the current pulse IL.

[0128] In this embodiment, the ramp generator 904 is therefore configured to receive the signal Sel and modify the slope of the voltage ramp Ramp1 it provides based on the signal Sel.

[0129] Furthermore, when circuit 902 switches signal cmd1 to switch switch IT1 to the off state, it simultaneously controls the start of voltage ramp Ramp2, for example, by providing signal start2 to generator 906 of voltage ramp Ramp2.

[0130] Circuit CTRL 908 compares the voltage ramp Ramp2 with a potential determined by a set value of potential Vout. In an embodiment, as ramp Ramp2 increases from zero, it is compared with potential Vref, or as ramp Ramp2 decreases from potential Vsupply, it is compared with a potential equal to potential Vsupply minus potential Vref.

[0131] In an embodiment, circuit 908 provides the result of the comparison to circuit 902 in the form of signal Comp2.

[0132] In this embodiment, the ramp Ramp2 increases from zero, and the signal Comp2 is at a "low level" as long as the ramp Ramp2 is below the potential Vref, and then switches to a "high level" when the ramp Ramp2 becomes above the potential Vref.

[0133] In this embodiment, circuit 902 switches signal cmd2 at the start of ramp Ramp2 and switches it back when ramp Ramp2 becomes greater than the Vref potential. Therefore, the slope of ramp Ramp2 and the Vref potential determine the duration of the "on" state of switch IT2.

[0134] The duration of the "on" state of switch IT2 must be adapted according to the value val1 or val2 selected as valmax so that the current IL is zero when the "on" state of switch IT2 ends. In this embodiment, the ramp generator 906 is therefore configured to receive the signal Sel and modify the slope of the voltage ramp Ramp2 it provides based on the signal Sel.

[0135] Figure 10 It shows Figure 9Exemplary embodiments of ramp generators for converters, such as ramp generator 904, are provided. Those skilled in the art will be able to deduce corresponding exemplary embodiments of ramp generator 906 from the following description of ramp generator 904.

[0136] The ramp generator 904 includes a current source 1000, a switch IT3, and a controllable capacitor 1002. The current source 1000 and the switch IT3 are connected in series between node 104 (receiving potential Vsupply) and one electrode 1004 of the capacitor 1002. The other electrodes of the capacitor 1002 are connected to node 102 (receiving reference potential GND). A voltage ramp Ramp1 is available across the capacitor 1002, or in other words, across terminal 1004 of the capacitor 1002.

[0137] Current source 1000 is configured to provide a current I for charging capacitor 1002. Preferably, current I is proportional to (Vsupply - Vout) or (Vsupply - Vref) such that the duration of the “on” state of switch IT1 is independent of the value of the power supply potential Vsupply.

[0138] Switch IT3 is controlled by signal start1. Specifically, when circuit 902 ( Figure 9 When the start signal start1 controls the start of ramp Ramp1, switch IT3 is configured to switch to the "on" state, causing capacitor 1002 to charge and ramp voltage Ramp1 to be available across it.

[0139] For example, although in Figure 10 As not shown, a device for resetting the ramp 1 (such as a device for discharging the capacitor 1002) is provided in the ramp generator 904 controlled by the signal start1, similar to a switch connected in parallel with the capacitor 1002.

[0140] In this embodiment, the value of capacitor 1002 is controlled by signal Sel. When signal Sel indicates that value valmax equals value val1, capacitor 1002 has a first value C1, and when signal Sel indicates that value valmax equals value val2, capacitor 1002 has a second value C2. In this example where value val2 is greater than value val1, value C1 is less than value C2. Therefore, when capacitor 1002 is at value C1, the slope of ramp Ramp1 is greater than the slope when capacitor 1002 is at value C2. Consequently, when capacitor 1002 has value C1, the duration of the "on" state of switch IT1 is greater than the duration when capacitor 1002 has value C2.

[0141] In this embodiment, capacitor 1002 includes capacitor Cval1, which has a first electrode corresponding to electrode 1004 of capacitor 1002 and a second electrode connected to node 102. Capacitor Cval1 has a value C1. Additionally, capacitor 1002 includes a switch IT4 connected in series with capacitor Cval2 between node 102 and electrode 1004 of capacitor 1002. The series combination of capacitor Cval2 and switch IT4 is therefore connected in parallel to capacitor Cval1. Capacitor Cval2 has a value such that when switch IT4, controlled by signal Sel, is turned on, capacitor 1002 has a value C2. In this case, switch IT4 is turned on when value val2 is selected, and otherwise turned off.

[0142] Although more detailed embodiments of the ramp generator have been combined Figure 10 The description is provided, but those skilled in the art can conceive of embodiments of the ramp generators 904 and 906 that differ from those described, but allow for implementation combinations. Figures 2 to 6 The method described.

[0143] More generally, more detailed embodiments of the circuit CTRL have been combined Figure 9 The description states that the duration of the "on" state of switches IT1 and IT2 is determined by comparing a voltage ramp with one or more potentials determined by a set value of potential Vout. Those skilled in the art can envision other embodiments of the circuit CTRL in which the duration of the "on" state of switches IT1 and IT2 is determined differently, for example using a voltage-controlled oscillator (VCO), and modified when the value of valmax, selected as the maximum value, is modified, wherein these durations of the "on" state increase or decrease as the value valmax increases or decreases, respectively.

[0144] Furthermore, in the previous combination Figures 1 to 10 In the exemplary embodiments, implementation modes, and variations described, the maximum value valmax of the current pulse IL is selected only from two values, val1 and val2. However, in other embodiments, the value valmax is selected from any number of values ​​greater than two. The implementation of these embodiments is within the capabilities of those skilled in the art based on the functional indications given above.

[0145] In this embodiment, the value valmax can be selected from the values ​​val1, val2, and an additional value val3. In this embodiment, the value val3 is greater than the value val2.

[0146] Figure 11 It is shown in the form of a flowchart Figures 2 to 4 An alternative embodiment of the method, wherein the value valmax is selected from three values ​​val1, val2, and val3. For example, Figure 11 The method therein is implemented by the circuit CTRL.

[0147] and Figure 3 compared with the method of Figure 11 the method further comprises: selecting the value val3 as the maximum value valmax of a current pulse when the average current Im is greater than a threshold th3 which is greater than a threshold th1; and selecting the value val2 when the average current Im is less than a threshold th4 which is greater than the threshold th1 and less than or equal to the threshold th3. Preferably, the threshold th4 is lower than (that is, strictly lower than in this case) the threshold th3, so that hysteresis is achieved when switching valmax between the value val2 and val3.

[0148] Therefore, Figure 11 the method comprises combining steps 300, 302, 304 and 306 described in Figure 3 and therefore will not be detailed herein, and further comprises steps 1100, 1102 and 1104. Contrary to the description combined with Figure 3 in step 306, when the average current Im is less than the threshold th2 (output N of step 306), the method proceeds to step 1100 (the block "Im>th3"), which comprises verifying whether the current Im is greater than the threshold th3.

[0149] If the current Im is less than the threshold th3 (output N of step 1100), the method proceeds in step 304 and valmax remains equal to val2.

[0150] If the current Im is greater than the threshold th3 (output Y of step 1100), the method proceeds to step 1102 (the block "valmax=val3").

[0151] In step 1102, valmax becomes equal to val3, or in other words, the circuit CTRL selects val3 as the maximum current valmax. In other words, valmax is switched from the value val2 to the value val3.

[0152] Step 1102 is followed by step 1104 (the block "Im<th4"), in which the circuit CTRL compares the current Im with the threshold th4.

[0153] If the current Im is greater than the threshold th4 (output N of step 1104), the method proceeds in step 1102 and valmax remains equal to val3.

[0154] If the current Im is less than the threshold th4 (output Y of step 1104), the method proceeds to step 304, in which valmax becomes equal to val2, that is, is switched from the value val3 to the value val2.

[0155] Although the case where the threshold th3 is lower than the threshold th3 has been combined Figure 11 However, those skilled in the art can apply the above method to the case where thresholds th3 and th4 are equal.

[0156] In an embodiment, step 1100 can be performed in a manner similar to combination. Figure 5 The method described is implemented as follows. In this case, step 1100, implemented when the current valmax equals val2, includes: at the end of each current pulse IL, a timed temp3, representing, for example, a threshold th3, is triggered by the circuit CTRL; and, for example, if the start of the next current pulse IL occurs during the timed temp3 (output Y of step 1100), the value val3 is selected by the circuit CTRL. Conversely, if the start of the next current pulse IL occurs at the end of the timed temp3 (output N of step 1100), the method continues to step 306 and the value valmax remains equal to the value val2.

[0157] Similarly, for example, step 1104 in a similar manner to combination Figure 6 The method described is implemented as follows. In this case, step 1104, implemented when valmax equals val3, includes: at the end of each current pulse IL, a timed temp4, representing, for example, a threshold th4, is triggered by the circuit CTRL; and, for example, if the start of the next current pulse IL occurs after timed temp4 has ended (output Y of step 1104), the value val2 is selected by the circuit CTRL. Conversely, if the start of the next current pulse IL occurs during timed temp4 (output N of step 1104), the method continues to step 1102 and the value valmax remains equal to the value val3.

[0158] Will Figures 1 to 10 The description applies to Figure 11 The method is within the scope of those skilled in the art.

[0159] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will be readily apparent to them.

[0160] Finally, based on the functional description provided above, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art. Specifically, those skilled in the art can determine the possible values ​​of the maximum value valmax of the current pulse IL, the corresponding threshold values, and the delay duration representing these thresholds when the current Im is estimated by the delay between two consecutive current pulses IL. In the embodiments already described, the value valmax is selected only from two discrete values ​​val1 and val2, or only from three discrete values ​​val1, val2, and val3. Those skilled in the art will understand how the embodiments herein can be applied to selection from multiple discrete values ​​including val1 and val2, or from multiple discrete values ​​including only val1, val2, and val3.

[0161] While this description has been detailed, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various drawings, the same elements are designated by the same reference numerals. Moreover, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as those skilled in the art will readily understand from this disclosure that existing or later-developed processes, machines, manufactures, material compositions, components, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

[0162] Therefore, this description and drawings are simply to be regarded as a description of this disclosure as defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations or equivalents falling within the scope of this description.

Claims

1. A switch-mode power supply (SMPS) buck converter, comprising: A first switch is coupled between a first node and an internal node of the SMPS buck converter, the first node being arranged to receive a power supply potential. A second switch is coupled between the internal node and the second node, which is arranged to receive a reference potential GND. An inductor element is arranged to couple the internal node to the output node of the SMPS buck converter; as well as A control circuit is configured to control the first switch and the second switch such that the current pulse in the inductor has a maximum value, the maximum value being selected by the control circuit from at least a first value and a second value based on the average current drawn at the output node; The average current is determined by the delay between every two consecutive current pulses, and the delay begins at the end of the first current pulse in every two consecutive current pulses and ends at the beginning of the second current pulse in every two consecutive current pulses.

2. The SMPS buck converter of claim 1, wherein the maximum value increases in response to an increase in the average current, and wherein the maximum value decreases in response to a decrease in the average current.

3. The SMPS buck converter of claim 1, wherein the first value is less than the second value, and wherein the control circuit is configured to: The second value is selected in response to the average current being higher than a first threshold; and The first value is selected in response to the average current being less than a second threshold, wherein the second threshold is less than or equal to the first threshold.

4. The SMPS buck converter according to claim 3, wherein the second threshold is less than the first threshold.

5. The SMPS buck converter of claim 3, wherein in response to selecting the first value, the control circuit is configured to: At the end of each current pulse, a first time-based event representing the first threshold is triggered; and The second value is selected in response to the start of the next current pulse that has occurred during the first time period.

6. The SMPS buck converter of claim 5, wherein the control circuit is configured to: in response to selecting the second value. At the end of each current pulse, a second time-rendering representing the second threshold is triggered; and The first value is selected in response to the start of the next current pulse that has occurred after the second time-rendering.

7. The SMPS buck converter of claim 6, wherein the duration of each first timed phase is less than the duration of each second timed phase, wherein the end of each current pulse corresponds to the opening of the second switch when the first switch is open, wherein the start of the next current pulse corresponds to the closing of the first switch when the second switch is open, and wherein the first switch and the second switch are PFM controlled by pulse frequency modulation.

8. A switch-mode power supply (SMPS) buck converter, comprising: A first switch is coupled between a first node and an internal node of the SMPS buck converter, the first node being arranged to receive a power supply potential. A second switch is coupled between the internal node and the second node, which is arranged to receive a reference potential GND. An inductor element is arranged to couple the internal node to the output node of the SMPS buck converter; as well as A control circuit is configured to control the first switch and the second switch such that the current pulse in the inductor has a maximum value, the maximum value being selected from at least a first value, a second value, and a third value based on the average current drawn at the output node, the third value being greater than the second value, and the second value being greater than the first value; The average current is determined by the delay between every two consecutive current pulses, and the delay begins at the end of the first current pulse in every two consecutive current pulses and ends at the beginning of the second current pulse in every two consecutive current pulses.

9. The SMPS buck converter of claim 8, wherein the maximum value increases in response to an increase in the average current, wherein the maximum value decreases in response to a decrease in the average current, and wherein the control circuit is configured to: The second value is selected in response to the average current being higher than a first threshold; and The first value is selected in response to the average current being less than a second threshold, wherein the second threshold is less than or equal to the first threshold.

10. The SMPS buck converter of claim 9, wherein the control circuit is configured to: The third value is selected in response to the average current being greater than a third threshold, the third threshold being greater than the first threshold; and The second value is selected in response to the average current being below a fourth threshold, which is greater than the first threshold and less than or equal to the third threshold.

11. The SMPS buck converter of claim 10, wherein the control circuit is configured to: in response to selecting the first value. At the end of each current pulse, a first time-based event representing the first threshold is triggered; and The second value is selected in response to the start of the next current pulse that has occurred during the first time period.

12. The SMPS buck converter of claim 11, wherein the control circuit is configured to: in response to selecting the second value. At the end of each current pulse, a second time-based event representing the third threshold is triggered; and The third value is selected in response to the start of the next current pulse that has occurred after the second time-rendering.

13. The SMPS buck converter of claim 12, wherein the control circuit is configured to: in response to selecting the third value. At the end of each current pulse, a third time-based event representing the fourth threshold is triggered; and The second value is selected in response to the start of the next current pulse that has occurred after the third time-out.

14. The SMPS buck converter of claim 13, wherein the duration of each first timed phase is less than the duration of each second timed phase, wherein the end of each current pulse corresponds to the opening of the second switch when the first switch is open, and wherein the start of the next current pulse corresponds to the closing of the first switch when the second switch is open.

15. The SMPS buck converter of claim 14, wherein the first switch and the second switch are controlled by pulse frequency modulation (PFM), wherein the duration of the on-state of the first switch at each current pulse is determined by a comparison of a first voltage ramp with a first potential, the first potential being determined by a set value of the output potential of the SMPS buck converter, wherein the duration of the on-state of the second switch at each current pulse is determined by a comparison of a second voltage ramp with a second potential, the second potential being determined by the set value, and wherein the slopes of the first voltage ramp and the second voltage ramp differ according to the selected maximum value.

16. The SMPS buck converter of claim 8, further comprising circuitry configured to provide a signal indicating when the current in the inductor element is zero to the control circuitry.

17. A method for a switch-mode power supply SMPS buck converter, comprising: The control circuit selects the maximum value of a current pulse from at least a first value and a second value, the current pulse corresponding to an inductor that couples an internal node of the switch-mode power supply SMPS buck converter to an output node of the SMPS buck converter, the selection being made based on the average current drawn at the output node; The control circuit controls the first switch connecting the first node and the internal node, wherein the first node receives the power supply potential; as well as The control circuit controls a second switch connected between the internal node and the second node, the second node receiving a reference potential GND, and the control of the first and second switches causes the maximum value to be equal to the selected value; The average current is determined by the delay between every two consecutive current pulses, and the delay begins at the end of the first current pulse in every two consecutive current pulses and ends at the beginning of the second current pulse in every two consecutive current pulses.

18. The method of claim 17, wherein the first value is less than the second value, the method further comprising: The control circuit selects the second value in response to the average current being higher than a first threshold. as well as The control circuit selects the first value in response to the average current being less than a second threshold, wherein the second threshold is less than or equal to the first threshold.

19. The method of claim 18, wherein in response to selecting the first value, the method further comprises: The control circuit triggers a first time-based event representing the first threshold at the end of each current pulse. as well as The control circuit selects the second value in response to the start of the next current pulse that has occurred during the first time period.

20. The method of claim 19, wherein in response to selecting the second value, the method further comprises: The control circuit triggers a second time-based event representing the second threshold at the end of each current pulse. as well as The first value is selected by the control circuit in response to the start of the next current pulse that has occurred after the second time-rendering.

21. The method of claim 20, wherein the duration of each first timed phase is less than the duration of each second timed phase, wherein the end of each current pulse corresponds to the opening of the second switch when the first switch is open, wherein the start of the next current pulse corresponds to the closing of the first switch when the second switch is open, and wherein the first switch and the second switch are PFM controlled by pulse frequency modulation.

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