Low power flip-flop
By designing a low-power trigger that includes a clock control module and a trigger module, the problem of high dynamic power consumption of the trigger is solved, and dynamic power consumption is reduced when the reset signal is valid for a long time or multiple times, thereby improving system performance and energy efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2022-06-15
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, the dynamic power consumption of triggers is relatively high, which makes the clock network the main source of energy consumption in large-scale integrated circuit systems, affecting system performance and energy consumption.
Design a low-power trigger that includes a clock control module and a trigger module. The clock signal is controlled by the input signal RESETB and the clock signal Clock to achieve selective latching and reduce dynamic power consumption.
When the reset signal is active for a long time or multiple times, dynamic power consumption is significantly reduced, system performance is improved and energy consumption is reduced.
Smart Images
Figure CN115333508B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a low-power trigger. Background Technology
[0002] In current circuit design, flip-flops are widely used. In very large-scale integrated circuits (VLSI), reducing energy consumption is the direct goal of low-power design, and the main reason for energy consumption is the constant switching between 0 and 1 at high frequencies. Other energy consumption consists of dynamic and static components depending on the circuit characteristics. Dynamic circuits consume energy by pre-charging the capacitors at circuit nodes, while static circuits mainly consume energy in the form of subthreshold leakage current. Therefore, the clock network composed of timing units (flip-flops and latches) is the main source of energy consumption in VLSI systems.
[0003] In typical integrated circuit designs, approximately 30% to 60% of the energy consumption is in the clock network. Reducing the energy consumption of flip-flops directly reduces the overall system energy consumption. Furthermore, improving flip-flop performance directly reduces the distributed constraints of the clock network and enhances the overall system performance. Therefore, the proper design and selection of flip-flops have a significant impact on the overall system performance and energy consumption. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a low-power trigger to solve the problem of high dynamic power consumption of triggers in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides a low-power trigger, comprising at least: a clock control module, including a first input signal terminal and a clock signal terminal; the clock control module is configured to receive an input signal RESETB through the first input signal terminal and a clock signal Clock through the clock signal terminal, and to control the clock signal Clock to generate a controlled clock signal;
[0006] The trigger module includes a second input signal terminal and an output signal terminal; the second input signal terminal is used to receive an input signal D; the output signal terminal is used to generate an output signal Q; the trigger module is configured to selectively latch the input signal D by the input signal D, the input signal RESETB, and the controlled clock signal generated by the clock control module to generate the output signal Q.
[0007] Preferably, the clock control module includes: first to fourth PMOS and first to fourth NMOS; wherein the drain of the first PMOS, the drain of the first NMOS, the gate of the third PMOS, and the gate of the fourth NMOS are interconnected to form a connection terminal RESET; the gate of the first PMOS is connected to the gate of the first NMOS; the drain of the third PMOS is connected to the source of the fourth PMOS; the drain of the fourth PMOS, the drain of the third NMOS, the drain of the fourth NMOS, the gate of the second PMOS, and the gate of the second NMOS are interconnected to form a connection terminal CKN; the drain of the second PMOS is connected to the drain of the second NMOS to form a connection terminal CKP; and the gate of the fourth PMOS is connected to the gate of the third NMOS to form a connection terminal CLK.
[0008] Preferably, the source of the first NMOS is grounded; the source of the third NMOS is connected to the source of the fourth NMOS and grounded; the source of the second NMOS is grounded.
[0009] Preferably, the connection point where the gate of the first PMOS is connected to the gate of the first NMOS forms the first signal input terminal, which is connected to the input signal RESETB; the signal level of the connection terminal RESET is opposite to the level of the input signal RESETB.
[0010] Preferably, the connection terminal CLK is connected to the clock signal Clock.
[0011] Preferably, when the input signal RESETB is low, the third PMOS is turned off and the fourth NMOS is turned on; the signal at the connection terminal CKN is pulled down to low, and the signal at the connection terminal CKP is correspondingly high.
[0012] Preferably, when the input signal D and the output signal Q are the same, the signals of the connection terminal CKN and the connection terminal CKP no longer change.
[0013] Preferably, when the input signal RESETB is high, the third PMOS is turned on, the fourth NMOS is turned off, and the signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the clock signal terminal CLK.
[0014] As described above, the low-power trigger of the present invention has the following beneficial effects: compared with ordinary triggers without a clock control module, the present invention can significantly reduce dynamic power consumption when the reset signal is valid for a long time or multiple times. Attached Figure Description
[0015] Figure 1 The diagram shown is a schematic of the low-power trigger circuit of the present invention;
[0016] Figure 2 The diagram shows the circuit structure of the clock control module in this invention.
[0017] Figure 3 The graph shows a power consumption comparison between the trigger with a clock control module and a conventional trigger with a reset function in the prior art.
[0018] Figure 4 This is a functional simulation diagram of a trigger that resets to 5 clock cycles every 10 clock cycles in the prior art;
[0019] Figure 5 The diagram shown is a functional simulation of the low-power trigger that resets to 5 clock cycles every 10 clock cycles in this invention. Detailed Implementation
[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0021] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0022] This invention provides a low-power trigger, such as... Figure 1 As shown, Figure 1 The diagram shows a low-power trigger circuit of the present invention. The trigger includes at least a clock control module (CLK_CONTROL), which includes a first input signal terminal and a clock signal terminal. The clock control module is configured to receive an input signal RESETB through the first input signal terminal and a clock signal Clock through the clock signal terminal, and to control the clock signal Clock to generate a controlled clock signal.
[0023] A trigger module (DFF) includes a second input signal terminal and an output signal terminal; the second input signal terminal is used to receive an input signal D; the output signal terminal is used to generate an output signal Q; the trigger module is configured to selectively latch the input signal D using the controlled clock signal generated by the input signal D, the input signal RESETB, and the clock control module (CLK_CONTROL) to generate the output signal Q.
[0024] like Figure 2 As shown, Figure 2 The diagram shows a schematic of the clock control module circuit structure in this invention. Further, the clock control module in this embodiment includes: a first to a fourth PMOS and a first to a fourth NMOS; wherein the drain of the first PMOS (01), the drain of the first NMOS (02), the gate of the third PMOS (05), and the gate of the fourth NMOS (08) are interconnected to form a connection terminal RESET; the gate of the first PMOS is connected to the gate of the first NMOS; the drain of the third PMOS is connected to the source of the fourth PMOS (06); the drain of the fourth PMOS, the drain of the third NMOS (07), the drain of the fourth NMOS, the gate of the second PMOS (03), and the gate of the second NMOS (04) are interconnected to form a connection terminal CKN; the drain of the second PMOS is connected to the drain of the second NMOS to form a connection terminal CKP; and the gate of the fourth PMOS is connected to the gate of the third NMOS to form a connection terminal CLK.
[0025] In a further embodiment of the present invention, the source of the first NMOS is grounded; the source of the third NMOS is connected to the source of the fourth NMOS and grounded; and the source of the second NMOS is grounded.
[0026] In a further embodiment of the present invention, the source of the first PMOS is connected to the power supply voltage; the source of the third PMOS is connected to the power supply voltage; and the source of the second PMOS is connected to the power supply voltage.
[0027] In a further embodiment of the present invention, the connection terminal where the gate of the first PMOS and the gate of the first NMOS are connected forms the first signal input terminal, which is connected to the input signal RESETB; the signal level of the connection terminal RESET is opposite to the level of the input signal RESETB.
[0028] Furthermore, in this embodiment, the connection terminal CLK is connected to the clock signal Clock.
[0029] Furthermore, in this embodiment, when the input signal RESETB is low (0), that is, when the reset signal is valid, the third PMOS is turned off and the fourth NMOS is turned on; the signal of the connection terminal CKN is pulled down to low (0), and the signal of the connection terminal CKP is correspondingly high (1).
[0030] Furthermore, in this embodiment, when the input signal D and the output signal Q are the same, the signals of the connection terminal CKN and the connection terminal CKP no longer change.
[0031] Furthermore, in this embodiment, when the input signal RESETB is high (1), that is, when the reset signal is invalid, the third PMOS is turned on, the fourth NMOS is turned off, and the signals of the connection terminal CKN and the connection terminal CKP follow the clock signal Clock of the clock signal terminal CLK.
[0032] like Figure 3 As shown, Figure 3 The graph shows a power consumption comparison between the trigger with a clock control module and a conventional trigger with a reset function in the prior art. Compared with a conventional trigger with a reset function but without a clock control module, the low-power trigger proposed in this invention has significantly lower dynamic power consumption when the trigger is subjected to multiple resets or long-term resets.
[0033] like Figure 4 and Figure 5 As shown, Figure 4 This is a functional simulation diagram of a trigger that resets to 5 clock cycles every 10 clock cycles in the prior art; Figure 5 The diagram shown is a functional simulation of the low-power trigger that resets for 5 clock cycles every 10 clock cycles in this invention. As can be seen from the comparison, when the reset signal is valid for a long time or multiple times, the trigger of this invention can significantly reduce dynamic power consumption.
[0034] In summary, compared with ordinary triggers without a clock control module, this invention can significantly reduce dynamic power consumption when the reset signal is valid for a long time or multiple times. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0035] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A low power flip-flop, characterized by, At least including: The clock control module includes a first input signal terminal and a clock signal terminal; The clock control module is configured to receive an input signal RESETB through the first input signal terminal and a clock signal Clock through the clock signal terminal, and to control the clock signal Clock to generate a controlled clock signal. The trigger module includes a second input signal terminal and an output signal terminal; The second input signal terminal is used to receive the input signal D; the output signal terminal is used to generate the output signal Q. The trigger module is configured to selectively latch the input signal D using the input signal D, the input signal RESETB, and the controlled clock signal generated by the clock control module, in order to generate the output signal Q. When the input signal D and the output signal Q are the same, the controlled clock signal generated by the clock control module no longer changes; When the input signal RESETB is high, the controlled clock signal generated by the clock control module follows the clock signal Clock.
2. The low-power trigger according to claim 1, characterized in that: The clock control module includes: first to fourth PMOS and first to fourth NMOS; wherein the drain of the first PMOS, the drain of the first NMOS, the gate of the third PMOS, and the gate of the fourth NMOS are interconnected to form a connection terminal RESET; the gate of the first PMOS is connected to the gate of the first NMOS; the drain of the third PMOS is connected to the source of the fourth PMOS; the drain of the fourth PMOS, the drain of the third NMOS, the drain of the fourth NMOS, the gate of the second PMOS, and the gate of the second NMOS are interconnected to form a connection terminal CKN; the drain of the second PMOS is connected to the drain of the second NMOS to form a connection terminal CKP; and the gate of the fourth PMOS is connected to the gate of the third NMOS to form a connection terminal CLK.
3. The low-power trigger according to claim 2, characterized in that: The source of the first NMOS is grounded; the source of the third NMOS is connected to the source of the fourth NMOS and is grounded; the source of the second NMOS is grounded.
4. The low-power trigger according to claim 2, characterized in that: The connection point where the gate of the first PMOS is connected to the gate of the first NMOS forms the first signal input terminal, which is connected to the input signal RESETB; the signal level of the connection terminal RESET is opposite to the level of the input signal RESETB.
5. The low-power trigger according to claim 4, characterized in that: The connection terminal CLK is connected to the clock signal Clock.
6. The low-power trigger according to claim 5, characterized in that: When the input signal RESETB is low, the third PMOS is turned off and the fourth NMOS is turned on; the signal at the connection terminal CKN is pulled down to low, and the signal at the connection terminal CKP is correspondingly high.
7. The low-power trigger according to claim 6, characterized in that: When the input signal D and the output signal Q are the same, the signals at the connection terminals CKN and CKP no longer change.
8. The low-power trigger according to claim 5, characterized in that: When the input signal RESETB is high, the third PMOS is turned on and the fourth NMOS is turned off. The signals at the connection terminals CKN and CKP follow the clock signal Clock at the clock signal terminal CLK.