A POR circuit

Abstract

The application discloses a POR circuit, which comprises a starting unit, a flip-flop unit, a first inverter unit, a delay unit and a second inverter unit which are sequentially connected in sequence; the input end of the starting unit is connected with a power supply VCC, and the output end of the second inverter unit is connected with a digital module; the starting unit is used for controlling the opening of the POR circuit; the flip-flop unit is used for outputting an equivalent voltage of the input voltage of the power supply VCC; the first inverter unit is used for generating a first voltage by inverting the equivalent voltage; the delay unit is used for charging by using the current inputted by a current mirror control current generating circuit, thereby controlling the power-on time of the POR circuit, and generating a second voltage by inverting the first voltage; and the second inverter unit is used for generating a third voltage by continuously inverting the second voltage and outputting. The conventional RC charging and discharging delay module is changed into a charging and discharging delay module loaded with a current mirror control, the area of the capacitor and the resistor of the RC charging and discharging part is reduced, and therefore the area of the POR circuit is smaller.

Description

Technical Field

[0001] This application relates to the field of circuit testing technology, and more particularly to a POR circuit. Background Technology

[0002] With the rapid development of technology, more and more electronic products are appearing in people's lives. Different electronic products contain many different circuit systems, and different circuit systems contain many different constituent circuits.

[0003] Power-on reset (POR) circuits are widely used in power supply systems. Their function in control systems is to initiate the operation of a microcontroller. However, power supply instability can occur during power-on and normal operation due to voltage abnormalities or interference, potentially severely impacting the stability of the microcontroller. Therefore, a reset signal is output to the chip after a delay upon power-on. To meet market demands, POR circuits are increasingly designed for smaller size, lower power consumption, and higher stability. Current POR circuits typically use RC charging with a capacitor and resistor for the power-on delay, which increases the circuit area due to the introduction of a large capacitor and resistor.

[0004] Therefore, how to make the POR circuit area smaller is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a POR circuit that utilizes a charge / discharge delay module controlled by a current mirror to detect the voltage generated by the voltage generation circuit, thereby reducing the area of ​​the capacitor and resistor sections in the traditional RC charge / discharge section and solving the problem of excessive area in the POR circuit in the prior art.

[0006] To address the aforementioned technical problems, this application discloses a POR circuit, comprising:

[0007] The startup unit, trigger unit, first inverter unit, delay unit, and second inverter unit are connected in sequence.

[0008] The input terminal of the startup unit is connected to the power supply VCC, and the output terminal of the second inverter unit is connected to the digital module.

[0009] The startup unit is used to receive the input voltage of the power supply VCC, and to start the POR circuit when the input voltage reaches the start-up threshold.

[0010] The trigger unit is used to respond to the start-up signal sent by the start-up unit to enable the POR circuit and output the equivalent voltage of the input voltage of the power supply VCC.

[0011] The first inverter unit is used to receive the equivalent voltage output by the flip-flop unit; flip the equivalent voltage to generate a first voltage; and output the first voltage.

[0012] The delay unit is used to charge the device using the current input from the current generation circuit controlled by the current mirror; when the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage, and then outputs the second voltage.

[0013] The second inverter unit is used to receive the second voltage, continuously flip the second voltage to generate a third voltage, and output the third voltage.

[0014] Optionally, the startup unit includes:

[0015] First resistor, second resistor, first NMOS transistor, second NMOS transistor, third NMOS transistor;

[0016] One end of the second resistor is connected to the drain of the first NMOS transistor, and the other end is connected to the power supply VCC.

[0017] The source of the first NMOS transistor is connected to the drain of the second NMOS transistor;

[0018] The source of the second NMOS transistor is connected to the drain of the third NMOS transistor;

[0019] The source of the third NMOS transistor is grounded;

[0020] The gates of the first NMOS transistor to the third NMOS transistor are connected to the first resistor and connected to the power supply VCC; wherein the first resistor is used to protect the first NMOS transistor to the third NMOS transistor.

[0021] Optionally, the trigger unit is a Schmitt trigger unit.

[0022] Optionally, the trigger unit includes:

[0023] First PMOS transistor, second PMOS transistor, third PMOS transistor, fourth NMOS transistor, third resistor;

[0024] The source of the first PMOS transistor is connected to the power supply VCC, and the drain is connected to the source of the second PMOS transistor.

[0025] The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor;

[0026] The source of the fourth NMOS transistor is grounded;

[0027] The third resistor is connected to the drain of the third PMOS transistor;

[0028] The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the source of the second PMOS transistor, and the gate is connected to the drain of the second PMOS transistor and the drain of the fourth NMOS transistor.

[0029] The gates of the first PMOS transistor, the second PMOS transistor, and the fourth NMOS transistor are connected to the drain of the first NMOS transistor in the startup unit.

[0030] Optionally, the first inverter unit includes:

[0031] The fourth PMOS transistor and the fifth NMOS transistor;

[0032] The source of the fourth PMOS transistor is connected to the power supply VCC, and the drain is connected to the fifth NMOS transistor.

[0033] The source of the fifth NMOS transistor is grounded;

[0034] The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor and is connected to the drain of the fourth NMOS transistor in the trigger unit.

[0035] Optionally, the delay unit includes:

[0036] The fifth PMOS transistor, the sixth NMOS transistor, and the first capacitor;

[0037] The source of the fifth PMOS transistor is connected to the current generation circuit controlled by the current mirror.

[0038] The drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source is grounded;

[0039] One end of the first capacitor is connected to the drain of the sixth NMOS transistor, and the other end is grounded;

[0040] The gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor and is connected to the drain of the fifth NMOS transistor in the first inverter unit.

[0041] Optionally, the second inverter unit includes:

[0042] The sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor;

[0043] The sixth PMOS transistor and the seventh NMOS transistor constitute the first inverter;

[0044] The source of the sixth PMOS transistor is connected to the power supply VCC;

[0045] The drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source is grounded.

[0046] The gates of the sixth PMOS transistor and the seventh NMOS transistor are connected to and connected to the drain of the sixth NMOS transistor in the delay unit;

[0047] The seventh PMOS transistor and the eighth NMOS transistor constitute the second inverter;

[0048] The source of the seventh PMOS transistor is connected to the power supply VCC;

[0049] The drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source is grounded.

[0050] The gates of the eighth NMOS transistor and the seventh PMOS transistor are connected and connected to the drain of the seventh NMOS transistor.

[0051] The eighth PMOS transistor and the ninth NMOS transistor constitute the third inverter;

[0052] The source of the eighth PMOS transistor is connected to the power supply VCC;

[0053] The drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source is grounded.

[0054] The gates of the ninth NMOS transistor and the eighth PMOS transistor are connected to and connected to the drain of the eighth NMOS transistor.

[0055] The ninth PMOS transistor and the tenth NMOS transistor constitute the fourth inverter;

[0056] The source of the ninth PMOS transistor is connected to the power supply VCC.

[0057] The drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor and connected to the digital module, while the source is grounded.

[0058] The gates of the tenth NMOS transistor and the ninth PMOS transistor are connected to the drain of the ninth NMOS transistor.

[0059] Optionally, the current-mirror-controlled current-generating circuit includes:

[0060] The tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the fourth resistor;

[0061] The source of the tenth PMOS transistor is connected to the power supply VCC, and the drain is connected to one end of the fourth resistor.

[0062] The other end of the fourth resistor is connected to one end of the first switch;

[0063] The other end of the first switch is connected to the current mirror;

[0064] The sources of the eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are connected to the power supply VCC, and their drains are connected to the second, third, fourth, and fifth switches, respectively, and connected to the source of the fifth PMOS transistor in the delay unit.

[0065] The gates of the eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are connected to and connected to the connection terminal of the fourth resistor and the first switch.

[0066] Optionally, the POR circuit further includes:

[0067] The fifteenth PMOS transistor;

[0068] The source of the fifteenth PMOS transistor is connected to the power supply VCC;

[0069] The drain of the fifteenth PMOS transistor is connected to the drain of the sixth NMOS transistor of the delay unit;

[0070] The gate of the fifteenth PMOS transistor is connected to the gates of the seventh PMOS transistor and the eighth NMOS transistor of the second inverter.

[0071] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0072] In this embodiment, it can be determined that this application provides a POR circuit composed of a startup unit, a trigger unit, a first inverter unit, a delay unit, and a second inverter unit connected in sequence. The input terminal of the startup unit is connected to the power supply VCC, and the output terminal of the second inverter unit is connected to a digital module. When the input voltage of the power supply VCC received by the startup unit reaches the activation threshold, the POR is activated. Then, the trigger unit circuit responds to the activation signal sent by the startup unit, outputting an equivalent voltage of the power supply VCC input voltage to the first inverter unit and flipping it to generate a first voltage, which is then sent to the delay unit. A charge / discharge delay unit controlled by a current mirror then charges using the current generated by the current mirror-controlled current generation circuit. When the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage. The delay module then sends the generated second voltage to the second inverter unit, causing the second inverter unit to continuously flip the second voltage to generate a third voltage, which is finally output. By replacing the traditional RC charge / discharge delay module with a charge / discharge delay unit controlled by a current mirror, the area of ​​the capacitor and resistor in the RC charge / discharge section is reduced, thus making the POR circuit area smaller. Attached Figure Description

[0073] Figure 1 This is a structural block diagram of a POR circuit disclosed in an embodiment of this application;

[0074] Figure 2 This is a circuit diagram of a startup unit disclosed in an embodiment of this application;

[0075] Figure 3 This application discloses a circuit structure for a trigger unit in an embodiment.

[0076] Figure 4 This is a circuit structure diagram of a first inverter unit disclosed in an embodiment of this application;

[0077] Figure 5 This is a circuit structure diagram of a delay unit disclosed in an embodiment of this application;

[0078] Figure 6 This is a circuit diagram of a second inverter unit disclosed in an embodiment of this application;

[0079] Figure 7 This application discloses a current-mirror-controlled current-generating circuit.

[0080] Figure 8 This is a circuit structure diagram of a POR circuit disclosed in an embodiment of this application;

[0081] Figure 9 This is a structural block diagram of an application scenario for a POR circuit disclosed in an embodiment of this application. Detailed Implementation

[0082] As mentioned earlier, the power-on delay module of the existing POR circuit typically occupies a large area. Specifically, the power-on delay module of the existing POR circuit usually uses RC charging with a capacitor and resistor. Because of the use of RC charging and discharging delay module, a large capacitor and resistor are introduced, resulting in an excessively large area occupied by the POR circuit, which cannot meet the market demand for small-area POR circuits.

[0083] To address the aforementioned problems, this application provides a POR circuit, comprising: a startup unit, a trigger unit, a first inverter unit, a delay unit, and a second inverter unit connected sequentially. The input terminal of the startup unit is connected to the power supply VCC, and the output terminal of the second inverter unit is connected to a digital module. When the input voltage of the power supply VCC received by the startup unit reaches the startup threshold, the POR is activated. Then, the trigger unit circuit responds to the POR activation signal sent by the startup unit, outputting an equivalent voltage of the power supply VCC input voltage to the first inverter unit and flipping it to generate a first voltage, which is then sent to the delay module. A charge / discharge delay module controlled by a current mirror then charges the circuit using the current generated by the current mirror-controlled current generation circuit. When the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage. The delay module then sends the generated second voltage to the second inverter unit, causing the second inverter unit to continuously flip the second voltage to generate a third voltage, which is finally output.

[0084] In this way, the traditional RC charge / discharge delay module is replaced with a charge / discharge delay module controlled by a current mirror, which reduces the area of ​​the capacitor and resistor in the RC charge / discharge section, thus making the POR circuit smaller.

[0085] It should be noted that the POR circuit provided in this application can be widely used in various system chips.

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0087] Figure 1 A block diagram of a POR circuit disclosed in this application includes:

[0088] The unit includes a startup unit (101), a trigger unit (102), a first inverter unit (103), a delay unit (104), and a second inverter unit (105).

[0089] The startup unit, trigger unit, first inverter unit, delay unit, and second inverter unit are connected in sequence.

[0090] The startup unit is used to receive the input voltage of the power supply VCC, and to start the POR circuit when the input voltage reaches the start-up threshold.

[0091] The trigger unit is used to respond to the start-up signal sent by the start-up unit to enable the POR circuit and output the equivalent voltage of the input voltage of the power supply VCC.

[0092] The first inverter unit is used to receive the equivalent voltage output by the flip-flop unit; flip the equivalent voltage to generate a first voltage; and output the first voltage.

[0093] The delay unit is used to charge the device using the current input from the current generation circuit controlled by the current mirror; when the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage, and then outputs the second voltage.

[0094] The second inverter unit is used to receive the second voltage, continuously flip the second voltage to generate a third voltage, and output the third voltage.

[0095] In practical applications, a POR circuit is formed by sequentially connecting a startup unit, a trigger unit, a first inverter unit, a delay unit, and a second inverter unit. The input terminal of the startup unit is connected to the power supply VCC and is responsible for receiving the input voltage VCC. When the received input voltage of the power supply VCC reaches the activation threshold, the POR is activated. Then, the trigger unit circuit responds to the activation signal sent by the startup unit, outputting an equivalent voltage of the input voltage of the power supply VCC to the first inverter unit and flipping it to generate a first voltage, which is then sent to the delay unit. A charge / discharge delay module controlled by a current mirror then charges the circuit using the current generated by the current mirror-controlled current generator. When the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage. The delay module then sends the generated second voltage to the second inverter unit, causing the second inverter unit to continuously flip the second voltage to generate a third voltage, which is finally output. The current mirror is a circuit block whose function is to generate a copy of the current flowing into or out of the input terminal by replicating the current in the output terminal. The characteristic of a current mirror is to maintain a constant input and output current. When the power supply system or the voltage to be detected powers on slowly, exceeding the power-on delay of the POR circuit, we can reduce the input current by controlling the switch of the current mirror, thereby slowing down the power-on time of the POR circuit. By replacing the traditional RC charge / discharge delay module with a charge / discharge delay unit controlled by a current mirror, the area of ​​the capacitors and resistors in the RC charge / discharge section is reduced, resulting in a smaller POR circuit area.

[0096] Figure 2 This application discloses a circuit diagram of a startup unit. Specifically, the startup unit includes:

[0097] First resistor (R1), second resistor (R2), first NMOS transistor (MN1), second NMOS transistor (MN2), third NMOS transistor (MN3);

[0098] One end of the second resistor is connected to the drain of the first NMOS transistor, and the other end is connected to the power supply VCC.

[0099] The source of the first NMOS transistor is connected to the drain of the second NMOS transistor;

[0100] The source of the second NMOS transistor is connected to the drain of the third NMOS transistor;

[0101] The source of the third NMOS transistor is grounded;

[0102] The gates of the first NMOS transistor to the third NMOS transistor are connected to the first resistor and connected to the power supply VCC; wherein the first resistor is used to protect the first NMOS transistor to the third NMOS transistor.

[0103] In practical applications, the magnitude of the power supply VCC input voltage determines whether NMOS transistors MN1, MN2, and MN3 are turned on or off. During the initial power-up process of VCC, MN1, MN2, and MN3 are initially off, and the POR circuit is not activated. At this time, the junction voltage between MN1 and R2 is equal to the input voltage of the power supply VCC. When the input voltage reaches the turn-on threshold of NMOS transistors MN1, MN2, and MN3, the POR circuit activates, and NMOS transistors MN1, MN2, and MN3 turn on. At this point, due to the voltage division of the NMOS transistors, the junction voltage between MN1 and R2 is not equal to the input voltage, resulting in a voltage difference. To protect NMOS transistors MN1, MN2, and MN3, a resistor R1 is connected to the gate of MN1, MN2, and MN3.

[0104] As one implementation method, for different trigger units in different systems, the trigger unit described in this application is specifically a Schmitt trigger unit.

[0105] In practical applications, for a standard Schmitt trigger, the output is high when the input voltage is higher than the positive threshold voltage; the output is low when the input voltage is lower than the negative threshold voltage; and the output remains unchanged when the input voltage is between the positive and negative threshold voltages.

[0106] Figure 3 This application discloses a circuit structure diagram of a trigger unit, specifically, the trigger unit includes:

[0107] The first PMOS transistor (MP1), the second PMOS transistor (MP2), the third PMOS transistor (MP3), the fourth NMOS transistor (MN4), and the third resistor (R3);

[0108] The source of the first PMOS transistor is connected to the power supply VCC, and the drain is connected to the source of the second PMOS transistor.

[0109] The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor;

[0110] The source of the fourth NMOS transistor is grounded;

[0111] The third resistor is connected to the drain of the third PMOS transistor;

[0112] The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the source of the second PMOS transistor, and the gate is connected to the drain of the second PMOS transistor and the drain of the fourth NMOS transistor.

[0113] The gates of the first PMOS transistor, the second PMOS transistor, and the fourth NMOS transistor are connected to the drain of the first NMOS transistor in the startup unit.

[0114] In practical applications, after NMOS transistors MN1, MN2, and MN3 are turned on, the Schmitt trigger unit turns on when the difference between the node voltage between MN1 and R2 and the input voltage of the power supply VCC reaches the threshold of MP1 and MP2. At this time, MP1 and MP2 pull the drain voltage of MN4 from 0 to the same level as the input voltage of the power supply VCC, i.e., it becomes high, generating an equivalent voltage equal to the input voltage, and then outputting it to the next unit. This Schmitt trigger unit can also act as a hysteresis voltage. For example, if the turn-on threshold of a trigger unit is 10mA, when the input voltage fluctuates between 9-11mA, a glitch occurs, causing the trigger to repeatedly switch between on and off states, affecting normal operation. However, the threshold voltage corresponding to the output voltage fluctuation of the power supply VCC—that is, when the output flips from high to low or from low to high—is different. The output only changes when the input voltage changes sufficiently. This double-threshold action is called hysteresis, indicating that the Schmitt trigger has memory.

[0115] Figure 4 This application discloses a circuit structure diagram of a first inverter unit. Specifically, the first inverter unit includes:

[0116] The fourth PMOS transistor (MP4) and the fifth NMOS transistor (MN5);

[0117] The source of the fourth PMOS transistor is connected to the power supply VCC, and the drain is connected to the fifth NMOS transistor.

[0118] The source of the fifth NMOS transistor is grounded;

[0119] The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor and is connected to the drain of the fourth NMOS transistor in the trigger unit.

[0120] In practical applications, an inverter can flip the phase of an input signal by 180 degrees. That is, when the input signal is at a high potential, the output signal of the inverter is at a low potential; when the input signal is at a low voltage, the output signal of the inverter is at a high potential.

[0121] Figure 5 This application discloses a circuit structure diagram of a delay unit, specifically, the delay unit includes:

[0122] The fifth PMOS transistor (MP5), the sixth NMOS transistor (MN6), and the first capacitor (C1);

[0123] The source of the fifth PMOS transistor is connected to the current generation circuit controlled by the current mirror.

[0124] The drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source is grounded.

[0125] One end of the first capacitor is connected to the drain of the sixth NMOS transistor, and the other end is grounded;

[0126] The gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor and is connected to the drain of the fifth NMOS transistor in the first inverter unit.

[0127] In practical applications, the PMOS transistor is in the ON state when its gate voltage is low. At this time, the MP5 uses the current generated by the current mirror-controlled current generator to charge capacitor C1. Only when capacitor C1 is fully charged will the input signal be toggled, changing the low level to a high level, thus providing a delay.

[0128] Figure 6 This application discloses a circuit structure diagram of a second inverter unit. Specifically, the second inverter unit includes:

[0129] The sixth PMOS transistor (MP6), the seventh PMOS transistor (MP7), the eighth PMOS transistor (MP8), the ninth PMOS transistor (MP9), the seventh NMOS transistor (MN7), the eighth NMOS transistor (MN8), the ninth NMOS transistor (MN9), and the tenth NMOS transistor (MN10);

[0130] The sixth PMOS transistor and the seventh NMOS transistor constitute the first inverter;

[0131] The source of the sixth PMOS transistor is connected to the power supply VCC;

[0132] The drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source is grounded.

[0133] The gates of the sixth PMOS transistor and the seventh NMOS transistor are connected to and connected to the drain of the sixth NMOS transistor in the delay unit;

[0134] The seventh PMOS transistor and the eighth NMOS transistor constitute the second inverter;

[0135] The source of the seventh PMOS transistor is connected to the power supply VCC;

[0136] The drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source is grounded.

[0137] The gates of the eighth NMOS transistor and the seventh PMOS transistor are connected and connected to the drain of the seventh NMOS transistor.

[0138] The eighth PMOS transistor and the ninth NMOS transistor constitute the third inverter;

[0139] The source of the eighth PMOS transistor is connected to the power supply VCC;

[0140] The drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source is grounded.

[0141] The gates of the ninth NMOS transistor and the eighth PMOS transistor are connected to and connected to the drain of the eighth NMOS transistor.

[0142] The ninth PMOS transistor and the tenth NMOS transistor constitute the fourth inverter;

[0143] The source of the ninth PMOS transistor is connected to the power supply VCC.

[0144] The drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor and connected to the digital module, while the source is grounded.

[0145] The gates of the tenth NMOS transistor and the ninth PMOS transistor are connected to the drain of the ninth NMOS transistor.

[0146] In practical applications, because the input signal to the second inverter unit may fluctuate, multiple inverters connected in series can be used to flip the input signal to reduce or eliminate the fluctuation. In this application, the first inverter flips the input signal by 180 degrees and then outputs it to the second inverter. The second inverter flips the received signal by another 180 degrees and outputs it to the third inverter. The third inverter flips the received signal by another 180 degrees and outputs it to the fourth inverter. Finally, the fourth inverter flips the received signal by another 180 degrees and outputs it.

[0147] Figure 7 This application discloses a current mirror-controlled current generation circuit, specifically, the current mirror-controlled current generation circuit includes:

[0148] The tenth PMOS transistor (MP10), the eleventh PMOS transistor (MP11), the twelfth PMOS transistor (MP12), the thirteenth PMOS transistor (MP13), the fourteenth PMOS transistor (MP14), the first switch (S1), the second switch (S2), the third switch (S3), the fourth switch (S4), the fifth switch (S5), and the fourth resistor (R4);

[0149] The source of the tenth PMOS transistor is connected to the power supply VCC, and the drain is connected to one end of the fourth resistor.

[0150] The other end of the fourth resistor is connected to one end of the first switch;

[0151] The other end of the first switch is connected to the current mirror;

[0152] The sources of the eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are connected to the power supply VCC, and their drains are connected to the second, third, fourth, and fifth switches, respectively, and connected to the source of the fifth PMOS transistor in the delay unit.

[0153] The gates of the eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are connected to and connected to the connection terminal of the fourth resistor and the first switch.

[0154] In practical applications, a current mirror can maintain constant input and output current, and its area is much smaller than that of the capacitor and resistor in a traditional RC delay module. When the power-on delay of the power supply system exceeds the power-on delay of the POR circuit, the input current of the current generation circuit can be adjusted by using a range switch to adjust the delay, ensuring that a high-level voltage is output only when the power supply system is fully operational. For example, if the power supply system or the voltage to be detected powers on slowly, exceeding the power-on delay of the POR circuit, we can reduce the TRIM current by controlling the switch of the current mirror to slow down the power-on time of the POR circuit.

[0155] Figure 8 This application discloses a circuit structure diagram of a POR circuit. Specifically, to stabilize the second voltage output by the delay unit, the POR circuit further includes:

[0156] The fifteenth PMOS transistor (MP15);

[0157] The source of the fifteenth PMOS transistor is connected to the power supply VCC;

[0158] The drain of the fifteenth PMOS transistor is connected to the drain of the sixth NMOS transistor of the delay unit;

[0159] The gate of the fifteenth PMOS transistor is connected to the gates of the seventh PMOS transistor and the eighth NMOS transistor of the second inverter.

[0160] In practical applications, since the second voltage output by the delay unit is not stable and may exhibit glitches, a PMOS transistor MP15 can be connected after the delay circuit to ensure that the second voltage can be output stably.

[0161] Figure 9 This is a structural block diagram of an application scenario for a POR circuit disclosed in an embodiment of this application. The POR circuit provided by this invention receives the output voltage of a voltage generation circuit (such as an LDO). When a large voltage spike occurs in the voltage generation circuit, affecting the normal operation of the circuit, the POR circuit needs to generate a low-level reset signal and send it to the digital module to inform the system that the voltage is abnormal and needs to stop working.

[0162] In summary, this application provides a POR circuit composed of a startup unit, a trigger unit, a first inverter unit, a delay unit, and a second inverter unit connected sequentially. The input terminal of the startup unit is connected to the power supply VCC, and the output terminal of the second inverter unit is connected to a digital module. When the input voltage of the power supply VCC received by the startup unit reaches the startup threshold, the POR is activated. Then, the trigger unit circuit responds to the POR activation signal sent by the startup unit, outputting an equivalent voltage of the power supply VCC input voltage to the first inverter unit and flipping it to generate a first voltage, which is then sent to the delay module. The current-mirror-controlled charge / discharge delay module then charges using the current generated by the current-mirror-controlled current generation circuit. When the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage. The delay module then sends the generated second voltage to the second inverter unit, causing the second inverter unit to continuously flip the second voltage to generate a third voltage, which is finally output. By replacing the traditional RC charge / discharge delay module with a charge / discharge delay module controlled by a current mirror, the area of ​​the capacitor and resistor in the RC charge / discharge section is reduced, thus making the POR circuit area smaller.

[0163] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A POR circuit, characterized in that, include: The startup unit, trigger unit, first inverter unit, delay unit, and second inverter unit are connected in sequence. The input terminal of the startup unit is connected to the power supply VCC, and the output terminal of the second inverter unit is connected to the digital module. The startup unit is used to receive the input voltage of the power supply VCC, and to start the POR circuit when the input voltage reaches the start-up threshold. The trigger unit is used to respond to the start-up signal sent by the start-up unit to enable the POR circuit and output the equivalent voltage of the input voltage of the power supply VCC. The first inverter unit is used to receive the equivalent voltage output by the flip-flop unit; The equivalent voltage is inverted to generate a first voltage, and the first voltage is output. The delay unit is used to charge the device using the current input from the current generation circuit controlled by the current mirror; when the accumulated charge reaches a set threshold, it receives the first voltage and flips it to generate a second voltage, and then outputs the second voltage. The second inverter unit is used to receive the second voltage, continuously flip the second voltage to generate a third voltage, and output the third voltage.

2. The POR circuit according to claim 1, characterized in that, The startup unit includes: a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; One end of the second resistor is connected to the drain of the first NMOS transistor, and the other end is connected to the power supply VCC. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor; The source of the second NMOS transistor is connected to the drain of the third NMOS transistor; The source of the third NMOS transistor is grounded; The gates of the first NMOS transistor to the third NMOS transistor are connected to the first resistor and connected to the power supply VCC; wherein the first resistor is used to protect the first NMOS transistor to the third NMOS transistor.

3. A POR circuit according to claim 2, characterized in that, The trigger unit is a Schmitt trigger unit.

4. A POR circuit according to claim 3, characterized in that, The trigger unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, and a third resistor; The source of the first PMOS transistor is connected to the power supply VCC, and the drain is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the fourth NMOS transistor is grounded; The third resistor is connected to the drain of the third PMOS transistor; The source of the third PMOS transistor is connected to the drain of the first PMOS transistor and the source of the second PMOS transistor, and the gate is connected to the drain of the second PMOS transistor and the drain of the fourth NMOS transistor. The gates of the first PMOS transistor, the second PMOS transistor, and the fourth NMOS transistor are connected to the drain of the first NMOS transistor in the startup unit.

5. A POR circuit according to claim 4, characterized in that, The first inverter unit includes: a fourth PMOS transistor and a fifth NMOS transistor; The source of the fourth PMOS transistor is connected to the power supply VCC, and the drain is connected to the fifth NMOS transistor. The source of the fifth NMOS transistor is grounded; The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor and is connected to the drain of the fourth NMOS transistor in the trigger unit.

6. A POR circuit according to claim 5, characterized in that, The delay unit includes: a fifth PMOS transistor, a sixth NMOS transistor, and a first capacitor; The source of the fifth PMOS transistor is connected to the current generation circuit controlled by the current mirror. The drain of the sixth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source is grounded; One end of the first capacitor is connected to the drain of the sixth NMOS transistor, and the other end is grounded; The gate of the fifth PMOS transistor is connected to the gate of the sixth NMOS transistor and is connected to the drain of the fifth NMOS transistor in the first inverter unit.

7. A POR circuit according to claim 6, characterized in that, The second inverter unit includes: a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor; The sixth PMOS transistor and the seventh NMOS transistor constitute the first inverter; The source of the sixth PMOS transistor is connected to the power supply VCC; The drain of the seventh NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source is grounded. The gates of the sixth PMOS transistor and the seventh NMOS transistor are connected to and connected to the drain of the sixth NMOS transistor in the delay unit; The seventh PMOS transistor and the eighth NMOS transistor constitute the second inverter; The source of the seventh PMOS transistor is connected to the power supply VCC; The drain of the eighth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the source is grounded. The gates of the eighth NMOS transistor and the seventh PMOS transistor are connected and connected to the drain of the seventh NMOS transistor. The eighth PMOS transistor and the ninth NMOS transistor constitute the third inverter; The source of the eighth PMOS transistor is connected to the power supply VCC; The drain of the ninth NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source is grounded. The gates of the ninth NMOS transistor and the eighth PMOS transistor are connected to and connected to the drain of the eighth NMOS transistor. The ninth PMOS transistor and the tenth NMOS transistor constitute the fourth inverter; The source of the ninth PMOS transistor is connected to the power supply VCC. The drain of the tenth NMOS transistor is connected to the drain of the ninth PMOS transistor and connected to the digital module, while the source is grounded. The gates of the tenth NMOS transistor and the ninth PMOS transistor are connected to the drain of the ninth NMOS transistor.

8. A POR circuit according to claim 6, characterized in that, The current generation circuit controlled by the current mirror includes: a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a fourth resistor. The source of the tenth PMOS transistor is connected to the power supply VCC, and the drain is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to one end of the first switch; The other end of the first switch is connected to the current mirror; The sources of the eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are connected to the power supply VCC, and their drains are connected to the second, third, fourth, and fifth switches, respectively, and connected to the source of the fifth PMOS transistor in the delay unit. The gates of the eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are connected to and connected to the connection terminal of the fourth resistor and the first switch.

9. A POR circuit according to claim 7, characterized in that, The POR circuit also includes: a fifteenth PMOS transistor; The source of the fifteenth PMOS transistor is connected to the power supply VCC; The drain of the fifteenth PMOS transistor is connected to the drain of the sixth NMOS transistor of the delay unit; The gate of the fifteenth PMOS transistor is connected to the gates of the seventh PMOS transistor and the eighth NMOS transistor of the second inverter.

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