A method and apparatus for transmitting and receiving path information

Abstract

The application discloses a method and device for sending and receiving path information, and relates to the field of computing devices to obtain the shortest path between nodes in a large-scale graph. The specific scheme is as follows: in the tth iteration, a first computing vertex sends K first path information to a second computing vertex, K is an upper limit value of the number of first path information allowed to be sent by the first computing vertex in the tth iteration; the first path information is used for indicating a known shortest path from the first computing vertex to the second computing vertex; after sending the K first path information to the second computing vertex, if the first computing vertex determines that there is unsent first path information, the first computing vertex sends the remaining first path information to the second computing vertex in subsequent iterations.

Description

Technical Field

[0001] This application relates to the field of computing devices, and more particularly to a method and apparatus for sending and receiving path information. Background Technology

[0002] The shortest path is the path from one node to another in a graph that minimizes the sum of the weights of all edges. The shortest path problem aims to find the shortest path between two nodes in a network and has wide applications in social networks, fault detection, and other fields.

[0003] A common algorithm for finding the shortest path uses an adjacency matrix to store the weights (distances) between two points. For each pair of nodes, if a shorter path exists in the graph than the known path, the corresponding value in the adjacency matrix is ​​updated. The final values ​​in the adjacency matrix represent the shortest path between each pair of nodes. However, this algorithm has high space complexity. For large-scale graphs, the adjacency matrix consumes a large amount of memory resources, making it unfeasible on a single machine with insufficient storage resources.

[0004] In summary, finding the shortest path between nodes in a large-scale graph is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a method and apparatus for sending and receiving path information to obtain the shortest path between nodes in a large-scale graph.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a method for sending path information is provided. This method may include: in the t-th iteration, a first computational vertex sends K pieces of first path information to a second computational vertex, where K is an upper limit on the number of first path information pieces that the first computational vertex is allowed to send in the t-th iteration; the second computational vertex is a downstream computational vertex adjacent to the first computational vertex; the first path information indicates the known shortest path from the first computational vertex to the second computational vertex; after sending K pieces of first path information to the second computational vertex, if the first computational vertex determines that there is unsent first path information, the first computational vertex sends the remaining first path information to the second computational vertex in subsequent iterations. Where t and K are both positive integers.

[0008] The method for sending path information provided in this application configures an upper limit K for the number of first path information messages that can be sent. This limits the number of first path information messages sent from a first computing vertex to its adjacent downstream second computing vertex to a maximum of K messages at a time. If there are too many first path information messages to be sent, they are sent in multiple batches. By setting a K value that conforms to the network architecture, when obtaining the shortest path between nodes in a large-scale graph, the problem of nodes with excessively large inputs failing to obtain the shortest path due to insufficient memory or message timeouts caused by receiving too many path messages at once can be avoided. Furthermore, by sending the remaining first path information to the second computing vertex in subsequent iterations when it is determined that there is unsent first path information, the transmission of all first path information is guaranteed. Using the scheme provided in this application, each computing vertex in a large-scale graph can obtain the shortest path between computing vertices in the graph after multiple iterations through a time-for-space tradeoff.

[0009] In one possible implementation, the first computation vertex sends the remaining first path information to the second computation vertex in subsequent iterations, further comprising: if the number of remaining first path information is greater than K, then sending it through at least two iterations; if the number of remaining first path information is less than or equal to K, then sending it through one iteration.

[0010] In another possible implementation, K can be a fixed value, which can easily implement the scheme of this application and obtain the shortest path between nodes in a large-scale graph.

[0011] In another possible implementation, the method for sending path information provided in this application may further include: obtaining the number of currently stored first path information entries for the first computing vertex and the number of adjacent downstream computing vertices of the first computing vertex; and determining K based on the number of currently stored first path information entries for the first computing vertex and the number of adjacent downstream computing vertices of the first computing vertex. Determining K by using the number of currently stored first path information entries for the first computing vertex and the number of adjacent downstream computing vertices of the first computing vertex allows for dynamic configuration of K according to the sending requirements of each computing vertex. In the process of obtaining the shortest path between nodes in a large-scale graph, this improves the resource utilization of the computing device where the computing vertex is located while avoiding excessively long computation processes caused by information backlog.

[0012] In another possible implementation, if the amount of currently stored first path information of the first computation vertex is large, a larger K value is determined; if the amount of currently stored first path information of the first computation vertex is small, a smaller K value is determined. Similarly, if the number of adjacent downstream computation vertices of the first computation vertex is large, a larger K value is determined; if the number of adjacent downstream computation vertices of the first computation vertex is small, a smaller K value is determined. This approach, while obtaining the shortest path between nodes in a large-scale graph, avoids excessively long computation processes due to information backlog, thus improving the efficiency of the solution.

[0013] In another possible implementation, the method for sending path information provided in this application may further include: obtaining the memory operation parameters of the computing device to which the first computing vertex belongs; the memory operation parameters being used to indicate the memory usage level of the computing device; and determining K based on the memory operation parameters. Determining K based on the memory usage level allows for reasonable configuration of the K value while ensuring normal memory operation.

[0014] In another possible implementation, after the first computation vertex sends K pieces of first path information to the second computation vertex, if the first computation vertex determines that there is unsent first path information, it sends the remaining first path information to the second computation vertex in subsequent iterations. Specifically, after sending K pieces of first path information to the second computation vertex, the first computation vertex receives a first flag information sent by the second computation vertex. This first flag information is used to indicate that the first computation vertex remains active. When the first computation vertex is active, it sends the remaining first path information to the second computation vertex in subsequent iterations. This avoids the first computation vertex entering an inactive state when there is still unsent first path information, ensuring that the shortest path between nodes in the graph can be completely obtained.

[0015] In another possible implementation, the method provided in this application may further include: after sending less than or equal to K first path information to the second computation vertex, if the first computation vertex does not receive the first flag information sent by the second computation vertex, the first computation vertex enters an inactive state.

[0016] In another possible implementation, after sending K first path information messages to the second computation vertex, if the first computation vertex determines that there is unsent first path information, it remains active in subsequent iterations. Specifically, after sending K first path information messages to the second computation vertex, if the first computation vertex determines that there is unsent first path information, it sends second flag information to the second computation vertex. This second flag information indicates the existence of unsent path information. The first computation vertex receives the first flag information sent by the second computation vertex, which instructs the receiver to remain active. The first flag information is sent by the second computation vertex based on the second flag information. This implementation is compatible with the Pregel protocol, and the computation vertex remains active during message reception iterations, improving the scheme's compatibility.

[0017] In another possible implementation, the second flag information can be a marker indicating the existence of unsent path information, or the second flag information can be the number of unsent path information.

[0018] In another possible implementation, the first computing vertex sends K first path information to the second computing vertex, including: if the number of first path information stored in the first computing vertex is greater than or equal to K, sending K first path information to the second computing vertex; if the number of first path information stored in the first computing vertex is less than K, sending all the stored first path information to the second computing vertex.

[0019] In another possible implementation, the first path information includes the known shortest path to the first computed vertex, and the weights of the edges between the first computed vertex and the second computed vertex.

[0020] Secondly, another method for receiving path information is provided. This method may include: in the (t+1)th iteration, a second computational vertex receives K pieces of first path information sent by a first computational vertex; the first computational vertex is an upstream computational vertex adjacent to the second computational vertex, and K is an upper limit value of the number of first path information that the first computational vertex is allowed to send in the tth iteration; the first path information is used to indicate the known shortest path from the first computational vertex to the second computational vertex; the second computational vertex sends first flag information to the first computational vertex, the first flag information being used to instruct the first computational vertex to remain active, so that the first computational vertex sends the remaining first path information to the second computational vertex in subsequent iterations. Here, t and K are both positive integers.

[0021] The method for receiving path information provided in this application configures an upper limit K for the number of first path information messages that can be sent. This limits the number of first path information messages sent from the first computing vertex to the adjacent downstream second computing vertex to a maximum of K messages at a time. If there are too many first path information messages to be sent, they are sent in multiple batches. By setting a K value that conforms to the network architecture, when obtaining the shortest path between nodes in a large-scale graph, the problem of nodes with excessively large inputs failing to obtain the shortest path due to insufficient memory or message processing timeouts caused by receiving too many path messages at once can be avoided. Furthermore, by sending the remaining first path information to the second computing vertex in subsequent iterations when it is determined that there is unsent first path information, the transmission of all first path information is guaranteed. Using the scheme provided in this application, each computing vertex in the large-scale graph can obtain the shortest path between nodes after multiple iterations through a time-for-space tradeoff.

[0022] In one possible implementation, the second computation vertex sends a first flag to the first computation vertex. Specifically, the second computation vertex receives a second flag from the first computation vertex, the second flag indicating the existence of unsent path information. After receiving the second flag, the second computation vertex sends the first flag back to the first computation vertex. This implementation is compatible with the Pregel protocol, and the computation vertex remains active during message iterations, improving the scheme's compatibility.

[0023] Thirdly, another method for sending path information is provided, which may include: in the t-th iteration, a first computational vertex sends K pieces of first path information to a second computational vertex, where K is an upper limit on the number of first path information pieces that the first computational vertex is allowed to send in the t-th iteration; the second computational vertex is a downstream computational vertex adjacent to the first computational vertex, and the first path information is used to indicate the known shortest path from the first computational vertex to the second computational vertex; in the t+1-th iteration, the second computational vertex receives the K pieces of first path information sent by the first computational vertex; the second computational vertex sends first flag information to the first computational vertex, which is used to indicate that the first computational vertex remains active; in the t+2-th iteration, the first computational vertex receives the first flag information sent by the second computational vertex, and the first computational vertex remains active in subsequent iterations, and sends the remaining first path information to the second computational vertex while in an active state. Where t and K are both positive integers.

[0024] The method for sending path information provided in this application configures an upper limit K for the number of first path information messages that can be sent. This limits the number of first path information messages sent from a first computing vertex to its adjacent downstream second computing vertex, allowing a maximum of K messages to be sent at a time. If there are too many first path information messages to send, they are sent in multiple batches. By setting a K value that conforms to the network architecture, when obtaining the shortest path between nodes in a large-scale graph, the problem of nodes with excessively large inputs failing to obtain the shortest path due to insufficient memory or message timeouts caused by receiving too many path messages at once can be avoided. Furthermore, by sending the remaining first path information to the second computing vertex in subsequent iterations when it is determined that there is unsent first path information, the transmission of all first path information is guaranteed. Using the scheme provided in this application, each computing vertex in a large-scale graph can obtain the shortest path between nodes after multiple iterations through a time-for-space tradeoff.

[0025] Fourthly, an apparatus for transmitting path information is provided. This apparatus is deployed at a first computing vertex and includes a transmitting unit and a first determining unit. Wherein:

[0026] A sending unit is used to send K pieces of first path information to the second computation vertex in the t-th iteration. Here, K is the upper limit of the number of first path information pieces that the first computation vertex is allowed to send in the t-th iteration. The second computation vertex is a downstream computation vertex adjacent to the first computation vertex; the first path information indicates the known shortest path from the first computation vertex to the second computation vertex. Here, t and K are both positive integers.

[0027] The first determining unit is used to determine whether there is any unsent first path information after sending K first path information to the second computing vertex.

[0028] The sending unit is also used to send the remaining first path information to the second computation vertex in subsequent iterations if the determining unit determines that there is unsent first path information after sending K first path information to the second computation vertex.

[0029] In one possible implementation, the sending unit is specifically used to: send the information through at least two iterations if the number of remaining first path information is greater than K; and send the information through one iteration if the number of remaining first path information is less than or equal to K.

[0030] In another possible implementation, the device may further include an acquisition unit and a determination unit. The acquisition unit is used to acquire the number of currently stored first path information entries for the first computation vertex and the number of adjacent downstream computation vertices of the first computation vertex. The determination unit is used to determine K based on the number of currently stored first path information entries for the first computation vertex and the number of adjacent downstream computation vertices of the first computation vertex.

[0031] In another possible implementation, the device may further include: an acquisition unit and a second determination unit. The acquisition unit is used to acquire the memory operating parameters of the computing device to which the first computing vertex belongs; the memory operating parameters are used to indicate the memory usage of the computing device; the second determination unit is used to determine K based on the memory operating parameters.

[0032] In another possible implementation, the device may further include a receiving unit, configured to receive first flag information sent by the second computational vertex after sending K pieces of first path information to the second computational vertex. The first flag information is used to indicate that the first computational vertex remains active. Specifically, the sending unit is configured to send the remaining first path information to the second computational vertex in subsequent iterations when the first computational vertex is active.

[0033] In another possible implementation, the device may further include a state control unit, which is used to: after the sending unit sends less than or equal to K first path information to the second computing vertex, if the receiving unit does not receive the first flag information sent by the second computing vertex, control the first computing vertex to enter an inactive state.

[0034] In another possible implementation, the sending unit is further configured to, after sending K pieces of first path information to the second computation vertex, if it is determined that the first computation vertex has unsent first path information, send second flag information to the second computation vertex. The second flag information is used to indicate the existence of unsent path information. The device also includes a receiving unit configured to receive the first flag information sent by the second computation vertex. The first flag information is used to instruct the receiver to remain active. When the first computation vertex is active, the remaining first path information is sent to the second computation vertex in subsequent iterations. The first flag information is sent by the second computation vertex based on the second flag information.

[0035] In another possible implementation, the sending unit is specifically used to: send K pieces of first path information to the second computing vertex if the first computing vertex stores more than or equal to K pieces of first path information; and send all the stored first path information to the second computing vertex if the first computing vertex stores less than K pieces of first path information.

[0036] In another possible implementation, the first path information includes the known shortest path to the first computed vertex, and the weights of the edges between the first computed vertex and the second computed vertex.

[0037] Fifthly, another means for receiving path information is provided, which is deployed at the second computing vertex and may include a receiving unit and a transmitting unit. Wherein:

[0038] The receiving unit is used to receive K first path information messages sent by the first computation vertex in the (t+1)th iteration. The first computation vertex is the upstream computation vertex adjacent to the second computation vertex, and K is the upper limit of the number of first path information messages that the first computation vertex is allowed to send in the tth iteration. The first path information is used to indicate the known shortest path from the first computation vertex to the second computation vertex. Here, t and K are both positive integers.

[0039] The sending unit is used to send first flag information to the first computing vertex. The first flag information is used to instruct the first computing vertex to remain active so that the first computing vertex can send the remaining first path information to the second computing vertex in subsequent iterations.

[0040] In one possible implementation, the receiving unit is further configured to receive second flag information sent by the first computation vertex, the second flag information being used to indicate the existence of unsent path information. Specifically, the sending unit is configured to send the first flag information to the first computation vertex after the receiving unit receives the second flag information.

[0041] A sixth aspect provides a computing device having a first computing vertex and / or a second computing vertex deployed thereon as described in any of the foregoing aspects or any possible implementations.

[0042] In a seventh aspect, a system for transmitting path information is provided, including a computing device as described in the sixth aspect.

[0043] Eighthly, a computing device is provided that can implement the functions of a first computing vertex and / or a second computing vertex as described in the method examples of any of the preceding aspects. These functions can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the aforementioned functions. The computing device can exist in the form of a chip.

[0044] In one possible implementation, the computing device may include a processor and a transmission interface. The transmission interface is used to receive and send data. The processor is configured to invoke program instructions stored in memory to cause the computing device to perform the functions of the first computing vertex and / or the second computing vertex in the method examples described above.

[0045] Ninth aspect, a computer-readable storage medium is provided, including instructions that, when executed on a computer, cause the computer to perform the method of sending path information as described in any of the preceding aspects or any possible implementations, or to perform the method of receiving path information as described in any of the preceding aspects or any possible implementations.

[0046] In a tenth aspect, a computer program product is provided that, when run on a computer, causes the computer to perform the method for sending path information as described in any of the above aspects or any possible implementations, or to perform the method for receiving path information as described in any of the above aspects or any possible implementations.

[0047] Eleventhly, a chip system is provided, which includes a processor and may also include a memory for implementing the functions described above. The chip system may be composed of chips or may include chips and other discrete devices.

[0048] The solutions provided in aspects four through eleven above are used to implement the methods provided in aspect one or aspect two above, and therefore can achieve the same beneficial effects as aspect one or aspect two, which will not be elaborated here.

[0049] It should be noted that any of the possible implementations of any of the above aspects can be combined, provided that the solutions do not contradict each other. Attached Figure Description

[0050] Figure 1 A schematic diagram of a large-scale graph is provided;

[0051] Figure 2 A schematic diagram of a graph computing architecture provided in an embodiment of this application;

[0052] Figure 3 This application provides a schematic diagram of the structure of a server according to an embodiment of the present application.

[0053] Figure 4 A schematic diagram of vertex state transitions in a Pregel is provided.

[0054] Figure 5 A flowchart illustrating a method for sending path information provided in an embodiment of this application;

[0055] Figure 6 A schematic diagram of a directed graph provided for an embodiment of this application;

[0056] Figure 7 A schematic diagram of a directed graph is provided;

[0057] Figure 8This is a schematic diagram illustrating a K-value allocation strategy provided in an embodiment of this application.

[0058] Figure 9 A flowchart illustrating another method for sending path information provided in an embodiment of this application;

[0059] Figure 10 A schematic diagram of a distributed graph provided in an embodiment of this application;

[0060] Figure 11 A flowchart illustrating a method for receiving path information provided in an embodiment of this application;

[0061] Figure 12 This application provides a schematic diagram of a scenario for sending path information in a distributed graph, as illustrated in an embodiment of the present application.

[0062] Figure 13 This is a schematic diagram illustrating another scenario for sending path information in a distributed graph, provided in an embodiment of this application.

[0063] Figure 14 This is a schematic diagram illustrating another scenario for sending path information in a distributed graph, as provided in an embodiment of this application.

[0064] Figure 15 This is a schematic diagram illustrating another scenario for sending path information in a distributed graph, as provided in an embodiment of this application.

[0065] Figure 16 This is a schematic diagram of the structure of a device for sending path information provided in an embodiment of this application;

[0066] Figure 17 A schematic diagram of another device for sending path information provided in an embodiment of this application;

[0067] Figure 18 A schematic diagram of the structure of another device for receiving path information provided in an embodiment of this application;

[0068] Figure 19 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0069] The terms "first," "second," and "third," etc., used in this application specification, claims, and the aforementioned drawings are used to distinguish different objects, not to limit a specific order.

[0070] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0071] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between the related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0072] In the embodiments of this application, at least one can also be described as one or more, and multiple can be two, three, four or more, and this application does not impose any restrictions.

[0073] Before describing the embodiments of this application, the terms used in the embodiments of this application will be explained.

[0074] A graph is a data structure in computers, consisting of vertices and edges. Much large datasets can be represented as large-scale graphs or networks. Examples include social networks, the spread of infectious diseases, and the impact of traffic accidents on road networks. Graph data structures effectively express the relationships between data. Graphs can include directed graphs and undirected graphs.

[0075] A vertex is the smallest element that makes up a graph; it can also be called a computational vertex. A vertex can contain data, and a graph can have multiple vertices. In this application, the device that deploys vertices is referred to as a computing device.

[0076] An adjacency vertex is a set of other computational vertices that a computational vertex can access via an edge.

[0077] An upstream computation vertex is a computation vertex that precedes the current vertex on a path.

[0078] An adjacent upstream computation vertex is a computation vertex on a path that precedes the current computation vertex and is connected to the current computation vertex by an edge. For example, in a directed graph, adjacent upstream computation vertices refer to the set of computation vertices connected to the current computation vertex by its incident edge.

[0079] An adjacent downstream computation vertex is a computation vertex on a path that follows the current computation vertex and is connected to the current computation vertex by an edge. For example, in a directed graph, adjacent downstream computation vertices refer to the set of computation vertices connected by outgoing edges from the current computation vertex.

[0080] The in-degree of a vertex is the number of incident edges to a vertex in a directed graph.

[0081] The out-degree of a vertex is the number of outgoing edges of a vertex in a directed graph.

[0082] Edge weight refers to the distance, size, or length between two computed vertices in a graph. For example, edge weight can represent the probability of a character's corresponding binary code appearing.

[0083] The shortest path is the path that has the shortest distance between two vertices in a graph.

[0084] Single-source shortest path: Given a source vertex, compute the shortest path from the other compute vertices.

[0085] Multi-source shortest path: calculate the shortest path between any two vertices.

[0086] Path information is information used to indicate a path. For example, path information can be used to indicate the distance (or weight) from one vertex to another.

[0087] This application provides a method for sending path information. It configures a maximum value K of path information that a computational vertex is allowed to send in one iteration, sending a maximum of K path information at a time. If there is too much path information, it is sent in multiple iterations. By setting a K value that conforms to the network architecture, when obtaining the shortest path between nodes in a large-scale graph, it avoids the problem of nodes with excessively large ingress values ​​failing to obtain the shortest path due to insufficient memory or message processing timeouts caused by receiving too many path messages at once. Furthermore, by sending the remaining first path information to the second computational vertex in subsequent iterations when it is determined that there is unsent first path information, it ensures that all first path information is sent. Using the scheme provided in this application, each computational vertex in a large-scale graph can obtain the shortest path between computational vertices in the graph after multiple iterations through a time-for-space tradeoff.

[0088] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0089] The solution provided in this application can be applied to graph computing architectures, which include computing devices, such as servers, for graph computation and storage, for example, for determining the shortest path between vertices in the graph. The graph computing architecture can have one or more servers; when the graph is large, it can be divided into multiple subgraphs, with different servers used for computation and storage in different subgraphs. Figure 1 The diagram illustrates a large-scale graph, where a dot represents a computational vertex within that graph.

[0090] Figure 2 This illustrates a graph computing architecture, such as Figure 2 As shown, the graph computing architecture may include a master server 201 and multiple worker servers 202. Each worker server 202, acting as a computing device, is responsible for the computation and storage of the subgraph. Each vertex in the subgraph handled by a worker server 202 is called a computation vertex. The worker server 202 can be the computing device described in this application. The master server 201 controls the multiple worker servers 202.

[0091] It should be noted that the above Figure 2 The schematic diagram of the computing architecture is only an example to illustrate the application scenario of the solution in this application, and is not intended to limit the application scenario of the solution in this application.

[0092] The solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0093] On one hand, embodiments of this application provide a server 30 for executing the method for sending path information provided in this application. For example, the server 30 can be... Figure 2 The diagram shows the working server 202.

[0094] Figure 3 This diagram illustrates the structure of the server 30 provided in an embodiment of this application. Figure 3 As shown, server 30 may include processor 301, memory 302, and transceiver 303.

[0095] The following is combined Figure 3 A detailed introduction to each component of server 30:

[0096] The memory 302 may be volatile memory, such as random-access memory (RAM); or non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid-state drive (SSD); or a combination of the above types of memory, used to store application code, configuration files, data information, or other content that can implement the methods of this application. In other possible cases, the memory 302 may also be deployed in other devices independent of server 30.

[0097] Transceiver 303 is used for information exchange between server 30 and other devices.

[0098] Processor 301 can be the control center of server 30. For example, processor 301 can be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0099] For example, processor 301 can perform the following functions by running or executing software programs and / or modules stored in memory 302:

[0100] In the t-th iteration, K first path information is sent to the second computing node, where K is the upper limit of the number of first path information that the first computing vertex is allowed to send in the t-th iteration; the second computing vertex is the downstream computing vertex adjacent to the first computing vertex; the first path information is used to indicate the known shortest path from the first computing vertex to the second computing vertex; after sending K first path information to the second computing vertex, if the first computing vertex determines that there is unsent first path information, the first computing vertex sends the remaining first path information to the second computing vertex in subsequent iterations.

[0101] For example, processor 301 can perform the following functions by running or executing software programs and / or modules stored in memory 302:

[0102] In the (t+1)th iteration, the second computation vertex receives K first path information sent by the first computation vertex; the first computation vertex is the upstream computation vertex adjacent to the second computation vertex, and K is the upper limit of the number of first path information that the first computation vertex is allowed to send in the tth iteration; the first path information is used to indicate the known shortest path from the first computation vertex to the second computation vertex; the second computation vertex sends first flag information to the first computation vertex, the first flag information is used to indicate that the first computation vertex remains active, so that the first computation vertex sends the remaining first path information to the second computation vertex in subsequent iterations.

[0103] For example, processor 301 can perform the following functions by running or executing software programs and / or modules stored in memory 302:

[0104] In the t-th iteration, the first computation vertex sends K first path information to the second computation vertex, where K is the upper limit of the number of first path information that the first computation vertex is allowed to send in the t-th iteration. The second computation vertex is the downstream computation vertex adjacent to the first computation vertex, and the first path information is used to indicate the known shortest path from the first computation vertex to the second computation vertex. In the t+1-th iteration, the second computation vertex receives the K first path information sent by the first computation vertex. The second computation vertex sends first flag information to the first computation vertex, which is used to indicate that the first computation vertex remains active. In the t+2-th iteration, the first computation vertex receives the first flag information sent by the second computation vertex. The first computation vertex remains active in subsequent iterations and sends the remaining first path information to the second computation vertex while in an active state.

[0105] On the other hand, this application provides a method for sending path information, applied in the process of obtaining the shortest path between vertices in graph computation. The solution provided in this application is based on sending path information to obtain the shortest path, and can obtain a single-source shortest path or a multi-source shortest path. The embodiments of this application are not limited to specific application scenarios. For example, the solution provided in the embodiments of this application can perform graph computation based on Pregel technology.

[0106] Pregel is a Spark-based parallel graph processing system. The process of finding the shortest path between vertices in a graph using Pregel involves a series of global supersteps (iterations). Initially, all vertices are active. In the current iteration (t), each computed vertex (called the current computed vertex) can read path information sent to it by other computed vertices in the previous iteration (t-1). This path information indicates the shortest path from an upstream computed vertex to the current computed vertex (e.g., a path information received by the current computed vertex may include the known shortest path from an upstream computed vertex to an adjacent upstream computed vertex, and the weights of the edges between the current computed vertex and its adjacent upstream computed vertices; or, a path information received by the current computed vertex may only include the weights of the edges between the current computed vertex and its adjacent upstream computed vertices).

[0107] If the current computation vertex does not receive any information, its state is changed to inactive. If the current computation vertex receives information (path information or other information), it performs computation based on the received path information to determine the shortest path from the upstream computation vertex to the adjacent downstream computation vertex. If a new shortest path is found during computation, the found path message is sent along the outgoing edge; this path information will be received by the target computation vertex in the next superstep (t+1), and then the next iteration begins. If no new shortest path is found during computation, the current computation vertex switches its state to inactive. During the iteration process, paths from computation vertices with the same origin are merged until all computation vertices are inactive. At this point, all computation vertices will know the shortest path to all computation vertices whose endpoint is this computation vertex. The state switching of computation vertices in Pregel can be done as follows: Figure 4 As shown.

[0108] It should be noted that in the process of obtaining the shortest path between computation vertices in graph computation, the computation logic of each computation vertex is the same in each iteration (superstep). The following only describes the computation process of the first computation vertex in one iteration, and the others will not be repeated. The first computation vertex is any computation vertex in the graph. In the initial state, all computation vertices in the graph are in an active state; in one iteration, a computation vertex can read the path information sent to it by other computation vertices in the previous iteration, and the active computation vertex also sends path information to its adjacent downstream computation vertices in this iteration.

[0109] like Figure 5 As shown, a method for sending path information provided in this application may include:

[0110] S501. In the t-th iteration, the first computation vertex sends K first path information to the second computation vertex, where K is the upper limit of the number of first path information that the first computation vertex is allowed to send in the t-th iteration.

[0111] Specifically, S501 is the operation performed when the first computation vertex is in an active state during an iteration and there is unsent first path information. Here, t and K are both positive integers.

[0112] The first path information indicates the known shortest path from the first computation vertex to the second computation vertex (the shortest path determined by the path information obtained before the current time is called the known shortest path). The second computation vertex is the downstream computation vertex adjacent to the first computation vertex.

[0113] For example, the first path information may include the known shortest path to the first computed vertex, and the weights of the edges between the first computed vertex and its adjacent downstream computed vertices.

[0114] In this diagram, each upstream computational vertex reachable from the first computational vertex can reach the second computational vertex via the first computational vertex. The upstream computational vertices reachable from the first computational vertex can be the computational vertices preceding the first computational vertex on each path reaching the first computational vertex, as well as the first computational vertex itself. The number of upstream computational vertices of the first computational vertex depends on the size and directionality of the graph, which is not limited in this embodiment.

[0115] For example, such as Figure 6 In the schematic directed graph, the upstream vertices of vertex X are vertices A and B; the upstream vertices of vertex Y are vertices A, B, and X.

[0116] Specifically, when the first computing vertex executes S501, the first path information to be sent can be the first path information determined in this iteration, and / or the first path information determined in previous iterations but not yet sent. This application embodiment does not limit this.

[0117] If the source vertex in the path indicated by the first path information is not the first calculated vertex, the first path information is determined based on the received second path information.

[0118] The second path information is used to indicate a known shortest path from a certain upstream computational vertex of the first computational vertex to the first computational vertex. It should be understood that the second path information can also be used to indicate a known shortest path from a third computational vertex to the first computational vertex. For example, the second path information may include a known shortest path to a third computational vertex (the third computational vertex being an upstream computational vertex adjacent to the first computational vertex), and the weights of the edges between the third computational vertex and the first computational vertex. The first computational vertex determines the known shortest path from the third computational vertex to the first computational vertex based on the second path information and the weights of the edges between the third computational vertex and the first computational vertex. The first computational vertex may use the known shortest path from the third computational vertex to the first computational vertex, and the weights of the edges between the first computational vertex and the second computational vertex, as the first path information.

[0119] Specifically, the first computation vertex can superimpose the second path information onto the path between the first computation vertex and the second computation vertex to determine the first path information.

[0120] For example, the second path information received by the first computation vertex (R) is: Z->R (10), the path weight between the first computation vertex (R) and the adjacent downstream computation vertex (P) is 3, and the first computation vertex determines the first path information as: Z->P (13).

[0121] In some embodiments, this iteration is the first iteration. The first path information to be sent by the first node device when executing S501 is the weight of the edge between the first node device and each adjacent downstream computed vertex, and the source vertex of the path is the first computed vertex.

[0122] In some other embodiments, this iteration is not the first iteration. In this iteration, the first computing vertex receives the second path information. In this iteration, the first computing vertex determines the first path information based on the second path information. The first path information to be sent when the first computing vertex executes S501 includes the first path information determined based on the second path information in this iteration.

[0123] For example, the process of the first computation vertex sending the first path information in S501, or determining the first path information based on the second path information, can be referred to the implementation of the Pregel algorithm in GraphX. The following example illustrates this.

[0124] For example, for Figure 7For a directed graph, the Pregel-based multi-source shortest path algorithm can be implemented as follows: In the initial state, all computational vertices are active. In the first iteration, each computational vertex sends path information to its adjacent downstream computational vertices. The path information to be sent by each computational vertex can be illustrated in Table 1. This path information may include the known shortest path from an upstream computational vertex to the upstream computational vertex adjacent to the current computational vertex, and the weights of the edges between the upstream computational vertices adjacent to the current computational vertex and the current computational vertex; alternatively, it may only include the weights of the edges between the upstream computational vertices adjacent to the current computational vertex and the current computational vertex.

[0125] Table 1

[0126]

[0127] Figure 7 In the computational vertices A through E, there are path information to be sent. In this iteration, executing operation S501 allows each vertex to send K path information to its adjacent downstream vertices based on its respective K value. Assume... Figure 7 The schematic directed graph is summarized, and the K value of each computation vertex is a fixed value of 5. The path information to be sent for each computation vertex shown in Table 1 will be sent.

[0128] In the next iteration, Figure 7 In the illustrated directed graph, each computation vertex can read the path information sent to it by other computation vertices in the previous iteration, and use the received path information and the weights of its edges to adjacent downstream computation vertices as its own path information to be sent. In this iteration, the path information for each vertex is illustrated in Table 2. In this iteration, computation vertex C does not receive any path information, so its state switches to an inactive state. Since computation vertices A, C, and F have no outgoing edges, they have no path information to be sent.

[0129] Table 2

[0130]

[0131] For example, in S501, the first computation vertex sends the first path information, which can be done using the `sendMsg` function in the Pregel algorithm. In the process of determining the first path information based on the second path information in S501, paths from computation vertices with the same origin can be merged, specifically using the `mergeMsg` function in the Pregel algorithm.

[0132] In one possible implementation, when executing S501, the first computing vertex sends K first path information to the second computing vertex. Specifically, this can be implemented as follows: if the first computing vertex stores more than or equal to K first path information, it sends K first path information to the second computing vertex; if the first computing vertex stores less than K first path information, it sends all the stored first path information to the second computing vertex.

[0133] In one possible implementation, K can be a fixed value. For example, the value of K can be configured based on actual needs or network performance, and practical experience. This application embodiment does not limit the value of K. A larger K value results in fewer iterations, shorter computation time, and a higher probability of insufficient memory or computation timeout leading to failure to obtain the shortest path. Conversely, a smaller K value results in more iterations, longer computation time, and a lower probability of insufficient memory or computation timeout leading to failure to obtain the shortest path.

[0134] For example, K can be configured to be 1, meaning that the first computed vertex sends only one first path information in one iteration.

[0135] In another possible implementation, K can be a dynamic value that can be adjusted dynamically. In practical applications, when entering an iteration, the first computation vertex first determines the value of K and then executes S501. It should be noted that the value of K can be determined by the computation node itself, or it can be determined by a centralized device and then sent to each computation vertex; this embodiment does not limit this approach.

[0136] Specifically, the specific implementation schemes for determining K may include, but are not limited to, the following schemes 1 to 3:

[0137] Scheme 1, K is determined by the number of currently stored first path information of the computed vertex and / or the number of downstream computed vertices adjacent to the computed vertex.

[0138] The number of downstream computed vertices adjacent to a computed vertex can be understood as the out-degree of the computed vertex.

[0139] In Scheme 1, the specific process of determining K may include: obtaining the number of currently stored first path information of the first computation vertex and the number of adjacent downstream computation vertices of the first computation vertex; determining K based on the number of currently stored first path information of the first computation vertex and the number of adjacent downstream computation vertices of the first computation vertex.

[0140] In one possible implementation, K is proportional to the amount of currently stored first path information for the computed vertex.

[0141] In another possible implementation, K is proportional to the number of downstream computation vertices adjacent to the first computation vertex.

[0142] In another possible implementation, K is proportional to the number of first path information currently stored in the computed vertex and the number of downstream computed vertices adjacent to the first computed vertex.

[0143] Figure 8 This illustrates a strategy for allocating K values, from Figure 8 As can be seen from the diagram, the larger the out-degree, the larger the K value; the more path information stored, the larger the K value.

[0144] For example, the value of K can be an expression for reference information (the number of currently stored first path information of the computed vertex and / or the number of downstream computed vertices adjacent to the computed vertex), K = f(x), where x identifies the reference information, and the content of f(.) can be configured according to actual needs.

[0145] In Scheme 2, K is determined by the memory operating parameters of the computing device to which the computing vertex belongs. The memory operating parameters are used to indicate the memory usage of the computing device.

[0146] Among them, the memory operation parameters can be memory usage, memory utilization, or other parameters.

[0147] In Scheme 2, the specific process of determining K may include: obtaining the memory operating parameters of the computing device to which the first computing vertex belongs; and determining K based on the memory operating parameters.

[0148] In one possible implementation, the memory operating parameters can be inversely proportional to K.

[0149] In another possible implementation, the memory's operating parameters can be monitored periodically. When the memory operating parameters are below a threshold, the value of K is increased; when the memory operating parameters are close to the threshold, the value of K is decreased, ensuring that the memory operating parameters are less than or equal to the threshold. This allows for dynamic adjustment of the value of K. The threshold can be the maximum allowable value for the memory operating parameter.

[0150] Of course, the specific strategy for determining K based on memory operating parameters can be configured according to actual needs; the embodiments in this application are merely examples.

[0151] Scheme 3: K is determined by the number of first path information currently stored in the computation vertex, the number of downstream computation vertices adjacent to the computation vertex, and the memory operation parameters of the computation device to which the computation vertex belongs.

[0152] Specifically, the content referenced in determining K in Scheme 3 combines the content of Scheme 1 and Scheme 2. The specific implementation of determining K in Scheme 3 can refer to the specific implementation of Scheme 1 and Scheme 2, which will not be elaborated here.

[0153] S502. After sending K first path information to the second computation vertex, if the first computation vertex determines that there is unsent first path information, the first computation vertex sends the remaining first path information to the second computation vertex in subsequent iterations.

[0154] The specific implementation of determining whether there is unsent first path information in S502 can include the following mechanisms:

[0155] Mechanism 1: The second computing vertex sends a first flag information to instruct the first computing vertex to remain active. The first computing vertex remains active according to the first flag information. When the first computing vertex is active, it sends the remaining first path information to the second computing vertex in subsequent iterations.

[0156] The content and format of the first identifier information are not limited in the embodiments of this application.

[0157] In current graph computation, such as the Pregel technique, a computed vertex enters an inactive state if it does not receive information. Since this application limits the number of path information sent by using a K value, there may still be unsent path information when a computed vertex has not received information. If it enters an inactive state at this time, it may result in the omission of this unsent path information. Mechanism 1 provided in this application involves an adjacent downstream computed vertex sending a first flag to indicate that the first computed vertex remains active, ensuring that the first computed vertex, while active, sends the remaining first path information to the second computed vertex in subsequent iterations.

[0158] Furthermore, in the Pregel technique, the message sent by the vertex is computed in one iteration, and the receiver receives it in the next iteration. The first flag information sent by the second compute vertex is received by the first compute vertex in the next iteration after the first flag information is sent, and the first compute vertex remains active.

[0159] In one possible implementation, after receiving the first path information sent by the first computational vertex, the second computational vertex sends a first flag. It should be understood that upon receiving the first path information from the first computational vertex, the second computational vertex assumes that the first computational vertex may have unsent first path information, and thus sends the first flag to keep the first computational vertex active, ensuring that the first path information is sent in subsequent iterations.

[0160] In another possible implementation, after receiving the first path information sent by the first computing vertex, the second computing vertex sends first flag information if it determines that the first computing vertex has not sent the first path information.

[0161] For example, the second computation vertex can determine whether the first computation vertex has unsent first path information based on the K value of the first computation vertex in the t-th iteration. After receiving the first path information sent by the first computation vertex, the second computation vertex determines whether the number of first path information received this time is K. If it is K, it considers that the first computation vertex may have unsent first path information, and thus sends a first flag to keep the first computation vertex active, ensuring that the first path information is sent. If it is not K, it considers that the first computation vertex may not have unsent first path information, and thus sends a first flag to keep the first computation vertex active, ensuring that the first path information is sent.

[0162] In a scheme where K is a fixed value, K is a known value for each computation vertex; in a scheme where K is not a dynamic value, the first computation vertex can send the value of K in this iteration to the second downstream computation vertex when executing S501 (or after or before).

[0163] For example, the second computation vertex can determine whether the first computation vertex has unsent first path information based on the second flag information. The second flag information can be used to indicate the existence of unsent path information, and the second flag information is sent by the first computation vertex when unsent first path information exists.

[0164] For example, the second flag information may be a marker indicating the existence of unsent path information, or the second flag information may be the number of unsent path information in the first computed vertex, or something else.

[0165] Correspondingly, such as Figure 9 As shown, after sending K first path information to the second computing vertex, the method provided in this application embodiment may further include S503.

[0166] S503. If the first computing vertex determines that there is unsent first path information, the first computing vertex sends second flag information to the second computing vertex.

[0167] Corresponding to S503, the first flag information in mechanism 1 is sent by the adjacent downstream computation vertices according to the second flag information. S503 and S501 are completed in one iteration.

[0168] Correspondingly, if the scheme of mechanism 1 is adopted, if in a certain iteration, after the first computing vertex sends less than or equal to K first path information to the second computing vertex, if the first computing vertex does not receive the first flag information sent by the second computing vertex, the first computing vertex enters an inactive state.

[0169] Mechanism 2: The first computing vertex determines on its own whether there is any unsent first path information. If so, the first computing vertex remains active. When the first computing vertex is active, it sends the remaining first path information to the second computing vertex in subsequent iterations.

[0170] In mechanism 2, after executing S501, the first computation vertex remains active if there is unsent first path information, depending on the actual situation. If there is no unsent first path information, the first computation vertex can enter an inactive state.

[0171] Furthermore, due to the limitation of K, the first computing vertex can only send a maximum of K first path information in one iteration. In S502, the first computing vertex sends the remaining first path information to the second computing vertex in subsequent iterations. Specifically, if the number of remaining first path information is greater than K, it is sent through at least two iterations; if the number of remaining first path information is less than or equal to K, it is sent through one iteration.

[0172] For example, assuming the K of the first computation vertex is 2 and fixed, in the t-th iteration, the first computation vertex has 5 first path information to send. In the t-th iteration, the first computation vertex sends 2 first path information, leaving 3 first path information remaining. Assuming no other computation vertex sends path information to the first computation vertex in the t-th iteration, then in the (t+1)-th iteration, the first computation vertex still has 3 unsent first path information. In the (t+1)-th iteration, the first computation vertex sends 2 first path information, leaving 1 first path information remaining. Assuming no other computation vertex sends path information to the first computation vertex in the (t+1)-th iteration, then in the (t+2)-th iteration, the first computation vertex still has 1 unsent first path information. In the (t+2)-th iteration, the first computation vertex sends 1 first path information, which is non-existent.

[0173] In this example, for the t-th iteration, there are two subsequent iterations (the (t+1)-th iteration and the (t+2)-th iteration). For the (t+1)-th iteration, there is one subsequent iteration (the (t+2)-th iteration).

[0174] The method for sending path information provided in this application configures an upper limit K for the number of first path information messages that can be sent. This limits the number of first path information messages sent from a first computing vertex to its adjacent downstream second computing vertex to a maximum of K messages at a time. If there are too many first path information messages to be sent, they are sent in multiple batches. By setting a K value that conforms to the network architecture, when obtaining the shortest path between nodes in a large-scale graph, the problem of nodes with excessively large inputs failing to obtain the shortest path due to insufficient memory or message timeouts caused by receiving too many path messages at once can be avoided. Furthermore, by sending the remaining first path information to the second computing vertex in subsequent iterations when it is determined that there is unsent first path information, the transmission of all first path information is guaranteed. Using the scheme provided in this application, each computing vertex in a large-scale graph can obtain the shortest path between computing vertices in the graph after multiple iterations through a time-for-space tradeoff.

[0175] like Figure 10 In the distributed graph shown, computational vertices X and Y are two adjacent computational vertices. In the t-th iteration, computational vertex X has n shortest path messages (the first path messages to be sent) to computational vertex Y, but only K messages are sent in this iteration. In the (t+1)-th iteration, computational vertex Y receives the K messages sent by computational vertex X and sends a first flag message to computational vertex X in this iteration. The setting of K avoids computational vertex Y receiving a large number of messages from other computational vertices simultaneously, reducing memory requirements. The first flag message prevents computational vertex X from being inactive, ensuring that it completes sending all the first path messages in subsequent iterations.

[0176] On the other hand, this application embodiment also provides a method for receiving path information, which is applied to the second computation vertex in the foregoing embodiment. In the t-th iteration, the first computation vertex sends K pieces of first path information to the second computation vertex, and in the (t+1)-th iteration, the second computation vertex receives K pieces of first path information. Figure 11 As shown, the method for receiving path information provided in this application embodiment may include S1101 and S1102.

[0177] S1101. In the (t+1)th iteration, the second computation vertex receives K first path information sent by the first computation vertex.

[0178] The first computation vertex is the upstream computation vertex adjacent to the second computation vertex.

[0179] K is the upper limit of the number of first path information that the first computation vertex is allowed to send in the t-th iteration. Both t and K are positive integers.

[0180] The first path information is used to indicate the known shortest path from the first computed vertex to the second computed vertex.

[0181] The content received by the second computing vertex in S1101, which is the same content sent from the first computing vertex to the second computing vertex in S501, will not be described again here.

[0182] S1102, the second computing vertex sends a first flag information to the first computing vertex. The first flag information is used to instruct the first computing vertex to remain active so that the first computing vertex can send the remaining first path information to the second computing vertex in subsequent iterations.

[0183] In one possible implementation, after receiving the first path information sent by the first computing vertex, the second computing vertex executes S1102.

[0184] In another possible implementation, after receiving the first path information sent by the first computing vertex, if the second computing vertex determines that the first computing vertex has unsent first path information, then execute S1102.

[0185] Specifically, the implementation of the second computation vertex determining whether the first computation vertex has unsent first path information can be found in the description of mechanism 1 in S502, and will not be repeated here.

[0186] In some embodiments, the second computing vertex determines that the first computing vertex has unsent first path information based on the second flag information sent by the first computing vertex. Specifically, S1102 can be implemented as follows: the second computing vertex receives the second flag information sent by the first computing vertex, the second flag information being used to indicate the existence of unsent path information; after receiving the second flag information, the second computing vertex sends the first flag information to the first computing vertex.

[0187] It should be noted that the above Figure 5 or Figure 9 or Figure 11 The illustrated embodiment only describes the computational logic of the first and second computational vertices in two iterations. In practical applications, when determining the shortest path between computational vertices in a graph, each computational vertex can perform the above-described operation. Figure 5 or Figure 9 or Figure 11 The illustrated method continues until all computation vertices enter an inactive state, then the known shortest path stored by each computation vertex with itself as the destination is taken as the shortest path between computation vertices in the graph.

[0188] It should also be noted that the above Figure 5 or Figure 9 or Figure 11 The execution order of each step in the illustrated embodiment can be configured according to actual needs. Figure 5 or Figure 9 or Figure 11 This only illustrates one possible execution order and does not constitute a specific limitation.

[0189] The following example, using the configuration of K=1 to find the shortest path across multiple sources, illustrates the solution provided in this application.

[0190] exist Figure 6 In the schematic directed graph, in the initial state, all computation vertices are active.

[0191] In the first iteration, each computation vertex sends its path information (the weight of the edge between itself and its neighboring downstream computation vertex) to its adjacent downstream computation vertex. Computation vertex A sends A->X(5) to computation vertex X, computation vertex B sends B->X(3) to computation vertex X, and computation vertex X sends X->Y(6) to computation vertex Y. The information sent by each computation vertex during the first iteration, and the path information stored in each computation vertex after the first iteration, are as follows: Figure 12 As shown.

[0192] In the second iteration, the computation logic for each vertex is as follows:

[0193] Vertex X receives two path information A->X(5) and B->X(3). Vertex X sends a first flag to vertex A and to vertex B. Based on the received path information, vertex X determines two first path information to vertex Y: {A->X(5), X->Y(6)} and {B->X(3), X->Y(6)}. According to the constraint K, vertex X sends only one path information {A->X(5), X->Y(6)} to vertex Y. Since vertex X receives path information in this iteration, it remains active.

[0194] Vertex Y receives a path information X->Y(6) and sends its first flag information to vertex X. Since vertex Y has no adjacent downstream vertices, it stores the received path information X->Y(6) as the shortest path from X to Y. Because vertex Y receives path information in this iteration, it remains active.

[0195] Both computational vertex A and computational vertex B receive the first tag information sent by computational vertex X and remain active based on the first tag information.

[0196] During the second iteration, the information sent by each computation vertex, and the path information stored in each computation vertex after the second iteration, are as follows: Figure 13 As shown.

[0197] In the third iteration, the computation logic for each vertex is as follows:

[0198] Vertex X receives the first flag information sent by vertex Y and remains active according to the first flag information. Vertex X sends a path information {B->X(3), X->Y(6)} to vertex Y according to the constraint of K.

[0199] Vertex Y receives a path information {A->X(5), X->Y(6)} and sends the first flag information to vertex X. Since vertex Y has no adjacent downstream vertices, the received path information is merged into A->X->Y(11) and stored as the shortest path from A to Y. Because vertex Y receives path information in this iteration, it remains active.

[0200] Vertex A and vertex B received no information and entered an inactive state in the third iteration.

[0201] During the third iteration, the information sent by each computation vertex, and the path information stored in each computation vertex after the third iteration, are as follows: Figure 14 As shown.

[0202] In the fourth iteration, the computation logic for each vertex is as follows:

[0203] Vertex X receives the first flag information sent by vertex Y and remains active based on the first flag information. Since there is no unsent path information in vertex X, vertex X does not send any path information.

[0204] Vertex Y receives a path information {B->X(3), X->Y(6)} and sends the first flag information to vertex X. Since vertex Y has no adjacent downstream vertices, the received path information is merged into B->X->Y(9) and stored as the shortest path from vertex B to vertex Y. Because vertex Y receives path information in this iteration, it remains active.

[0205] Vertex A and vertex B remain inactive.

[0206] During the fourth iteration, the information sent by each computation vertex, and the path information stored in each computation vertex after the fourth iteration, are as follows: Figure 15 As shown.

[0207] In the fifth iteration, the computation logic for each vertex is as follows:

[0208] Vertex X receives the first flag information sent by vertex Y and remains active based on the first flag information. Since there is no unsent path information in vertex X, vertex X does not send any path information.

[0209] Vertex Y has not received any messages and has entered an inactive state.

[0210] Vertex A and vertex B remain inactive.

[0211] In the sixth iteration, the computation logic for each vertex is as follows: Vertex X receives no message and enters an inactive state. Vertices Y, A, and B remain inactive.

[0212] After the sixth iteration, all computation vertices enter an inactive state, ending the iteration. The shortest paths stored in each computation vertex (A->X(5), B->X(3), A->X->Y(11), A->X->Y(11)) are then used as... Figure 6 Calculate the shortest path between vertices in the illustrated directed graph.

[0213] The above content mainly introduces the solution provided by the embodiments of the present invention from the perspective of the working principle of the device. It is understood that computing devices, etc., include hardware structures and / or software modules corresponding to the execution of each function in order to achieve the above functions. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0214] This application embodiment can divide the device for sending path information provided in this application into functional modules based on the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. The module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0215] When dividing each function into modules according to its corresponding function. Figure 16A possible structural schematic diagram of a device for transmitting path information deployed in the computing device involved in the above embodiments is shown. This device 160 for transmitting path information can be a functional module or a chip, and it is used to perform the functions of the first computing vertex described in the above embodiments. Figure 16 As shown, the device 160 for sending path information may include: a sending unit 1601 and a first determining unit 1602. The sending unit 1601 is used to perform... Figure 5 or Figure 9 In processes S501, S502, or Figure 9 In step S503, the first determining unit 1602 is used to determine whether there is any unsent first path information after the sending unit 1601 sends K pieces of first path information to the second computing vertex. All relevant content of each step involved in the above method embodiment can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0216] Furthermore, such as Figure 17 As shown, the device 160 for sending path information may further include an acquisition unit 1603 and a second determination unit 1604. The acquisition unit 1603 is used to acquire the number of currently stored first path information of the first computation vertex and the number of downstream computation vertices adjacent to the first computation vertex. The second determination unit 1604 is used to determine K based on the number of currently stored first path information of the first computation vertex and the number of downstream computation vertices adjacent to the first computation vertex.

[0217] Alternatively, the acquisition unit 1603 is used to acquire the memory operating parameters of the computing device to which the first computing vertex belongs; the memory operating parameters are used to indicate the memory usage of the computing device. The second determination unit 1604 is used to determine K based on the memory operating parameters.

[0218] Furthermore, such as Figure 17 As shown, the device 160 for sending path information may further include a receiving unit 1605. The receiving unit 1605 is configured to receive first flag information sent by the second computing vertex after sending K pieces of first path information to the second computing vertex. The first flag information is used to instruct the first computing vertex to remain active.

[0219] When dividing each function into modules according to its corresponding function. Figure 18 This diagram illustrates another possible structural schematic of a device for receiving path information deployed in the computing device involved in the above embodiments. This path information receiving device 180 can be a functional module or a chip, and it is used to perform the functions of the second computing vertex described in the above embodiments. Figure 18As shown, the device 180 for receiving path information may include: a receiving unit 1801 and a sending unit 1802. The receiving unit 1801 is used to perform... Figure 11 The process S1101; the sending unit 1802 is used to execute Figure 11 The process S1102 is described above. All relevant content regarding each step in the above method embodiment can be found in the functional descriptions of the corresponding functional modules, and will not be repeated here.

[0220] When using integrated units, Figure 19 A possible structural diagram of the computing device involved in the above embodiments is shown. The computing device 190 may include: a processing module 1901 and a communication module 1902. The processing module 1901 is used to control and manage the operation of the computing device, and the communication module 1902 is used to communicate with other devices. For example, the processing module 1901 is used to execute... Figure 5 or Figure 9 In processes S501, S502, or Figure 9 S503 in, or Figure 11 The process is S1101 or S112. The computing device 190 may also include a storage module 1903 for storing the program code and data of the computing device 190.

[0221] Among them, the processing module 1901 can be Figure 3 The processor 301 in the physical structure of the server shown can be a processor or a controller. For example, it can be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processing module 1901 can also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc. The communication module 1902 can be... Figure 3 The transceiver 303 and communication module 1902 in the physical structure of the server 30 shown can be a communication port, or a transceiver, transceiver circuit, or communication interface, etc. Alternatively, the aforementioned communication interface can achieve communication with other devices through the aforementioned transceiver components. The aforementioned transceiver components can be implemented by antennas and / or radio frequency devices. The storage module 1903 can be... Figure 3 The memory 302 in the physical structure of the server 30 shown.

[0222] As mentioned above, the device 160 for sending path information, the device 180 for receiving path information, or the computing device 190 provided in the embodiments of this application can be used to implement the corresponding functions in the methods implemented in the embodiments of this application. For ease of explanation, only the parts related to the embodiments of this application are shown. For specific technical details not disclosed, please refer to the embodiments of this application.

[0223] As another embodiment of this invention, a computer-readable storage medium is provided, on which instructions are stored, which, when executed, perform the method for sending path information in the above method embodiments, or perform the method for receiving path information in the above method embodiments.

[0224] As another form of this embodiment, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to execute the method for sending path information in the above method embodiment, or to execute the method for receiving path information in the above method embodiment.

[0225] This application provides another chip system, which includes a processor for implementing the technical methods of the embodiments of the present invention. In one possible design, the chip system further includes a memory for storing program instructions and / or data necessary for the embodiments of the present invention. In another possible design, the chip system further includes a memory for the processor to call application code stored in the memory. This chip system may be composed of one or more chips, or may include chips and other discrete devices; this application does not specifically limit this.

[0226] The steps of the methods or algorithms described in this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in RAM, flash memory, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, read-only optical discs (CD-ROMs), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a core network interface device. Of course, the processor and storage medium can also exist as discrete components in the core network interface device. Alternatively, the memory can be coupled to the processor; for example, the memory can exist independently and be connected to the processor via a bus. The memory can also be integrated with the processor. The memory can be used to store application code that executes the technical solutions provided in the embodiments of this application, and its execution is controlled by the processor. The processor is used to execute application code stored in memory, thereby implementing the technical solutions provided in the embodiments of this application.

[0227] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0228] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0229] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0230] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0231] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of this application embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0232] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for sending path information, characterized in that, The method is applied to a graph computing architecture, which includes a server for performing graph computation and storage; the method includes: Obtain the number of first path information currently stored in the first computing vertex and the number of downstream computing vertices adjacent to the first computing vertex; K is determined based on the number of first path information currently stored in the first computing vertex and the number of downstream computing vertices adjacent to the first computing vertex; wherein, K is proportional to the number of first path information currently stored in the first computing vertex, and / or K is proportional to the number of downstream computing vertices adjacent to the first computing vertex; In the t-th iteration, the first computation vertex sends the K first path information to the second computation vertex, where K is the upper limit of the number of first path information that the first computation vertex is allowed to send in the t-th iteration; the second computation vertex is the downstream computation vertex adjacent to the first computation vertex; the first path information is used to indicate the known shortest path from the first computation vertex to the second computation vertex; where t and K are both positive integers. After sending K first path information to the second computing vertex, if the first computing vertex determines that there is unsent first path information, the first computing vertex sends the remaining first path information to the second computing vertex in subsequent iterations.

2. The method according to claim 1, characterized in that, In subsequent iterations, the first computation vertex sends the remaining first path information to the second computation vertex, further including: If the number of remaining first path information is greater than K, then it is sent through at least two iterations; If the remaining number of the first path information is less than or equal to K, it is sent in one iteration.

3. The method according to claim 1 or 2, characterized in that, After the first computing vertex sends K pieces of first path information to the second computing vertex, if the first computing vertex determines that there is unsent first path information, the first computing vertex sends the remaining first path information to the second computing vertex in subsequent iterations, including: After sending K first path information to the second computing vertex, the first computing vertex receives first flag information sent by the second computing vertex. The first flag information is used to indicate that the first computing vertex remains active. When the first computation vertex is active, the remaining first path information is sent to the second computation vertex in subsequent iterations.

4. The method according to claim 3, characterized in that, The method further includes: After sending less than or equal to K first path information to the second computing vertex, if the first computing vertex does not receive the first flag information sent by the second computing vertex, the first computing vertex enters an inactive state.

5. The method according to claim 1 or 2, characterized in that, After sending K pieces of first path information to the second computation vertex, if the first computation vertex determines that there is unsent first path information, the first computation vertex sends the remaining first path information to the second computation vertex in subsequent iterations, including: After sending K first path information to the second computing vertex, if the first computing vertex determines that there is unsent first path information, the first computing vertex sends second flag information to the second computing vertex. The second flag information is used to indicate that there is unsent path information. The first computing vertex receives first flag information sent by the second computing vertex. The first flag information is used to instruct the receiver to remain active. When the first computing vertex is active, it sends the remaining first path information to the second computing vertex in subsequent iterations. The first flag information is sent by the second computing vertex according to the second flag information.

6. The method according to any one of claims 1, 2, or 4, characterized in that, The first computing vertex sends K first path information to the second computing vertex, including: If the first path information stored in the first computing vertex is greater than or equal to K, send K pieces of the first path information to the second computing vertex. If the number of first path information items stored in the first computing vertex is less than K, then all the stored first path information items are sent to the second computing vertex.

7. The method according to any one of claims 1, 2, or 4, characterized in that, The first path information includes the known shortest path to the first computation vertex, and the weights of the edges between the first computation vertex and the second computation vertex.

8. A method for receiving path information, characterized in that, The method is applied to a graph computing architecture, which includes a server for performing graph computation and storage; the method includes: In the (t+1)th iteration, the second computation vertex receives K first path information messages sent by the first computation vertex; the first computation vertex is an upstream computation vertex adjacent to the second computation vertex, and K is the upper limit of the number of first path information messages that the first computation vertex is allowed to send in the tth iteration. K is determined based on the number of first path information messages currently stored by the first computation vertex and the number of downstream computation vertices adjacent to the first computation vertex; K is proportional to the number of first path information messages currently stored by the first computation vertex, and / or K is proportional to the number of downstream computation vertices adjacent to the first computation vertex; the first path information is used to indicate the known shortest path from the first computation vertex to the second computation vertex; wherein, t and K are both positive integers; The second computing vertex sends a first flag information to the first computing vertex. The first flag information is used to instruct the first computing vertex to remain active, so that the first computing vertex sends the remaining first path information to the second computing vertex in subsequent iterations.

9. The method according to claim 8, characterized in that, The second computing vertex sends first flag information to the first computing vertex, including: The second computing vertex receives second flag information sent by the first computing vertex, the second flag information being used to indicate the existence of unsent path information; After receiving the second flag information, the second computing vertex sends the first flag information to the first computing vertex.

10. A method for sending path information, characterized in that, The method is applied to a graph computing architecture, which includes a server for performing graph computation and storage; the method includes: Obtain the number of first path information currently stored in the first computing vertex and the number of downstream computing vertices adjacent to the first computing vertex; K is determined based on the number of first path information currently stored in the first computing vertex and the number of downstream computing vertices adjacent to the first computing vertex; wherein, K is proportional to the number of first path information currently stored in the first computing vertex, and / or K is proportional to the number of downstream computing vertices adjacent to the first computing vertex; In the t-th iteration, the first computation vertex sends K first path information to the second computation vertex, where K is the upper limit of the number of first path information that the first computation vertex is allowed to send in the t-th iteration; the second computation vertex is the downstream computation vertex adjacent to the first computation vertex, and the first path information is used to indicate the known shortest path from the first computation vertex to the second computation vertex; where t and K are both positive integers; In the (t+1)th iteration, the second computing vertex receives K pieces of the first path information sent by the first computing vertex; the second computing vertex sends first flag information to the first computing vertex, the first flag information being used to indicate that the first computing vertex remains active; In the (t+2)th iteration, the first computing vertex receives the first flag information sent by the second computing vertex. The first computing vertex remains active in subsequent iterations and sends the remaining first path information to the second computing vertex while in the active state.

11. A computing device, characterized in that, The computing device is configured with the first computing vertex and / or the second computing vertex as described in any one of claims 1-10, and when the computing device is running, the computing device is used to perform the method as described in any one of claims 1-10.

12. A system for sending path information, characterized in that, Includes the computing device as described in claim 11.

13. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on a computer, cause the computer to perform the method of sending path information as described in any one of claims 1-7 or 10, or to perform the method of receiving path information as described in claim 8 or 9.

Images