Semiconductor memory device

Abstract

A semiconductor storage device includes a memory string, a first wiring electrically connected to the memory string, a second wiring electrically connected to the first wiring, a transistor electrically connected between the first wiring and the second wiring, and a third wiring commonly connected to gate electrodes of the transistor. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wiring. The semiconductor storage device performs a first read operation in response to input of a first command set, and performs a second read operation in response to input of a second command set. A first voltage that turns on the transistor is applied to the third wiring from an end of the first read operation to a start of the second read operation.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims the benefit of Japanese Patent Application No. 2021-080885, filed on May 12, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein generally relate to semiconductor memory devices. Background Technology

[0004] A semiconductor memory device is known, comprising a memory string and a plurality of first wirings electrically connected to the memory string. The memory string includes a plurality of memory transistors connected in series, and the gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings. Summary of the Invention

[0005] A semiconductor memory device according to one embodiment includes a memory string, a plurality of first wirings electrically connected to the memory string, a plurality of second wirings electrically connected to the plurality of first wirings, a plurality of transistors electrically connected between the plurality of first wirings and the plurality of second wirings, and a third wiring commonly connected to the gate electrodes of the plurality of transistors. The memory string includes a plurality of memory transistors connected in series. The gate electrodes of the plurality of memory transistors are connected to the plurality of first wirings. The semiconductor memory device performs a first read operation in response to input of a first set of commands, and performs a second read operation in response to input of a second set of commands. From the end of the first read operation to the start of the second read operation, a first voltage that turns on the plurality of transistors is applied to the third wiring.

[0006] According to an embodiment, at least one of the operating current and time required for a read operation can be reduced. Attached Figure Description

[0007] Figure 1 This is a schematic block diagram illustrating the configuration of the storage system 10 according to the first embodiment;

[0008] Figure 2 This is a schematic side view illustrating an exemplary configuration of the storage system 10;

[0009] Figure 3 This is a schematic plan view illustrating an exemplary configuration of the storage system 10;

[0010] Figure 4 This is a schematic block diagram illustrating the configuration of the memory die MD according to the first embodiment;

[0011] Figure 5 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0012] Figure 6 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0013] Figure 7 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0014] Figure 8 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0015] Figure 9 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0016] Figure 10 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0017] Figure 11 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD;

[0018] Figure 12 This is a schematic plan view of a memory die (MD).

[0019] Figure 13 This is a schematic perspective view of a memory die (MD).

[0020] Figure 14 It is by Figure 12 A schematic enlarged view of the portion indicated by A in the diagram;

[0021] Figure 15 It is by Figure 13 A schematic enlarged view of the portion indicated by A in the diagram;

[0022] Figure 16A It is a schematic histogram used to describe the threshold voltage of the memory cell MC that stores 3 bits of data;

[0023] Figure 16B This is a table illustrating an exemplary relationship between the threshold voltage of the storage cell MC that stores 3 bits of data and the data stored.

[0024] Figure 16C This is another exemplary table showing the threshold voltage of the storage cell MC that stores 3 bits of data and the data stored therein;

[0025] Figure 17 It is a timing diagram used to describe the read operation;

[0026] Figure 18 It is a schematic cross-sectional view used to describe the read operation;

[0027] Figure 19 It is a timing diagram used to describe the read operation;

[0028] Figure 20 It is a schematic timing diagram used to describe the reading standby mode according to the first embodiment;

[0029] Figure 21 It is a schematic timing diagram used to describe the reading standby mode according to the first embodiment;

[0030] Figure 22 It is a schematic timing diagram used to describe the operating current of the memory die MD;

[0031] Figure 23 It is a schematic timing diagram used to describe the operating current of the memory die MD;

[0032] Figure 24 It is a schematic timing diagram used to describe the operating current of the memory die MD;

[0033] Figure 25 It is a schematic timing diagram used to describe the method for reading the standby mode settings;

[0034] Figure 26 It is a schematic timing diagram used to describe the method for reading the standby mode settings;

[0035] Figure 27 This is a schematic timing diagram used to describe the read standby mode according to the second embodiment; and

[0036] Figure 28 This is a schematic timing diagram used to describe the read standby mode according to the third embodiment. Detailed Implementation

[0037] The semiconductor memory device according to embodiments will now be described in detail with reference to the accompanying drawings. The following embodiments are merely examples and are not intended to limit the scope of the invention. The following drawings are schematic, and for ease of description, some parts of the configuration, etc., are sometimes omitted. Common parts in various embodiments are given the same reference numerals, and their description may be omitted.

[0038] In this specification, when referring to "semiconductor memory device," it can mean a memory die and a memory system including the control die, such as memory chips, memory cards, and solid-state drives (SSDs). Furthermore, it can mean a configuration including host computers, such as smartphones, tablets, and personal computers.

[0039] In this specification, "control circuit" may refer to peripheral circuitry set in the memory die, such as a sequencer; it may refer to control die, control chip, etc. connected to the memory die; and it may refer to a configuration that includes both.

[0040] In this specification, when it is mentioned that the first configuration is "electrically connected" to the second configuration, the first configuration can be directly connected to the second configuration, or the first configuration can be connected to the second configuration via wiring, semiconductor elements, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even when the second transistor is in the off state.

[0041] In this specification, when it is mentioned that the first configuration is "connected" between the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0042] In this specification, when referring to a circuit or the like as "electrically conducting" two wirings, it may mean, for example, that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings and is turned on.

[0043] In this specification, the direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0044] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along the predetermined plane and intersecting the first direction may be referred to as a second direction, and a direction intersecting the predetermined plane may be referred to as a third direction. Each of these first, second, and third directions may correspond to any one of the X, Y, and Z directions, and they need not correspond to any of these directions.

[0045] In this specification, terms such as "above" and "below" are based on the substrate. For example, the direction away from the substrate along the Z-direction is called "above," and the direction closer to the substrate along the Z-direction is called "below." The lower surface and lower end of a configuration refer to the surface and end on the substrate side of that configuration. The upper surface and upper end of a configuration refer to the surface and end on the side opposite to the substrate of that configuration. Surfaces intersecting the X-direction or Y-direction are called side surfaces, etc.

[0046] [First Embodiment]

[0047] [Storage System 10]

[0048] Figure 1 This is a schematic block diagram illustrating the configuration of the storage system 10 according to the first embodiment.

[0049] Storage system 10 reads, writes, and erases user data, for example, in response to signals sent from host computer 20. Storage system 10 is, for example, any system capable of storing user data, including memory chips, memory cards, and SSDs. Storage system 10 includes multiple memory dies (MD) and control dies (CD).

[0050] The storage die (MD) stores user data. The storage die (MD) comprises multiple storage blocks (BLKs). Each storage block (BLK) comprises multiple page pairs (PGs). The storage block (BLK) can be the unit of execution for erase operations. Each page (PG) can be the unit of execution for read and write operations.

[0051] like Figure 1 As shown, the control die CD is connected to multiple memory dies MD and a host computer 20. The control die CD includes, for example, a logic-to-physical translation table 21, a file allocation table (FAT) 22, an erase counter holding unit 23, an ECC circuit 24, and a microprocessor unit (MPU) 25.

[0052] The logical-to-physical translation table 21 associates the logical addresses received from the host computer 20 with the physical addresses of the pages PG allocated to the memory die MD, and maintains them. The logical-to-physical translation table 21 is implemented, for example, by random access memory (RAM) (not shown).

[0053] FAT 22 maintains FAT information indicating the status of the corresponding page PG. This FAT information includes, for example, information indicating "valid," "invalid," and "erased." For example, a "valid" page PG stores valid data read in response to an instruction from host computer 20. An "invalid" page PG stores invalid data that was not read in response to an instruction from host computer 20. An "erased" page PG does not store any data after an erase operation is performed. FAT 22 is implemented, for example, using RAM (not shown).

[0054] The erase count holding unit 23 associates and holds the physical address corresponding to the memory block BLK with the count of erase operations performed on the memory block BLK. The erase count holding unit 23 is implemented, for example, by RAM (not shown).

[0055] ECC circuit 24 detects errors in the data read from the memory die MD and corrects the data when possible.

[0056] The MPU 25 references the logic-physical translation table 21, FAT 22, erase counter holding unit 23, and ECC circuit 24, and performs processes such as logical address to physical address conversion, bit error detection / correction, garbage collection (compacting), and wear leveling.

[0057] Figure 2This is a schematic side view illustrating an exemplary configuration of the storage system 10 according to an embodiment. Figure 3 This is a schematic floor plan illustrating an exemplary configuration. For ease of description, Figure 2 and Figure 3 A portion of the configuration has been omitted.

[0058] like Figure 2 As shown, the storage system 10 according to an embodiment includes a mounting substrate (MSB), a plurality of memory dies (MDs), and a control die (CD). Pad electrodes P are disposed on the upper surface of the mounting substrate (MSB) in the region of its end in the Y direction. Regions of the upper surface of the mounting substrate (MSB) excluding the end in the Y direction are bonded to the lower surface of the memory die (MD) via an adhesive or the like. The plurality of memory dies (MDs) are stacked on the mounting substrate (MSB). Pad electrodes P are disposed on the upper surface of the memory die (MD) in the region of its end in the Y direction. Regions of the upper surface of the memory die (MD) excluding the end in the Y direction are bonded to the lower surface of another memory die (MD) or control die (CD) via an adhesive or the like. Control dies (CDs) are stacked on the memory dies (MDs). Pad electrodes P are disposed on the upper surface of the control die (CD) in the region of its end in the Y direction.

[0059] like Figure 3 As shown, each of the mounting substrate MSB, multiple memory dies MD, and control die CD includes multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P disposed to each of the mounting substrate MSB, multiple memory dies MD, and control die CD are interconnected via bonding wires B.

[0060] Notice, Figure 2 and Figure 3 The configurations shown are merely examples, and specific configurations can be adjusted as appropriate. For example, in Figure 2 and Figure 3 In the example shown, the control die CD is stacked on top of multiple memory dies MD. The memory dies MD and the control die CD are connected via bonding wire B. Multiple memory dies MD and control die CD are included in a single package. However, the control die CD can be included in a different package than the memory dies MD. Furthermore, multiple memory dies MD and control die CD can be connected to each other via electrodes or the like instead of bonding wire B.

[0061] [Circuit configuration of memory die MD]

[0062] Figure 4 This is a schematic block diagram illustrating the configuration of the memory die MD according to the first embodiment. Figures 5 to 11 This is a schematic circuit diagram showing a portion of the configuration of a memory die MD.

[0063] Figure 4Multiple control terminals are shown. In some cases, these multiple control terminals are indicated as control terminals corresponding to a high activation signal (positive logic signal). In some cases, these multiple control terminals are indicated as control terminals corresponding to a low activation signal (negative logic signal). In some cases, these multiple control terminals are indicated as control terminals corresponding to both a high activation signal and a low activation signal. Figure 4 In this specification, the reference symbol for the control terminal corresponding to the low activation signal includes an overline. In this specification, the reference symbol for the control terminal corresponding to the low activation signal includes a forward slash (" / "). Figure 4 The description is illustrative, and certain aspects are subject to adjustment. For example, a portion or all of a high activation signal may be changed to a low activation signal, or a portion or all of a low activation signal may be changed to a high activation signal.

[0064] like Figure 4 As shown, the memory die MD includes a memory cell array MCA and peripheral circuitry PC. The peripheral circuitry PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. The peripheral circuitry PC also includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. Finally, the peripheral circuitry PC includes input / output control circuitry I / O and logic circuitry CTR.

[0065] [Circuit configuration of the memory cell array (MCA)]

[0066] like Figure 5 As shown, the memory cell array MCA includes multiple memory blocks BLK as described above. Each of these multiple memory blocks BLK includes multiple string cells SU. Each of these multiple string cells SU includes multiple memory strings MS. Each of these multiple memory strings SM has one end connected to the peripheral circuit PC via a bit line BL. Each of these multiple memory strings MS has the other end connected to the peripheral circuit PC via a common source line SL.

[0067] The memory string (MS) comprises a drain-side select transistor (STD), multiple memory cells (MCs) (memory transistors), a source-side select transistor (STS), and a source-side select transistor (STSb). The STD, MCs, STS, and STSb are connected in series between the bit line BL and the source line SL. In the following text, in some cases, the STD, STS, and STSb will be simply referred to as the select transistors (STD, STS, STSb).

[0068] A memory cell MC is a field-effect transistor. A memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer serves as the channel region. The gate insulating film includes a charge accumulation film. The memory cell MC has a threshold voltage that varies corresponding to the amount of charge in the charge accumulation film. A memory cell MC stores one or more bits of data. The gate electrodes of multiple memory cells MC corresponding to a memory string MS are connected to corresponding word lines WL. Each of these word lines WL is collectively connected to all memory strings MS in a memory block BLK.

[0069] The select transistors (STD, STS, STSb) are field-effect transistors. Each select transistor (STD, STS, STSb) includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer serves as the channel region. The gate electrodes of the select transistors (STD, STS, STSb) are respectively connected to select gate lines (SGD, SGS, SGSb). A drain-side select gate line SGD is commonly connected to all memory strings MS in a string cell SU. A source-side select gate line SGS is commonly connected to all memory strings MS in a memory block BLK. A source-side select gate line SGSb is commonly connected to all memory strings MS in a memory block BLK.

[0070] [Circuit configuration of voltage generation circuit VG]

[0071] For example, such as Figure 6 As shown, the voltage generation circuit VG( Figure 4 It includes multiple voltage generation units vg1 to vg3. During read, write, and erase operations, voltage generation units vg1 to vg3 generate a voltage of a predetermined amplitude, which is then transmitted via voltage supply line L. VG Output. For example, voltage generation unit vg1 outputs the program voltage used in the write operation. Voltage generation unit vg2 outputs the read voltage V, which will be described later in the read operation. READ Standby voltage V READ_WAIT The voltage generation unit VG2 outputs the write pass voltage used in the write operation. The voltage generation unit VG3 outputs the read voltage, which will be described later in the read operation. The voltage generation unit VG3 outputs the verification voltage, which will be described later in the write operation. For example, voltage generation units VG1 to VG3 can be boost circuits such as charge pump circuits, or buck circuits such as regulators. Each of these buck and boost circuits is connected to the voltage supply line L. P Voltage supply line L P A power supply voltage V is applied CC or ground voltage V SS ( Figure 4 These voltage supply lines L P For example, it is connected to a reference. Figure 2 and Figure 3 The pad electrode P is described. The operating voltage output from the voltage generation circuit VG is adjusted as needed based on the control signal from the sequencer SQC.

[0072] The charge pump circuit 32 in the voltage generation circuit VG Figure 7 This includes a voltage output circuit 32a, a voltage divider circuit 32b, and a comparator 32c. The voltage output circuit 32a supplies voltage to the voltage supply line L. VG Output voltage V OUT The voltage divider circuit 32b is connected to the voltage supply line L. VG Comparator 32c outputs a feedback signal FB to voltage output circuit 32a. This feedback signal FB is compared with the voltage V output from voltage divider circuit 32b. OUT 'With reference voltage V REF The magnitude relationships between them correspond.

[0073] like Figure 8 As shown, the voltage output circuit 32a includes multiple transistors 32a2a and 32a2b. These transistors 32a2a and 32a2b are alternately connected to the voltage supply line L. VG With voltage supply line L P Between. The voltage supply line L shown. P A power supply voltage V is applied CC Multiple transistors 32a2a and 32a2b connected in series have their gate electrodes connected to their respective drain electrodes and corresponding capacitors 32a3. The voltage output circuit 32a includes a circuit 32a4, a level shifter 32a5a, and a level shifter 32a5b. The clock signal CLK and feedback signal FB output by the circuit 32a4 are logically separated. The level shifter 32a5a boosts and outputs the output signal from the circuit 32a4. The level shifter 32a5a includes an output terminal connected to the gate electrode of transistor 32a2a via capacitor 32a3. The level shifter 32a5b boosts and outputs the inverted signal of the output signal from the circuit 32a4. The level shifter 32a5b includes an output terminal connected to the gate electrode of transistor 32a2b via capacitor 32a3.

[0074] When the feedback signal FB is in the "H" state, it corresponds to the output clock signal CLK of circuit 32a4. In response, electrons flow from the voltage supply line L... VG Transmitted to voltage supply line L P And the voltage supply line L VG The voltage increases. Simultaneously, when the feedback signal FB is in the "L" state, circuit 32a4 does not output the clock signal CLK. Therefore, the voltage supply line L... VG The voltage does not increase.

[0075] like Figure 7 As shown, the voltage divider circuit 32b includes a resistor element 32b2 and a variable resistor element 32b4. Resistor element 32b2 is connected to the voltage supply line L. VG Between the voltage divider terminal 32b1 and the voltage supply line L. A variable resistor element 32b4 is connected in series between the voltage divider terminal 32b1 and the voltage supply line L. P Between. Voltage supply line L P A ground voltage V is applied SS The variable resistor element 32b4 has a control signal V based on the operating voltage. CTRL The resistance value is adjustable. Therefore, the voltage V at the voltage divider terminal 32b1 is... OUT The amplitude is based on the operating voltage control signal V. CTRL Adjustable.

[0076] like Figure 9 As shown, the variable resistor element 32b4 includes multiple current paths 32b5. These multiple current paths 32b5 are connected in parallel between the voltage divider terminal 32b1 and the voltage supply line L. P Between. Multiple current paths 32b5, each including a resistor element 32b6 and a transistor 32b7 connected in series. The resistor element 32b6 disposed in the respective current path 32b5 can have different resistance values. Operating voltage control signal V CTRL Different bits are input to the gate electrode of the corresponding transistor 32b7. The variable resistor element 32b4 may include a current path 32b8 without transistor 32b7.

[0077] like Figure 7 As shown, comparator 32c outputs a feedback signal FB. For example, when the voltage V at voltage divider terminal 32b1... OUT 'Greater than the reference voltage V' REF When this happens, the feedback signal FB changes to the "L" state. For example, when the voltage V... OUT Less than the reference voltage V REF At that time, the feedback signal FB changes to the "H" state.

[0078] [Circuit configuration of line decoder RD]

[0079] For example, such as Figure 6 As shown, the line decoder RD includes the block decoder BLKD, the word line decoder WLD, the driver circuit DRV, and the address decoder (not shown).

[0080] The block decoder BLKD comprises multiple block decoding units (blkd). These multiple block decoding units (blkd) correspond to multiple memory blocks (BLK) in the memory cell array (MCA). Each block decoding unit (blkd) comprises multiple transistors (T). BLK Multiple transistors TBLK This corresponds to multiple word lines WL in the memory block BLK. Transistor T BLK For example, a field-effect NMOS transistor. Transistor T BLK This includes the drain electrode connected to the word line WL. Transistor T BLK This includes the source electrode connected to the wiring CG. The wiring CG is connected to all block decoding units (blkd) in the block decoder (BLKD). Transistor T BLK This includes the gate electrode connected to the signal line BLKSEL. Multiple signal lines BLKSEL are configured corresponding to all block decoding units (blkd). The signal lines BLKSEL are connected to all transistors T in the block decoding unit (blkd). BLK .

[0081] In read operations, write operations, etc., for example, with the address register ADR ( Figure 4 In the block address, the voltage of one BLKSEL signal line becomes "H", and the voltages of other BLKSEL signal lines become "L". For example, one BLKSEL signal line is applied with a predetermined drive voltage of positive amplitude, while other BLKSEL signal lines are applied with a ground voltage V. SS Therefore, all word lines (WL) in one memory block (BLK) corresponding to this block address are conductive for all routing (CG). All word lines (WL) in other memory blocks (BLK) become floating.

[0082] The word line decoder (WLD) comprises multiple word line decoding units (wld). These multiple wld units correspond to multiple memory cells (MC) in the memory string (MS). In the example shown, the word line decoding unit wld includes two transistors T. WLS T WLU Transistor T WLS T WLU For example, a field-effect NMOS transistor. Transistor T WLS T WLU This includes the drain electrode connected to the wiring CG. Transistor T WLS Including those connected to the wiring CG S The source electrode. Transistor T WLU Including those connected to the wiring CG U The source electrode. Transistor T WLS Including those connected to the signal line WLSEL S The gate electrode of the transistor T. WLU Including those connected to the signal line WLSEL U The gate electrode. Multiple signal lines WLSEL S With a transistor T included in all word line decoding units wld WLSCorrespondingly configured. Multiple signal lines WLSEL U With other transistors T included in all word line decoding units wld WLU The corresponding settings are configured.

[0083] In read operations, write operations, etc., for example, with the address register ADR ( Figure 4 The signal line WLSEL corresponding to the word line decoding unit wld of the page address in ) S The voltage changes to the "H" state, and the corresponding signal line WLSEL U The voltage changes to the "L" state. The signal line WLSEL, corresponding to the other word line decoding units wld, is... S The voltage changes to the "L" state, and the corresponding signal lines WLSEL U The voltage changes to the "H" state. Wiring CG S The WL line is applied to the selected word line. S Corresponding voltage. Wiring CG U The word line WL is applied with the unselected word line. U The corresponding voltage. Therefore, a word line WL corresponding to the page address is applied with the voltage equal to the selected word line WL. S The corresponding voltage. Other word lines WL are applied with the same voltage as the unselected word lines WL. U The corresponding voltage.

[0084] The drive circuit DRV includes, for example, six transistors T DRV1 To T DRV6 Transistor T DRV1 To T DRV6 For example, a field-effect NMOS transistor. Transistor T DRV1 To T DRV4 Including those connected to the wiring CG S The drain electrode. Transistor T DRV5 T DRV6 Including those connected to the wiring CG U The drain electrode. Transistor T DRV1 Including via voltage supply line L VG1 The source electrode is connected to the output terminal of the voltage generation unit vg1. Transistor T DRV2 T DRV5 Including via voltage supply line L VG2 The source electrode is connected to the output terminal of the voltage generation unit vg2. Transistor T DRV3 Including via voltage supply line L VG3 The source electrode is connected to the output terminal of the voltage generation unit vg3. Transistor T DRV4 T DRV6 Including via voltage supply line LP Connected to reference Figure 2 and Figure 3 The source electrode of the pad electrode P is described. Transistor T DRV1 To T DRV6 This includes gate electrodes that are connected to signal lines VSEL1 through VSEL6 respectively.

[0085] In read operations, write operations, etc., for example, with wiring CG S One of the voltages on the corresponding signal lines VSEL1 to VSEL4 changes to the "H" state, while the others change to the "L" state. (This is related to the wiring CG.) U One of the voltages on the corresponding two signal lines VSEL5 and VSEL6 becomes "H" and the other becomes "L".

[0086] Address decoder (not shown), for example, based on the sequencer SQC ( Figure 4 The control signals are sequentially referenced to the address register ADR. Figure 4 The row address RA is the address of the page. The row address RA includes the block address and page address described above. The address decoder control signal lines BLKSEL and WLSEL are also included. S and WLSEL U The voltage is in either the "H" or "L" state.

[0087] exist Figure 6 In the example, the row decoder RD includes one block decoding unit blkd for each storage block BLK. However, this configuration can be changed as needed. For example, one block decoding unit blkd can be set for two or more storage block BLKs.

[0088] [Circuit configuration of the Sensing Amplifier Module (SAM)]

[0089] For example, such as Figure 10 As shown, the sensing amplifier module SAM ( Figure 4 This includes multiple sense amplifier units (SAUs). Each sense amplifier unit (SAU) corresponds to multiple bit lines (BLs). Each sense amplifier unit (SAU) includes a sense amplifier (SA), wiring (LBUS), latch circuitry (SDL), and DL0 to DLn. L (n L (It is a natural number). The wiring LBUS is connected to the charging transistor 55 ( Figure 11 (This is used for pre-charging.) The wiring LBUS is connected to the wiring DBUS via a switching transistor DSW.

[0090] like Figure 11As shown, the sensing amplifier SA includes a sensing transistor 41. The sensing transistor 41 discharges the charge in the wiring LBUS according to the current flowing in the bit line BL. The source electrode of the sensing transistor 41 is connected to a voltage V applied to ground. SS The voltage supply line is connected to the LBUS wiring via the switching transistor 42. The gate electrode of the sensing transistor 41 is connected to the bit line BL via the sensing node SEN, the discharge transistor 43, the node COM, the clamping transistor 44, and the high breakdown voltage transistor 45. The sensing node SEN is connected to the internal control signal line CLKSA via the capacitor 48.

[0091] The sensing amplifier SA includes a voltage transfer circuit. Based on data latched by the latching circuit SDL, the voltage transfer circuit selectively connects node COM and sensing node SEN to the applied voltage V. DD The voltage supply line or the voltage V applied to it SRC The voltage supply line is electrically connected. The voltage transmission circuit includes node N1, charging transistor 46, charging transistor 49, charging transistor 47, and discharging transistor 50. Charging transistor 46 is connected between node N1 and sensing node SEN. Charging transistor 49 is connected between node N1 and node COM. Charging transistor 47 is connected between node N1 and the applied voltage V. DD The discharge transistor 50 is connected between node N1 and the voltage supply line. SRC Between the voltage supply lines. The charging transistor 47 and the discharging transistor 50 include the gate electrode of the node INV_S of the latch circuit SDL, which is commonly connected.

[0092] Sensing transistor 41, switching transistor 42, discharging transistor 43, clamping transistor 44, charging transistor 46, charging transistor 49, and discharging transistor 50 are, for example, enhancement-mode NMOS transistors. High breakdown voltage transistor 45 is, for example, a depletion-mode NMOS transistor. Charging transistor 47 is, for example, a PMOS transistor.

[0093] Switching transistor 42 includes a gate electrode connected to signal line STB. Discharging transistor 43 includes a gate electrode connected to signal line XXL. Clamping transistor 44 includes a gate electrode connected to signal line BLC. High breakdown voltage transistor 45 includes a gate electrode connected to signal line BLS. Charging transistor 46 includes a gate electrode connected to signal line HLL. Charging transistor 49 includes a gate electrode connected to signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL, and BLX are connected to sequencer SQC.

[0094] The latch circuit SDL includes nodes LAT_S and INV_S, inverter 51, inverter 52, switching transistor 53, and switching transistor 54. Inverter 51 includes an output terminal connected to node LAT_S and an input terminal connected to node INV_S. Inverter 52 includes an input terminal connected to node LAT_S and an output terminal connected to node INV_S. Switching transistor 53 is disposed in the current path between node LAT_S and wiring LBUS. Switching transistor 54 is disposed in the current path between node INV_S and wiring LBUS. Switching transistors 53 and 54 are, for example, NMOS transistors. Switching transistor 53 includes a gate electrode connected to sequencer SQC via signal line STL. Switching transistor 54 includes a gate electrode connected to sequencer SQC via signal line STI.

[0095] Latch circuits DL0 to DLn L It is configured to be almost identical to the latch circuit SDL. However, as described above, node INV_S of the latch circuit SDL is electrically turned on for the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA. In this respect, latch circuits DL0 to DLn L Unlike the latch circuit SDL.

[0096] The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The switching transistor DSW includes a gate electrode connected to the sequencer SQC via the signal line DBS.

[0097] like Figure 10 As shown, each of the signal lines STB, HLL, XXL, BLX, BLC, and BLS described above is commonly connected to all the sense amplifier units SAU included in the sense amplifier module SAM. A voltage V is applied. DD The voltage supply line and the voltage V applied SRC Each of the voltage supply lines is commonly connected to all the sense amplifier units (SAUs) included in the sense amplifier module (SAM). Similarly, the signal lines STI and STL of the latch circuit SDL are also commonly connected to all the sense amplifier units (SAUs) included in the sense amplifier module (SAM). L The signal lines STI and STL correspond to the signal lines TI0 to TIn. L TL0 to TLn L Each of them is commonly connected to all the sense amplifier units (SAUs) included in the sense amplifier module (SAM). Simultaneously, multiple signal lines (DBS) are configured corresponding to all the respective sense amplifier units (SAUs) included in the sense amplifier module (SAM).

[0098] [Circuit configuration of cache memory CM]

[0099] Cache memory CM ( Figure 4 This includes multiple latching circuits. These multiple latching circuits are connected to the latching circuits in the sense amplifier module (SAM) via a DBUS wiring system. The data DAT contained in these multiple latching circuits is sequentially transmitted to the sense amplifier module (SAM) or the input / output control circuitry (I / O).

[0100] A decoding circuit and a switching circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA latched in the address register ADR. In response to the output signal of the decoding circuit, the switching circuit causes the latch circuit corresponding to the column address CA to switch with the bus DB. Figure 4 Electrical conduction.

[0101] [Circuit configuration of sequencer SQC]

[0102] According to the command data D latched in the command register CMR CMD Sequencer SQC ( Figure 4 The sequencer (SQC) outputs internal control signals to the line decoder (RD), sense amplifier module (SAM), and voltage generation circuit (VG). The sequencer (SQC) outputs status data (D) indicating its own status to the status register (STR) as needed. ST .

[0103] The sequencer SQC generates a ready / busy signal and outputs it to terminal RY / / BY. During the period when the voltage at terminal RY / / BY is in the "L" state (busy period), access to memory die MD is essentially disabled. During the period when the voltage at terminal RY / / BY is in the "H" state (ready period), access to memory die MD is enabled. Terminal RY / / BY is connected via, for example, a reference... Figure 2 and Figure 3 The pad electrode P described is used to achieve this.

[0104] [Circuit configuration of input / output control circuit (I / O)]

[0105] The input / output control circuitry (I / O) includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS and / DQS, multiple input circuits, multiple output circuits, a shift register, and a buffer circuit. Each of the multiple input circuits, multiple output circuits, shift register, and buffer circuit is connected to a power supply voltage V. CCQ and ground voltage V SS The terminals.

[0106] Data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, and the terminal to which the power supply voltage V is applied. CCQ The terminals are connected via, for example, a reference. Figure 2 and Figure 3 The described pad electrode P is used to implement this. In response to an internal control signal from the logic circuit CTR, data input via data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, address register ADR, or command register CMR. In response to an internal control signal from the logic circuit CTR, data output via data signal input / output terminals DQ0 to DQ7 is input from the cache memory CM or status register STR to the buffer circuit.

[0107] Multiple input circuits include, for example, comparators connected to any one of the data signal input / output terminals DQ0 to DQ7 or toggle signal input / output terminals DQS and / DQS. Multiple output circuits include, for example, off-chip driver (OCD) circuits connected to any one of the data signal input / output terminals DQ0 to DQ7 or toggle signal input / output terminals DQS and / DQS.

[0108] [Circuit configuration of the CTR logic circuit]

[0109] Logic circuit CTR ( Figure 4 The internal control signal is received from the control die CD via external control terminals / CEn, CLE, ALE, / WE, RE, / RE, and in response to the external control signal, the internal control signal is output to the input / output control circuit I / O. The external control terminals / CEn, CLE, ALE, / WE, RE, / RE are connected via, for example, a reference... Figure 2 and Figure 3 The pad electrode P described is used to achieve this.

[0110] [Structure of memory die MD]

[0111] Figure 12 This is a schematic plan view of a memory die (MD). Figure 13 This is a schematic perspective view of a memory die (MD). Figure 13 It is a schematic diagram used to describe the configuration of a memory die (MD) and does not indicate the specific number, shape, arrangement, etc. of the components. Figure 14 It is by Figure 12 A schematic enlarged view of the part indicated by A in the diagram. Figure 15 It is by Figure 13 A schematic enlarged view of the portion indicated by A in the diagram. Figure 14 In a portion of the region, the bit line BL is omitted. Figure 14In a portion of the region, the drain-side selected gate line (SGD) is omitted.

[0112] For example, such as Figure 12 As shown, the memory die MD includes a semiconductor substrate 100. In the example shown, the semiconductor substrate 100 includes four memory cell array regions R arranged in the X and Y directions. MCA .

[0113] For example, such as Figure 13 As shown, the memory die MD includes a semiconductor substrate 100 and a transistor layer L disposed on the semiconductor substrate 100. TR Set in transistor layer L TR The storage cell array layer L above MCA and those set in the memory cell array layer L MCA The wiring layer above (not shown).

[0114] [Structure of semiconductor substrate 100]

[0115] For example, the semiconductor substrate 100 is formed of P-type silicon (Si) containing P-type impurities (such as boron (B)). On the surface of the semiconductor substrate 100, an N-type well region containing N-type impurities (such as phosphorus (P)), a P-type well region containing P-type impurities (such as boron (B)), a semiconductor substrate region in which no N-type well region or P-type well region is provided, and an insulating region 100I are provided.

[0116] [Transistor layer L] TR [Structure]

[0117] For example, such as Figure 13 As shown, a wiring layer GC is disposed on the upper surface of a semiconductor substrate 100 via an insulating layer. The wiring layer GC includes a plurality of electrodes gc opposite to the surface of the semiconductor substrate 100. These plurality of electrodes gc respectively serve as gate electrodes of a plurality of transistors Tr constituting a peripheral circuit PC, electrodes of a plurality of capacitors, etc. These plurality of electrodes gc are connected to corresponding contacts CS. The contacts CS may include, for example, a stacked film of a barrier conductive film (such as titanium nitride (TiN)) and a metal film (such as tungsten (W)). These plurality of contacts CS are connected to a plurality of wirings included in wiring layers D0, D1, and D2. Each of these plurality of wirings may include, for example, a stacked film of a barrier conductive film (such as titanium nitride (TiN)) and a metal film (such as tungsten (W)).

[0118] [Storage cell array layer L] MCA [Structure]

[0119] For example, such as Figure 12 As shown, the storage cell array layer L MCA This includes multiple storage blocks (BLKs) arranged in the Y direction. For example... Figure 14 As shown, a memory block BLK includes, for example, multiple string cells SU arranged in the Y direction. Between two adjacent memory blocks BLK in the Y direction, an inter-block insulating layer ST, such as silicon dioxide (SiO2), is provided. For example, as... Figure 14 As shown, an inter-string insulating layer SHE, such as silicon dioxide (SiO2), is provided between two adjacent string units SU in the Y direction.

[0120] For example, such as Figure 13 As shown, the memory block BLK includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the corresponding plurality of semiconductor layers 120.

[0121] The conductive layer 110 is an approximately plate-shaped conductive layer extending in the X direction. The conductive layer 110 may comprise a stack of barrier conductive films (such as titanium nitride (TiN)) and metal films (such as tungsten (W)). For example, the conductive layer 110 may comprise polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon dioxide (SiO2), is disposed between corresponding adjacent conductive layers 110 arranged in the Z direction. Figure 15 A contact electrode CC extending in the Z direction is disposed at one end of the conductive layer 110 in the X direction.

[0122] For example, such as Figure 13 As shown, a conductive layer 111 is disposed below a conductive layer 110. For example, the conductive layer 111 may comprise polysilicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 is disposed between the conductive layer 111 and the conductive layer 110.

[0123] A conductive layer 112 is disposed beneath the conductive layer 111. The conductive layer 112 may comprise, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 112 may comprise, for example, a conductive layer of a metal (such as tungsten (W), tungsten silicide, etc.), or another conductive layer. An insulating layer 101 is disposed between the conductive layer 112 and the conductive layer 111.

[0124] Conductive layer 112 is used as source line SL ( Figure 5 The conductive layer 112 is, for example, commonly disposed in the memory cell array region R. MCA ( Figure 12 Between all storage blocks (BLK) in ).

[0125] Conductive layer 111 is used as the source-side selected gate line SGSb ( Figure 5) and the gate electrodes of multiple source-side selection transistors STSb connected thereto. Conductive layer 111 is electrically independent for each memory block BLK.

[0126] Among the multiple conductive layers 110, one or more conductive layers 110 located at the bottom layer serve as the source-side select gate line (SGS). Figure 5 ) and the gate electrodes of multiple source-side selection transistors (STS) connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0127] Multiple conductive layers 110 located above these conductive layers 110 serve as word lines WL ( Figure 5 ) and multiple storage units MC connected to it Figure 5 The gate electrode of the memory block BLK. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0128] One or more conductive layers 110 located above these conductive layers 110 serve as drain-side selected gate lines (SGD) and multiple drain-side selected transistors (STD) connected thereto. Figure 5 The gate electrode of the plurality of conductive layers 110. The width of these multiple conductive layers 110 in the Y direction is Y SGD The width Y in the Y direction is smaller than that of the other conductive layers 110. WL For example, such as Figure 14 As shown. Between two adjacent conductive layers 110 in the Y direction, an inter-cell insulating layer SHE as described above is provided, for example, as... Figure 14 As shown. These multiple conductive layers 110 are electrically independent for each string cell SU.

[0129] For example, such as Figure 14 As shown, semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions. Semiconductor layer 120 is used in a memory string MS ( Figure 5 The semiconductor layer 120 includes multiple memory cells MC and channel regions of selection transistors (STD, STS, STSb). The semiconductor layer 120 is, for example, a polycrystalline silicon (Si) semiconductor layer. For example, such as... Figure 13 As shown, the semiconductor layer 120 has an approximately cylindrical shape and includes an insulating layer 125 of silicon dioxide or the like in its central portion.

[0130] Semiconductor layer 120 has its outer peripheral surface each surrounded by a plurality of conductive layers 110 and 111, and is opposite to these conductive layers 110 and 111. Semiconductor layer 120 has a lower end connected to conductive layer 112. Semiconductor layer 120 has an upper end connected to bit line BL via contacts Ch and Vy. Bit line BL extends in the Y direction and is arranged in the X direction.

[0131] The gate insulating film 130 has an approximately cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as Figure 15 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge accumulation film 132, and a bulk insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are insulating films such as silicon dioxide (SiO2). The charge accumulation film 132 is a film such as silicon nitride (Si3N4) capable of accumulating charge. The tunnel insulating film 131, the charge accumulation film 132, and the bulk insulating film 133, which have an approximately cylindrical shape, extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction, excluding the contact portion between the semiconductor layer 120 and the conductive layer 112.

[0132] Figure 15 An example is shown where the gate insulating film 130 includes a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may include, for example, a floating gate of polysilicon containing N-type or P-type impurities.

[0133] [Threshold voltage of memory cell MC]

[0134] Next, we will refer to Figure 16A , Figure 16B and Figure 16C Describes the threshold voltage of the memory cell MC.

[0135] Figure 16A This is a schematic histogram used to describe the threshold voltage of the memory cell MC that stores 3 bits of data. The horizontal axis indicates the voltage of the word line WL, and the vertical axis indicates the number of memory cells MC. Figure 16B This is a table illustrating an exemplary relationship between the threshold voltage of a storage cell MC that stores 3 bits of data and the data stored. Figure 16C This is another exemplary table showing the threshold voltage of the storage cell MC that stores 3 bits of data and the data stored.

[0136] exist Figure 16A In the example, the threshold voltage of the memory cell MC is controlled in eight modes. The threshold voltage of the memory cell MC controlled in state Er is less than the erase verification voltage V. VFYEr For example, the threshold voltage of the memory cell MC controlled in state A is greater than the verification voltage V. VFYA And less than the verification voltage V VFYB Furthermore, for example, the threshold voltage of the memory cell MC controlled in state B is greater than the verification voltage V. VFYB And less than the verification voltage V VFYC Similarly, in the following text, the threshold voltage of the memory cell MC controlled in states C to F is greater than the verification voltage V. VFYC To the verification voltage VVFYF And less than the verification voltage V VFYD To the verification voltage V VFYG For example, the threshold voltage of the memory cell MC controlled in state G is greater than the verification voltage V. VFYG And less than the reading voltage V READ .

[0137] exist Figure 16A In the example, the voltage V is read CGAR It is set between the threshold distribution corresponding to state Er and the threshold distribution corresponding to state A. Read voltage V CGBR It is set between the threshold distribution corresponding to state A and the threshold distribution corresponding to state B. The same applies to the following, and the voltage V is read. CGCR To read voltage V CGGR They are respectively set between the threshold distribution corresponding to state B and the threshold distribution corresponding to state C, and between the threshold distribution corresponding to state F and the threshold distribution corresponding to state G.

[0138] For example, state Er corresponds to the lowest threshold voltage. The memory cell MC of state Er is, for example, a memory cell MC in an erased state. For example, the data "111" is assigned to the memory cell MC of state Er.

[0139] The threshold voltage corresponding to state A is higher than the threshold voltage corresponding to state Er. For example, the data "101" is assigned to the storage cell MC in state A.

[0140] The threshold voltage corresponding to state B is higher than the threshold voltage corresponding to state A. For example, the data "001" is assigned to the storage unit MC in state B.

[0141] Similarly, in the following text, the threshold voltages corresponding to states C through G in the diagram are higher than the threshold voltages corresponding to states B through F. For example, the data “011”, “010”, “110”, “100”, and “000” are assigned to the storage cells MC for these states.

[0142] In the configuration illustrated in Figure 16, the data of the lower-order bits can be read using a single read voltage V. CGDR Distinguishing between the two. The data for the intermediate-order bits can be read using three voltage V values. CGAR V CGCR V CGFR Distinguishing between them. Higher-order bits of data can be read using three voltage V. CGBR V CGER V CGGR distinguish.

[0143] The number of bits of data stored in the storage unit MC, the number of states, and the allocation of data to each state can be changed as needed.

[0144] For example, in such Figure 16C In the illustrated allocation scenario, the data of the lower-order bits can be read using a single read voltage V. CGDR Distinguishing between the two. The data for the intermediate-order bits can be read using two voltages V. CGBR V CGFR Distinguishing between them. Higher-order bits of data can be read using four read voltages V. CGAR V CGCR V CGER V CGGR distinguish.

[0145] [Read operation]

[0146] The read operation of the semiconductor memory device according to this embodiment will be described next.

[0147] Figure 17 It is a timing diagram used to describe the read operation.

[0148] Figure 17 An example of the command set CS0 input to the memory die MD during a read operation is shown. The command set CS0 includes data C101, A101, A102, A103, A104, and A105, as well as data C102.

[0149] At timer t101, the control die CD inputs data C101 to the storage die MD as command data D. CMD ( Figure 4 In other words, according to the corresponding bit of data C101, the voltage of data signal input / output terminals DQ0 to DQ7 is set to "H" or "L". "H" is input to external control terminal CLE, and "L" is input to external control terminal ALE. In this state, the input signals of toggle signal input / output terminals DQS and / DQS are exchanged, or the external control terminal / WE rises from "L" to "H". Data C101 is the command input at the start of the read operation.

[0150] At timer t102, the control chip CD inputs data A101 to the memory chip MD as address data D. ADD ( Figure 4In other words, according to the corresponding bits of data A101, the voltages of data signal input / output terminals DQ0 to DQ7 are set to "H" or "L", with "L" input to external control terminal CLE and "H" input to external control terminal ALE. In this state, the input signals of toggle signal input / output terminals DQS and / DQS are swapped, or the external control terminal / WE rises from "L" to "H". Data A101 is part of the column address CA.

[0151] At timer t103, the control chip CD inputs data A102 to the memory chip MD as address data D. ADD ( Figure 4 Data A102 is part of column address CA.

[0152] At timer t104, the control chip CD inputs data A103 to the memory chip MD as address data D. ADD ( Figure 4 Data A103 is part of row address RA. Data A103 includes, for example, block address and page address. Block address is data that identifies storage block BLK. Page address is data that identifies string unit SU and word line WL.

[0153] At timer t105, the control die CD inputs data A104 to the memory die MD as address data D. ADD ( Figure 4 Data A104 is part of the row address RA. Data A104 includes, for example, the block address and the page address.

[0154] At timer t106, the control die CD inputs data A105 to the memory die MD as address data D. ADD ( Figure 4 Data A105 includes the chip address. The chip address is data that identifies a memory die MD controlled by the control die CD from among multiple memory dies MD.

[0155] At timer t107, the control die CD inputs data C102 to the storage die MD as command data D. CMD ( Figure 4 Data C102 is a command that indicates the termination of the input to the command set CS0 regarding the read operation.

[0156] At timer t108, the voltage at terminal RY / / BY changes from "H" to "L", disabling access to memory die MD. A read operation is then performed on memory die MD.

[0157] At timer t109, the read operation in memory die MD is terminated. Additionally, the voltage at terminal RY / / BY changes from the "L" state to the "H" state, allowing access to memory die MD.

[0158] Figure 18 It is a schematic cross-sectional view used to describe the read operation. Figure 19 It is a timing diagram used to describe the read operation.

[0159] In the following description, word line WL is the target of the operation and may be referred to as "the selected word line WL". S Furthermore, word lines WL other than the target of the operation can be referred to as "unselected word lines WL". U In the following description, the selected word line WL, which is connected to the target of the operation, will be described among the multiple memory cells MC included in the string cell SU. S This is an example of a storage unit MC (sometimes referred to below as "selected storage unit MC") performing a read operation. In the following description, a configuration including multiple such selected storage unit MCs may be referred to as a selected page PG.

[0160] In the following description, the data is for reference only. Figure 16C The described method is assigned to each memory cell (MC), and an example of reading data from the middle bit will be described.

[0161] For example, such as Figure 19 As shown, during the read operation, at timer t121, the selected word line WL S A read voltage V was applied READ In the Z direction, with the selected word line WL S Two adjacent unselected word lines WL U A read voltage V was applied READK And other unselected word lines WL U A read voltage V was applied READ Read the voltage V READK Greater than the read voltage V READ Therefore, all memory cells MC become ON. A voltage V is applied to the select gate lines (SGD, SGS, SGSb). SG Voltage V SG It has an amplitude sufficient to form an electron channel in the channel region of the selection transistor (STD, STS, STSb), thereby causing the selection transistor (STD, STS, STSb) to be in the on state.

[0162] For example, in a read operation, at timer t122, the selected word line WL S A reading voltage V was appliedCGBR ( Figure 16A Therefore, for example, such as Figure 18 As shown, some of the selected memory cells MC become active, while the other selected memory cells MC become inactive.

[0163] At time t122, for example, bit line BL is charged. For example, this causes... Figure 11 The latching circuit SDL latches "H" to set the states of signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". Therefore, the voltage V... DD A voltage V is applied to the bit line BL and the sensing node SEN, and their charging begins. SRC Applied to the source line SL ( Figure 5 Voltage V SRC For example, it has a ground voltage V SS The amplitudes are approximately the same. Voltage V SRC It can be, for example, slightly greater than the ground voltage V. SS And sufficiently smaller than voltage V DD The voltage.

[0164] In the read operation, from timer t123 to timer t124, for example, ... Figure 19 As shown, the sensing amplifier module SAM ( Figure 11 The system detects the on / off state of the memory cell MC and obtains data indicating the state of the memory cell MC. For example, when a predetermined bit line voltage is applied to bit line BL... Figure 5 In the state of ), the sensing amplifier SA ( Figure 11 The sensing node and bit line BL are electrically connected for a certain period of time. After the sensing operation is performed, the sensing transistor and wiring LBUS ( Figure 11 Electrical conduction occurs, and the charge on the wiring LBUS is either discharged or maintained. Any latching circuitry in the sense amplifier unit (SAU) is electrically connected to the wiring LBUS, and the data on the wiring LBUS is latched by that latching circuitry.

[0165] During the read operation, at timer t125, for example, at the selected word line WL S A reading voltage V was applied CGFR ( Figure 16A Therefore, a portion of the selected memory cells (MCs) become active, while the other selected memory cells (MCs) become inactive.

[0166] In the read operation, from timer t126 to timer t127, for example, ... Figure 19 As shown, the sensing amplifier module SAM ( Figure 11It detects the on / off state of the storage unit MC and obtains data indicating the state of the storage unit MC.

[0167] During the read operation, at timer t127, the voltage V is read. READ It is applied to the selected word line WLS, and all memory cells MC become on.

[0168] During the read operation, at timer t128, the ground voltage V SS Applied to the selected word line WL S Unselected word line WL U and select gate lines (SGD, SGS, SGSb).

[0169] During a read operation, arithmetic operations, such as AND and OR, are performed on the data indicating the state of the memory cell MC to calculate the data stored in the memory cell MC. This data is transmitted via a wiring LBUS (LBUS). Figure 11 The switching transistor DSW and wiring DBUS are transmitted to the cache memory CM. Figure 4 ).

[0170] [Read the operating current during the operation]

[0171] For reference Figure 19 As described, during the read operation from timer t121 to timer t122, all word lines WL included in the selected memory block BLK are charged to the read pass voltage V. READ Here, related to the high integration of semiconductor memory devices, the conductive layer 110 stacked in the Z direction ( Figure 13 The number of () has been increasing. Relatedly, the amount of charge required to charge the word line WL has increased, and this has increased when a power supply voltage V is applied. CC The operating current flowing in the pad electrode P continuously increases. Relatedly, in some cases, power consumption and heat generation increase. To reduce this operating current, for example, the time period from timer t121 to timer t122 ​​can be extended to reduce the amount of charge moving per unit time. However, in some cases, this extends the time period required for the read operation.

[0172] [Read standby mode]

[0173] Next, we will refer to Figure 20 and Figure 21 Describes the read standby mode according to an embodiment. Figure 20 and Figure 21 This is a schematic timing diagram used to describe the read standby mode according to an embodiment.

[0174] exist Figure 20 and Figure 21 The character line WL k To the word line WL k+4 The five letter lines WL are shown arranged in the Z direction. Figure 20 and Figure 21 In the example, for the word line WL k+2 The corresponding selected page PG is read, and subsequently, the word line WL is read. k+3 The corresponding selected page (PG) will be read.

[0175] Figure 20 The operation from timer t121 to timer t128 in the middle Figure 19 The operations from timer t121 to timer t128 are executed in a similar manner.

[0176] However, in Figure 20 In the example, at time t108, the control die CD inputs the command set CS1, which will be described later, to the storage die MD. Figure 24 (instead of the command set CS0 described above.) Figure 20 In the example, at time t128, the ground voltage V is replaced. SS Standby voltage V READ_WAIT It is applied to the word line WL. For example, the standby voltage V. READ_WAIT Less than the read voltage V READ And greater than the ground voltage V SS And the voltage V described above SRC For example, standby voltage V READ_WAIT It can be greater than the reading voltage V CGGR To read voltage V CGGR The largest read voltage V CGGR At time t129, the semiconductor memory device according to this embodiment is set to read standby mode.

[0177] Despite Figure 19 The diagram is omitted, but at timer t108, the voltage of the internal signal / Cash Busy drops from the "H" state to the "L" state. At timer t129, the voltage of the internal signal / Cash Busy rises from the "L" state to the "H" state. The internal signal / Cash Busy can be read out through status readout, etc.

[0178] In the standby mode according to the embodiment, the standby voltage V READ_WAIT The word line WL is applied to the memory block BLK, which is the target of the read operation. Therefore, in the read standby mode according to the embodiment, the voltage generated by the voltage generation unit vg2 is switched on and off. Figure 6Multiple transistors in the current path between (). For example, in the read standby mode according to the embodiment, the voltage of the signal line BLKSEL is maintained in the "H" state even when the read operation ends. In the read standby mode according to the embodiment, the voltage of the terminal RY / / BY is maintained in the "L" state even when the read operation ends. The voltage of the internal signal / Cash Busy is maintained in the "H" state.

[0179] exist Figure 20 The operation from timer t131 to timer t139 is executed in a manner that is approximately similar to the operation from timer t121 to timer t129.

[0180] However, in Figure 20 In the example, from timer t131 to timer t132, the voltage on word line WL changes from the standby voltage V. READ_WAIT Charged to read through voltage V READ Instead of from the ground voltage V SS Charging to read through voltage V READ .

[0181] exist Figure 20 In the example, at time t138, a ground voltage V is applied to the word line WL. SS Instead of standby voltage V READ_WAIT .exist Figure 20 In the example, after a read operation is performed from time t131 to time t139, the semiconductor memory device is not set to read standby mode.

[0182] Figure 21 The operation shown is basically the same as the reference. Figure 20 The described operations are performed similarly.

[0183] However, in Figure 21 In the example, at the timing point between timer t129 and timer t131, the control die CD will execute the command set CS1, which will be described later. Figure 24 Instead of the command set CS0 input described above, it is input to the memory die MD. Figure 21 In the example, at time t138, the ground voltage V is replaced. SS Standby voltage V READ_WAIT It is applied to the word line WL. At time t139, the semiconductor memory device is set to read standby mode.

[0184] Here, in Figure 19 In the example, during the read operation from timer t121 to timer t122, the voltage on the word line WL changes from the ground voltage V. SS Charged to read through voltage V READ V READKAt timer t127 during the read operation, the ground voltage V SS It is applied to the word line WL. Meanwhile, in Figure 20 and Figure 21 In the example, at time t127 during the read operation, the word line WL is not subjected to ground voltage V. SS Instead, it is higher than the ground voltage V. SS standby voltage V READ_WAIT And this state is maintained even after the read operation is completed. When the next read operation begins, from timer t131 to timer t132, the voltage of word line WL changes from the standby voltage V. READ_WAIT Charged to read through voltage V READ Or read through voltage V READK .

[0185] Using this method, the amount of charge required to charge the word line WL can be reduced when multiple read operations are performed on the same memory block BLK. Therefore, at least one of the operating current and time required for the read operation can be reduced.

[0186] For example, when using reference Figure 19 When the described method performs a read operation twice, such as Figure 22 As shown, the magnitudes of the maximum and average operating current in the second read operation are similar to those in the first read operation.

[0187] At the same time, when using reference Figure 20 or Figure 21 When the described method performs a read operation twice, such as Figure 23 As shown, the maximum and average operating current in the second read operation can be reduced to be less than the maximum and average operating current in the first read operation.

[0188] At the same time, when using reference Figure 20 or Figure 21 When the described method performs a read operation twice, such as Figure 24 As shown, if the magnitudes of the maximum and average operating currents in the second read operation are maintained at a similar level as those in the first read operation, the time required to charge the word line WL can be reduced, thereby allowing for a reduction in the time required for the read operation.

[0189] [Read standby mode settings]

[0190] Various methods are considered as a means of setting a semiconductor memory device to read standby mode.

[0191] As a method for setting a semiconductor memory device to read standby mode, consider, for example, using command data D CMD ( Figure 4 The method.

[0192] As the command data D is used CMD One approach, for example, is to consider adjusting the set of commands used in read operations. For example, see reference... Figure 19 As described, when the semiconductor memory device is not set to read standby mode after a read operation is performed, it can be used as described in the reference. Figure 17 The command set CS0 is described. Also, as a reference... Figure 20 The first read operation described herein, when the semiconductor memory device is set to read standby mode after the read operation is performed, can be performed using, as described in the reference. Figure 25 The command set CS1 is described. Figure 25 The command set CS1 shown is basically similar to Figure 17 The command set CS0 is shown. However, Figure 25 The command set CS1 shown includes data C201. When using command set CS1, the control die CD uses data C201 as command data D. CMD Enter the data into the memory chip MD. Enter data C201 before data C101.

[0193] As the command data D is used CMD Methods, for example, consider inputting predefined command data D CMD The memory die MD is set to read standby mode. For example, in Figure 26 In the example, at time t208, the control die CD uses data C202 as command data D. CMD Input is sent to the memory die MD. Relatedly, the memory die MD is set to read standby mode.

[0194] As a method for setting a semiconductor memory device to read standby mode, one approach is to consider using parameters. For example, when a predetermined parameter becomes active, the memory die MD can be automatically set to read standby mode after a read operation is performed.

[0195] As a method for setting a semiconductor memory device to read standby mode, for example, a method using a pad electrode P can be considered. For instance, when a command set CS0 indicating a read operation is input with "H" input to a predetermined pad electrode P, the memory die MD can be set to read standby mode after the read operation is performed. When the command set CS0 indicating a read operation is input with "L" input to the pad electrode P, the memory die MD does not need to be set to read standby mode after the read operation is performed.

[0196] [Reading the release of standby mode]

[0197] Various methods are considered as a means of releasing the read standby mode of a semiconductor memory device.

[0198] As a method for releasing the read standby mode of a semiconductor memory device, for example, a method for releasing it in response to the execution of a read operation, write operation, or erase operation is considered.

[0199] For example, as described above, when a semiconductor memory device is set to read standby mode by adjusting the command set used in a read operation, it can respond to, as referenced... Figure 17 The described command set CS0 ( Figure 25 The read standby mode is released when the read operation corresponding to the command set (C201) that has no data is executed.

[0200] For example, it is also considered to release read standby mode in response to input of a set of commands indicating the execution of a write or erase operation, or a set of commands CS0, CS1 indicating the execution of a read operation on another storage block BLK.

[0201] As a method for releasing the read standby mode of a semiconductor memory device, consider using command data D. CMD For example, consider releasing data D that has been input with a predetermined command. CMD The read standby mode of the memory die MD. For example, in Figure 26 In the example, at time t130, the control die CD uses data C203 as command data D. CMD Input is sent to the memory die MD. Relatedly, the read standby mode of the memory die MD is released.

[0202] As a method for releasing the read standby mode of a semiconductor memory device, a timer-based approach is considered. For example, consider a situation where a predetermined time has elapsed after the memory die MD has been set to read standby mode, and the read standby mode of the memory die MD is released accordingly.

[0203] [Second Embodiment]

[0204] Next, we will refer to Figure 27 The reading standby mode according to the second embodiment is described. Figure 27 This is a schematic timing diagram used to describe the read standby mode according to the second embodiment.

[0205] The read standby mode according to the second embodiment is substantially similar to the read standby mode according to the first embodiment.

[0206] However, in the read standby mode according to the first embodiment, the signal line BLKSEL is maintained in the "H" state. Meanwhile, in the read standby mode according to the second embodiment, the signal line BLKSEL is maintained in the "L" state. Furthermore, in the second embodiment, when a semiconductor memory device selects a memory block BLK and switches to read standby mode, the read standby mode is maintained during execution even when read, write, and erase operations are performed on other memory blocks BLK.

[0207] For example, Figure 27 The signal lines BLKSELA and BLKSELB are shown as two signal lines BLKSEL corresponding to the two memory blocks BLK. Figure 6 ). Word line WL BLKA WL BLKB Multiple word lines WL are shown as included in two memory blocks BLK. Electrical connections to the word lines WL are also shown. BLKA WL BLKB Wiring CG ( Figure 6 ).

[0208] From timer t221 to timer t229, a read operation is performed on the memory block BLK corresponding to signal line BLKSELA. The operation from timer t221 to timer t229 is similar to... Figure 20 The operations from timer t121 to timer t129 are executed in a similar manner.

[0209] However, in Figure 27 In the example, at time t229 (the timer when the read operation ends), the voltage on the signal line BLKSELB drops from the "H" state to the "L" state.

[0210] From timer t229 to timer t201, the voltage of wiring CG changes from the standby voltage V. READ_WAIT The voltage drops to ground voltage V SS Here, from timer t229 to timer t201, the voltage on signal line BLKSELA is "L". Therefore, word line WLBLKA is electrically isolated from wiring CG. Therefore, word line WL BLKA The voltage is maintained at the standby voltage V. READ_WAIT In the semiconductor memory device according to the embodiment, the memory block BLK corresponding to the signal line BLKSELA is set to read standby mode at time t201.

[0211] In the read standby mode according to an embodiment, the word line WL in the memory block BLK, which is the target of the read operation, is charged to the standby voltage V. READ_WAITIn this state, the signal line BLKSEL (e.g., signal line BLKSELA) is electrically isolated from the wiring CG. Therefore, in the read standby mode according to the embodiment, the voltage of the signal line BLKSEL (e.g., signal line BLKSELA) is maintained in the "L" state. In the read standby mode according to the embodiment, the voltage of the terminal RY / / BY is maintained in the "H" state, and the voltage of the internal signal / Cash Busy (not shown) is maintained in the "L" state.

[0212] At timer t202, the voltage at terminal RY / / BY drops from the "H" state to the "L" state. The voltage at signal line BLKSELB rises from the "L" state to the "H" state.

[0213] From timer t231 to timer t239, a read operation is performed on the memory block BLK corresponding to signal line BLKSELB. The operation from timer t231 to timer t239 is similar to... Figure 19 The operations from timer t121 to timer t129 are executed similarly.

[0214] At timer t239 (the timer for the end of the read operation), the voltage on signal line BLKSELB drops from the "H" state to the "L" state.

[0215] At timer t203, the voltage at terminal RY / / BY rises from the "L" state to the "H" state.

[0216] At timer t204, the voltage at terminal RY / / BY drops from the "H" state to the "L" state. The voltage on signal line BLKSELA rises from the "L" state to the "H" state. Relatedly, wiring CG is replaced by word line WL. BLKA The charge is charged, and the voltage of the wiring CG increases approximately to the standby voltage V. READ_WAIT .

[0217] From timer t241 to timer t248, a read operation is performed again on the memory block BLK corresponding to signal line BLKSELA. The operation from timer t241 to timer t248 is similar to... Figure 20 The operations from timer t121 to timer t128 are executed in a similar manner.

[0218] The methods described above, exemplified as the method for setting and releasing the read standby mode according to the first embodiment, can be substantially used as the method for setting and releasing the read standby mode according to the second embodiment. However, the read standby mode according to the second embodiment does not need to be released, for example, depending on the input of a set of commands instructing to perform a read operation, write operation, or erase operation on another storage block BLK.

[0219] [Third Embodiment]

[0220] Next, we will refer to Figure 28 The reading standby mode is described according to the third embodiment. Figure 28 This is a schematic timing diagram used to describe the read standby mode according to the third embodiment.

[0221] refer to Figure 12 The described memory die MD includes four memory cell array regions R MCA The corresponding four memory cell arrays MCA. The semiconductor memory device according to the third embodiment can process memory cell arrays in mutually different memory cell array regions R. MCA The selected pages (PGs) can perform read operations simultaneously, and read operations can be performed concurrently at independent timers.

[0222] Figure 28 The four memory cell arrays MCA are shown as memory cell arrays MCA0, MCA1, MCA2 and MCA3.

[0223] The semiconductor memory device according to the third embodiment can independently control the setting and release of the read standby mode for the four memory cell arrays (MCA). In the third embodiment, the read standby mode according to the first embodiment and the read standby mode according to the second embodiment can be used.

[0224] For example, in Figure 28 In the example, memory cell arrays MCA0, MCA1, and MCA2 are set to read standby mode and data is sequentially read from the three memory blocks BLK corresponding to memory cell arrays MCA0, MCA1, and MCA2. Meanwhile, memory cell array MCA3 is not set to read standby mode and performs operations as described in the reference... Figure 19 The described read operation.

[0225] [Other Embodiments]

[0226] The semiconductor memory devices according to the first to third embodiments have been described above. However, the semiconductor memory devices described above are merely examples, and their operation, configuration, etc., can be adjusted as needed.

[0227] For example, in the semiconductor memory device according to the first to third embodiments, as referenced Figure 16A , Figure 16B and Figure 16C As described, each storage cell (MC) stores 3 bits of data. However, the data stored in the storage cell (MC) can be 1 bit, 2 bits, 4 bits, or more.

[0228] Here, as a reference Figure 16A , Figure 16B , Figure 16CAs described above, when 3 bits of data are stored in the memory cell MC, one to four read voltages need to be supplied to the word line WL during a read operation. Conversely, when, for example, 1 bit of data is stored in the memory cell MC, only one read voltage is applied to the word line WL during a read operation. In this respect, data can be read at high speed. However, when the charging and discharging of the word line WL is repeated in each read operation, the amount of charge movement per unit time increases, which may increase the operating current. In this case, the operating current can be reduced more effectively when the read standby mode according to the first or second embodiment is applied.

[0229] [other]

[0230] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel methods and systems described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications as falling within the scope and spirit of the invention.

Claims

1. A semiconductor memory device, comprising: A memory string, which comprises multiple memory transistors connected in series; Multiple first wirings are connected to the gate electrodes of the multiple storage transistors; A plurality of second wirings are electrically connected to the plurality of first wirings; Multiple transistors are electrically connected between the multiple first wirings and the multiple second wirings; as well as The third wiring, which is commonly connected to the gate electrode of the plurality of transistors, wherein, In response to input of the first command set, perform the first read operation. In response to input of the second command set, perform the second read operation. From the end of the first read operation to the start of the second read operation, a first voltage is applied to the plurality of second wirings, and a second voltage that turns on the plurality of transistors is applied to the third wirings. After the second read operation ends, a third voltage is applied to the plurality of second wirings, and a fourth voltage that turns off the plurality of transistors is applied to the third wirings. The first voltage is greater than the third voltage.

2. The semiconductor memory device according to claim 1, wherein, In the first read operation, multiple different read voltages are applied to at least one of the multiple second wirings, and The first voltage is greater than the largest of the plurality of read voltages.

3. The semiconductor memory device according to claim 1, wherein, During the execution of the first read operation and the second read operation, a fifth voltage is applied to at least one of the plurality of second wirings, and The fifth voltage is greater than the first voltage.

4. The semiconductor memory device according to claim 1, wherein, The first command set includes first address data. The second command set includes second address data. The portion of the first command set that does not include the first address data includes the first data, and The portion of the second command set that does not include the second address data does not include the first data.

5. The semiconductor memory device according to claim 1, wherein, The first command set includes first address data. The second command set includes second address data, and The portion of the first command set that does not include the first address data matches the portion of the second command set that does not include the second address data.

6. The semiconductor memory device according to claim 1, further comprising: Substrate; as well as Multiple storage strings, wherein, The plurality of storage transistors and the plurality of first wirings are arranged in a first direction intersecting the surface of the substrate, and The plurality of storage strings are arranged in a second direction intersecting the first direction.

7. A semiconductor memory device, comprising: A memory string, which comprises multiple memory transistors connected in series; Multiple first wirings are connected to the gate electrodes of the multiple storage transistors; as well as A plurality of second wirings are electrically connected to the plurality of first wirings, wherein, In response to input of the first command set, perform the first read operation. In response to input of the second command set, perform the second read operation. At a first timing point after the first read operation ends, a first voltage is applied to the plurality of second wirings. At a second timing after the second read operation ends, a second voltage is applied to the plurality of second wirings, and The first voltage is greater than the second voltage.

8. The semiconductor memory device according to claim 7, wherein, In the first read operation, multiple different read voltages are applied to at least one of the multiple second wirings, and The first voltage is greater than the largest of the plurality of read voltages.

9. The semiconductor memory device according to claim 7, further comprising: Multiple transistors are electrically connected between the multiple first wirings and the multiple second wirings; as well as The third wiring, which is commonly connected to the gate electrode of the plurality of transistors, wherein, During the second timing, the voltage applied to the third wiring switches from a third voltage that turns on the plurality of transistors to a fourth voltage that turns off the plurality of transistors.

10. The semiconductor memory device according to claim 9, wherein, During the first timing, the voltage applied to the third wiring is maintained at the third voltage.

11. The semiconductor memory device according to claim 9, wherein, During the first timing, the voltage applied to the third wiring switches from the third voltage to the fourth voltage.

12. The semiconductor memory device according to claim 7, wherein, During the execution of the first read operation and the second read operation, a fifth voltage is applied to at least one of the plurality of second wirings, and The fifth voltage is greater than the first voltage.

13. The semiconductor memory device according to claim 7, wherein, The first command set includes first address data. The second command set includes second address data. The portion of the first command set that does not include the first address data includes the first data, and The portion of the second command set that does not include the second address data does not include the first data.

14. The semiconductor memory device according to claim 7, wherein, The first command set includes first address data. The second command set includes second address data, and The portion of the first command set that does not include the first address data matches the portion of the second command set that does not include the second address data.

15. The semiconductor memory device according to claim 7, further comprising: Substrate; as well as Multiple storage strings, wherein, The plurality of storage transistors and the plurality of first wirings are arranged in a first direction intersecting the surface of the substrate, and The plurality of storage strings are arranged in a second direction intersecting the first direction.

16. A semiconductor memory device, comprising: The first bonding pad electrode is subjected to a first voltage, wherein, In response to input of the first command set, perform the first read operation. In response to input of the second command set, perform the second read operation. When the second read operation is performed after the first read operation, the execution period of the second read operation is assumed to be a first period, and the average current flowing to the first bonding pad electrode during the execution of the second read operation is assumed to be a first current, and When the second read operation is performed after the second read operation is performed, the execution cycle of the latter second read operation is assumed to be the second cycle, and the average current flowing to the first bonding pad electrode during the execution of the latter second read operation is assumed to be the second current. The first period is less than the second period, or the first current is less than the second current.

17. The semiconductor memory device of claim 16, further comprising: A memory string, which comprises multiple memory transistors connected in series; Multiple first wirings are connected to the gate electrodes of the multiple storage transistors; as well as A plurality of second wirings are electrically connected to the plurality of first wirings, wherein, At a first timing point after the first read operation ends, a second voltage is applied to the plurality of second wirings. At a second timing point after the second read operation ends, a third voltage is applied to the plurality of second wirings, and The second voltage is greater than the third voltage.

18. The semiconductor memory device of claim 17, further comprising: Substrate; as well as Multiple storage strings, wherein, The plurality of storage transistors and the plurality of first wirings are arranged in a first direction intersecting the surface of the substrate, and The plurality of storage strings are arranged in a second direction intersecting the first direction.

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