A content-addressable memory

Abstract

A content addressable memory includes a bit cell array, a search line driving unit, a match signal unit and a first charging unit; the first charging unit is used for pre-charging an output end of a first match line and an output end of a second match line to a predetermined voltage; the search line driving unit is used for sending a search word to a first bit cell group; the first bit cell group is used for adjusting a first end voltage of the first match line according to the search word and a first storage word; adjusting a first end voltage of the second match line according to the search word and a second storage word; an amplifying unit is used for amplifying the first end voltage of the first match line to a first amplification voltage, and amplifying the first end voltage of the second match line to a second amplification voltage; the match signal unit is used for outputting a range match result according to the first amplification voltage and the second amplification voltage. The content addressable memory can save hardware resources occupied by range matching.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more particularly to a content-addressable memory. Background Technology

[0002] Content-addressable memory (CAM) is a special type of memory. See also... Figure 1A and Figure 1B CAM not only supports random writes but also table lookups. Table lookup refers to the process where, after a search term is input into CAM, CAM compares the search term with all stored terms in CAM simultaneously, determines whether the search term matches any of the stored terms, and outputs the address of the matching term and matching information.

[0003] Ternary content addressable memory (TCAM) is a commonly used type of memory module (CAM). A TCAM consists of multiple rows of bit cells, with each row containing multiple bit cells. Figure 2 This is a schematic diagram of a single bit cell. Please refer to [link / reference]. Figure 2 The bit unit includes transistors m1, m2, m3, and m4, a first static random access memory (SRAM) storage cell 201, and a second SRAM storage cell 202. Both the first SRAM storage cell 201 and the second SRAM storage cell 202 include two inverters for storing one bit. The first SRAM storage cell is connected to the gate of m1. The sources of m1 and m2, the drains of m1 and m2 are all connected to a match line (ml) 203. The gate of m2 is connected to the drain of m3 and the source of m4. The source of m3 is connected to a search line driving unit SL, and the drain of m4 is connected to a search line driving unit SL#. The gate of m3 is connected to one end of the second SRAM storage cell, and the gate of m4 is connected to the other end of the second SRAM storage cell.

[0004] However, TCAM can only represent interval ranges using wildcards. For example, when comparing an input search word with the interval [001, 111], TCAM cannot store [001, 111] in a single row of bits; instead, it needs to be stored in three rows of bits. One row stores 001, the second row stores 01, and so on. The third row of bits stores 1 , 01 The range represented is [010, 011], 1 The range represented is [100, 111]. In practical applications, such range matching requires a large amount of hardware resources (i.e., bit units). Summary of the Invention

[0005] In view of this, this application provides a content-addressable memory that can save hardware resources occupied by range matching.

[0006] A first aspect provides a content-addressable memory, comprising a bit cell array, a search line driving unit, a matching signal unit, and a first charging unit; the first charging unit is used to precharge the output terminals of a first matching line and a second matching line to a predetermined voltage; the search line driving unit is used to send a search word to a first bit cell array; the first bit cell array is used to adjust the voltage of the first terminal of the first matching line from the predetermined voltage to ground voltage when the search word and the pre-stored first storage word satisfy a first preset relationship, and to maintain the voltage of the first terminal of the first matching line at the predetermined voltage when the search word and the pre-stored first storage word do not satisfy the first preset relationship; to adjust the voltage of the first terminal of the second matching line from the predetermined voltage to ground voltage when the search word and the pre-stored second storage word satisfy a second preset relationship, and to maintain the voltage of the first terminal of the second matching line at the predetermined voltage when the search word and the pre-stored second storage word do not satisfy the second preset relationship; an amplification unit is used to amplify the voltage of the first terminal of the first matching line to a first amplified voltage and to amplify the voltage of the first terminal of the second matching line to a second amplified voltage; and the matching signal unit is used to output a range matching result according to the first amplified voltage and the second amplified voltage. In this system, the first bit cell group is any row of bit cells in the bit cell array. Each bit cell in the first bit cell group is connected to a first matching line and a second matching line. The first end of the first matching line is connected to the amplification unit and the first charging unit, and the first end of the second matching line is also connected to the amplification unit and the first charging unit. The bits of the first bit cell group are arranged along the first matching line in ascending order of storage bits, with the bit cell storing the lowest storage bit located on the side furthest from the first charging unit. The first charging unit includes a charging switch corresponding to each matching line. The first preset relationship is less than or greater than, and the second preset relationship is also less than or greater than. The first and second preset relationships can be the same or different. The first storage word is obtained by processing the upper limit of the target range using the first preset rule, and the second storage word is obtained by processing the lower limit of the target range using the second preset rule. Specifically, the first storage word can be the upper limit of the target range, the upper limit of the target range plus one, or the upper limit of the target range minus one. The second storage word can be the lower limit of the target range, the lower limit of the target range plus one, or the lower limit of the target range minus one.

[0007] Taking the upper limit of the target range as an example for the first storage word and the lower limit of the target range as an example for the second storage word, and taking "less than" as the first preset relationship as an example, a voltage can be output on the first matching line based on the search word and the first storage word. This voltage indicates whether the search word is less than the upper limit of the target range. Taking "greater than" as an example for the second preset relationship, a voltage can be output on the second matching line based on the search word and the second storage word. This voltage indicates whether the search word is greater than the lower limit of the target range. Combining the two voltages, a range matching result can be output, which indicates whether the search word is within the target range. A bit unit group includes n bit units, so the first storage word and the second storage word can be [0, 2]. n Any value of ] can be used to achieve range matching by storing two storage words in a single bit unit, thus saving hardware resources used in range matching.

[0008] It should be understood that when the target range is a closed interval or a half-open interval, the target range can be converted into an equivalent open interval. The upper limit of the converted open interval is the first storage word, and the lower limit of the converted open interval is the second storage word. It can be seen that when the first preset relationship is less than and the second preset relationship is greater than, the above-mentioned content-addressable memory can perform range matching between the search word and the open interval, closed interval, or half-open interval. It should be noted that when the first preset relationship is greater than, the matching signal unit can invert the first amplified voltage, thus determining whether the search word is less than the first storage word. When the second preset relationship is less than, the matching signal unit can invert the second amplified voltage, thus determining whether the search word is greater than the second storage word. Therefore, the above-mentioned content-addressable memory can perform range matching on any range based on the above-mentioned first and second preset relationships.

[0009] In one possible implementation, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy a first preset relationship, and turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the first preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to turn on the connection between the second matching line and ground when the second search line signal and the second storage bit satisfy a second preset relationship, and turn off the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the second preset relationship. The system comprises the following components: a first switching unit connected to the search line driving unit, the gate of the first transistor, and the first bit storage unit; the source and drain of the first transistor connected to the first matching line; a second switching unit connected to the search line driving unit, the first bit storage unit, the first matching line, and ground; a third switching unit connected to the search line driving unit, the gate of the second transistor, and the second bit storage unit; the source and drain of the second transistor connected to the second matching line; and a fourth switching unit connected to the search line driving unit, the second bit storage unit, the second matching line, and ground. In the first bit unit group, the first bit storage unit of each bit unit is used to store the first storage bit, and the second bit storage unit of each bit unit in the first bit unit group is used to store the second storage bit.

[0010] Taking the first preset relationship as less than as an example, when the search word is less than the first storage word, the second switching unit of one bit cell will necessarily be turned on, causing the first matching line to be grounded, thereby outputting a ground voltage. When the search word is greater than the first storage word, the first transistor of one bit cell will necessarily be turned off, causing the first matching line to be disconnected, and the second switching units near the first charging unit side will all be turned off, preventing the first matching line from being grounded, thus the first matching line outputs a predetermined voltage. When the search word is equal to the first storage word, the first transistors of all bit cells are turned on and the first matching line is not grounded, thus the first matching line outputs a predetermined voltage. Therefore, it can be seen that the first bit cell group and the first matching line can achieve less than matching. Similarly, the first bit cell group and the second matching line can achieve less than matching. It should be understood that when the first preset relationship or the second preset relationship is greater than, the above-mentioned bit cell group, first matching line, and second matching line can also achieve greater than matching.

[0011] In another possible implementation, the first switching unit includes a third transistor and a fourth transistor. The third transistor is connected to one end of the first memory cell and the search line driving unit, and the fourth transistor is connected to the other end of the first memory cell and the search line driving unit. Both the third and fourth transistors are connected to the gate of the first transistor. The second switching unit includes a fifth transistor and a sixth transistor connected together. The fifth transistor is connected to the first memory cell and ground, and the sixth transistor is connected to the search line driving unit and the first matching line. The third switching unit includes a seventh transistor and an eighth transistor connected together. The seventh transistor is connected to one end of the second memory cell and the search line driving unit, and the eighth transistor is connected to the other end of the second memory cell and the search line driving unit. Both the seventh and eighth transistors are connected to the gate of the second transistor. The fourth switching unit includes a ninth transistor and a tenth transistor connected together. The ninth transistor is connected to the second memory cell and ground, and the tenth transistor is connected to the search line driving unit and the second matching line. This provides specific implementations of the above-described switching units. It should be understood that each switching unit can also achieve its function using more transistors.

[0012] In another possible implementation, the sixth and tenth transistors are connected to the search line drive unit via different search lines, the fifth transistor is connected to the first terminal of the first memory cell, and the ninth transistor is connected to the second terminal of the second memory cell. The first and second terminals are different terminals. This implementation achieves a heterogeneous bit cell by controlling the grounding of the first matching line via the second switching unit in a different way than by controlling the grounding of the second matching line via the fourth switching unit. Such a bit cell can include two different matching circuits, thereby realizing two preset relationships.

[0013] In another possible implementation, the amplification unit includes a first sensitive amplifier and a second sensitive amplifier, and the matching signal unit includes a first NOT gate, a second NOT gate, and a first AND gate. The first sensitive amplifier is connected to the first matching line and the first NOT gate, the second sensitive amplifier is connected to the second matching line and the second NOT gate, and the first AND gate is connected to both the first NOT gate and the second NOT gate. In this content-addressable memory, the first sensitive amplifier amplifies the voltage at the first terminal of the first matching line to a first amplified voltage, the second sensitive amplifier amplifies the voltage at the first terminal of the second matching line to a second amplified voltage, the first NOT gate inverts the first amplified voltage, the second NOT gate inverts the second amplified voltage, and the first AND gate performs a bitwise AND operation between the inverted second amplified voltage and the inverted first amplified voltage to obtain the range matching result.

[0014] In another possible implementation, the matching signal unit further includes a second AND gate, which connects a second sensitive amplifier and a third sensitive amplifier. The third sensitive amplifier is connected to the first matching line of the second bit cell group, which is adjacent to the first bit cell group. The second AND gate performs an AND operation on the levels output by the matching lines connected to the adjacent bit cell groups, thereby outputting a new range matching result. The range corresponding to this range matching result lies between the two ranges stored in the adjacent bit cell groups. Therefore, for more than three consecutive intervals, this content-addressable memory can save hardware resources occupied by range matching.

[0015] In another possible implementation, the sixth and tenth transistors are connected to the search line drive unit via a search line, the fifth transistor is connected to the first terminal of the first memory cell, and the ninth transistor is connected to the first terminal of the second memory cell. The first terminal can be either the left or right terminal. Implemented in this way, controlling the grounding of the first matching line via the second switching unit is the same as controlling the grounding of the second matching line via the fourth switching unit, thus realizing an isomorphic bit cell. Such a bit cell includes two identical matching circuits, which facilitates manufacturing.

[0016] In another possible implementation, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate. The fourth sensitive amplifier is connected to the first matching line and the third NOT gate, the fifth sensitive amplifier is connected to the second matching line, and the third AND gate is connected to both the third NOT gate and the fifth sensitive amplifier. In this content-addressable memory, the fourth sensitive amplifier amplifies the voltage at the first terminal of the first matching line to a third amplified voltage, the fifth sensitive amplifier amplifies the voltage at the first terminal of the second matching line to a fourth amplified voltage, the first NOT gate inverts the third amplified voltage, and the first AND gate performs a bitwise AND operation between the fourth amplified voltage and the inverted third amplified voltage to obtain the range matching result.

[0017] In another possible implementation, the matching signal unit further includes a fourth NOT gate and a fourth AND gate; the fourth AND gate is connected to a sixth sensitive amplifier, which is connected to the first matching line of the second bit cell group, which is adjacent to the first bit cell group; the fourth NOT gate is connected to a fifth sensitive amplifier and the fourth AND gate. The fourth AND gate performs an AND operation on the levels output by the matching lines connected to adjacent bit cell groups, thereby outputting a new range matching result. The range corresponding to this range matching result lies between the two ranges stored in the adjacent bit cells. Therefore, for more than three consecutive intervals, this content-addressable memory can save hardware resources occupied by range matching.

[0018] In another possible implementation, the content-addressable memory further includes a second charging unit connected to the second end of the first matching line. The enable state of the second charging unit is opposite to that of the first charging unit. The first bit unit group is also used to turn on the first matching line when the search word is equal to the first stored word, and to turn off the first matching line when the search word is not equal to the first stored word. The amplification unit is also used to amplify the voltage at the first end of the first matching line. The matching signal unit is also used to output the amplified voltage at the first end of the first matching line. When the search word is equal to the first stored word, the first matching line is turned on, and a high level can reach the amplification unit from the second charging unit. The amplification unit can process the high level and transmit it to the matching signal unit, so that the matching signal unit can output a high level. When the search word is not equal to the first stored word, the first matching line is turned off, and the high level cannot reach the amplification unit from the second charging unit, so the matching signal unit outputs a low level. In this way, the equality of the search word and the first stored word can be determined based on the high and low levels, thereby achieving precise matching. It should be understood that when the search word is equal to the first stored word, the search word and the pre-stored first stored word do not satisfy the first preset relationship, so the first matching line will not be grounded.

[0019] Optionally, the second charging unit is also connected to the second end of the second matching line, and the first unit group is also used to turn on the second matching line when the search word is equal to the second stored word, and to turn off the second matching line when the search word is not equal to the second stored word; the amplification unit is also used to amplify the voltage at the first end of the second matching line; the matching signal unit is also used to output the amplified voltage at the first end of the second matching line. In this way, precise matching can be achieved through the second matching line.

[0020] In another possible implementation, the content-addressable memory further includes a wildcard matching enable line; each bit cell in the first bit cell group includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the eleventh transistor is connected to a third switching unit and a second storage cell, and is used to turn on or off according to the storage bit of the second storage cell; the twelfth transistor is connected to the wildcard matching enable line, the eleventh transistor, and a first matching line, and is used to turn on or off the connection between the eleventh transistor and the first matching line according to a control signal received from the wildcard matching enable line; the thirteenth transistor is used to turn off the connection between the first matching line and the second switching unit according to a control signal received from the wildcard matching enable line.

[0021] When the second charging unit is enabled, the connection between the eleventh transistor and the first matching line is turned on; when the second charging unit is disabled, the connection between the eleventh transistor and the first matching line is turned off. When the second storage bit of the i-th bit is X, the eleventh transistor is turned on, and regardless of whether the search word is 0 or 1, a high level can be output to the next stage through the eleventh and twelfth transistors of the i-th bit. When the second storage bit is 0 or 1, the eleventh transistor is turned off. Thus, the first transistor will turn on or off according to the comparison result between the search word and the first storage word, thereby determining whether the search word equals 0 or 1, thus achieving wildcard matching. The twelfth and thirteenth transistors are inverting switches. It should be understood that when the second charging unit is enabled, the thirteenth transistor is turned off, thus preventing the first matching line from being grounded. When the second charging unit is disabled and the first charging unit is enabled, the thirteenth transistor is turned on, allowing the second switching unit to control the connection between the first matching line and ground.

[0022] In another possible implementation, the content-addressable memory further includes a result control line and a first signal output line; the matching signal unit further includes a fourteenth transistor and a fifteenth transistor; the fourteenth transistor is connected to the result control line, the amplification unit, and the first signal output line, and the fifteenth transistor is connected to the result control line, the matching signal unit, and the first signal output line. The fourteenth transistor is used to turn on the connection between the amplification unit and the first signal output line according to a second control signal received from the result control line, or to turn off the connection between the amplification unit and the first signal output line according to a third control signal received from the result control line. The fifteenth transistor is used to turn on the connection between the matching signal unit and the first signal output line according to a third control signal received from the result control line, or to turn off the connection between the matching signal unit and the first signal output line according to the second control signal. When the fourteenth transistor is off and the fifteenth transistor is on, a range matching result is output; when the fourteenth transistor is on and the fifteenth transistor is off, an exact matching result or a wildcard matching result is output.

[0023] In another possible implementation, the content-addressable memory further includes a sixteenth transistor and a seventeenth transistor, a result control bit storage unit, and a second signal output line; the sixteenth transistor is connected to the result control bit storage unit, the second charging unit, and the first matching line; the seventeenth transistor is connected to the result control bit storage unit, the first charging unit, and the first matching line; the matching signal unit further includes an eighteenth transistor and a nineteenth transistor; the eighteenth transistor is connected to the result control bit storage unit, the amplification unit, and the second signal output line; the nineteenth transistor is connected to the result control bit storage unit, the matching signal unit, and the second signal output line. The sixteenth transistor is used to turn on or off the connection between the second charging unit and the first matching line according to the value stored in the result control bit storage unit. The seventeenth transistor is used to turn on or off the connection between the first charging unit and the first matching line according to the value stored in the result control bit storage unit. The eighteenth transistor is used to turn on or off the connection between the amplification unit and the second signal output line according to the value stored in the result control bit storage unit. The nineteenth transistor is used to turn on or off the connection between the matching signal unit and the second signal output line according to the value stored in the result control bit storage unit. Within one clock cycle, the switching states of transistors 16 and 18 are the same, the switching states of transistors 17 and 19 are the same, and the switching states of transistors 16 and 17 are opposite. When transistors 18 and 16 are on and transistors 17 and 19 are off, an exact match result or a wildcard match result is output. When transistors 18 and 16 are off and transistors 17 and 19 are on, a range match result is output.

[0024] A second aspect provides a content-addressable memory, comprising: a bit cell array, a search line driving unit, a matching signal unit, and a first charging unit; the first charging unit is used to precharge the output terminals of a first matching line and a second matching line to a predetermined voltage; the search line driving unit is used to send a search word to a first bit cell array; the first bit cell array is used to adjust the voltage at the first end of the first matching line from the predetermined voltage to ground voltage when the search word and the pre-stored first storage word satisfy a first preset relationship, and to maintain the voltage at the first end of the first matching line at the predetermined voltage when the search word and the pre-stored first storage word do not satisfy the first preset relationship; to adjust the voltage at the first end of the second matching line from the predetermined voltage to ground voltage when the search word and the pre-stored second storage word satisfy a second preset relationship, and to maintain the voltage at the first end of the second matching line at the predetermined voltage when the search word and the pre-stored second storage word do not satisfy the second preset relationship; an amplification unit is used to amplify the voltage at the first end of the first matching line to a first amplified voltage, and to amplify the voltage at the first end of the second matching line to a second amplified voltage; the matching signal unit is used to output a range matching result according to the first amplified voltage and the second amplified voltage. In this system, the first bit cell group is any row of bit cells in the bit cell array. Each bit cell in the first bit cell group is connected to a first matching line and a second matching line. The first end of the first matching line is connected to the amplification unit and the first charging unit, and the first end of the second matching line is also connected to the amplification unit and the first charging unit. The second ends of both the first and second matching lines are grounded. The bits of the first bit cell group are arranged along the first matching line in ascending order of storage bits, with the bit cell storing the lowest storage bit located on the side furthest from the first charging unit. The first charging unit includes a charging switch corresponding to each matching line. A first preset relationship is not less than or not greater than, and a second preset relationship is also not less than or not greater than. The first and second preset relationships can be the same or different. Specifically, the first storage word can be equal to the upper limit of the target range, the upper limit of the target range plus one, or the upper limit of the target range minus one. The second storage word can be equal to the lower limit of the target range, the lower limit of the target range plus one, or the lower limit of the target range minus one.

[0025] In this implementation, the first preset relationship is exemplified by "not greater than". Based on the search word and the first stored word, a voltage can be output on the first matching line. This voltage indicates whether the search word is less than or equal to the upper limit of the target range. The second preset relationship is also exemplified by "not less than". Based on the search word and the second stored word, a voltage can be output on the second matching line. This voltage indicates whether the search word is greater than or equal to the lower limit of the target range. Combining the two voltages outputs a range matching result, which indicates whether the search word is within the target range.

[0026] When the target range is an open interval or a half-open / half-closed interval, the target range can be converted into an equivalent closed interval. The upper limit of the converted closed interval is the first storage word, and the lower limit of the converted closed interval is the second storage word. Therefore, when the first preset relationship is not greater than and the second preset relationship is not less than, the above content-addressed storage can perform range matching between the search word and the open interval, closed interval, or half-open / half-closed interval.

[0027] In one possible implementation, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy a third preset relationship, and turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the third preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to turn on the connection between the second matching line and ground when the second search line signal and the second storage bit satisfy a fourth preset relationship, and turn off the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the fourth preset relationship. The system comprises the following components: a first switching unit connected to the search line driving unit, the gate of the first transistor, and the first bit storage unit; the source and drain of the first transistor connected to the first matching line; a second switching unit connected to the search line driving unit, the first matching line, the first bit storage unit, and ground; a third switching unit connected to the search line driving unit, the gate of the second transistor, and the second bit storage unit; the source and drain of the second transistor connected to the second matching line; and a fourth switching unit connected to the search line driving unit, the second matching line, the second bit storage unit, and ground. In the first bit unit group, the first bit storage unit of each bit unit stores the first storage bit, and in the first bit unit group, the second bit storage unit of each bit unit stores the second storage bit.

[0028] When the first preset relationship is not greater than, the third preset relationship is less than. When the first preset relationship is not less than, the third preset relationship is greater than. When the second preset relationship is not greater than, the fourth preset relationship is less than. When the second preset relationship is not less than, the fourth preset relationship is greater than. When the search word is less than the first storage word, the second switch unit of one bit unit must be turned on, so the first matching line outputs a ground voltage. When the search word is equal to the first storage word, the first transistors of all bit units are turned on and the first matching line is grounded, so the first matching line outputs a ground voltage. When the search word is greater than the first storage word, the second switch unit and the first transistor of one bit unit must be turned off, so the first matching line outputs a predetermined voltage, thus achieving a less than or equal to matching. Similarly, a greater than or equal to matching can be achieved.

[0029] In another possible implementation, the first switching unit includes a third transistor and a fourth transistor. The third transistor is connected to one end of the first memory cell and the search line driving unit, and the fourth transistor is connected to the other end of the first memory cell and the search line driving unit. Both the third and fourth transistors are connected to the gate of the first transistor. The second switching unit includes a fifth transistor and a sixth transistor connected together. The fifth transistor is connected to the first memory cell and ground, and the sixth transistor is connected to the search line driving unit and the first matching line. The third switching unit includes a seventh transistor and an eighth transistor connected together. The seventh transistor is connected to one end of the second memory cell and the search line driving unit, and the eighth transistor is connected to the other end of the second memory cell and the search line driving unit. Both the seventh and eighth transistors are connected to the gate of the second transistor. The fourth switching unit includes a ninth transistor and a tenth transistor connected together. The ninth transistor is connected to the second memory cell and ground, and the tenth transistor is connected to the search line driving unit and the second matching line. This provides specific implementations of the above-described switching units. It should be understood that each switching unit can also achieve its function using more transistors.

[0030] Optionally, the sixth and tenth transistors are connected to the search line drive unit via different search lines, the fifth transistor is connected to the first end of the first memory cell, and the ninth transistor is connected to the second end of the second memory cell.

[0031] Optionally, the amplification unit includes a first sensitive amplifier and a second sensitive amplifier, and the matching signal unit includes a first NOT gate, a second NOT gate, and a first AND gate; the first sensitive amplifier is connected to the first matching line and the first NOT gate, the second sensitive amplifier is connected to the second matching line and the second NOT gate, and the first AND gate is connected to the first NOT gate and the second NOT gate respectively.

[0032] Optionally, the matching signal unit further includes a second AND gate, which connects a second sensitive amplifier and a third sensitive amplifier. The third sensitive amplifier is connected to the first matching line of the second bit unit group, and the second bit unit group is adjacent to the first bit unit group.

[0033] Optionally, the sixth and tenth transistors are connected to the search line drive unit via a search line, the fifth transistor is connected to the first terminal of the first memory cell, and the ninth transistor is connected to the first terminal of the second memory cell.

[0034] In another possible implementation, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate. The fourth sensitive amplifier is connected to the first matching line and the third NOT gate, the fifth sensitive amplifier is connected to the second matching line, and the third AND gate is connected to both the third NOT gate and the fifth sensitive amplifier. In this content-addressable memory, the fourth sensitive amplifier amplifies the voltage at the first terminal of the first matching line to a first amplified voltage, the fifth sensitive amplifier amplifies the voltage at the first terminal of the second matching line to a second amplified voltage, the third NOT gate inverts the first amplified voltage, and the third AND gate performs a bitwise AND operation between the second amplified voltage and the inverted first amplified voltage to obtain the range matching result.

[0035] In another possible implementation, the matching signal unit further includes a fourth NOT gate and a fourth AND gate; the fourth NOT gate is connected to a sixth sensitive amplifier, which is connected to the first matching line of the second bit cell group, which is adjacent to the first bit cell group; the fourth AND gate is connected to the second sensitive amplifier and the fourth NOT gate. For more than three consecutive intervals, this content-addressable memory can save hardware resources occupied by range matching.

[0036] The composition, connection relationships, and beneficial effects of each unit in the possible implementation of the second aspect can be found in the corresponding description of the first aspect.

[0037] A third aspect provides a content-addressable memory, comprising: a bit cell array, a search line driving unit, a matching signal unit, and a first charging unit; the first charging unit is used to precharge the output terminals of a first matching line and a second matching line to a predetermined voltage; the search line driving unit is used to send a search word to a first bit cell array; the first bit cell array is used to adjust the voltage at the first end of the first matching line from the predetermined voltage to ground voltage when the search word and the pre-stored first storage word satisfy a first preset relationship, and to maintain the voltage at the first end of the first matching line at the predetermined voltage when the search word and the pre-stored first storage word do not satisfy the first preset relationship; to adjust the voltage at the first end of the second matching line from the predetermined voltage to ground voltage when the search word and the pre-stored second storage word satisfy a second preset relationship, and to maintain the voltage at the first end of the second matching line at the predetermined voltage when the search word and the pre-stored second storage word do not satisfy the second preset relationship; an amplification unit is used to amplify the voltage at the first end of the first matching line to a first amplified voltage, and to amplify the voltage at the first end of the second matching line to a second amplified voltage; the matching signal unit is used to output a range matching result according to the first amplified voltage and the second amplified voltage. In this system, the first bit cell group is any row of bit cells in the bit cell array. Each bit cell in the first bit cell group is connected to a first matching line and a second matching line. The first end of the first matching line is connected to the amplification unit and the first charging unit, and the first end of the second matching line is also connected to the amplification unit and the first charging unit. The second end of the first matching line is grounded, and the second end of the second matching line is not grounded. The bits of the first bit cell group are arranged along the first matching line in ascending order of storage bits, with the bit cell storing the lowest storage bit located on the side furthest from the first charging unit. The first charging unit includes a charging switch corresponding to each matching line. The first preset relationship is not less than or not greater than, and the second preset relationship is less than or greater than. Specifically, the first storage word can be equal to the upper limit of the target range, the upper limit of the target range plus one, or the upper limit of the target range minus one. The second storage word can be equal to the lower limit of the target range, the lower limit of the target range plus one, or the lower limit of the target range minus one.

[0038] In this implementation, the first preset relationship, taking "not greater than" as an example, outputs a voltage on the first matching line based on the search word and the first stored word. This voltage indicates whether the search word is less than or equal to the upper limit of the target range. The second preset relationship, taking "greater than" as an example, outputs a voltage on the second matching line based on the search word and the second stored word. This voltage indicates whether the search word is greater than the lower limit of the target range. Combining the two voltages, a range matching result is output. This range matching result indicates whether the search word is within the target range, which is a half-open, half-closed interval.

[0039] In one possible implementation, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy a third preset relationship, and turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the third preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to turn on the connection between the second matching line and ground when the second search line signal and the second storage bit satisfy a second preset relationship, and turn off the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the second preset relationship. The system comprises the following components: a first switching unit connected to the search line driving unit, the gate of the first transistor, and the first bit memory cell; the source and drain of the first transistor are connected to the first matching line. A second switching unit connected to the search line driving unit, the first matching line, and the second transistor; the second transistor is connected to the second switching unit, the first bit memory cell, and ground. A third switching unit connected to the search line driving unit, the gate of the second transistor, and the second bit memory cell; the source and drain of the second transistor are connected to the second matching line. A fourth switching unit connected to the search line driving unit, the second matching line, and the source of the fourth transistor; the gate of the fourth transistor is connected to the second bit memory cell, and the drain of the fourth transistor is grounded. When the first preset relationship is not less than, the third preset relationship is greater than.

[0040] When the third preset relationship is less than, if the search word is less than the first storage word, the second switching unit of one bit cell will necessarily be turned on, thus the first matching line outputs a ground voltage. If the search word is equal to the first storage word, the first transistors of all bit cells are turned on and the first matching line is grounded, thus the first matching line outputs a ground voltage. If the search word is greater than the first storage word, one bit cell will necessarily be turned off, thus the first matching line outputs a predetermined voltage. This achieves a less than or equal to matching. If the search word is equal to the second storage word, the second transistors of all bit cells are turned on and the second matching line is not grounded, thus the second matching line outputs a predetermined voltage, and the first bit cell group and the second matching line can achieve a greater than matching. It should be understood that when the first preset relationship is not less than or the second preset relationship is less than, the aforementioned bit cell group, first matching line, and second matching line can also achieve not less than or less than matching.

[0041] In another possible implementation, the first switching unit includes a third transistor and a fourth transistor. The third transistor is connected to one end of the first memory cell and the search line driving unit, and the fourth transistor is connected to the other end of the first memory cell and the search line driving unit. Both the third and fourth transistors are connected to the gate of the first transistor. The second switching unit includes a fifth transistor and a sixth transistor connected together. The fifth transistor is connected to the first memory cell and ground, and the sixth transistor is connected to the search line driving unit and the first matching line. The third switching unit includes a seventh transistor and an eighth transistor connected together. The seventh transistor is connected to one end of the second memory cell and the search line driving unit, and the eighth transistor is connected to the other end of the second memory cell and the search line driving unit. Both the seventh and eighth transistors are connected to the gate of the second transistor. The fourth switching unit includes a ninth transistor and a tenth transistor connected together. The ninth transistor is connected to the second memory cell and ground, and the tenth transistor is connected to the search line driving unit and the second matching line. This provides specific implementations of the above-described switching units. It should be understood that each switching unit can also achieve its function using more transistors.

[0042] In another possible implementation, the sixth and tenth transistors are connected to the search line drive unit via different search lines, the fifth transistor is connected to the first terminal of the first memory cell, and the ninth transistor is connected to the second terminal of the second memory cell. This implementation achieves a heterogeneous bit cell by controlling the grounding of the first matching line via the second switching unit in a different way than by controlling the grounding of the second matching line via the fourth switching unit. This allows the first preset relationship and the second preset relationship to be set differently.

[0043] In another possible implementation, the amplification unit includes a first sensitive amplifier and a second sensitive amplifier, and the matching signal unit includes a first NOT gate, a second NOT gate, and a first AND gate. The first sensitive amplifier is connected to the first matching line and the first NOT gate, the second sensitive amplifier is connected to the second matching line and the second NOT gate, and the first AND gate is connected to both the first NOT gate and the second NOT gate. In this content-addressable memory, the first sensitive amplifier amplifies the voltage at the first terminal of the first matching line to a first amplified voltage, the second sensitive amplifier amplifies the voltage at the first terminal of the second matching line to a second amplified voltage, the first NOT gate inverts the first amplified voltage, the second NOT gate inverts the second amplified voltage, and the first AND gate performs a bitwise AND operation between the inverted second amplified voltage and the inverted first amplified voltage to obtain the range matching result.

[0044] In another possible implementation, the matching signal unit further includes a second AND gate, which connects a second sensitive amplifier and a third sensitive amplifier. The third sensitive amplifier is connected to the first matching line of the second bit cell group, which is adjacent to the first bit cell group. The second AND gate performs an AND operation on the levels output by the matching lines connected to the adjacent bit cell groups, thereby outputting a new range matching result. The range corresponding to this range matching result lies between the two ranges stored in the adjacent bit cells. Therefore, for more than three consecutive intervals, this content-addressable memory can save hardware resources occupied by range matching.

[0045] In another possible implementation, the sixth and tenth transistors are connected to the search line driver unit via a search line, the fifth transistor is connected to the first terminal of the first memory cell, and the ninth transistor is connected to the first terminal of the second memory cell. This provides another feasible bit unit.

[0046] In another possible implementation, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate; the fourth sensitive amplifier is connected to the first matching line and the third NOT gate, the fifth sensitive amplifier is connected to the second matching line, and the third AND gate is connected to the third NOT gate and the fifth sensitive amplifier, respectively. This provides another amplification unit and matching signal unit.

[0047] In another possible implementation, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate. The fourth sensitive amplifier is connected to the first matching line, the fifth sensitive amplifier is connected to the second matching line and the third NOT gate, and the third AND gate is connected to the third NOT gate and the fourth sensitive amplifier, respectively. This provides another amplification unit and matching signal unit.

[0048] In another possible implementation, the matching signal unit further includes a fourth NOT gate and a fourth AND gate; the fourth NOT gate is connected to a sixth sensitive amplifier, the sixth sensitive amplifier is connected to the first matching line of the second bit cell group, and the second bit cell group is adjacent to the first bit cell group; the fourth AND gate is connected to the second sensitive amplifier and the fourth NOT gate.

[0049] The composition, connection relationships, and beneficial effects of each unit in the possible implementation of the third aspect can be found in the corresponding description of the first aspect.

[0050] A fourth aspect provides a content-addressable memory, comprising: a bit cell array, a search line driving unit, a matching signal unit, and a first charging unit; the first charging unit is used to precharge the output terminals of a first matching line and a second matching line to a predetermined voltage; the search line driving unit is used to send a search word to a first bit cell array; the first bit cell array is used to adjust the voltage of the first terminal of the first matching line from the predetermined voltage to ground voltage when the search word and the pre-stored first storage word satisfy a first preset relationship, and to maintain the voltage of the first terminal of the first matching line at the predetermined voltage when the search word and the pre-stored first storage word do not satisfy the first preset relationship; to adjust the voltage of the first terminal of the second matching line from the predetermined voltage to ground voltage when the search word and the pre-stored second storage word satisfy a second preset relationship, and to maintain the voltage of the first terminal of the second matching line at the predetermined voltage when the search word and the pre-stored second storage word do not satisfy the second preset relationship; an amplification unit is used to amplify the voltage of the first terminal of the first matching line to a first amplified voltage, and to amplify the voltage of the first terminal of the second matching line to a second amplified voltage; the matching signal unit is used to output a range matching result according to the first amplified voltage and the second amplified voltage. In this system, the first bit cell group is any row of bit cells in the bit cell array. Each bit cell in the first bit cell group is connected to a first matching line and a second matching line. The first end of the first matching line is connected to the amplification unit and the first charging unit, and the first end of the second matching line is also connected to the amplification unit and the first charging unit. The second end of the first matching line is not grounded, and the second end of the second matching line is grounded. The bits of the first bit cell group are arranged along the first matching line in ascending order of storage bits, with the bit cell storing the lowest storage bit located on the side furthest from the first charging unit. The first charging unit includes a charging switch corresponding to each matching line. The first preset relationship is less than or greater than, and the second preset relationship is not less than or not greater than. Specifically, the first storage word can be equal to the upper limit of the target range, the upper limit of the target range plus one, or the upper limit of the target range minus one. The second storage word can be equal to the lower limit of the target range, the lower limit of the target range plus one, or the lower limit of the target range minus one.

[0051] The first preset relationship, taking "less than" as an example, allows a voltage to be output on the first matching line based on the search word and the first stored word. This voltage indicates whether the search word is less than the upper limit of the target range. The second preset relationship, taking "not less than" as an example, allows a voltage to be output on the second matching line based on the search word and the second stored word. This voltage indicates whether the search word is greater than or equal to the lower limit of the target range. Combining the two voltages outputs a range matching result, which indicates whether the search word is within the target range.

[0052] In one possible implementation, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy a first preset relationship, and turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the first preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to turn on the connection between the second matching line and ground when the second search line signal and the second storage bit satisfy a third preset relationship, and turn off the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the third preset relationship. The first switching unit is connected to the search line driving unit, the gate of the first transistor, and the first bit memory cell, respectively. The source and drain of the first transistor are connected to the first matching line. The second switching unit is connected to the search line driving unit, the first matching line, the first bit memory cell, and ground, respectively. The third switching unit is connected to the search line driving unit, the gate of the second transistor, and the second bit memory cell, respectively. The source and drain of the second transistor are connected to the second matching line, respectively. The fourth switching unit is connected to the search line driving unit, the second matching line, the second bit memory cell, and ground, respectively.

[0053] In this implementation, when the search word is less than the first memory word, the second switching unit of one bit cell will necessarily be turned on, thus the first matching line outputs a ground voltage. When the search word is equal to the first memory word, the first transistors of all bit cells are turned on and the first matching line is not grounded, thus the first matching line outputs a predetermined voltage. When the search word is greater than the first memory word, both the second switching unit and the first transistor of one bit cell will necessarily be turned off, thus the first matching line outputs a predetermined voltage. This achieves less-than matching. When the search word is less than the second memory word, the second switching unit of one bit cell will necessarily be turned on, thus the second matching line outputs a ground voltage. When the search word is equal to the second memory word, the second transistors of all bit cells are turned on and the second matching line is grounded, thus the second matching line outputs a ground voltage. The first bit cell group and the second matching line can achieve less-than or equal matching.

[0054] In another possible implementation, the first switching unit includes a third transistor and a fourth transistor. The third transistor is connected to one end of the first memory cell and the search line driving unit, and the fourth transistor is connected to the other end of the first memory cell and the search line driving unit. Both the third and fourth transistors are connected to the gate of the first transistor. The second switching unit includes a fifth transistor and a sixth transistor connected together. The fifth transistor is connected to the first memory cell and ground, and the sixth transistor is connected to the search line driving unit and the first matching line. The third switching unit includes a seventh transistor and an eighth transistor connected together. The seventh transistor is connected to one end of the second memory cell and the search line driving unit, and the eighth transistor is connected to the other end of the second memory cell and the search line driving unit. Both the seventh and eighth transistors are connected to the gate of the second transistor. The fourth switching unit includes a ninth transistor and a tenth transistor connected together. The ninth transistor is connected to the second memory cell and ground, and the tenth transistor is connected to the search line driving unit and the second matching line. This provides specific implementations of the above-described switching units. It should be understood that each switching unit can also achieve its function using more transistors.

[0055] In another possible implementation, the sixth and tenth transistors are connected to the search line drive unit via different search lines, the fifth transistor is connected to the first terminal of the first memory cell, and the ninth transistor is connected to the second terminal of the second memory cell. This implementation achieves a heterogeneous bit cell by controlling the grounding of the first matching line via the second switching unit in a different way than by controlling the grounding of the second matching line via the fourth switching unit. This allows the first preset relationship and the second preset relationship to be set differently.

[0056] In another possible implementation, the amplification unit includes a first sensitive amplifier and a second sensitive amplifier, and the matching signal unit includes a first NOT gate, a second NOT gate, and a first AND gate. The first sensitive amplifier is connected to the first matching line and the first NOT gate, the second sensitive amplifier is connected to the second matching line and the second NOT gate, and the first AND gate is connected to both the first NOT gate and the second NOT gate. In this content-addressable memory, the first sensitive amplifier amplifies the voltage at the first terminal of the first matching line to a first amplified voltage, the second sensitive amplifier amplifies the voltage at the first terminal of the second matching line to a second amplified voltage, the first NOT gate inverts the first amplified voltage, the second NOT gate inverts the second amplified voltage, and the first AND gate performs a bitwise AND operation between the inverted second amplified voltage and the inverted first amplified voltage to obtain the range matching result.

[0057] In another possible implementation, the matching signal unit further includes a second AND gate, which connects a second sensitive amplifier and a third sensitive amplifier. The third sensitive amplifier is connected to the first matching line of the second bit unit group, and the second bit unit group is adjacent to the first bit unit group.

[0058] In another possible implementation, the sixth and tenth transistors are connected to the search line drive unit via a search line, the fifth transistor is connected to the first end of the first memory cell, and the ninth transistor is connected to the first end of the second memory cell.

[0059] In another possible implementation, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate; the fourth sensitive amplifier is connected to the first matching line and the third NOT gate, the fifth sensitive amplifier is connected to the second matching line, and the third AND gate is connected to the third NOT gate and the fifth sensitive amplifier respectively.

[0060] In another possible implementation, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, the matching signal unit includes a third NOT gate and a third AND gate, the fourth sensitive amplifier is connected to the first matching line, the fifth sensitive amplifier is connected to the second matching line and the third NOT gate, and the third AND gate is connected to the third NOT gate and the fourth sensitive amplifier respectively.

[0061] In another possible implementation, the matching signal unit further includes a fourth NOT gate and a fourth AND gate; the fourth NOT gate is connected to a sixth sensitive amplifier, the sixth sensitive amplifier is connected to the first matching line of the second bit cell group, and the second bit cell group is adjacent to the first bit cell group; the fourth AND gate is connected to the second sensitive amplifier and the fourth NOT gate.

[0062] The composition, connection relationships, and beneficial effects of each unit in the possible implementation of the fourth aspect can be found in the corresponding description of the first aspect.

[0063] A fifth aspect provides a network device including a processor and a content-addressable memory as described in any of the possible implementations of the first to fourth aspects. The processor is configured to receive a target range, determine a first storage word based on the upper limit of the target range, determine a second storage word based on the lower limit of the target range, and send the first storage word and the second storage word to the content-addressable memory. Optionally, the first storage word is equal to the upper limit of the target range, plus one, or minus one; and the second storage word is equal to the lower limit of the target range, plus one, or minus one.

[0064] A sixth aspect provides a chip system including a processor and a content-addressable memory, wherein the content-addressable memory is a content-addressable memory in any of the possible implementations of the first to fourth aspects. Attached Figure Description

[0065] Figure 1A A schematic diagram of a content-addressable memory; Figure 1B Another schematic diagram of content-addressable memory; Figure 2 This is a structural diagram of a bit cell in an existing tri-state content-addressable memory. Figure 3 This is a structural diagram of a content-addressable memory in an embodiment of this application; Figure 4 This is another structural diagram of the content-addressable memory in the embodiments of this application; Figure 5 This is a structural diagram of a mezzanine unit in an embodiment of this application; Figure 6 This is a schematic diagram showing the connection of the bit unit, the first charging unit, the amplification unit and the matching signal unit in an embodiment of this application; Figure 7 This is another schematic diagram showing the connection between the bit unit, the first charging unit, the amplification unit, and the matching signal unit in an embodiment of this application; Figure 8 This is another structural diagram of the intermediate unit in the embodiments of this application; Figure 9 This is another schematic diagram showing the connection between the bit unit, the first charging unit, the amplification unit, and the matching signal unit in an embodiment of this application; Figure 10 This is another schematic diagram showing the connection between the bit unit, the first charging unit, the amplification unit, and the matching signal unit in an embodiment of this application; Figure 11 This is another structural diagram of the content-addressable memory in the embodiments of this application; Figure 12 This is another structural diagram of the content-addressable memory in the embodiments of this application; Figure 13 This is another structural diagram of the intermediate unit in the embodiments of this application; Figure 14 This is another schematic diagram showing the connection between the bit unit, the first charging unit, the amplification unit, and the matching signal unit in an embodiment of this application; Figure 15 This is another schematic diagram showing the connection between the bit unit, the first charging unit, the amplification unit, and the matching signal unit in an embodiment of this application; Figure 16 This is another structural diagram of the content-addressable memory in the embodiments of this application; Figure 17 This is another structural diagram of the content-addressable memory in the embodiments of this application; Figure 18 This is another structural diagram of the content-addressable memory in the embodiments of this application; Figure 19 This is a structural diagram of a router in an embodiment of this application. Detailed Implementation

[0066] The content-addressable memory described in this application can be applied to network devices, including but not limited to routers or switches. Core routers used to connect backbone networks have interface speeds reaching 400 gigabits per second (Gbps), with single-line card forwarding reaching Tbps levels (1 Tbps = 1024 Gbps). Such speeds require core routers to forward hundreds of millions or even billions of data packets per second, and a key step in this process is table lookup (such as routing tables).

[0067] The lookup functions of network devices include, but are not limited to, longest prefix matches (LPM), exact matches (EM), wildcard matches, and range matches.

[0068] Wildcard matching refers to matching a search term with a stored term when either the search term or the stored term contains the letter 'X'. A stored term is also called a table entry. Wildcard matching is required in pattern recognition.

[0069] Exact match means that the search term and the stored term match when neither the search term nor the stored term contains X.

[0070] Longest prefix matching refers to the matching of the search word and the stored word when both contain the prefix "X", and the matched stored word contains the fewest instances of "X". "X" is also called the "don't care" bit, and can also be used as... Mark it.

[0071] Range matching refers to the process where a search term matches the target range if it falls within that range, and vice versa. For example, range matching is required when looking up access control lists (ACLs) or routes.

[0072] Some routers currently use TCAM for table lookups. TCAM allows for parallel lookups to achieve high-speed table lookups. Each bit in TCAM can store 0, 1, or X. Storing an X bit indicates a masked lookup; the lookup operation has no impact on the matching result. It can conveniently store entries with prefixes of different lengths, thus achieving longest prefix matching.

[0073] TCAM includes NAND TCAM and NOR TCAM. Figure 2 This is a schematic diagram of a non-TCAM bit cell.

[0074] like Figure 2As shown, when the first bit line BL is high, it indicates that the stored bit is X; when BL is low, it indicates that the stored bit is not X. When BL is low and the second bit line BL# is high, it indicates that the stored bit is the binary number 1; when BL is low and BL# is low, it indicates that the stored bit is the binary number 0. The level of BL# is opposite to the level of BL.

[0075] For searching data, when the search line SL is low and the search line SL# is high, the search bit is 0; when SL is high and SL# is low, the search bit is 1; and when both SL and SL# are high, the search bit is X. The level of SL# is opposite to that of SL.

[0076] A low level corresponds to the binary number 0, and a high level corresponds to the binary number 1. The correspondence between the storage bit line level and the value of the storage bit is shown in Table 1:

[0077] Table 1

[0078] The correspondence between the search bit line level and the search bit is shown in Table 2:

[0079] Table 2

[0080] When both the storage bit and the search bit are X, the search bit is determined to match the storage bit, thus enabling wildcard matching.

[0081] When both the storage bit and the search bit are 1, a match is determined between the search bit and the storage bit. When both the storage bit and the search bit are 0, a match is determined between the search bit and the storage bit. When the storage bit is 1 and the search bit is 0, a mismatch is determined between the search bit and the storage bit. When the storage bit is 0 and the search bit is 1, a mismatch is determined between the search bit and the storage bit. This allows for an exact match.

[0082] Non-TCAM bit cells are connected in series via a match line, representing a logical AND operation. For example, a row of bit cells can include n bit cells, which can store a storage word. The i-th bit cell stores the i-th bit of that storage word. Each bit cell is connected to SL and SL#, through which the search bit is received.

[0083] A high-level signal is transmitted from the i-th search bit to the (i+1)-th bit only when the i-th search bit matches the i-th storage bit. If the i-th search bit does not match the i-th storage bit, the i-th bit will disconnect the match line, and the high-level signal cannot be transmitted to the (i+1)-th bit. Thus, the match between the search word and the storage word can be determined by detecting the voltage at the output of the match line. A voltage of 0 at the output of the match line indicates a mismatch, while a voltage of 1 at the output indicates a match, where i is a positive integer not greater than n.

[0084] A storage word is also called a table entry, and the problem of range matching using multiple storage words is also known as the table entry bloat problem. Refer to Table 3; the table entry bloat rate of TCAM is described below:

[0085] Table 3

[0086] Under the three standard test sets A, B, and C, the average number of ACL entries is 242, with range entries accounting for an average of 24%. Using TCAM to represent 242 ACL entries requires 1009 TCAM entries, resulting in an average entry bloat rate of 4.21 times. This application proposes several content-addressable memories that can reduce entry bloat. The following sections describe these content-addressable memories: In the first type of content-addressable memory, both the first and second matching lines are not grounded. Less-than-match and greater-than-match operations can be performed via the first matching line, and the same applies to the second matching line.

[0087] In the second type of content-addressable memory, both the first matching line and the second matching line are grounded. The first matching line allows for both less-than and greater-than matching, and the second matching line also allows for both less-than and greater-than matching.

[0088] In the third type of content-addressable memory, the first matching line is grounded and the second matching line is not grounded. The first matching line allows for at least-or-greater-than matching, while the second matching line allows for less-or-greater-than matching.

[0089] In the fourth type of content-addressable memory, the first matching line is not grounded and the second matching line is grounded. Less-than or greater-than matching can be achieved through the first matching line, and no-less-than or no-greater-than matching can be achieved through the second matching line.

[0090] First, we will introduce the first type of content-addressable memory, see [reference]. Figure 3 One embodiment of the content-addressable memory 30 of this application includes: The system comprises a bit cell array 31, a search line drive unit 32, an amplification unit 33, a matching signal unit 34, and a first charging unit 35.

[0091] The bit cell array 31 includes one or more bit cell groups, each bit cell group is used to store two storage words, and the size of each storage word can be set according to actual needs. The first bit cell group can be any one of the multiple bit cell groups. Specifically, the first bit cell group can be any row of bit cells in the bit cell array 31.

[0092] See Figure 4 In one example, the bit cell array 31 includes m bit cell groups, namely bit cell group 311, bit cell group 312, ..., bit cell group 31m. Each bit cell group can include n bit cells, for example, bit cell group 311 includes n bit cells, namely bit cell group 3111, bit cell group 3112, ..., bit cell group 311n. m and n are positive integers, and the values ​​of m and n can be designed according to the actual situation.

[0093] The bit cell array 31 and the amplification unit 33 are connected by a matching line set 36. Specifically, the matching line set 36 includes multiple matching lines. Each matching line can be understood as multiple matching line segments separated by bit cells, and each bit cell connects two matching line segments.

[0094] Each bit cell group is connected to two matching lines. One matching line can be denoted as the first matching line, and the other as the second matching line. The first matching line can be called the upper matching line, and the second matching line can be called the lower matching line. For example, the first matching line corresponding to the first bit cell group 311 is matching line 361, and the second matching line corresponding to the first bit cell group 311 is matching line 362. The first matching line corresponding to the second bit cell group 312 is matching line 363, and the second matching line corresponding to the second bit cell group 312 is matching line 364.

[0095] Each bit cell in bit cell group 311 is connected to matching lines 361 and 362. The first end of matching line 361 is connected to sensitive amplifier 331 and charging switch 351, and the first end of matching line 362 is connected to sensitive amplifier 332 and charging switch 352. Each bit cell in bit cell group 312 is connected to matching lines 363 and 364. The first end of matching line 363 is connected to sensitive amplifier 333 and charging switch 353, and the first end of matching line 364 is connected to sensitive amplifier 334 and charging switch 354. The connection relationships between other matching lines and bit cell groups, sensitive amplifiers, and charging switches can be deduced similarly, and will not be elaborated here.

[0096] It should be understood that the first end and the second end refer to two ends in different directions. Figure 4In the content-addressable memory shown, the first end of the mating line refers to the right end of the mating line, and the second end refers to the left end. In other examples, the first end of the mating line can also be the left end, and the second end refers to the right end. When the mating line is arranged vertically, the first end can be the upper end, and the second end the lower end. Alternatively, the first end can be the lower end, and the second end the upper end.

[0097] It should be understood that each content-addressable memory also includes multiple bit lines, and each bit cell receives a storage bit through a storage bit line pair. A storage bit line pair includes two storage bit lines, one of which can be denoted as BL and the other as BL#. Each bit cell includes a first storage unit and a second storage unit, and the first and second storage units can each store 1 bit, so each bit cell can store 2 bits.

[0098] The number of bits in a storage word can be less than or equal to n. For example, if n is 32, the storage word includes 8 storage bits, with bit unit 3111 storing the lowest storage bit and bit unit 3118 storing the highest storage bit. The order of the storage bits corresponding to the bit units can be from low to high or from high to low. In the first bit unit group 311, the bit unit 3111 storing the lowest storage bit is located on the side away from the first charging unit 35. The distance from the i-th bit unit to the first connection point is greater than the distance from the (i+1)-th bit unit to the first connection point, where i is a positive integer not greater than n-1. The first connection point is the connection point between the first charging unit 35 and the matching line 361. The arrangement of bit units in other bit unit groups is similar to that in the first bit unit group 311.

[0099] The search line driving unit 32 is connected to the bit cell array 31 through multiple search lines. Each bit cell and the search line driving unit 32 are connected through a search line pair. A search line pair includes two search lines, one of which can be denoted as SL and the other as SL#. The correspondence between search lines and search bits can be found in Table 2.

[0100] The search line driving unit 32 can send search bits to each bit unit through search line pairs. Multiple search bits received by a bit unit group from the search line driving unit 32 constitute a search word. For example, bit unit group 311 receives 8 search bits, and these 8 search bits constitute a search word. The number of search bits and the value of n can be set according to the actual situation.

[0101] Amplification unit 33 amplifies the voltage of matching line 36. Amplification unit 33 includes multiple sensitive amplifiers, such as sensitive amplifier 331, sensitive amplifier 332, sensitive amplifier 333, and sensitive amplifier 334. Each sensitive amplifier is connected to a matching line to amplify the voltage output by that matching line.

[0102] The first charging unit 35 connects to an external power source and a matching line, and is used to pre-charge one or more matching lines; therefore, it can also be called a pre-charging unit. Specifically, the first charging unit 35 includes multiple charging switches, each connected to a matching line. Figure 4 As shown, the first charging unit 35 includes charging switches 351, 352, 353, and 354. For example, when charging switch 351 is turned on, the external power supply charges the matching line 361, causing the level of the matching line 361 to be high. When charging switch 351 is turned off, the level of the matching line 361 is low.

[0103] For ease of understanding, the first bit cell group below will be introduced using bit cell group 311 as an example, the first matching line of the first bit cell group will be introduced using matching line 361 as an example, and the second matching line of the first bit cell group will be introduced using matching line 362 as an example.

[0104] The first type of bit unit is described below; please refer to [link / reference]. Figure 5 In one optional embodiment, each bit unit includes a first transistor T1, a second transistor T2, a first switching unit 501, a second switching unit 502, a third switching unit 503, a fourth switching unit 504, a first storage unit 505, and a second storage unit 506.

[0105] The first switching unit 501 is used to turn on the first transistor T1 when the search bit is equal to the first storage bit, and turn off the first transistor T1 when the search bit is not equal to the first storage bit. The source and drain of the first transistor T1 are connected to the matching line 361. The second switching unit 502 is used to turn on the connection between the matching line 361 and ground when the first search line signal and the first storage bit satisfy the first preset relationship, and to turn off the connection between the matching line 361 and ground when the first search line signal and the first storage bit do not satisfy the first preset relationship. The first search line signal is a signal from the search line SL#. The third switching unit 503 is used to turn on the third transistor T3 when the search bit is equal to the second storage bit, and turn off the third transistor T3 when the search bit is not equal to the second storage bit. The source and drain of the third transistor T3 are connected to the matching line 362. The fourth switching unit 504 is used to connect the matching line 362 to ground when the second search line signal and the second storage bit satisfy the second preset relationship, and to disconnect the matching line 362 from ground when the second search line signal and the second storage bit do not satisfy the second preset relationship. The second search line signal is a signal from the search line SL.

[0106] In this embodiment, the second switch unit 502 is connected to the search line SL#, the matching line 361, the first storage unit 505, and ground; the fourth switch unit 504 is connected to the search line SL, the matching line 362, the second storage unit 506, and ground. The search line signal is the search line level, and its value can be 0 or 1.

[0107] The first storage cell 505 is connected to the first bit line BL and the second bit line BL#, and the second storage cell 506 is also connected to the first bit line BL and the second bit line BL#. The first storage cell 505 can store one bit of a first storage word, and the second storage cell 506 can store one bit of a second storage word. The first storage cell 505 and the second storage cell 506 can be a single SRAM storage cell, and a single SRAM storage cell includes, but is not limited to, six transistors.

[0108] The first storage word consists of n1 storage bits, and the second storage word consists of n2 storage bits, where n1 and n2 are both positive integers. When i is a positive integer less than or equal to n1, the first storage bit stored in the i-th bit unit is the i-th storage bit of the first storage word. When i is a positive integer less than or equal to n2, the second storage bit stored in the i-th bit unit is the i-th storage bit of the second storage word.

[0109] When the storage bit and the search bit are equal, the first transistor T1 of the i-th bit unit is turned on and the second switch unit 502 is turned off, allowing a high-level voltage (i.e., a predetermined voltage) to pass through the i-th bit unit along the matching line 361. When the relationship between the storage bit and the search bit satisfies a first preset relationship, the second switch unit 502 of the i-th bit unit is turned on, and the right-side matching line connected to the i-th bit unit on the matching line 361 is grounded. Similarly, when the storage bit and the search bit are equal, the second transistor T2 of the i-th bit unit is turned on and the second switch unit 502 is turned off, allowing a high-level voltage (i.e., a predetermined voltage) to pass through the i-th bit unit along the matching line 362. When the storage bit and the search bit satisfy a second preset relationship, the second switch unit 502 of the i-th bit unit is turned on, and the right-side matching line connected to the i-th bit unit on the matching line 362 is grounded.

[0110] In the following, the working process of the bit unit when the first preset relationship is "less than" is described. When the search word is less than the first storage word, there are n1 bit comparison results, where the bit comparison result refers to a result obtained by comparing one storage bit with one search bit. The bit comparison result may be: less than, equal to, or greater than. The bit unit corresponding to the first bit comparison result that is "less than" from right to left is denoted as the i1-th bit unit. When i1<n1, the first transistor T1 of the i1-th bit unit is turned off and the second switch unit 502 is turned on, and the first transistor T1 of each of the bit units from the (i1+1)-th bit unit to the n1-th bit unit is turned on and the second switch unit 502 thereof is turned off, so that the match line 361 is grounded to output a ground voltage. When i1=n1, the first transistor T1 of the n1-th bit unit is turned off and the second switch unit 502 is turned on, so that the match line 361 is grounded to output a ground voltage.

[0111] When the search word is equal to the first storage word, the first transistors T1 of all the n1 bit units are turned on, and the second switch units 502 included therein are all turned off, so that the match line 361 outputs a predetermined voltage.

[0112] When the search word is greater than the first storage word, the bit unit corresponding to the first bit comparison result that is "greater than" from right to left is denoted as the i2-th bit unit. The total number of search bits in the search word is denoted as n3. When i2<n3, the first transistor T1 of the i2-th bit unit is turned off and the second switch unit 502 is turned off, the first transistor T1 of each of the bit units from the (i2+1)-th bit unit to the n3-th bit unit is turned on and the second switch unit 502 thereof is turned off, and the match line 361 outputs a predetermined voltage. When i2=n3, the first transistor T1 of the n3-th bit unit is turned off and the second switch unit 502 is turned off, and the match line 361 outputs a predetermined voltage.

[0113] In the following, the working process of the bit unit when the second preset relationship is "greater than" is described. When the search word is greater than the second storage word, there are n2 bit comparison results.

[0114] The bit unit corresponding to the first bit comparison result that is "greater than" from right to left is denoted as the i3-th bit unit. When i3<n2, the second transistor T2 of the i3-th bit unit is turned off and the fourth switch unit 504 is turned on, and the second transistor T2 of each of the bit units from the (i3+1)-th bit unit to the n2-th bit unit is turned on and the fourth switch unit 504 thereof is turned off, so that the match line 362 is grounded to output a ground voltage. When i3=n2, the second transistor T2 of the n2-th bit unit is turned off and the fourth switch unit 504 is turned on, so that the match line 362 is grounded to output a ground voltage.

[0115] When the search word is equal to the second storage word, the second transistors T2 of all the n2 bit units are turned on, and the fourth switch units 504 included therein are all turned off, so that the match line 362 outputs a predetermined voltage.

[0116] When the search word is smaller than the second storage word, the bit cell corresponding to the comparison result of the first bit that satisfies "smaller" from right to left is denoted as the i4-th bit cell. When i4 is less than n3, the second transistor T2 of the i4-th bit cell is turned off and the fourth switch unit 504 is turned off, and the second transistor T2 of each bit cell from the (i4+1)-th bit cell to the n3-th bit cell is turned on and the fourth switch unit 504 is turned off, so that the match line 362 outputs a predetermined voltage. When i4 is equal to n3, the second transistor T2 of the n3-th bit cell is turned off and the fourth switch unit 504 is turned off, and the match line 362 outputs a predetermined voltage.

[0117] The ground voltages output by the two match lines can be respectively used to identify that the search word is smaller than the first storage word and that the search word is larger than the second storage word, so as to implement the judgment function. Similarly, for the case where the first preset relationship is greater than and / or the second preset relationship is less than, a corresponding identification voltage can also be output. Therefore, the above bit cell can be used to output voltages identifying the first preset relationship and the second preset relationship, so as to implement the judgment function.

[0118] It should be noted that, in the present application, that the preset relationship is less than means that the search word is smaller than the first storage word, that the preset relationship is greater than means that the search word is larger than the first storage word, that the preset relationship is not less than means that the search word is not smaller than the first storage word, and that the preset relationship is not greater than means that the search word is not larger than the first storage word. On this basis, the specific meanings of the first preset relationship, the second preset relationship, the third preset relationship and the fourth preset relationship can be known.

[0119] In another optional embodiment, the second switch unit 502 is connected to the search line SL, the match line 361, the first bit storage unit 505 and the ground, and the fourth switch unit 504 is connected to the search line SL#, the match line 362, the second bit storage unit 506 and the ground. In this embodiment, the first search line signal is a signal from the search line SL, and the second search line signal is a signal from the search line SL#.

[0120] The first switch unit 501, the second switch unit 502, the third switch unit 503, and the fourth switch unit 504 are described below.

[0121] Refer to Figure 5 , the first switch unit 501 includes a third transistor T3 and a fourth transistor T4, the third transistor T3 is connected to one end of the first bit storage unit 501 and the search line driving unit, the fourth transistor T4 is connected to the other end of the first bit storage unit 501 and the search line driving unit, and both the third transistor T3 and the fourth transistor T4 are connected to the gate of the first transistor T1; The second switching unit 502 includes a fifth transistor T5 and a sixth transistor T6 connected together, and the fifth transistor T5 is connected to the first memory unit 505 and ground, and the sixth transistor T6 is connected to the search line driving unit and the matching line 361. The third switching unit 503 includes a seventh transistor T7 and an eighth transistor T8 connected together. The seventh transistor T7 is connected to one end of the second bit storage unit 506 and the search line driving unit, and the eighth transistor T8 is connected to the other end of the second bit storage unit 506 and the search line driving unit. Both the seventh transistor T7 and the eighth transistor T8 are connected to the gate of the second transistor T2. The fourth switching unit 504 includes a ninth transistor T9 and a tenth transistor T10 connected together. The ninth transistor T9 is connected to the second bit storage unit 506 and ground, and the tenth transistor T10 is connected to the search line drive unit and the matching line 362.

[0122] In this embodiment, the third transistor T3 is connected to the search line driving unit via search line SL, and the fourth transistor T4 and the sixth transistor T6 are respectively connected to the search line driving unit via search line SL#. The seventh transistor T7 and the tenth transistor T10 are connected to the search line driving unit via search line SL, and the eighth transistor T8 is connected to the search line driving unit via search line SL#. The fifth transistor T5 is connected to the first terminal of the first memory cell 505, and the ninth transistor T9 is connected to the second terminal of the second memory cell 506.

[0123] In the first type of bit cell, the second switching unit 502 and the fourth switching unit 504 are connected to the search line driving unit 32 via different search lines. The fifth transistor T5 of the second switching unit 502 is connected to the first terminal of the first bit storage unit 505, and the ninth transistor T9 of the fourth switching unit 504 is connected to the second terminal of the second bit storage unit 506. The first terminal and the second terminal are different. For example, the first terminal is the left terminal and the second terminal is the right terminal. Or, the first terminal is the right terminal and the second terminal is the left terminal. Because the upper and lower parts of the bit cell are not similar, the first type of bit cell is also called a heterogeneous bit cell.

[0124] The above is only a specific example of the first switching unit 501, the second switching unit 502, the third switching unit 503, and the fourth switching unit 504. It should be understood that the above switching units can also implement their functions using more transistors.

[0125] for Figure 5 The bit unit group shown can be used in this application to provide corresponding amplification units and matching signal units to output matching results. The amplification unit and matching signal are described below; please refer to [reference needed]. Figure 6In one optional embodiment, the first bit unit group 311 includes bit unit 3111, bit unit 3112, ..., bit unit 311n. Charging switch 351 is connected to matching line 361, and charging switch 352 is connected to matching line 362. The amplification unit includes sensitive amplifier 331 and sensitive amplifier 332. The matching signal unit includes a first NOT gate 3401, a second NOT gate 3402, and a first AND gate 3403. Sensitive amplifier 331 is connected to matching line 361 and the first NOT gate 3401, sensitive amplifier 332 is connected to matching line 362 and the second NOT gate 3402, and the first AND gate 3403 is connected to both the first NOT gate 3401 and the second NOT gate 3402.

[0126] In this embodiment, sensitive amplifier 331 amplifies the voltage at the first terminal of matching line 361 to a first amplified voltage, and sensitive amplifier 332 amplifies the voltage at the first terminal of matching line 362 to a second amplified voltage. First NOT gate 3401 inverts the first amplified voltage, second NOT gate 3402 inverts the second amplified voltage, and first AND gate 3403 performs a bitwise AND operation between the inverted second amplified voltage and the inverted first amplified voltage to obtain a range matching result. It should be understood that inverting the ground voltage results in a high level, and inverting the predetermined voltage results in a low level. When the range matching result is high, it indicates that both the first and second matching lines output ground voltage. When the range matching result is low, it indicates that at least one matching line outputs the predetermined voltage. This provides a practical amplification unit and a matching signal unit.

[0127] exist Figure 6 Based on the illustrated embodiment, adding an AND gate to the matching signal unit 34 can output a wider range of matching results. See also... Figure 7 In another alternative embodiment, charging switch 353 is connected to matching line 363, and charging switch 354 is connected to matching line 364. The matching signal unit also includes a second AND gate 3404, which is connected to sensitive amplifier 332 and sensitive amplifier 333. Sensitive amplifier 333 is connected to the first matching line 363 of the second bit unit group 312, and the second bit unit group 312 is adjacent to the first bit unit group 311.

[0128] In this embodiment, the matching lines connected to the second bit unit group 312 include matching line 363 and matching line 364, and matching line 364 is connected to the sensitive amplifier 334. Matching line 364 is similar to matching line 362, and sensitive amplifier 334 is similar to sensitive amplifier 332, which will not be described again here.

[0129] Specifically, range 1 is (low1, high1), range 2 is [high1, low2), and range 3 is (low2, high2). When the first preset relationship is less than and the second preset relationship is greater than, the first storage word stored in the first bit cell group 311 is high2, and the second storage word is low2. The first storage word stored in the second bit cell group 312 is high1, and the second storage word is low1, so that it can be determined whether the search word belongs to (low1, high1) and whether the search word belongs to (low2, high2). Since data≥high1 is equivalent to !(data<high1), and data≤low2 is equivalent to !(data>low2), it can be determined whether data belongs to [high1, low2) according to the output voltage of the first match line 363 of the second bit cell group 312 and the output voltage of the match line 362 of the first bit cell group 311. Since no additional bit cells are allocated for [high1, low2), the hardware resources occupied by range matching can be reduced.

[0130] The second type of bit cell is described below, with reference to Figure 8 , in another optional embodiment, each bit cell includes a first transistor T1, a second transistor T2, a first switch unit 801, a second switch unit 802, a third switch unit 803, a fourth switch unit 804, a first bit storage unit 805 and a second bit storage unit 806.

[0131] The first switch unit 801 is configured to turn on the first transistor T1 when the search bit is equal to the first storage bit, and turn off the first transistor T1 when the search bit is not equal to the first storage bit, and the source and drain of the first transistor T1 are connected to the match line 361; The second switch unit 802 is configured to turn on the connection between the match line 361 and the ground when the first search line signal and the first storage bit satisfy a first preset relationship, and turn off the connection between the match line 361 and the ground when the first search line signal and the first storage bit do not satisfy the first preset relationship; The third switch unit 803 is configured to turn on the second transistor T2 when the search bit is equal to the second storage bit, and turn off the second transistor T2 when the search bit is not equal to the second storage bit, and the source and drain of the second transistor T2 are connected to the match line 362; The fourth switch unit 804 is configured to turn on the connection between the match line 362 and the ground when the second search line signal and the second storage bit satisfy a second preset relationship, and turn off the connection between the match line 362 and the ground when the second search line signal and the second storage bit do not satisfy the second preset relationship.

[0132] In this embodiment, the first search line signal and the second search line signal are the same. The second switch unit 802 and the fourth switch unit 804 are connected to the search line SL#, and both the first search line signal and the second search line signal are signals from the search line SL#.

[0133] The first switch unit 801, the second switch unit 802, the third switch unit 803, the fourth switch unit 804, the first storage unit 805, and the second storage unit 806 are respectively connected to... Figure 5 The first switch unit 501, the second switch unit 502, the third switch unit 503, the fourth switch unit 504, the first storage unit 505, and the second storage unit 506 in the illustrated embodiment or optional embodiment are similar and will not be described again here.

[0134] In the second type of bit unit, the second switching unit 802 and the fourth switching unit 804 are connected to the search line driving unit 32 via the same search line. The fifth transistor T5 of the second switching unit 802 is connected to the first terminal of the first bit storage unit 805, and the ninth transistor T9 of the fourth switching unit 804 is connected to the first terminal of the second bit storage unit 806. The first terminal can be either the left or right terminal. Because the upper and lower parts of the bit unit are similar, the second type of bit unit is also called a homogeneous bit unit. Specifically, the bit unit includes two matching circuits, both of which are either less than a matching circuit, greater than a matching circuit, not greater than a matching circuit, or not less than a matching circuit.

[0135] In another alternative embodiment, the second switching unit 802 and the fourth switching unit 804 are connected to the search line SL. The fifth transistor T5 of the second switching unit 802 is connected to the second terminal of the first memory cell 805, and the ninth transistor T9 of the fourth switching unit 804 is connected to the second terminal of the second memory cell 806. The second terminal is different from the first terminal. Both the first search line signal and the second search line signal originate from the search line SL.

[0136] for Figure 8 The bit unit group shown can be used in this application to provide corresponding amplification units and matching signal units to output matching results. The amplification unit and matching signal unit are described below; please refer to [reference needed]. Figure 9In another optional embodiment, the first bit unit group 311 includes bit unit 3111, bit unit 3112, ..., bit unit 311n. Charging switch 351 is connected to matching line 361, and charging switch 352 is connected to matching line 362. The amplification unit includes sensitive amplifier 331 and sensitive amplifier 332, and the matching signal unit includes a third NOT gate 3411 and a third AND gate 3412; sensitive amplifier 331 is connected to matching line 361 and the third NOT gate 3411, sensitive amplifier 332 is connected to matching line 362, and the third AND gate 3412 is connected to the third NOT gate 3411 and the sensitive amplifier 332 respectively.

[0137] In this embodiment, sensitive amplifier 331 amplifies the voltage at the first end of matching line 361 to a first amplified voltage, sensitive amplifier 332 amplifies the voltage at the first end of matching line 362 to a second amplified voltage, third NOT gate 3411 inverts the first amplified voltage, and third AND gate 3412 performs an AND operation on the second amplified voltage and the inverted first amplified voltage to obtain a range matching result. This provides a concrete and feasible amplification unit 33 and matching signal unit 34.

[0138] The above are merely illustrative examples of the amplification unit and the matching signal unit. It should be understood that the matching signal unit can also implement its function through combinations of NOT gates, AND gates, and OR gates. In the embodiments of this application, only a portion of some units (e.g., the amplification unit, the matching signal unit, the first charging unit, the matching line set, etc.) are shown to facilitate the description of their operation. It should be understood that the above examples should not be considered as limitations on this application.

[0139] The following is combined Figure 9 The matching signal unit shown illustrates the process of range matching in content-addressable memory: Both the first and second preset relations are less than. Taking the target range (10, 100) as an example, the first storage word is 100, and the second storage word is 11. The first storage word includes 9 storage bits, and the second storage word includes 4 storage bits.

[0140] After receiving 100 and 11 from the bit line, the bit unit group 311 stores the storage bits of the first storage word from low to high in bit units 3111 to bit units 3119, and stores each storage bit of the second storage word in bit units 3111 to bit units 3114.

[0141] When charging switch 351 and charging switch 352 are turned on, the right end of matching line 361 and the right end of matching line 362 can be precharged to a predetermined voltage.

[0142] Taking the search word 20 obtained by bit unit group 311 from search line drive unit 32 as an example, since 20 and 100 satisfy the first preset relationship (i.e., the search word is less than the first storage word), bit unit 3119 grounds the matching line 361, causing the matching line 361 to output a ground voltage. Since 20 and 11 do not satisfy the second preset relationship (i.e., the search word is less than the second storage word), bit units 3111 to bit units 3114 maintain the voltage of the matching line 362 at a predetermined voltage.

[0143] Sensitive amplifier 331 amplifies the ground voltage, and sensitive amplifier 332 amplifies the predetermined voltage.

[0144] The third NOT gate 3411 inverts the amplified ground voltage. Since the inverted ground voltage is high and the predetermined voltage is high, the first AND gate 3412 outputs a high level based on the inverted ground voltage and the predetermined voltage. This high level is used to indicate that the search word 20 is within (10, 100).

[0145] In another example, the target range is (10, 100), and the search word is 10. Since 10 and 100 satisfy the first preset relationship (i.e., the search word is less than the first storage word), bit unit 3119 grounds the matching line 361, causing the matching line 361 to output a ground voltage. Since 10 and 11 satisfy the second preset relationship (i.e., the search word is less than the second storage word), bit unit 3111 grounds the voltage of the second matching line, causing the matching line 362 to output a ground voltage.

[0146] Sensitive amplifier 331 amplifies the ground voltage, and sensitive amplifier 332 amplifies the predetermined voltage.

[0147] The third NOT gate 3411 inverts the amplified ground voltage. Since the inverted ground voltage is high and the ground voltage is low, the first AND gate 3412 outputs a low level based on the high and low levels. This low level is used to indicate that the search word 10 is not within (10,100).

[0148] As can be seen, a single bit unit group in this application can perform range matching on any set range, thus saving hardware resources occupied by range matching and reducing table entry bloat.

[0149] The above describes a method for range matching when the target range is an open interval. This application can also perform range matching when the target range is a closed interval or a half-open / half-closed interval. The target range is described below: The target range can be an open interval, a closed interval, or a half-open / half-closed interval. The upper limit of the target range is denoted as high, and the lower limit of the target range is denoted as low. In this application, since the search word, the first storage word, and the second storage word are all integers, for any positive integer a, greater than a is equivalent to greater than or equal to a+1, and less than a is equivalent to less than a-1.

[0150] When the target open interval is the open interval (low, high), the open interval (low, high) is equivalent to the closed interval [low+1, high-1], and the open interval (low, high) is also equivalent to the half-open and half-closed interval [low+1, high) or (low, high-1).

[0151] When the target range is a closed interval [low, high], the closed interval [low, high] is also equivalent to the open interval (low-1, high+1), and also equivalent to the half-open and half-closed interval [low, high+1) or (low-1, high).

[0152] When the target range is the first type of half-open and half-closed interval [low, high), [low, high) is equivalent to the open interval (low-1, high), and also equivalent to the closed interval [low, high-1] or the half-open and half-closed interval (low-1, high-1).

[0153] When the target range is the second type of half-open and half-closed interval (low, high], (low, high] is equivalent to the open interval (low, high+1), and also equivalent to the closed interval [low+1, high] or the half-open and half-closed interval [low+1, high+1).

[0154] As can be seen from the above, open intervals, closed intervals, and half-open / half-closed intervals can be converted into each other.

[0155] It should be understood that when the target range is an open interval (low, high), the search word being within the target range is equivalent to: determining that the search word is greater than low and less than high.

[0156] When the first preset relationship is less than and the second preset relationship is greater than, the first stored word is high and the second stored word is low.

[0157] When the first preset relationship is less than and the second preset relationship is less than, the first stored word is high. Since data>low is equivalent to !(data<(low +1)), when the second stored word is low+1, inverting the second amplified voltage is equivalent to judging data>low.

[0158] When the first preset relation is greater than and the second preset relation is greater than, the second storage word is low. Since data<high is equivalent to !(data>(high-1)), when the first storage word is high-1, inverting the first amplified voltage is equivalent to determining data<high.

[0159] When the first preset relation is greater than and the second preset relation is less than, data>low is equivalent to !(data<(low+1)), and data<high is equivalent to !(data>(high-1)), so the first storage word is high-1, and the second storage word is low+1.

[0160] When the target range is a closed interval or a half-open half-closed interval, the target range can be converted into an open interval, and then corresponding calculations can be performed to obtain the first storage word and the second storage word.

[0161] It should be noted that when the search word and the storage word satisfy the first preset relation, the voltage output by the match line 361 is the ground voltage. In order to use a high level to indicate that the range match is successful, an inverter needs to be added to invert the ground voltage. When the search word and the storage word do not satisfy the first preset relation, the voltage output by the match line 361 is a predetermined voltage. In order to use a low level to indicate that the range match fails, an inverter needs to be added to invert the predetermined voltage.

[0162] In the Figure 9 on the basis of the illustrated embodiment, AND gates and inverters can be added to output more range matching results. Refer to Figure 10 , in another optional embodiment, the charge switch 353 is connected to the match line 363, and the charge switch 354 is connected to the match line 364. The matching signal unit further comprises a fourth inverter 3413 and a fourth AND gate 3414; the fourth inverter 3413 is connected to the sense amplifier 332, the match line 363 is connected to the sense amplifier 333 and the second bit cell group 312, and the second bit cell group 312 is adjacent to the first bit cell group 311. The fourth AND gate 3414 is connected to the sense amplifier 333 and the fourth inverter 3413.

[0163] In this embodiment, the match lines connected to the second bit cell group 312 include a match line 363 and a match line 364, and the match line 364 is connected to the sense amplifier 334. The match line 364 is similar to the match line 362, the sense amplifier 334 is similar to the sense amplifier 332, the inverter connected to the sense amplifier 333 is similar to the third inverter 3411, and the AND gate connected to the sense amplifier 334 is similar to the third AND gate 3412, which will not be repeated here.

[0164] The following describes the range matching process of the content addressable memory shown in Figure 10 : In an example, range 1 is (low1, high1), range 2 is [high1, low2], and range 3 is (low2, high2). When both the first preset relationship and the second preset relationship are "less than", the first storage word stored in the first bit cell group 311 is high2, and the second storage word is low2+1. The first storage word stored in the second bit cell group 312 is high1, and the second storage word is low1+1. According to Figure 5 the description of the illustrated embodiment, it can be seen that this can determine whether the search word belongs to (low1, high1) and whether the search word belongs to (low2, high2).

[0165] The search word is denoted as data. Since data≥high1 is equivalent to !(data<high1), and data≤low2 is implemented equivalently by data<(low2+1). In this way, it can be determined whether the search word belongs to [high1, low2] according to the output voltage of the match line 363 and the output voltage of the match line 362.

[0166] For example, range 1 is (1, 10), range 2 is [10, 100], range 3 is (100, 200), and the search word is 20. Since 20 and 10 do not satisfy the first preset relationship (that is, the search word is less than the first storage word), the match line 363 outputs a predetermined voltage, and the sense amplifier 333 amplifies the predetermined voltage to a high level. Since 20 and 100 satisfy the second preset relationship (that is, the search word is less than the second storage word), a ground voltage is output. The second NOT gate 3413 inverts the amplified ground voltage to obtain a high level, the second AND gate 3414 performs an AND operation on the high level output by the sense amplifier 333 and the high level output by the second NOT gate, and the high level obtained by the AND operation indicates that the range matching is successful, and the search word 20 belongs to [10, 100].

[0167] Taking the search word 9 as an example, since 9 and 10 satisfy the first preset relationship, the sense amplifier 333 outputs a low level. Since 9 and 100 satisfy the second preset relationship, a ground voltage is output. The second NOT gate 3413 inverts the amplified ground voltage to obtain a high level, the second AND gate 3414 performs an AND operation on the low level output by the sense amplifier 333 and the high level output by the second NOT gate, and the low level obtained by the AND operation indicates that the range matching fails, and the search word 9 does not belong to [10, 100].

[0168] It can be seen that the content-addressable memory of the present application only needs 2 bit cell groups and the above-mentioned matching signal unit to perform three range matches. It can be inferred that m bit cell groups and corresponding matching signal units can perform 2m-1 range matches, where m is a positive integer. For more than three consecutive intervals, the content-addressable memory can save hardware resources occupied by range matching.

[0169] The above describes the method for range matching of content-addressable memory in this application. This application also provides another method for precise matching of content-addressable memory.

[0170] See Figure 11 In another optional embodiment, the content-addressable memory 30 includes a first bit cell group 311, a search line driving unit 32, an amplification unit 33, a matching signal unit 34, a first charging unit 35, and a second charging unit 37. The second charging unit 37 is connected to the second end of the matching line 361 and the second end of the matching line 362. The first bit cell group 311, search line driving unit 32, amplification unit 33, matching signal unit 34, first charging unit 35, matching line 361, and matching line 362 can be found in [reference needed]. Figure 3 The corresponding description in the illustrated embodiment.

[0171] In this embodiment, bit unit group 311 is used to turn on the matching line 361 when the search word is equal to the first storage word, and to turn off the matching line 361 when the search word is not equal to the first storage word; amplification unit 33 is used to amplify the voltage at the first end of the matching line 361; matching signal unit 34 is used to output the amplified voltage at the first end of the matching line 361. And / or, bit unit group 311 is used to turn on the matching line 362 when the search word is equal to the second storage word, and to turn off the matching line 362 when the search word is not equal to the second storage word; amplification unit 33 is used to amplify the voltage at the first end of the matching line 362; matching signal unit 34 is used to output the amplified voltage at the first end of the matching line 362.

[0172] The enabling state of the second charging unit 37 is opposite to that of the first charging unit 35; that is, when the second charging unit 37 is in the working state, the first charging unit 35 is in the non-working state. When the first charging unit 35 is in the working state, the second charging unit 37 is in the non-working state.

[0173] When the second charging unit 37 is in operation, it can charge the matching line 361 to a predetermined voltage. The supply voltage of the second charging unit 37 can be the same as or different from the supply voltage of the first charging unit 35.

[0174] When the search word is equal to the first stored word, a high-level signal is transmitted from the second end of the matching line 361 to the first end of the matching line 361. After being amplified by the amplification unit, a high-level signal is output by the matching signal unit, indicating that the search word is equal to the first stored word. When the search word is not equal to the first stored word, the bit unit group 311 disconnects the matching line 361, and the high-level signal cannot pass through the bit unit group 311. The matching line 361 outputs a low-level signal, which is amplified by the amplification unit 33 and output by the matching signal unit 34, indicating that the search word is not equal to the first stored word. Therefore, this content-addressable memory can achieve precise matching between the search word and any stored word.

[0175] It should be noted that the second charging unit 37 can be connected to one matching line in the content-addressable memory, thus enabling precise matching with a single memory word. The second charging unit 37 can also be connected to multiple matching lines in the content-addressable memory, allowing for simultaneous precise matching with multiple memory words. When the second charging unit 37 is connected to the second end of other matching lines, the operation of the bit cell group and matching lines in the content-addressable memory is similar to... Figure 10 The operation of the bit unit group 311 and the matching line 361 described in the illustrated embodiment is similar.

[0176] The bit unit of this application includes 22 transistors. One bit unit can be used to perform an exact match between a search word and two stored words. Such an exact match requires 11 transistors per bit unit.

[0177] exist Figure 11 Based on the illustrated embodiment, adding a wildcard matching enable line and multiple transistors can achieve wildcard matching. The following section describes this content-addressable memory; please refer to [link / reference]. Figure 12 In another alternative embodiment, the content-addressable memory 30 further includes a wildcard matching enable line 1201, which connects to one or more of a column of bit cells.

[0178] The following describes the connection between the wildcard matching enable line 1201 and the bit cells of the bit cell group 311. (See reference...) Figure 13Each bit unit in the bit unit group also includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13; the eleventh transistor T11 is connected to the second bit storage unit 506 and is used to turn on or off according to the storage bit of the second bit storage unit; the twelfth transistor T12 is connected to the wildcard matching enable line 1201, the eleventh transistor T11, and the matching line 361, and is used to turn on or off the connection between the eleventh transistor T11 and the matching line 361 according to the control signal received from the wildcard matching enable line 1201; the thirteenth transistor T13 is disposed between the matching line 361 and the second switching unit 502 and is used to turn off the connection between the matching line 361 and the second switching unit 502 according to the control signal received from the wildcard matching enable line 1201.

[0179] In this embodiment, the twelfth transistor T12 and the thirteenth transistor T13 are reverse switches.

[0180] The thirteenth transistor, T13, is a P-channel metal-oxide-semiconductor (NMOS). Alternatively, the twelfth transistor, T12, is a PMOS, and the thirteenth transistor, T13, is an NMOS.

[0181] A control signal can be sent to a bit cell in bit cell group 311 via wildcard enable line 1201. The control signal can be 0 or 1. The control signal for turning on the twelfth transistor T12 is denoted as the first control signal, and the control signal for turning on the thirteenth transistor T13 is denoted as the second control signal. When the second charging unit is enabled, the first control signal is sent to the twelfth transistor T12 and the thirteenth transistor T13 via wildcard matching enable line 1201, turning on the twelfth transistor T12 and turning off the thirteenth transistor T13. After turning off the thirteenth transistor T13, matching line 361 will not be grounded. After turning on the twelfth transistor T12, the following situations exist: First, when the value stored in the second memory cell is X, the eleventh transistor T11 is turned on. Thus, regardless of whether the search word is 0 or 1, the high level passes through both the eleventh transistor T11 and the twelfth transistor T12, indicating that the high level flows through the memory cell storing X to the next memory cell. This achieves wildcard matching.

[0182] Second, when the value stored in the second memory cell is not X, the eleventh transistor T11 is turned off. This prevents a high-level signal from passing through the eleventh transistor T11.

[0183] The first transistor T1 is turned on or off based on the comparison result between the search word and the first stored word. When the search word and the first stored word are equal, the first transistor T1 is turned on, and a high-level signal flows through the first transistor T1, indicating that the high-level signal flows to the next level through the current bit unit. Specifically, if the current bit unit is not the last bit unit of the first bit unit group, the next level refers to the next bit unit. If the current bit unit is the last bit unit of the first bit unit group, the next level refers to the amplification unit. When the search word and the first stored word are not equal, the first transistor T1 is turned off, and a high-level signal cannot flow through the first transistor T1 or the eleventh transistor T11, indicating that the high-level signal cannot flow through the current bit unit. Thus, the matching line 361 outputs a low level, thereby achieving precise matching.

[0184] It should be noted that when the wildcard matching enable line 1201 is connected to a column of bit cells in the bit cell array, the search word can be matched with multiple storage words simultaneously using wildcards. When the wildcard matching enable line 1201 is enabled, the matching line 362 is disabled. For example, when the second charging unit 37 is connected to the matching line 362, the second charging unit 37 disconnects from the matching line 362.

[0185] Please refer to Table 4, which describes the number of transistors per bit cell in several types of memory:

[0186] Table 4

[0187] Memory 1 is a TCAM, memory 2 is an existing range matching content addressable memory (RM-CAM), and memory 3 is the content addressable memory of this application.

[0188] TCAM cannot perform arbitrary range matching, but it can perform wildcard matching and exact matching. Each bit cell in TCAM includes 16 transistors. Existing RM-CAM can perform range matching and exact matching, but not wildcard matching.

[0189] In existing RM-CAM, a bit cell includes 30 transistors, and each bit cell can store 2 storage bits. Thus, the first bit cell group can be used to search for a word and perform an exact match with the two storage words, which means that an exact match requires 15 transistors per bit cell.

[0190] Figure 12The content-addressable memory (COM) of this application, as shown, includes 25 transistors per bit cell. This COM is capable of range matching, exact matching, and wildcard matching. In the COM of this application, the first bit cell group can be used for exact matching of a search word with two stored words, indicating that exact matching requires 12.5 transistors per bit cell. It can be seen that the number of transistors per bit cell in the COM of this application is less than the number of transistors per bit cell in existing COMs.

[0191] Figure 11 The content-addressable memory shown can output range matching results or exact matching results. Figure 12 The content-addressable memory shown can output range matching results, exact matching results, or wildcard matching results. The matching signal unit used to select the output result is described below: See Figure 14 In another alternative embodiment, the content-addressable memory includes a second charging unit 37, a first bit cell group 311, a first charging unit 35, an amplification unit 33, a matching signal unit 34, a result control line 1401, and a first signal output line 1402. The first bit cell group 311 includes bit cells 3111, 3112, ..., 311n. The amplification unit 33 includes a sensitive amplifier 331 and a sensitive amplifier 332.

[0192] The matching signal unit 34 includes a first NOT gate 3411, a first AND gate 3412, a fourteenth transistor T14, and a fifteenth transistor T15; the fourteenth transistor T14 is connected to the result control line 1401, the amplification unit 33, and the first signal output line 1402; the fifteenth transistor T15 is connected to the result control line 1401, the first AND gate 3412, and the first signal output line 1402.

[0193] In this embodiment, the second charging unit 37, the first element unit group 311, the first charging unit 35, the amplification unit 33, and the matching signal unit 34 can be found in [reference needed]. Figures 3 to 13 The corresponding description in the illustrated embodiment.

[0194] Transistor T14 (fourteenth transistor) and transistor T15 (fifteenth transistor) are reverse switches. Transistor T14 is a PMOS and transistor T15 is an NMOS. Alternatively, transistor T14 is an NMOS and transistor T15 is a PMOS.

[0195] As a result, control line 1401 is used to send control signals to the fourteenth transistor T14 and the fifteenth transistor T15. The control signal that turns on the fourteenth transistor T14 is denoted as the third control signal, and the control signal that turns on the fifteenth transistor T15 is denoted as the fourth control signal.

[0196] The fourteenth transistor T14 is turned on according to the third control signal, thus enabling the connection between the amplifier unit 33 and the first signal output line 1402. When there is no wildcard enable line or the wildcard enable line is disabled, the first signal output line 1402 outputs a precise matching result; when the wildcard enable line is enabled, the first signal output line 1402 outputs a wildcard matching result. The fourteenth transistor T14 is also turned off according to the third control signal, thus preventing the output of either a precise matching result or a wildcard matching result.

[0197] The fifteenth transistor T15 is turned on according to the fourth control signal, thus connecting the first AND gate 3412 and the first signal output line 1402, which outputs the range matching result. The fifteenth transistor T15 is also turned off according to the fourth control signal, thus preventing the output of the range matching result.

[0198] It should be understood that the matching signal unit can include multiple transistor pairs, each transistor pair including two transistors that are inverting switches. One transistor controls the output of an exact match result or a wildcard match result, and the other transistor controls the output of a range match result. The result control line can connect to multiple transistor pairs to send control signals to multiple transistor pairs simultaneously. This allows for the simultaneous output of multiple range match results, or multiple exact match results or wildcard match results, enabling function switching on a block-by-block basis.

[0199] It should be understood that the above is only one example of a matching signal unit. The matching signal unit may also include other branch circuits that selectively output precise matching results, wildcard matching results, or range matching results.

[0200] See Figure 15 In another alternative embodiment, the content-addressable memory 30 includes a second charging unit 37, a first bit cell group 311, a first charging unit 35, an amplification unit 33, a matching signal unit 34, a sixteenth transistor T16, a seventeenth transistor T17, a result control bit storage unit 1501, a second signal output line 1502, and a wildcard matching enable bit storage unit 1503. The first bit cell group 311 includes bit cells 3111, 3112, ..., 311n. The amplification unit 33 includes a sensitive amplifier 331 and a sensitive amplifier 332.

[0201] The sixteenth transistor T16 is connected to the result control bit storage unit 1501, the second charging unit 37 and the matching line 361; the seventeenth transistor T17 is connected to the result control bit storage unit 1501, the first charging unit 35 and the matching line 361. The matching signal unit 34 includes a first NOT gate 3411, a first AND gate 3412, an eighteenth transistor T18, and a nineteenth transistor T19; the eighteenth transistor T18 is connected to the result control bit storage unit 1501, the sensitive amplifier 331, and the second signal output line 1502; the nineteenth transistor T19 is connected to the result control bit storage unit 1501, the first AND gate 3412, and the second signal output line 1502. Each bit cell in the first bit cell group also includes a twentieth transistor, a twenty-first transistor, and a twenty-second transistor. The twentieth transistor is connected to the second bit storage cell 506 and is used to turn on or off the storage bit of the second bit storage cell 506 according to the storage bit. The twenty-first transistor is connected to the wildcard matching enable bit storage cell 1503, the twentieth transistor, and the matching line 361 and is used to turn on or off the storage bit of the wildcard matching enable bit storage cell 1503 according to the storage bit. The twenty-second transistor is used to turn on or off the storage bit of the wildcard matching enable bit storage cell 1503 according to the storage bit.

[0202] In this embodiment, the sixteenth transistor T16 and the seventeenth transistor T17 are reverse switches. The sixteenth transistor T16 is a PMOS and the seventeenth transistor T17 is an NMOS. Alternatively, the sixteenth transistor T16 is an NMOS and the seventeenth transistor T17 is a PMOS.

[0203] Transistor T18 (18th transistor) and transistor T19 (19th transistor) are reverse switches. Transistor T18 is a PMOS and transistor T19 is an NMOS. Alternatively, transistor T18 is an NMOS and transistor T19 is a PMOS.

[0204] In the first bit cell group, the twentieth, twenty-first, and twenty-second transistors are similar to the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13, respectively, as detailed in the preceding descriptions. It should be understood that the number of wildcard matching enable bit storage cells 1503 can be multiple; for example, each bit cell may have one corresponding wildcard matching enable bit storage cell 1503.

[0205] The content-addressable memory may include one or more result control bit storage units 1501, which may be one or more SRAM cells. Each SRAM cell can store 0 or 1 as a control signal. The control signal used to turn on the sixteenth transistor T16 and the eighteenth transistor T18 is denoted as the sixth control signal, and the control signal used to turn on the seventeenth transistor T17 and the nineteenth transistor T19 is denoted as the seventh control signal. When the second charging unit 37 is enabled, the value of the result control bit storage unit 1501 is set to the sixth control signal. The sixteenth transistor T16 and the eighteenth transistor T18 then connect the second charging unit 37 to the matching line 361 and the amplification unit 33 to the second signal output line 1502 according to the sixth control signal, to output a precise matching result or a wildcard matching result.

[0206] When the first charging unit 35 is enabled, the value of the result control bit storage unit 1501 is set to the seventh control signal. The seventeenth transistor T17 and the nineteenth transistor T19 are connected according to the seventh control signal to connect the first charging unit with the matching line 361 and the amplification unit 33 with the second signal output line 1502, so as to output the range matching result.

[0207] As can be seen from the above, the result control bit storage unit 1501 can control the matching result output by a matching line. When the content-addressable memory includes multiple result control bit storage units 1501, the result control bit storage unit 1501 can store different control signals, thereby realizing control by stored word. In this way, the matching signal unit 34 can simultaneously output the exact matching result, the wildcard matching result, and the range matching result.

[0208] The second type of content-addressable memory is described below; please refer to [link / reference]. Figure 16 Another embodiment of the content-addressable memory of this application includes: The array includes a bit cell array, a search line drive unit 32, an amplification unit 33, a matching signal unit 34, and a first charging unit 35. The bit cell array includes bit cell groups 311, 312, ..., 31n. Bit cell group 311 includes bit cells 3111, 3112, ..., 311n.

[0209] The first charging unit 35 is used to precharge the output terminals of the matching line 361 and the matching line 362 to a predetermined voltage. The search line drive unit 32 is used to send the search word to the first element unit group; The first bit unit group is 311, the first matching line is 361, and the second matching line is 362. Bit unit group 311 is used to adjust the voltage at the first end of matching line 361 from a predetermined voltage to ground voltage when the search word and the pre-stored first memory word satisfy a first preset relationship; and to maintain the voltage at the first end of matching line 361 at a predetermined voltage when the search word and the pre-stored first memory word do not satisfy the first preset relationship. Similarly, when the search word and the pre-stored second memory word satisfy a second preset relationship, the voltage at the first end of matching line 362 is adjusted from a predetermined voltage to ground voltage; and to maintain the voltage at the first end of matching line 362 at a predetermined voltage when the search word and the pre-stored second memory word do not satisfy the second preset relationship. The amplification unit 33 is used to amplify the voltage at the first end of the matching line 361 to a first amplified voltage, and to amplify the voltage at the first end of the matching line 362 to a second amplified voltage; The matching signal unit 34 is used to output the range matching result based on the first amplification voltage and the second amplification voltage.

[0210] In this embodiment, the composition and connection relationship of the bit cell array, bit cell group 312~bit cell group 31m, search line drive unit 32, amplification unit 33, matching signal unit 34 and first charging unit 35, matching line 361, matching line 362, matching line 363, and matching line 364 can be found in [reference needed]. Figures 3 to 13 The corresponding description in the illustrated embodiment.

[0211] The second ends of matching line 361 and matching line 362 are grounded. Taking the search word being less than or equal to the first stored word as an example, when the search word is less than or equal to the first stored word, matching line 361 is grounded. This adjusts the voltage at the first end of matching line 361 from a predetermined voltage to a ground voltage. Thus, when the first preset relationship is less than or equal to, a ground voltage is output; otherwise, a predetermined voltage is output. This allows for less-than-or-equal matching by indicating the output voltage.

[0212] The second preset relationship takes the search word being less than or equal to the second stored word as an example. When the search word is less than or equal to the second stored word, the second matching line is grounded. This can adjust the voltage at the first end of the second matching line from the predetermined voltage to the ground voltage. This allows the ground voltage to be output when the second preset relationship is less than or equal to the second stored word, and the predetermined voltage to be output otherwise.

[0213] For preset relationships of greater than or equal to, the content-addressable memory of this application can perform non-less-than matching. This provides another feasible content-addressable memory.

[0214] In one optional embodiment, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to connect the first matching line to ground when the search line signal and the first storage bit satisfy a third preset relationship, and turn off the connection between the first matching line and ground when the search line signal and the first storage bit do not satisfy the third preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to connect the second matching line to ground when the search line signal and the second storage bit satisfy a fourth preset relationship, and turn off the connection between the second matching line and ground when the search line signal and the second storage bit do not satisfy the fourth preset relationship. The system comprises the following components: a first switching unit connected to the search line driving unit, the gate of the first transistor, and the first bit storage unit; the source and drain of the first transistor connected to the first matching line; a second switching unit connected to the search line driving unit, the first matching line, the first bit storage unit, and ground; a third switching unit connected to the search line driving unit, the gate of the second transistor, and the second bit storage unit; the source and drain of the second transistor connected to the second matching line; and a fourth switching unit connected to the search line driving unit, the second matching line, the second bit storage unit, and ground. In the first bit unit group, the first bit storage unit of each bit unit stores the first storage bit, and in the first bit unit group, the second bit storage unit of each bit unit stores the second storage bit.

[0215] In this embodiment, when the first preset relationship is not greater than, the third preset relationship is less than. When the first preset relationship is not less than, the third preset relationship is greater than. When the second preset relationship is not greater than, the fourth preset relationship is less than. When the second preset relationship is not less than, the fourth preset relationship is greater than.

[0216] When the search word is less than the first memory word, the second switching unit of one bit cell will be turned on, resulting in a ground voltage output on the first matching line. When the search word is equal to the first memory word, the first transistors of all bit cells will be turned on and the first matching line will be grounded, resulting in a ground voltage output on the first matching line. When the search word is greater than the first memory word, the second switching unit and the first transistor of one bit cell will be turned off, resulting in a predetermined voltage output on the first matching line. Thus, the output voltage of the first matching line can indicate whether it is less than or equal to the first memory word. Alternatively, the output voltage of the first matching line can indicate whether it is greater than or equal to the first preset relationship. Similarly, the output voltage of the second matching line can indicate a second preset relationship.

[0217] In another alternative embodiment, the first switching unit includes a third transistor and a fourth transistor. The third transistor is connected to one end of the first memory cell and the search line driving unit, and the fourth transistor is connected to the other end of the first memory cell and the search line driving unit. Both the third transistor and the fourth transistor are connected to the gate of the first transistor. The second switching unit includes a fifth transistor and a sixth transistor connected together, with the fifth transistor connected to the first memory cell and ground, and the sixth transistor connected to the search line drive unit and the first matching line. The third switching unit includes a seventh transistor and an eighth transistor connected together. The seventh transistor is connected to one end of the second memory cell and the search line driving unit, and the eighth transistor is connected to the other end of the second memory cell and the search line driving unit. Both the seventh transistor and the eighth transistor are connected to the gate of the second transistor. The fourth switching unit includes a ninth transistor and a tenth transistor connected together, with the ninth transistor connected to the second bit storage unit and ground, and the tenth transistor connected to the search line drive unit and the second matching line.

[0218] In another alternative embodiment, the sixth transistor and the tenth transistor are connected to the search line driving unit via different search lines, the fifth transistor is connected to the first end of the first memory cell, and the ninth transistor is connected to the second end of the second memory cell.

[0219] In another alternative embodiment, the amplification unit includes a first sensitive amplifier and a second sensitive amplifier, and the matching signal unit includes a first NOT gate, a second NOT gate and a first AND gate; the first sensitive amplifier is connected to the first matching line and the first NOT gate, the second sensitive amplifier is connected to the second matching line and the second NOT gate, and the first AND gate is connected to the first NOT gate and the second NOT gate respectively.

[0220] In another alternative embodiment, the sixth transistor and the tenth transistor are connected to the search line driving unit via a search line, the fifth transistor is connected to the first end of the first memory cell, and the ninth transistor is connected to the first end of the second memory cell.

[0221] In another optional embodiment, the amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate; the fourth sensitive amplifier is connected to the first matching line and the third NOT gate, the fifth sensitive amplifier is connected to the second matching line, and the third AND gate is connected to both the third NOT gate and the fifth sensitive amplifier. In this content-addressable memory, the fourth sensitive amplifier amplifies the voltage at the first terminal of the first matching line to a first amplified voltage, the fifth sensitive amplifier amplifies the voltage at the first terminal of the second matching line to a second amplified voltage, the third NOT gate inverts the first amplified voltage, and the third AND gate performs a bitwise AND operation between the second amplified voltage and the inverted first amplified voltage to obtain the range matching result.

[0222] In another alternative embodiment, the matching signal unit further includes a fourth NOT gate and a fourth AND gate; the fourth NOT gate is connected to a sixth sensitive amplifier, which is connected to the first matching line of the second bit cell group, and the second bit cell group is adjacent to the first bit cell group; the fourth AND gate is connected to the second sensitive amplifier and the fourth NOT gate. For more than three consecutive intervals, this content-addressable memory can save hardware resources occupied by range matching.

[0223] In another alternative embodiment, the content-addressable memory further includes a second charging unit connected to a second end of the first matching line. The content-addressable memory may also include a ground switch, which may be, but is not limited to, a transistor. When the second charging unit is enabled, the ground switch disconnects the second end of the first matching line from ground, thus de-grounding the first matching line.

[0224] In another alternative embodiment, the content-addressable memory further includes a result control line and a first signal output line; the matching signal unit further includes a fourteenth transistor and a fifteenth transistor; the fourteenth transistor is connected to the result control line, the amplification unit and the first signal output line; the fifteenth transistor is connected to the result control line, the first AND gate and the first signal output line.

[0225] In this embodiment, the matching signal unit, bit unit group, result control line, and first signal output line can be found in [reference needed]. Figure 14 The corresponding descriptions in the illustrated embodiments will not be repeated here.

[0226] In another alternative embodiment, the content-addressable memory further includes sixteenth and seventeenth transistors, a result control bit storage unit, a wildcard match enable bit storage unit, and a second signal output line; the match signal unit further includes eighteenth and nineteenth transistors; each bit unit in the first bit unit group further includes twentieth, twenty-first, and twenty-second transistors. See details for further information. Figure 15 The corresponding description in the illustrated embodiment.

[0227] The third type of content-addressable memory is described below; please refer to [link / reference]. Figure 17 This application also discloses another embodiment of a content-addressable memory, including: The array includes a bit cell array, a search line drive unit 32, an amplification unit 33, a matching signal unit 34, and a first charging unit 35.

[0228] The bit cell array includes bit cell group 311, bit cell group 312, ..., bit cell group 31m. Bit cell group 311 includes bit cell 3111, bit cell 3112, ..., bit cell 311n.

[0229] The first charging unit 35 is used to precharge the output terminal of the first matching line and the output terminal of the second matching line to a predetermined voltage. The search line drive unit 32 is used to send the search word to the first element unit group; The first bit unit group is 311, the first matching line is 361, and the second matching line is 362. Bit unit group 311 is used to adjust the voltage at the first end of matching line 361 from a predetermined voltage to ground voltage when the search word and the pre-stored first memory word satisfy a first preset relationship; and to maintain the voltage at the first end of matching line 361 at a predetermined voltage when the search word and the pre-stored first memory word do not satisfy the first preset relationship. Similarly, when the search word and the pre-stored second memory word satisfy a second preset relationship, the voltage at the first end of matching line 362 is adjusted from a predetermined voltage to ground voltage; and to maintain the voltage at the first end of matching line 362 at a predetermined voltage when the search word and the pre-stored second memory word do not satisfy the second preset relationship. The amplification unit 33 is used to amplify the voltage at the first end of the matching line 361 to a first amplified voltage, and to amplify the voltage at the first end of the matching line 362 to a second amplified voltage; The matching signal unit 34 is used to output the range matching result based on the first amplification voltage and the second amplification voltage.

[0230] In this embodiment, the composition and connection relationship of the bit cell array, bit cell group 312~bit cell group 31m, search line drive unit 32, amplification unit 33, matching signal unit 34 and first charging unit 35, matching line 361, matching line 362, matching line 363, and matching line 364 can be found in [reference needed]. Figure 3 , Figure 4 , Figure 5 or Figure 8 The corresponding description in the illustrated embodiment.

[0231] The second end of matching line 361 is grounded, while the second end of matching line 362 is not grounded. With the second end of matching line 361 grounded, less-than-or-equal-match or greater-than-or-equal-match can be achieved. With the second end of matching line 362 not grounded, less-than-match or greater-than-match can be achieved using matching line 362. This provides another feasible content-addressable memory.

[0232] In one optional embodiment, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to connect the first matching line to ground when the search line signal and the first storage bit satisfy a third preset relationship, and turn off the connection between the first matching line and ground when the search line signal and the first storage bit do not satisfy the third preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to connect the second matching line to ground when the search line signal and the second storage bit satisfy a second preset relationship, and turn off the connection between the second matching line and ground when the search line signal and the second storage bit do not satisfy the second preset relationship.

[0233] The system comprises the following configurations: a first switching unit is connected to the search line driving unit, the gate of the first transistor, and the first bit storage unit; the source and drain of the first transistor are connected to the first matching line. A second switching unit is connected to the search line driving unit, the first matching line, and the second transistor; the second transistor is connected to the second switching unit, the first bit storage unit, and ground. A third switching unit is connected to the search line driving unit, the gate of the second transistor, and the second bit storage unit; the source and drain of the second transistor are connected to the second matching line. A fourth switching unit is connected to the search line driving unit, the second matching line, and the source of the fourth transistor; the gate of the fourth transistor is connected to the second bit storage unit, and the drain of the fourth transistor is grounded. In the first bit unit group, the first bit storage unit of each bit unit stores the first storage bit, and the second bit storage unit of each bit unit stores the second storage bit. When the first preset relationship is not less than, the third preset relationship is greater than.

[0234] Taking the third preset relationship as an example (less than), when the search word is less than the first storage word, the second switch unit of one bit cell will necessarily be turned on, thus the first matching line outputs a ground voltage. When the search word is equal to the first storage word, the first transistors of all bit cells are turned on and the first matching line is grounded, thus the first matching line outputs a ground voltage. When the search word is greater than the first storage word, the second switch unit and the first transistor of one bit cell will necessarily be turned off, thus the first matching line outputs a predetermined voltage. This allows for matching that is less than or equal to the first storage word.

[0235] When the search word equals the second storage word, the second transistors of all bit cells are turned on and the second matching line is not grounded. This allows the second matching line to output a predetermined voltage, enabling the first bit cell group and the second matching line to achieve a greater than / less than match. It should be understood that when the first preset relationship is not less than or the second preset relationship is less than, the aforementioned bit cell group, first matching line, and second matching line can also achieve a not less than or less than match.

[0236] The fourth type of content-addressable memory is described below. (See attached document.) Figure 18 Another embodiment of the content-addressable memory in this application includes: The array includes a bit cell array, a search line drive unit 32, an amplification unit 33, a matching signal unit 34, and a first charging unit 35. The bit cell array includes bit cell groups 311, 312, ..., 31n. Bit cell group 311 includes bit cells 3111, 3112, ..., 311n.

[0237] The first charging unit 35 is used to precharge the output terminal of the first matching line and the output terminal of the second matching line to a predetermined voltage. The search line drive unit 32 is used to send the search word to the first element unit group; The first bit unit group is 311, the first matching line is 361, and the second matching line is 362. The first bit unit group, 311, is used to adjust the voltage at the first end of the matching line 361 from a predetermined voltage to ground voltage when the search word and the pre-stored first memory word satisfy a first preset relationship, and to maintain the voltage at the first end of the matching line 361 at a predetermined voltage when the search word and the pre-stored first memory word do not satisfy the first preset relationship; and to adjust the voltage at the first end of the matching line 362 from a predetermined voltage to ground voltage when the search word and the pre-stored second memory word satisfy a second preset relationship, and to maintain the voltage at the first end of the matching line 362 at a predetermined voltage when the search word and the pre-stored second memory word do not satisfy the second preset relationship. The amplification unit 33 is used to amplify the voltage at the first end of the matching line 361 to a first amplified voltage, and to amplify the voltage at the first end of the matching line 362 to a second amplified voltage; The matching signal unit 34 is used to output the range matching result based on the first amplification voltage and the second amplification voltage.

[0238] In this embodiment, the composition and connection relationship of the bit cell array, bit cell group 312~bit cell group 31m, search line drive unit 32, amplification unit 33, matching signal unit 34 and first charging unit 35, matching line 361, matching line 362, matching line 363, and matching line 364 can be found in [reference needed]. Figure 3 , Figure 4 , Figure 5 or Figure 8 The corresponding description in the illustrated embodiment.

[0239] The second end of the first matching line is not grounded, while the second end of the second matching line is grounded. Taking the search word being less than the first stored word as an example, when the search word is less than the first stored word, the first matching line is grounded. This adjusts the voltage at the first end of the first matching line from a predetermined voltage to the ground voltage; otherwise, a predetermined voltage is output. This allows the less-than-matching condition to be achieved through the output voltage of the first matching line.

[0240] Taking the second preset relationship as an example of the search word being less than or equal to the second stored word, when the search word is less than or equal to the second stored word, the second matching line is grounded. This adjusts the voltage at the first end of the second matching line from a predetermined voltage to a ground voltage. Thus, when the second preset relationship is less than or equal to, a ground voltage is output; otherwise, a predetermined voltage is output. In this way, the less than or equal to matching can be achieved through the output voltage of the second matching line.

[0241] For cases where the first preset relationship is greater than and the second preset relationship is greater than or equal to, the content-addressable memory of this application can perform greater than matching or not less than matching. This provides another feasible content-addressable memory.

[0242] In one possible implementation, each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a first bit storage unit, and a second bit storage unit. The first switch unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The second switch unit is used to connect the first matching line to ground when the search line signal and the first storage bit satisfy a first preset relationship, and turn off the connection between the first matching line and ground when the search line signal and the first storage bit do not satisfy the first preset relationship. The third switch unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and turn off the second transistor when the search bit is not equal to the second storage bit. The fourth switch unit is used to connect the second matching line to ground when the search line signal and the second storage bit satisfy a third preset relationship, and turn off the connection between the second matching line and ground when the search line signal and the second storage bit do not satisfy the third preset relationship.

[0243] The system comprises the following components: a first switching unit connected to the search line driving unit, the gate of the first transistor, and the first bit storage unit; the source and drain of the first transistor are connected to the first matching line. A second switching unit connected to the search line driving unit, the first bit storage unit, the first matching line, and ground. A third switching unit connected to the search line driving unit, the gate of the second transistor, and the second bit storage unit; the source and drain of the second transistor are connected to the second matching line. A fourth switching unit connected to the search line driving unit, the second bit storage unit, the second matching line, and ground. In the first bit unit group, the first bit storage unit of each bit unit stores the first storage bit, and the second bit storage unit of each bit unit stores the second storage bit. When the second preset relationship is not less than, the third preset relationship is greater than. When the second preset relationship is not greater than, the third preset relationship is less than.

[0244] When the search word is less than the first storage word, the second switching unit of one bit cell will necessarily be turned on, thus the first matching line outputs a ground voltage. When the search word is equal to the first storage word, the first transistors of all bit cells are turned on and the first matching line is not grounded, thus the first matching line outputs a predetermined voltage. When the search word is greater than the first storage word, the first transistor of one bit cell will necessarily be turned off and the second switching units of all bit cells near the first charging unit 35 will be turned off, thus the first matching line outputs a predetermined voltage. Therefore, it can be seen that the first bit cell group and the first matching line can achieve a less-than-match condition.

[0245] When the search word is less than the second storage word, the second transistor of one bit cell will necessarily be turned on, grounding the second matching line. When the search word is equal to the second storage word, the second transistors of all bit cells will be turned on, grounding the second matching line. In this way, the second matching line outputs a ground voltage, and the first bit cell group and the second matching line can achieve a match of less than or equal to each other.

[0246] The relationship between the search term and the upper limit of the target range and the relationship between the search term and the lower limit of the target range in this application are shown in Table 5:

[0247] Table 5

[0248] It should be understood that each relation can be represented using one or more relational operators. The content addressing memory of this application can implement greater than, less than, greater than or equal to, and less than or equal to, and combined with NOT gates, can achieve various types of range matching, as well as range matching of arbitrary size.

[0249] The content-addressable memory has been described above. The network device described in this application will now be described. A router will be used as an example of the network device. (See attached document for details.) Figure 19One embodiment of the router 1900 includes a processor 1901 and a content-addressable memory 1902.

[0250] Processor 1901 is used to receive a target range; determine a first storage word based on the upper limit of the target range; determine a second storage word based on the lower limit of the target range; and send the first storage word and the second storage word to the content-addressable memory. Content-addressable memory 1902 is a content-addressable memory in any embodiment or optional embodiment of this application.

[0251] In this embodiment, the processor 1901 may be a central processing unit (CPU), a field-programmable gate array, or a dedicated circuit capable of performing the above steps.

[0252] Optionally, the first storage word is equal to the upper limit of the target range. Alternatively, the first storage word is equal to the upper limit of the target range plus one. Or, the first storage word is equal to the upper limit of the target range minus one. And, the second storage word is equal to the lower limit of the target range, which is either the lower limit of the target range plus one or the lower limit of the target range minus one.

[0253] Specifically, in the content-addressable memory, when both the first and second matching lines are not grounded, and the target range is an open interval (low, high), and the first preset relationship is less than and the second preset relationship is greater than, the processor 1901 determines that the first storage word is equal to high and the second storage word is equal to low. When both the first and second preset relationships are less than, the processor 1901 determines that the first storage word is high and the second storage word is low+1. When both the first and second preset relationships are greater than, the processor 1901 determines that the second storage word is low and the first storage word is high-1. When both the first and second preset relationships are greater than, the processor 1901 determines that the first storage word is high-1 and the second storage word is low+1.

[0254] When the first matching line and the second matching line are grounded in the content-addressable memory, and the target range is an open interval (low, high), and the first preset relationship is not greater than and the second preset relationship is not less than, the processor 1901 determines that the first storage word is equal to high-1 and the second storage word is equal to low+1.

[0255] When the first preset relationship is not greater than and the second preset relationship is not greater than, the processor 1901 determines that the first storage word is high-1 and the second storage word is low.

[0256] When the first preset relationship is not less than and the second preset relationship is not less than, the processor 1901 determines that the first storage word is high and the second storage word is low+1.

[0257] When the first preset relationship is not less than and the second preset relationship is not greater than, the processor 1901 determines that the first storage word is high and the second storage word is low.

[0258] In the content-addressable memory, when the first matching line is not grounded and the second matching line is grounded, and when the target range is an open interval (low, high), the first preset relationship is not greater than and the second preset relationship is less than, the processor 1901 determines that the first storage word is equal to high-1 and the second storage word is equal to low+1.

[0259] When the first preset relationship is not greater than and the second preset relationship is greater than, the processor 1901 determines that the first storage word is high-1 and the second storage word is low.

[0260] When the first preset relationship is not less than and the second preset relationship is less than, the processor 1901 determines that the first storage word is high and the second storage word is low+1.

[0261] When the first preset relationship is not less than and the second preset relationship is greater than, the processor 1901 determines that the first storage word is high and the second storage word is low.

[0262] In a content-addressable memory, when the first matching line is grounded and the second matching line is not grounded, and the target range is an open interval (low, high), and the first preset relationship is greater than and the second preset relationship is not less than, the processor 1901 determines that the first storage word is equal to high-1 and the second storage word is equal to low+1.

[0263] When the first preset relationship is greater than and the second preset relationship is not greater than, the processor 1901 determines that the first storage word is high-1 and the second storage word is low.

[0264] When the first preset relationship is less than and the second preset relationship is not less than, the processor 1901 determines that the first storage word is high and the second storage word is low+1.

[0265] When the first preset relationship is less than and the second preset relationship is not greater than, the processor 1901 determines that the first storage word is high and the second storage word is low.

[0266] When the target range is a closed interval or a half-open / half-closed interval, the target range can be converted into an open interval, and then the corresponding calculations can be performed to obtain the first storage word and the second storage word. It should be understood that the type of the target range, the correspondence between the first preset relationship and the first storage word, and the type of the target range, the correspondence between the second preset relationship and the second storage word can be stored in memory.

[0267] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A content-addressable memory, characterized in that, include: Bit cell array, search line drive unit, amplification unit, matching signal unit and first charging unit; Each bit cell in the first bit cell group is connected to the first matching line and the second matching line respectively. The bit cell storing the lowest storage bit in the first bit cell group is located on the side away from the first charging unit. The first charging unit is used to precharge the first end of the first matching line and the first end of the second matching line to a predetermined voltage. The first end of the first matching line is connected to the amplification unit and the first charging unit, and the first end of the second matching line is connected to the amplification unit and the first charging unit. The search line driving unit is connected to the first bit unit group and is used to send search words to the first bit unit group; The first bit unit group is used to adjust the voltage at the first end of the first matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored first storage word satisfy the first preset relationship, and to keep the voltage at the first end of the first matching line at the predetermined voltage when the search word and the first storage word do not satisfy the first preset relationship. The first preset relationship is less than or greater than. The first bit unit group is further configured to adjust the voltage at the first end of the second matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored second storage word satisfy the second preset relationship, and to maintain the voltage at the first end of the second matching line at the predetermined voltage when the search word and the second storage word do not satisfy the second preset relationship, wherein the second preset relationship is less than or greater than. The amplification unit is used to amplify the voltage at the first end of the first matching line to a first amplified voltage, and to amplify the voltage at the first end of the second matching line to a second amplified voltage; The matching signal unit is used to match the output range of the first amplified voltage and the second amplified voltage based on the result.

2. The content-addressable memory according to claim 1, characterized in that, Each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first bit storage unit, and a second bit storage unit. The first switching unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The source and drain of the first transistor are connected to the first matching line. The second switching unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy the first preset relationship, and to turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the first preset relationship. The third switching unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and to turn off the second transistor when the search bit is not equal to the second storage bit. The source and drain of the second transistor are connected to the second matching line. The fourth switching unit is used to connect the second matching line to ground when the second search line signal and the second storage bit satisfy the second preset relationship, and to disconnect the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the second preset relationship.

3. The content-addressable memory according to claim 2, characterized in that, The first switching unit includes a third transistor and a fourth transistor. The third transistor is connected to one end of the first bit storage unit and the search line driving unit, and the fourth transistor is connected to the other end of the first bit storage unit and the search line driving unit. Both the third transistor and the fourth transistor are connected to the gate of the first transistor. The second switching unit includes a fifth transistor and a sixth transistor connected together, wherein the fifth transistor is connected to the first memory cell and ground, and the sixth transistor is connected to the search line driving unit and the first matching line; The third switching unit includes a seventh transistor and an eighth transistor connected together. The seventh transistor is connected to one end of the second bit memory cell and the search line driving unit, and the eighth transistor is connected to the other end of the second bit memory cell and the search line driving unit. Both the seventh transistor and the eighth transistor are connected to the gate of the second transistor. The fourth switching unit includes a ninth transistor and a tenth transistor connected together, with the ninth transistor connected to the second bit storage unit and ground, and the tenth transistor connected to the search line driving unit and the second matching line.

4. The content-addressable memory according to claim 3, characterized in that, The sixth transistor and the tenth transistor are connected to the search line driving unit via different search lines. The fifth transistor is connected to the first end of the first memory cell, and the ninth transistor is connected to the second end of the second memory cell.

5. The content-addressable memory according to claim 4, characterized in that, The amplification unit includes a first sensitive amplifier and a second sensitive amplifier, and the matching signal unit includes a first NOT gate, a second NOT gate and a first AND gate; the first sensitive amplifier is connected to the first matching line and the first NOT gate, the second sensitive amplifier is connected to the second matching line and the second NOT gate, and the first AND gate is connected to the first NOT gate and the second NOT gate respectively.

6. The content-addressable memory according to claim 5, characterized in that, The matching signal unit further includes a second AND gate, which connects the second sensitive amplifier and the third sensitive amplifier. The third sensitive amplifier is connected to the first matching line of the second bit unit group, and the second bit unit group is adjacent to the first bit unit group.

7. The content-addressable memory according to claim 3, characterized in that, The sixth transistor and the tenth transistor are connected to the search line driving unit via a search line, the fifth transistor is connected to the first end of the first memory cell, and the ninth transistor is connected to the first end of the second memory cell.

8. The content-addressable memory according to claim 7, characterized in that, The amplification unit includes a fourth sensitive amplifier and a fifth sensitive amplifier, and the matching signal unit includes a third NOT gate and a third AND gate; the fourth sensitive amplifier is connected to the first matching line and the third NOT gate, the fifth sensitive amplifier is connected to the second matching line, and the third AND gate is connected to the third NOT gate and the fifth sensitive amplifier respectively.

9. The content-addressable memory according to claim 8, characterized in that, The matching signal unit further includes a fourth NOT gate and a fourth AND gate; The fourth AND gate is connected to the sixth sensitive amplifier, the sixth sensitive amplifier is connected to the first matching line of the second bit cell group, and the second bit cell group is adjacent to the first bit cell group; The fourth NOT gate is connected to the fifth sensitive amplifier and the fourth AND gate.

10. The content-addressable memory according to any one of claims 5 to 6, characterized in that, The content-addressable memory further includes a second charging unit, which is connected to the second end of the first matching line, and the enable state of the second charging unit is opposite to that of the first charging unit.

11. The content-addressable memory according to claim 10, characterized in that, The content-addressable memory also includes a wildcard matching enable line; Each bit cell in the first bit cell group also includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The eleventh transistor is connected to the second bit storage cell and is used to turn on or off according to the storage bit of the second bit storage cell; The twelfth transistor is connected to the wildcard matching enable line, and the eleventh transistor and the first matching line are used to turn on or off according to the control signal received from the wildcard matching enable line. The thirteenth transistor is used to turn on or off the connection between the second switching unit and the first matching line according to the control signal received from the wildcard matching enable line, and the thirteenth transistor and the twelfth transistor are reversible switches.

12. The content-addressable memory according to claim 10, characterized in that, The content-addressable memory also includes a result control line and a first signal output line; The matching signal unit further includes a fourteenth transistor and a fifteenth transistor; the fourteenth transistor is connected to the result control line, the amplification unit and the first signal output line, and is used to turn on or off according to the control signal received from the result control line; the fifteenth transistor is connected to the result control line, the first AND gate and the first signal output line, and is used to turn on or off according to the control signal received from the result control line, and the fourteenth transistor and the fifteenth transistor are reversible switches.

13. The content-addressable memory according to claim 10, characterized in that, The content-addressable memory further includes a sixteenth transistor and a seventeenth transistor, a result control bit storage unit, a wildcard matching enable bit storage unit, and a second signal output line; the sixteenth transistor is connected to the result control bit storage unit, the second charging unit, and the first matching line, and is used to turn on or off according to a control signal received from the result control bit storage unit; The seventeenth transistor is connected to the result control bit storage unit, the first charging unit and the first matching line, and is used to turn on or off according to the control signal received from the result control bit storage unit. The sixteenth transistor and the seventeenth transistor are reversible switches. The matching signal unit further includes an eighteenth transistor and a nineteenth transistor; the eighteenth transistor is connected to the result control bit storage unit, the amplification unit and the second signal output line; the nineteenth transistor is connected to the result control bit storage unit, the first AND gate and the second signal output line, and the eighteenth transistor and the nineteenth transistor are mutual inverting switches; Each bit cell in the first bit cell group further includes a twentieth transistor, a twenty-first transistor, and a twenty-second transistor. The twentieth transistor is connected to the second bit storage cell and is used to turn on or off according to the storage bit of the second bit storage cell. The twenty-first transistor is connected to the wildcard matching enable bit storage cell, the twentieth transistor and the first matching line, and is used to turn on or off the storage bit of the wildcard matching enable bit storage cell according to the wildcard matching enable bit storage cell. The 22nd transistor is used to enable or disable the storage bit of the enable bit storage cell according to the wildcard matching, and the 22nd transistor and the 21st transistor are inverting switches.

14. A content-addressable memory, characterized in that, include: Bit cell array, search line drive unit, amplification unit, matching signal unit and first charging unit; Each bit cell in the first bit cell group is connected to the first matching line and the second matching line respectively. The bit cell storing the lowest storage bit in the first bit cell group is located on the side away from the first charging unit. The first charging unit is used to precharge the first end of the first matching line and the first end of the second matching line to a predetermined voltage. The first end of the first matching line is connected to the amplification unit and the first charging unit, and the second end of the first matching line is grounded. The first end of the second matching line is connected to the amplification unit and the first charging unit, and the second end of the second matching line is grounded. The search line driving unit is connected to the first bit unit group and is used to send search words to the first bit unit group; The first bit unit group is used to adjust the voltage at the first end of the first matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored first storage word satisfy the first preset relationship, and to keep the voltage at the first end of the first matching line at the predetermined voltage when the search word and the first storage word do not satisfy the first preset relationship. The first preset relationship is not less than or not greater than. The first bit unit group is further configured to adjust the voltage at the first end of the second matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored second storage word satisfy the second preset relationship, and to maintain the voltage at the first end of the second matching line at the predetermined voltage when the search word and the second storage word do not satisfy the second preset relationship, wherein the second preset relationship is not less than or not greater than. The amplification unit is used to amplify the voltage at the first end of the first matching line to a first amplified voltage, and to amplify the voltage at the first end of the second matching line to a second amplified voltage; The matching signal unit is used to match the output range of the first amplified voltage and the second amplified voltage based on the result.

15. The content-addressable memory according to claim 14, characterized in that, Each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first bit storage unit, and a second bit storage unit. The first switching unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The source and drain of the first transistor are connected to the first matching line. The second switching unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy the third preset relationship, and to turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the third preset relationship. The third switching unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and to turn off the second transistor when the search bit is not equal to the second storage bit. The source and drain of the second transistor are connected to the second matching line. The fourth switching unit is used to connect the second matching line to ground when the second search line signal and the second storage bit satisfy the fourth preset relationship, and to disconnect the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the fourth preset relationship.

16. A content-addressable memory, characterized in that, include: Bit cell array, search line drive unit, amplification unit, matching signal unit and first charging unit; Each bit cell in the first bit cell group is connected to the first matching line and the second matching line respectively. The bit cell storing the lowest storage bit in the first bit cell group is located on the side away from the first charging unit. The first charging unit is used to precharge the first end of the first matching line and the first end of the second matching line to a predetermined voltage. The first end of the first matching line is connected to the amplification unit and the first charging unit, the second end of the first matching line is grounded, and the first end of the second matching line is connected to the amplification unit and the first charging unit. The search line driving unit is connected to the first bit unit group and is used to send search words to the first bit unit group; The first bit unit group is used to adjust the voltage at the first end of the first matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored first storage word satisfy the first preset relationship, and to keep the voltage at the first end of the first matching line at the predetermined voltage when the search word and the pre-stored first storage word do not satisfy the first preset relationship. The first preset relationship is not less than or not greater than. The first bit unit group is further configured to adjust the voltage at the first end of the second matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored second storage word satisfy the second preset relationship, and to maintain the voltage at the first end of the second matching line at the predetermined voltage when the search word and the pre-stored second storage word do not satisfy the second preset relationship, wherein the second preset relationship is less than or greater than. The amplification unit is used to amplify the voltage at the first end of the first matching line to a first amplified voltage, and to amplify the voltage at the first end of the second matching line to a second amplified voltage; The matching signal unit is used to match the output range of the first amplified voltage and the second amplified voltage based on the result.

17. The content-addressable memory according to claim 16, characterized in that, Each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first bit storage unit, and a second bit storage unit. The first switching unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The source and drain of the first transistor are connected to the first matching line. The second switching unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy the third preset relationship, and to turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the third preset relationship. The third switching unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and to turn off the second transistor when the search bit is not equal to the second storage bit. The source and drain of the second transistor are connected to the second matching line. The fourth switching unit is used to connect the second matching line to ground when the second search line signal and the second storage bit satisfy the second preset relationship, and to disconnect the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the second preset relationship.

18. A content-addressable memory, characterized in that, include: Bit cell array, search line drive unit, amplification unit, matching signal unit and first charging unit; Each bit cell in the first bit cell group is connected to the first matching line and the second matching line respectively. The bit cell storing the lowest storage bit in the first bit cell group is located on the side away from the first charging unit. The first charging unit is used to precharge the first end of the first matching line and the first end of the second matching line to a predetermined voltage. The first end of the first matching line is connected to the amplification unit and the first charging unit, the first end of the second matching line is connected to the amplification unit and the first charging unit, and the second end of the second matching line is grounded. The search line driving unit is connected to the first bit unit group and is used to send search words to the first bit unit group; The first bit unit group is used to adjust the voltage at the first end of the first matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored first storage word satisfy the first preset relationship, and to keep the voltage at the first end of the first matching line at the predetermined voltage when the search word and the first storage word do not satisfy the first preset relationship. The first preset relationship is less than or greater than. The first bit unit group is further configured to adjust the voltage at the first end of the second matching line from the predetermined voltage to the ground voltage when the search word and the pre-stored second storage word satisfy the second preset relationship, and to maintain the voltage at the first end of the second matching line at the predetermined voltage when the search word and the second storage word do not satisfy the second preset relationship, wherein the second preset relationship is not less than or not greater than. The amplification unit is used to amplify the voltage at the first end of the first matching line to a first amplified voltage, and to amplify the voltage at the first end of the second matching line to a second amplified voltage; The matching signal unit is used to match the output range of the first amplified voltage and the second amplified voltage based on the result.

19. The content-addressable memory according to claim 18, characterized in that, Each bit unit in the first bit unit group includes a first transistor, a second transistor, a first switching unit, a second switching unit, a third switching unit, a fourth switching unit, a first bit storage unit, and a second bit storage unit. The first switching unit is used to turn on the first transistor when the search bit is equal to the first storage bit, and turn off the first transistor when the search bit is not equal to the first storage bit. The source and drain of the first transistor are connected to the first matching line. The second switching unit is used to turn on the connection between the first matching line and ground when the first search line signal and the first storage bit satisfy the first preset relationship, and to turn off the connection between the first matching line and ground when the first search line signal and the first storage bit do not satisfy the first preset relationship. The third switching unit is used to turn on the second transistor when the search bit is equal to the second storage bit, and to turn off the second transistor when the search bit is not equal to the second storage bit. The source and drain of the second transistor are connected to the second matching line. The fourth switching unit is used to connect the second matching line to ground when the second search line signal and the second storage bit satisfy the third preset relationship, and to disconnect the connection between the second matching line and ground when the second search line signal and the second storage bit do not satisfy the third preset relationship.

20. A network device, characterized in that, include: A processor is configured to receive a target range and determine a first storage word based on the upper limit of the target range; The second storage word is determined according to the lower limit of the target range, and the first storage word and the second storage word are sent to the content addressing memory. The content-addressable memory is the content-addressable memory as described in any one of claims 1 to 19.

21. The network device according to claim 20, characterized in that, The first stored word is equal to the upper limit of the target range, which is either the upper limit of the target range plus one or the upper limit of the target range minus one. as well as, The second stored word is equal to the lower limit of the target range, which is either the lower limit of the target range plus one or the lower limit of the target range minus one.

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