Method for forming a semiconductor device pattern and method for manufacturing a semiconductor device

Abstract

The present disclosure provides a method for forming a semiconductor device pattern and a manufacturing method of a semiconductor device. The method for forming a semiconductor device pattern comprises the following steps. A semiconductor substrate is provided, and a to-be-processed layer is formed above the semiconductor substrate. Then a second stack and a first stack are sequentially formed on the to-be-processed layer. The first stack is subjected to a patterning process by using a first mask to form a first preset pattern on the first stack. A second preset pattern is formed based on the first preset pattern. Based on the second preset pattern, the second stack is subjected to a patterning process by using a second mask to form a third preset pattern on the second stack, and finally the third preset pattern can be transferred to the to-be-processed layer. The present disclosure ingeniously omits the deposition process and realizes the formation of a new pattern through a photoresist double-coating process. Moreover, the technical solution provided by the present disclosure can replace the traditional PEPE process with the PPE process, greatly simplifying the process steps and reducing the cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device processing technology, and more specifically, this disclosure can provide a method for forming semiconductor device patterns and a method for manufacturing semiconductor devices. Background Technology

[0002] Currently, semiconductor devices are becoming increasingly smaller and more highly integrated. This presents a greater challenge to photolithography, one of the core processes in semiconductor device fabrication. As the size of semiconductor device patterns shrinks with increasing design requirements, even maximizing the exposure performance of photolithography machines cannot further improve exposure efficiency using conventional methods. When encountering complex patterns in semiconductor devices, conventional solutions often require adding processing steps, ultimately leading to longer processing times, reduced reliability, and increased manufacturing costs. Summary of the Invention

[0003] To address the problem of excessive steps in conventional processes for forming complex patterns in semiconductor devices, this disclosure provides a method for forming patterns in semiconductor devices and a method for manufacturing semiconductor devices, thereby achieving technical objectives such as reducing pattern forming steps, reducing processing time, and reducing processing costs.

[0004] To achieve the above-mentioned technical objectives, this disclosure provides a method for forming a pattern for a semiconductor device; the pattern forming method may include, but is not limited to, at least one of the following steps.

[0005] A semiconductor substrate is provided, and a layer to be processed is formed on the semiconductor substrate. Then, a second stack and a first stack are sequentially formed on the layer to be processed, wherein the first stack is disposed on the second stack. The first stack is patterned using a first mask to form a first preset pattern on the first stack. A second preset pattern is formed based on the first preset pattern, and the second preset pattern is also formed on the first stack. Based on the second preset pattern and using a second mask, the second stack is patterned to form a third preset pattern on the second stack. Finally, the third preset pattern is transferred to the layer to be processed by etching. The first stack includes a first anti-reflective coating and a first photoresist layer sequentially coated, and the second stack includes a second anti-reflective coating and a second photoresist layer sequentially coated. The first preset pattern is formed on the first photoresist layer, and the third preset pattern is formed on the second photoresist layer.

[0006] To achieve the above-mentioned technical objectives, this disclosure also specifically provides a method for manufacturing a semiconductor device. This manufacturing method may include, but is not limited to, the method for forming a semiconductor device pattern as described in any embodiment of this disclosure.

[0007] The beneficial effects of this disclosure are as follows: Compared with the prior art, the method for forming semiconductor device patterns specifically provided in this disclosure cleverly omits the deposition process, and instead can mainly achieve the formation of new patterns through a double coating process of photoresist. Moreover, this disclosure can replace the traditional PEPE (photolithography-etching-photolithography-etching) process with a PPE (photolithography-photolithography-etching) process, which greatly simplifies the process steps and significantly reduces the cost of processing complex patterns in semiconductor devices.

[0008] Furthermore, the technical solution provided in this disclosure has significant advantages such as ease of implementation, wide applicability, and low implementation cost. This disclosure greatly simplifies the process steps, helps to significantly shorten the processing time of semiconductor devices, and increases the output of semiconductor device products. Attached Figure Description

[0009] Figure 1 This illustration shows a schematic diagram of the longitudinal cross-sectional structure of a device after forming a layer to be processed on a semiconductor substrate and coating a second anti-reflective coating in one or more embodiments of the present disclosure.

[0010] Figure 2 A schematic diagram of the longitudinal cross-sectional structure of a device having a second photoresist layer coated on a second antireflective coating is shown in one or more embodiments of this disclosure.

[0011] Figure 3 A schematic diagram of the longitudinal cross-sectional structure of the device after a first anti-reflective coating is coated on a second photoresist layer is shown in one or more embodiments of this disclosure.

[0012] Figure 4 This illustration shows a schematic diagram of one or more embodiments of the present disclosure after a first photoresist layer is coated on a first antireflective coating and then exposed.

[0013] Figure 5 A schematic diagram of the longitudinal cross-sectional structure of the device after a first preset pattern is formed on a first photoresist layer is shown in one or more embodiments of the present disclosure.

[0014] Figure 6 A schematic diagram of the longitudinal cross-sectional structure of the device after coating with a curing material layer is shown in one or more embodiments of this disclosure.

[0015] Figure 7 A schematic diagram of the longitudinal cross-sectional structure of the device after removing the cured material below the second preset pattern gap is shown in one or more embodiments of this disclosure.

[0016] Figure 8 A schematic diagram of the longitudinal cross-sectional structure of the device after removing the first anti-reflective coating material below the second preset pattern gap is shown in one or more embodiments of this disclosure.

[0017] Figure 9 This illustration shows a schematic diagram of the exposure of a second photoresist layer using a second mask based on a second preset pattern in one or more embodiments of the present disclosure.

[0018] Figure 10 A top view of the second mask placed above the cured material layer during secondary photolithography is shown in one or more embodiments of this disclosure.

[0019] In the picture,

[0020] 100. Semiconductor substrate.

[0021] 200. Layer to be processed.

[0022] 300. Second anti-reflective coating.

[0023] 400. Second photoresist layer.

[0024] 500. First anti-reflective coating.

[0025] 600, First photoresist layer.

[0026] 700, First mask.

[0027] 701. First line structure.

[0028] 702. Second line structure.

[0029] 800, Cured material layer. Detailed Implementation

[0030] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0031] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0033] This disclosure provides a method for forming a semiconductor device pattern in one or more embodiments, which may include, but is not limited to, at least one of the following steps.

[0034] like Figure 1 As shown, a semiconductor substrate 100 is provided, and a layer 200 to be processed can be formed on the semiconductor substrate 100.

[0035] Next, a second stack and a first stack are sequentially formed on the layer to be processed 200, with the first stack on top of the second stack. The semiconductor substrate 100 involved in this disclosure may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by selective epitaxial growth (SEG). The layer to be processed involved in this disclosure may be a device layer that needs to be finally patterned, such as, but not limited to, a silicon oxide layer, a silicon nitride layer, or a metal layer. It is understood that this disclosure can directly form a layer to be processed 200 on the upper surface of the semiconductor substrate 100; or there may be one or more other film layers or device layers between the layer to be processed 200 formed in this disclosure and the semiconductor substrate 100.

[0036] like Figure 1 , 2 As shown, the second stack includes, but is not limited to, the second anti-reflective coating 300 and the second photoresist layer 400 coated sequentially, that is, the second anti-reflective coating 300 is coated and then the second photoresist layer 400 is coated.

[0037] The second anti-reflective coating 300 disclosed herein can be a bottom anti-reflection coating (BARC), whose main components may be crosslinkable resins, thermogenic acid generators, surfactants, and solvents, and has the functions of reducing reflection and standing waves. In some embodiments of this disclosure, the second anti-reflective coating 300 may include, but is not limited to, a spin-on-hardmask (SOH) layer or an amorphous carbon layer (ACL), etc. The second photoresist layer 400 disclosed herein may be, for example, a positive photoresist.

[0038] like Figure 3 ,4 As shown, the first stack includes, but is not limited to, a first anti-reflective coating 500 and a first photoresist layer 600 coated sequentially, i.e., the first anti-reflective coating 500 is coated first and then the first photoresist layer 600 is coated.

[0039] The first anti-reflective coating 500 in one or more embodiments of this disclosure is an anti-reflective coating (ARC) that is directly soluble in a water-soluble developer and is partially removed in subsequent processes. The first photoresist layer 600 of this disclosure may be a positive photoresist.

[0040] like Figure 4 , 5 As shown, a first mask 700 is used to pattern the first stacked layer to form a first preset pattern on the first stacked layer. Specifically, one or more embodiments of this disclosure include patterning the first stacked layer by using a negative tone development (NTD) process to pattern the first photoresist layer 600, thereby forming a first preset pattern (such as...) on the first photoresist layer 600. Figure 5 (As shown). The first mask 700 has a first preset pattern. Figure 4 The arrows in the diagram indicate the direction of light during exposure using the lithography machine disclosed herein.

[0041] like Figures 6 to 8 As shown, a second preset pattern is formed based on a first preset pattern, meaning the second preset pattern is obtained based on the first preset pattern. More specifically, the second preset pattern is disposed on the first layer. One or more embodiments of this disclosure involve the following steps to form the second preset pattern based on the first preset pattern. Figure 6 The curing material layer 800 shown is coated onto the first stack, which can be accomplished, for example, by a chemical attach process. In some embodiments of this disclosure, the curing material layer 800 primarily consists of a cross-linked agent, resin, and solvent. A baking and cleaning process is then performed sequentially, retaining the cured material adhered to the first stack to form a second predetermined pattern.

[0042] In specific implementation, one or more embodiments of this disclosure sequentially perform baking and cleaning processes, including at least one of the following processes.

[0043] like Figure 7 As shown, the first photoresist layer 600 after being coated with the curing material layer 800 is baked, and the curing material on the surface of the first photoresist layer 600 is retained. The baking process can be a hard bake.

[0044] like Figure 8 As shown, the first anti-reflective coating 500 is cleaned to remove the first anti-reflective coating material below the gaps in the second preset pattern. It is understood that in some embodiments of this disclosure, the cured material below the gaps in the second preset pattern may be removed after baking, followed by cleaning to remove the first anti-reflective coating material below the gaps in the second preset pattern. Alternatively, in other embodiments of this disclosure, both the cured material below the gaps in the second preset pattern and the first anti-reflective coating material are removed during the cleaning process.

[0045] In some embodiments of this disclosure, cleaning the first anti-reflective coating 500 includes cleaning the first anti-reflective coating 500 using a developer. In specific implementations, the first anti-reflective coating material within the pattern gaps can be completely removed, and the first anti-reflective coating 500 beneath the first photoresist layer 600 will be slightly corroded. In one or more embodiments of this disclosure, the developer (water or alcohol developer) is composed of an aqueous solution (Water Developer) or an alcohol solution (Alcohol Developer).

[0046] like Figure 9 As shown, based on the second preset pattern, the second layer is patterned using the second mask to form the third preset pattern on the second layer.

[0047] This disclosure describes a patterning process for the second layer, including: a second preset pattern and a second mask together forming a third preset pattern; or, it can be understood that the second preset pattern and the second mask function as a mask with the third preset pattern. One or more embodiments of this disclosure can use a positive tone development (PTD) process to pattern the second photoresist layer 400, forming the third preset pattern on the second photoresist layer 400. Figure 4 The downward-pointing arrow indicates the direction of light during lithography exposure.

[0048] like Figure 10 As shown, in some embodiments of this disclosure, the second mask includes at least one first line structure 701 and at least one second line structure 702, and the first line structure 701 and the second line structure 702 are arranged intersectingly. In some embodiments of this disclosure, multiple first line structures 701 are arranged parallel to each other, multiple second line structures 702 are arranged parallel to each other, and the first line structure 701 and the second line structure 702 are arranged perpendicularly to each other.

[0049] It is understood that the technical solutions provided in this disclosure can form complex patterns with fine dimensions and stitching using a second mask with a line structure, which can meet the needs of semiconductor device processing in various situations. For example, some embodiments of this disclosure... Figure 10 The shape shown can also be represented as the final pattern after After Develop Inspection (ADI).

[0050] Finally, this disclosure enables the transfer of a third preset pattern onto the layer 200 to be processed. Some embodiments of this disclosure include transferring the third preset pattern onto the layer 200 to be processed by: removing the first stack and the cured material layer 800, using a second photoresist layer 400 having the third preset pattern as a mask, and sequentially etching the second antireflective coating 300 and the layer 200 to be processed to form the third preset pattern on the layer 200 to be processed.

[0051] The method for forming semiconductor device patterns provided in this disclosure can achieve two photolithography processes using commonly used photolithography equipment such as ArF immersion lithography machines. Therefore, the technical solution provided in this disclosure has outstanding advantages such as ease of implementation, wide applicability, and effective reduction of device process costs. Specifically, the technical solution provided in this disclosure replaces the traditional PEPE (Photo-Etch-Photo-Etch-Etch-Etch) process with a PPE (Photo-Photo-Etch) process, omitting the film deposition process.

[0052] It is understood that this disclosure can also provide a method for manufacturing a semiconductor device, which may include, but is not limited to, the method for forming a semiconductor device pattern in any embodiment of this disclosure. The semiconductor devices involved in this disclosure may include, but are not limited to, semiconductor memory devices or logic devices. For example, a semiconductor memory device may be a dynamic random access memory (DRAM), which can contain multiple memory cells arranged in a matrix structure, each memory cell consisting of a transistor and a semiconductor capacitor controlled by the transistor. The semiconductor devices provided based on the technical solutions of this disclosure can be applied to electronic devices, including but not limited to smartphones, computers, tablets, wearable devices, artificial intelligence devices, and power banks, etc.

[0053] This disclosure can greatly improve the processing efficiency of semiconductor devices, shorten the wafer fabrication steps and the time consumed during wafer fabrication. This disclosure can significantly shorten the processing time of semiconductor devices, increase the output of semiconductor devices, and is suitable for widespread promotion and application.

[0054] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0055] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for forming a pattern for a semiconductor device, characterized in that, include: A semiconductor substrate is provided, and a layer to be processed is formed on the semiconductor substrate; A second stack and a first stack are sequentially formed on the layer to be processed, with the first stack on the second stack; The first layer is patterned using a first mask to form a first preset pattern on the first layer; A second preset pattern is formed based on the first preset pattern, and the second preset pattern is disposed on the first layer; Based on the second preset pattern, the second stack is patterned using a second mask to form a third preset pattern on the second stack; wherein, forming the second preset pattern based on the first preset pattern includes: coating a curing material layer on the first stack; performing baking and cleaning processes in sequence, and retaining the curing material adhering to the first stack to form the second preset pattern; The third preset pattern is transferred onto the layer to be processed.

2. The method for forming a semiconductor device pattern according to claim 1, characterized in that, The first stack includes a first anti-reflective coating and a first photoresist layer coated sequentially; the patterning process of the first stack includes: The first photoresist layer is patterned to form the first preset pattern on the first photoresist layer.

3. The method for forming a semiconductor device pattern according to claim 2, characterized in that, The sequential baking and cleaning processes include: The first photoresist layer after being coated with the curing material layer is baked while retaining the curing material on the surface of the first photoresist layer; the first anti-reflective coating is cleaned to remove the first anti-reflective coating material below the second preset pattern gap.

4. The method for forming a semiconductor device pattern according to claim 3, characterized in that, The cleaning of the first anti-reflective coating includes: The first antireflective coating is cleaned using a developing solution.

5. The method for forming a semiconductor device pattern according to claim 4, characterized in that, The developing solution is composed of an aqueous solution or an alcoholic solution.

6. The method for forming a semiconductor device pattern according to claim 1, characterized in that, The second stack includes a second anti-reflective coating and a second photoresist layer coated sequentially; the patterning process of the second stack includes: The second photoresist layer is patterned to form the third preset pattern on the second photoresist layer.

7. The method for forming a semiconductor device pattern according to claim 6, characterized in that, The step of transferring the third preset pattern onto the layer to be processed includes: Remove the first stack and the cured material layer; Using the second photoresist layer with the third preset pattern as a mask, the second anti-reflective coating and the layer to be processed are etched sequentially to form the third preset pattern on the layer to be processed.

8. The method for forming a semiconductor device pattern according to claim 1, characterized in that, The first mask has a first preset pattern; the second mask includes at least one first line structure and at least one second line structure, and the first line structure and the second line structure are arranged to intersect.

9. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes the method for forming a semiconductor device pattern as described in any one of claims 1 to 8.

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