Etching methods and semiconductor structures

Abstract

This application provides an etching method and a semiconductor structure, wherein the method includes: providing a substrate, the substrate including at least an etching layer and a first photoresist layer having a first opening on the etching layer; depositing a first protective layer on the sidewall of the first opening to form a first photoresist layer having a second opening; and etching the etching layer through the second opening to form a first target pattern in the etching layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, an etching method and a semiconductor structure. Background Technology

[0002] Photolithography is typically used to etch desired patterns onto an etched layer. However, as products are continuously upgraded, the requirements for the critical dimension (CD) within the pattern walls are becoming increasingly smaller. Since the process window for the critical dimension in photolithography is generally larger than 38 nanometers (nm), it is impossible to further shrink the critical dimension. Therefore, reducing the critical dimension mainly relies on etching. However, as the critical dimension shrinks further, it becomes increasingly difficult to reduce it through etching; simultaneously, the etching process window becomes smaller, making problems such as hole breaks, hole disappearances, short circuits, and open circuits more likely. Therefore, a new etching method is needed to increase the etching process window and reduce the critical dimension. Summary of the Invention

[0003] In view of this, embodiments of this application provide an etching method and a semiconductor structure.

[0004] In a first aspect, embodiments of this application provide an etching method, the method comprising: providing a substrate, the substrate comprising at least an etched layer and a first photoresist layer having a first opening on the etched layer; depositing a first protective layer on the sidewall of the first opening to form a first photoresist layer having a second opening; and etching the etched layer through the second opening to form a first target pattern in the etched layer.

[0005] In some embodiments, depositing a first protective layer on the sidewall of the first opening to form a first photoresist layer having a second opening includes: depositing an initial first protective layer on the first photoresist layer; removing the initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening, and retaining the initial first protective layer on the sidewall of the first opening to form a first photoresist layer having a second opening.

[0006] In some embodiments, providing a substrate includes: forming the first photoresist layer on the etched layer; and patterning the first photoresist layer to form a first photoresist layer having the first opening.

[0007] In some embodiments, before forming the first photoresist layer on the etched layer, the method further includes: sequentially forming a first hard mask layer, an etch stop layer, an etch penetration layer, and a second hard mask layer on the etched layer; correspondingly, the step of etching the etched layer through the second opening to form a first target pattern in the etched layer includes: etching the second hard mask layer, the etch penetration layer, and the etch stop layer through the second opening to form an etch stop layer with a first intermediate pattern; and etching the first hard mask layer and the etched layer through the first intermediate pattern to form the first target pattern in the etched layer.

[0008] In some embodiments, etching the second hard mask layer, the etching penetration layer, and the etching stop layer through the second opening to form an etching stop layer with a first intermediate pattern includes: using a first dry etching process to etch the second hard mask layer through the second opening to form a second hard mask layer with a second intermediate pattern; and using a second dry etching process to etch the etching penetration layer and the etching stop layer through the second intermediate pattern to form an etching stop layer with the first intermediate pattern.

[0009] In some embodiments, the process parameters of the second dry etching process include: a carbon hexafluoride gas flow rate of 22 to 26 standard milliliters per minute (sccm), an argon gas flow rate of 160 to 200 sccm, an oxygen gas flow rate of 20 to 24 sccm, a gas pressure of 13 to 17 millitors (mTorr), a high-frequency power of greater than 500 watts (W), a low-frequency power of greater than 2000 W, and a bias voltage of greater than 450 V.

[0010] In some embodiments, after forming an etch stop layer having a first intermediate pattern, the method further includes: forming a third intermediate pattern in the etch stop layer; etching the first hard mask layer and the etch layer through the first intermediate pattern to form a first target pattern in the etch layer, while simultaneously etching the first hard mask layer and the etch layer through the third intermediate pattern to form a second target pattern in the etch layer.

[0011] In some embodiments, forming a third intermediate pattern in the etch stop layer includes: sequentially forming a third hard mask layer and a second photoresist layer having a third opening on the etch penetration layer; depositing a second protective layer on the sidewall of the third opening to form a second photoresist layer having a fourth opening; and etching the third hard mask layer, the etch penetration layer, and the etch stop layer through the fourth opening to form the third intermediate pattern in the etch stop layer.

[0012] In some embodiments, before sequentially forming a third hard mask layer and a second photoresist layer with a third opening on the etch-through layer, the method further includes: removing all layers located above the etch-through layer.

[0013] In some embodiments, under the same etching conditions, the etching rate of the etching stop layer is less than the etching rate of the etching penetration layer.

[0014] In some embodiments, a third dry etching process is used to etch the initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening, while retaining the initial first protective layer on the sidewall of the first opening to form a first photoresist layer with a second opening. The process parameters of the third dry etching process include: a trifluoromethane flow rate in the range of 25 to 35 sccm, a helium flow rate in the range of 90 to 110 sccm, a gas pressure in the range of 4 to 6 mTorr, and a bias voltage in the range of greater than 200V.

[0015] In some embodiments, the materials of the first protective layer and the etching penetration layer include oxides, and the material of the etching stop layer includes silicon oxynitride.

[0016] In some embodiments, the depth range of the first intermediate pattern and the third intermediate pattern in the etch stop layer is 10 nm to 30 nm, and the thickness range of the etch stop layer is 25 nm to 35 nm.

[0017] In some embodiments, the initial first protective layer is deposited using an atomic vapor deposition process, and the thickness of the initial first protective layer ranges from 5 nm to 10 nm.

[0018] In some embodiments, the first target pattern is used to form a contact plug in a peripheral region of a semiconductor structure, the contact plug being used to connect the source or drain of a transistor in the peripheral region to a metal interconnect layer in the peripheral region.

[0019] Secondly, embodiments of this application provide a semiconductor structure, which is prepared according to the etching method described above.

[0020] In this embodiment, a first photoresist layer with a first opening is first provided, comprising at least an etched layer and a first photoresist layer with a first opening located on the etched layer; then a first protective layer is deposited on the sidewall of the first opening to form a first photoresist layer with a second opening; finally, the etched layer is etched through the second opening to form a first target pattern in the etched layer. This achieves the following effect:

[0021] Firstly, since a first protective layer is deposited on the sidewall of the first opening, the horizontal dimension of the first opening is greater than that of the second opening, i.e., the horizontal dimension of the second opening is smaller than that of the first opening. The horizontal dimension of the second opening affects the critical dimension of the target pattern. Therefore, it is possible to reduce the critical dimension of the first target pattern formed under the condition of the same size first opening.

[0022] Secondly, since the first opening is formed by photolithography, its size cannot be too small due to the influence of the photolithography process. However, by depositing a first protective layer on the sidewall of the first opening, the size of the opening on the photoresist layer can be reduced, and the photolithography process window can be increased.

[0023] Thirdly, by depositing a first protective layer on the sidewall of the first opening, the verticality and consistency of the first target pattern formed in the etching layer can be improved, reducing the occurrence of problems such as hole breakage, hole disappearance, short circuit, and open circuit. Attached Figure Description

[0024] Figure 1A A schematic diagram illustrating the implementation process of the "LELE" process provided in this application embodiment;

[0025] Figure 1B A schematic flowchart of an etching method provided in an embodiment of this application;

[0026] Figures 1C to 1E , Figure 1G , Figure 1H A schematic diagram illustrating the implementation process of an etching method provided in an embodiment of this application;

[0027] Figure 1F A schematic diagram of the thickness of an initial first protective layer deposited using the ALD process is provided for an embodiment of this application;

[0028] Figures 2A to 2C A schematic diagram illustrating the process of forming a second target pattern, provided in an embodiment of this application;

[0029] Figure 3A , Figure 3B , Figures 3D to 3F A schematic diagram illustrating another implementation process for forming the first target graphic and the second target graphic, provided for an embodiment of this application;

[0030] Figure 3C A schematic diagram showing that the etch stop layer provided in the embodiments of this application includes a first intermediate pattern;

[0031] Figures 4A to 4G This is a schematic diagram illustrating another implementation process for forming a first target graphic and a second target graphic, provided in an embodiment of this application. Detailed Implementation

[0032] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0033] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Before introducing the solution of this application, let's first introduce the current methods for improving the critical dimensions of the etching process (denoted as POR):

[0038] In related technologies, because the etching process has a small CD, the photoresist cannot be formed in a single exposure. Therefore, the etching pattern is split and double exposure is performed, namely photolithography, etching, photolithography, etching (LITHO-ETCH-LITHO-ETCH, LELE). Figure 1A Figure 1 is a schematic diagram of the implementation process of the "LELE" process. Figure 2 shows the first photolithography process, in which a first opening 103 is formed on the first photoresist layer 102; Figure 3 shows the first etching process, in which the etching layer 101 is etched through the first opening 103 in Figure 2a to form a first target pattern 107 on the etching layer 101; Figure 4 shows the second etching process, in which a fifth opening 202 is formed on the third photoresist layer 201; Figure 5 shows the second etching process, in which the etching layer 101 is etched through the fifth opening 202 in Figure 5c to form a second target pattern 205 on the etching layer 101.

[0039] Because the etching process has a small CD (cutoff value), the process window for photolithography becomes smaller and smaller, which can easily lead to problems such as poor uniformity of critical dimensions, broken holes, missing holes, short circuits, and open circuits.

[0040] Based on this, embodiments of this application provide an etching method, such as... Figure 1B As shown, the method includes the following steps S101 to S103:

[0041] Step S101: Provide a substrate, the substrate comprising at least an etched layer and a first photoresist layer having a first opening on the etched layer;

[0042] like Figure 1C As shown, the provided substrate 10 includes at least an etched layer 101 and a first photoresist layer 102 with a first opening 103 located on the etched layer 101.

[0043] Here, the etched layer refers to the layer used to etch and form the target pattern, and the target pattern refers to the pattern that needs to be formed in the etched layer through the etching process.

[0044] The photoresist layer refers to the layer containing the photoresist, also known as photoresist, which is a thin film etching material whose solubility changes upon irradiation or radiation such as ultraviolet light, electron beams, ion beams, and X-rays. Photoresist is photosensitive and includes components such as photosensitive resin, sensitizer, and solvent. It is used as an anti-corrosion coating material in the photolithography process. The first opening refers to the opening used to form the target pattern. A photoresist layer with a first opening indicates that the photoresist layer has undergone exposure and development, forming a first photoresist layer with the first opening.

[0045] In some embodiments, to protect the etched layer and reduce stress during the etching process, a hard mask layer is first formed on the etched layer, and then a first photoresist layer with a first opening is formed on the hard mask layer. The material of the hard mask layer may include at least one of carbon, silicon nitride, titanium nitride, and silicon oxide.

[0046] In some embodiments, the implementation of step S101 may include the following steps S1011 and S1012:

[0047] Step S1011: Form the first photoresist layer on the etched layer;

[0048] Here, photoresists can be divided into positive photoresists and negative photoresists according to their polarity. The difference is that the exposed area of ​​a negative photoresist hardens and is retained after exposure and development, while the unexposed part is dissolved by the developer; after exposure, the colloidal polymer in the exposed area of ​​a positive photoresist will break and soften due to photodissolution and eventually be dissolved by the developer, while the unexposed part is retained. The polarity of the photoresist is not limited in the embodiments of this application.

[0049] Step S1012: Pattern the first photoresist layer to form a first photoresist layer having the first opening.

[0050] Here, patterning the first photoresist layer refers to exposing and developing the first photoresist layer, wherein a portion of the first photoresist layer is dissolved to form a first opening, thereby forming a first photoresist layer with the first opening.

[0051] Step S102: Deposit a first protective layer on the sidewall of the first opening to form a first photoresist layer with a second opening;

[0052] like Figure 1D As shown, a first protective layer 104 is deposited on the sidewall of the first opening 103 to form a first photoresist layer 102 with a second opening 105.

[0053] Here, the material of the first protective layer may include oxides, such as zinc oxide, silicon oxide, etc. The first protective layer can be formed by a deposition process, including any of the following: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and any other suitable deposition process. Among these, the deposition layer formed by ALD has extremely uniform thickness and excellent consistency. In some embodiments, in order to deposit a first protective layer of a certain thickness and uniformity on the sidewall of the first opening, the first protective layer may be formed using an ALD process.

[0054] In step S102, by depositing a first protective layer on the sidewall of the first opening, a first photoresist layer with a second opening is formed, which has the following effects:

[0055] Firstly, because a first protective layer is deposited on the sidewall of the first opening, the horizontal dimension d1 of the first opening (e.g., Figure 1C As shown, the dimension parallel to the base) is compared to the horizontal dimension d2 of the second opening (as shown). Figure 1D As shown, the second opening has increased sidewall thickness, meaning its horizontal dimension d2 is smaller than the first opening's horizontal dimension d1. Since the target pattern is obtained by etching through the second opening on the photoresist layer, its horizontal dimension affects the critical dimensions of the target pattern. Therefore, reducing the horizontal dimension of the second opening reduces the critical dimensions of the target pattern. Furthermore, with the same opening size on the photoresist layer, the lithography process window can be increased, i.e., the size of the first opening can be increased, reducing the difficulty of the lithography process. The critical dimension refers to the dimension that affects the pattern performance and requires close control. The critical dimension can be determined based on the shape of the target pattern and the fabrication process. For example, for an etching process, when the target pattern is cylindrical, the diameter of the circular surface is the critical dimension; when the target pattern is cube-shaped, the side length is the critical dimension.

[0056] Secondly, by depositing a first protective layer on the sidewall of the first opening, the consistency of the second opening is improved.

[0057] Table 1: Statistics on the critical dimensions, standard deviation (Sigma), and delta (CD) of the first and second openings.

[0058]

[0059] Table 1 shows the critical dimensions and Sigma values ​​of the first and second openings, where CD represents the dimension at 30% of the depth from the bottom. As shown in Table 1, the CD of the second opening is smaller than that of the first opening, and the Sigma value is also smaller. Therefore, depositing the first protective layer on the sidewall of the first opening can result in better consistency of the second opening.

[0060] In some embodiments, the implementation of step S102, "depositing a first protective layer on the sidewall of the first opening to form a first photoresist layer having a second opening," may include the following steps S1021 and S1022:

[0061] Step S1021: Deposit an initial first protective layer on the first photoresist layer;

[0062] like Figure 1E As shown, an initial first protective layer 106 is deposited on the first photoresist layer 102.

[0063] Here, step S1021 can be performed by forming an initial first protective layer through a deposition process. The deposition process includes any of the following: chemical vapor deposition, physical vapor deposition, atomic layer deposition (ALD), and any other suitable deposition process. ALD produces a deposition layer with extremely uniform thickness and excellent consistency, and better step coverage. In some embodiments, to ensure that the sidewalls of the first opening have a uniform initial first protective layer of a certain thickness, step S1021 can be performed using an ALD process to deposit the initial first protective layer.

[0064] In some embodiments, the thickness of the initial first protective layer ranges from 5 nm to 10 nm. On the one hand, the initial first protective layer cannot be too thick, as it is difficult to form and poses a certain challenge to the process; on the other hand, the initial first protective layer cannot be too thin, as it cannot effectively reduce the critical dimensions of the target pattern and improve the perpendicularity of the second opening later. The initial first protective layer is, for example, silicon oxide. In some embodiments, since silicon nitride has higher stress and poorer contact with the first photoresist layer 102, silicon oxide can be preferentially chosen as the initial first protective layer.

[0065] Figure 1F The thickness of the initial first protective layer deposited using the ALD process is shown. From Figure 1F As can be seen from Figures (a) and (b), the initial thicknesses of the first protective layer are 9.346 nm, 9.034 nm, 9.346 nm, 7.788 nm, 9.034 nm, 8.723 nm, 8.723 nm, and 8.723 nm, respectively. These thicknesses are between 7.5 and 9.5 nm and are uniformly deposited on the sidewalls and bottom of the first opening.

[0066] Step S1022: Remove the initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening, and retain the initial first protective layer on the sidewall of the first opening to form a first photoresist layer with a second opening.

[0067] like Figure 1E As shown, the initial first protective layer 106 comprises three parts: a first part 1061 located on the upper surface of the first photoresist layer, a second part 1062 located on the sidewall of the first opening, and a third part 1063 located at the bottom of the first opening. The initial first protective layer located on the upper surface of the first photoresist layer (i.e., the first part 1061 of the initial first protective layer) and the initial first protective layer at the bottom of the first opening (i.e., the third part 1063 of the initial first protective layer) are removed, while the initial first protective layer on the sidewall of the first opening (i.e., the second part 1062 of the initial first protective layer) is retained to form a structure as shown. Figure 1D The first photoresist layer 102 shown has a second opening 105.

[0068] Here, step S1022 can be implemented by using a third dry etching process to etch away the initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening. The third dry etching process may include reactive ion etching, plasma etching, deep reactive ion etching, and xenon difluoride (XeF2) isotropic etching, etc. The type of the third dry etching process is not limited in the embodiments of this application.

[0069] In some embodiments, to preserve the initial first protective layer on the sidewall of the first opening, the process parameters of the third dry etching process may include: a trifluoromethane flow rate of 25 to 35 sccm, a helium flow rate of 90 to 110 sccm, a gas pressure of 4 to 6 mTorr, and a bias voltage greater than 200 V. For example, a trifluoromethane flow rate of 30 sccm, a helium flow rate of 100 sccm, a gas pressure of 5 mTorr, and a bias voltage of 250 V. Under these process parameters, the initial first protective layer on the sidewall of the first opening can be protected while the upper surface of the first photoresist layer and the bottom of the first opening are etched away.

[0070] In this embodiment of the application, by depositing an initial first protective layer on the first photoresist layer, then removing the initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening, and retaining the initial first protective layer on the sidewall of the first opening, the deposition of the first protective layer on the sidewall of the first opening is achieved, thereby forming a first photoresist layer with a second opening.

[0071] Step S103: Etch the etching layer through the second opening to form a first target pattern in the etching layer.

[0072] like Figure 1D As shown, the etching layer 101 is etched through the second opening 105 to form a shape in the etching layer 101 as shown. Figure 1G The first target graphic shown is 107.

[0073] In some embodiments, such as Figure 1H As shown, the substrate 10 includes an etched layer 101, a hard mask layer 108 located on the etched layer 101, and a first photoresist layer 102 with a second opening 105 located on the hard mask layer 108. The implementation of step S103 may include: etching the hard mask layer 108 and the etched layer 101 through the second opening 105 to form a photoresist layer 101 as shown in the figure. Figure 1H The first target pattern 107 is shown. A seventh opening 109 is formed in the hard mask layer 108.

[0074] Here, because the horizontal dimension of the second opening is smaller and the consistency is better, the critical dimension of the first target pattern formed in the etched layer through the second opening is also smaller and the consistency is better.

[0075] Table 2: Statistics of Key Dimensions at the Top and Bottom of the Seventh and Eighth Openings

[0076] TCD (Top CD) 36.5nm 28.3nm BCD (Bottom CD) 18.1nm 16.7nm B / T (Bottom CD / Top CD) 0.49 0.59

[0077] Table 2 shows the critical dimensions of the top and bottom of the seventh and eighth openings. The eighth opening is constructed without depositing the first protective layer on the sidewall of the first opening; instead, it is etched directly through the first opening. Figure 1H The hard mask layer 108 and etching layer 101 shown are shown, with openings formed in the hard mask layer 108. The difference between the seventh and eighth openings is that the seventh opening is formed in the hard mask layer after the first protective layer is deposited on the sidewall of the first opening; while the eighth opening is formed in the hard mask layer without depositing the first protective layer on the sidewall of the first opening. As shown in Table 2, compared to the seventh opening, the eighth opening has a smaller TCD and BCD, and a higher B / T. This means that after depositing the first protective layer on the sidewall of the first opening, the critical dimension at the opening in the hard mask layer can be reduced, and the B / T can be increased, making the sidewall of the seventh opening more vertical. Because the critical dimension of the seventh opening is smaller and more vertical than that of the eighth opening, when continuing to etch the etching layer through the seventh opening, the critical dimension of the first target pattern finally formed in the etching layer can also be smaller and have better verticality.

[0078] Table 3: Sigma values ​​and deviation statistics of key dimensions of the first target graphic

[0079]

[0080] Table 3 shows the Sigma values ​​and deviations of the critical dimensions of the first target pattern. As can be seen from Table 3, the solution provided in this application, compared to the solution (POR) in related technologies, reduces both the Sigma value and the deviation (the deviation at test point 3 is essentially equal). For example, for test point 1, the Sigma value decreased from 1.44 to 1.06, and the deviation decreased from 2.73 to 1.62, indicating better consistency of the critical dimensions of the first target pattern formed in the etched layer.

[0081] In summary, by etching the etching layer through the second opening, the critical dimensions of the first target pattern formed in the etching layer can be smaller, and the verticality and consistency can be better.

[0082] In this embodiment, a first photoresist layer with a first opening is first provided, comprising at least an etched layer and a first photoresist layer with a first opening located on the etched layer; then, a first protective layer is deposited on the sidewall of the first opening to form a first photoresist layer with a second opening; finally, the etched layer is etched through the second opening to form a first target pattern in the etched layer. This achieves the following effect:

[0083] Firstly, since a first protective layer is deposited on the sidewall of the first opening, the horizontal dimension of the first opening is greater than that of the second opening, i.e., the horizontal dimension of the second opening is smaller than that of the first opening. The horizontal dimension of the second opening affects the critical dimension of the target pattern. Therefore, it is possible to reduce the critical dimension of the first target pattern formed under the condition of the same size first opening.

[0084] Secondly, since the first opening is formed by photolithography, its size cannot be too small due to the influence of the photolithography process. However, by depositing a first protective layer on the sidewall of the first opening, the size of the opening on the photoresist layer can be reduced, and the photolithography process window can be increased.

[0085] Thirdly, by depositing a first protective layer on the sidewall of the first opening, the verticality and consistency of the first target pattern formed in the etching layer can be improved, reducing the occurrence of problems such as hole breakage, hole disappearance, short circuit, and open circuit.

[0086] In some embodiments, after step S103 "forming the first target pattern in the etched layer", the method further includes the following step S104:

[0087] Step S104: Form a second target pattern in the etched layer.

[0088] Here, as the size of semiconductor structures continues to decrease, the density of patterns within the semiconductor structure becomes increasingly higher, and a single exposure can no longer meet the requirements. Therefore, it is necessary to split the pattern into two parts and perform double exposure, or "LELE". The first target pattern is the pattern etched in the first exposure, and the second target pattern is the pattern etched in the second exposure.

[0089] In some embodiments, the method of forming the second target pattern in the etched layer in step S104 is the same as the method of forming the first target pattern in the etched layer. In practice, this may include the following steps S1041 to S1043:

[0090] Step S1041: As Figure 2A As shown, a third photoresist layer 201 with a fifth opening 202 is formed on the etched layer 101;

[0091] Step S1042: As Figure 2A As shown, deposits are formed on the sidewall of the fifth opening 202 as follows. Figure 2B The third protective layer 203 shown forms a third photoresist layer 201 with a sixth opening 204;

[0092] Step S1043: As Figure 2B As shown, the etching layer 101 is etched through the sixth opening 204 to form a shape in the etching layer 101 as shown. Figure 2C The second target graphic 205 is shown.

[0093] Here, after etching the etched layer through the sixth opening, all layers above the etched layer can be removed to form a shape like... Figure 2C The first target graphic 107 and the second target graphic 205 are shown.

[0094] In this embodiment, after forming a first target pattern in the etched layer, a second target pattern can also be formed in the etched layer, providing an etching method for forming two target patterns for the dual exposure process, which can be well applied to small-sized semiconductor structures.

[0095] In some embodiments, before step S1011 "forming the first photoresist layer on the etched layer", the method may further include: sequentially forming a first hard mask layer, an etch stop layer, an etch penetration layer, and a second hard mask layer on the etched layer.

[0096] like Figure 3A As shown, a first hard mask layer 301, an etch stop layer 302, an etch penetration layer 303, and a second hard mask layer 304 are sequentially formed on the etch layer 101.

[0097] Correspondingly, the implementation of step S103, "etching the etched layer through the second opening to form a first target pattern in the etched layer," may include the following steps S1031 and S1032a:

[0098] Step S1031: Etch the second hard mask layer, the etching penetration layer and the etching stop layer through the second opening to form an etching stop layer with a first intermediate pattern;

[0099] like Figure 3A As shown, the second hard mask layer 304, the etching penetration layer 303, and the etching stop layer 302 are etched through the second opening 105 to form a layer as shown in the figure. Figure 3B The etch stop layer 302 shown has a first intermediate pattern 305. Wherein, Figure 3B This is a schematic diagram of the structure formed after etching the second hard mask layer 304, the etch-through layer 303 and the etch-stop layer 302 through the second opening 105, and then removing all layers above the etch-stop layer.

[0100] Here, the second hard mask layer may include a bottom anti-reflectivity coating (BARC) and a spin-on hard mask (SOH). The BARC's function is to better absorb the exposure light reaching the initial photoresist layer (the photoresist layer before exposure and development), reducing reflection of the exposure light at the interface between the initial photoresist layer and the spin-on hard mask layer, thereby allowing for more uniform exposure of the initial photoresist layer. The bottom anti-reflectivity coating may include a silicon oxynitride layer; the spin-on hard mask layer may include at least one of the following: a spin-on silicon dioxide layer, a spin-on silicon nitride layer, a spin-on organic dielectric layer, or a spin-on carbon layer (SOC). This application embodiment does not limit the types of the bottom anti-reflectivity coating and the spin-on hard mask layer.

[0101] In some embodiments, step S1031 may also form other hard mask layers on the etched layer to reduce stress during the etching process or to make the target pattern formed in the etched layer meet the size requirements. For example, a fourth hard mask layer may be formed before the first hard mask layer. The material of the fourth hard mask layer may be silicon nitride. The embodiments of this application do not limit the number and material of the hard mask layers.

[0102] An etch-through layer refers to a layer that can be penetrated by the etching process, while an etch-stop layer refers to a layer that can stop the etching process. The terms etch-through layer and etch-stop layer are relative. In some embodiments, the etch-through layer and etch-stop layer can be etched using the same etching process conditions. To ensure that the etch-through layer can penetrate and the etch-stop layer can stop under the same etching process conditions, the etching rate of the etch-stop layer can be lower than the etching rate of the etch-through layer.

[0103] In some embodiments, the thickness of the etch stop layer can range from 25 nm to 35 nm. If the etch stop layer is too thin, it is difficult to stop the etching process, and if the preceding deposition process causes a deviation in the thickness of the first protective layer, the etch stop layer can easily be etched through. If the etch stop layer is too thick, it increases the difficulty of the deposition process and results in waste. Therefore, a thickness range of 25 nm to 35 nm for the etch stop layer is preferable.

[0104] Since the thickness of the etch stop layer ranges from 25nm to 35nm, in order to stop the etching process at the etch stop layer, in some embodiments, the depth of the first intermediate pattern in the etch stop layer can range from 10nm to 30nm.

[0105] like Figure 3C The diagram shows an etch stop layer containing a first intermediate pattern. It can be seen that the thickness of the etch stop layer 302 is 33.40 nm, and the depth of the first intermediate pattern in the etch stop layer 302 is 11.94 nm.

[0106] Because the etch stop layer stops the etching process, the bottom dimension of the first intermediate pattern can be larger than that without the etch stop layer, thereby improving the bottom-to-tick (B / T) ratio of the first intermediate pattern. Furthermore, since the first target pattern is subsequently formed by etching the first intermediate pattern, the improved B / T ratio of the first intermediate pattern will also improve the B / T ratio of the first target pattern.

[0107] In some embodiments, the implementation of step S1031, "etching the second hard mask layer, the etch penetration layer, and the etch stop layer through the second opening to form an etch stop layer with a first intermediate pattern," may include the following steps S131a and S131b:

[0108] Step S131a: Using a first dry etching process, the second hard mask layer is etched through the second opening to form a second hard mask layer with a second intermediate pattern;

[0109] Here, the second intermediate pattern is the pattern formed by etching away the part on the second hard mask layer using the first dry etching process.

[0110] Since the material of the second hard mask layer may differ from that of the etching penetration layer and the etching stop layer, to facilitate control under the same etching process conditions—where the etching rate of the etching stop layer can be lower than that of the etching penetration layer, and the second hard mask layer can be completely etched away—a first dry etching process can be used on the second hard mask layer, and a second dry etching process can be used on the etching penetration layer and the etching stop layer. That is, the second hard mask layer and the etching penetration layer and etching stop layer are etched step-by-step. Of course, if a single etching process condition can be used to completely etch away the second hard mask layer, and the etching rate of the etching stop layer can be lower than that of the etching penetration layer, then a single etching process condition can also be used. This application does not limit this approach.

[0111] Step S131b: Using a second dry etching process, the etching penetration layer and the etching stop layer are etched through the second intermediate pattern to form an etching stop layer with a first intermediate pattern.

[0112] Here, in the second dry etching process, the etching rate of the etching stop layer can be less than the etching rate of the etching penetration layer, so that the etching process can penetrate the etching penetration layer and stop at the etching stop layer.

[0113] In some embodiments, the process parameters of the second dry etching process may include: a carbon hexafluoride gas flow rate ranging from 22 to 26 sccm, an argon gas flow rate ranging from 160 to 200 sccm, an oxygen gas flow rate ranging from 20 to 24 sccm, a gas pressure ranging from 13 to 17 mTorr, a high-frequency power range greater than 500 W, a low-frequency power range greater than 2000 W, and a bias voltage range greater than 450 V. For example: a carbon hexafluoride gas flow rate of 24 sccm, an argon gas flow rate of 180 sccm, an oxygen gas flow rate of 22 sccm, a gas pressure of 15 mTorr, a high-frequency power of 550 W, a low-frequency power of 2100 W, and a bias voltage of 500 V.

[0114] Step S1032a: Etch the first hard mask layer and the etched layer through the first intermediate pattern to form a first target pattern in the etched layer.

[0115] like Figure 3B As shown, the first hard mask layer 301 and the etched layer 101 are etched through the first intermediate pattern 305 to form a pattern in the etched layer 101 as shown. Figure 1G The first target graphic shown is 107.

[0116] In this embodiment, before forming the first photoresist layer on the etched layer, a first hard mask layer, an etch stop layer, an etch penetration layer, and a second hard mask layer are sequentially formed on the etched layer. Then, the second hard mask layer, the etch penetration layer, and the etch stop layer are etched through a second opening to form an etch stop layer with a first intermediate pattern. Finally, the first hard mask layer and the etched layer are etched through the first intermediate pattern to form a first target pattern within the etched layer. In this way, by utilizing the stopping effect of the etch stop layer on the etching process, the bottom dimension of the first intermediate pattern is larger than that without an etch stop layer, thereby improving the bottom-to-top (B / T) ratio of the first intermediate pattern. Furthermore, since the first target pattern is formed by etching through the first intermediate pattern, the B / T ratio of the first target pattern also increases with the increase in the B / T ratio of the first intermediate pattern, resulting in better verticality of the first target pattern.

[0117] In some embodiments, after step S1031 "forming an etch stop layer having a first intermediate pattern", the method further includes the following steps S1032b and S1033b:

[0118] Step S1032b: Form a third intermediate pattern in the etch stop layer;

[0119] like Figure 3D As shown, a third intermediate pattern 306 is formed in the etch stop layer 302.

[0120] Here, the method for forming the third intermediate pattern in the etch stop layer in step S1032b can be the same as the method for forming the first intermediate pattern in the etch stop layer. The difference is that all layers above the etch penetration layer can be removed first, and then a new hard mask layer and a photoresist layer with openings can be deposited on the etch penetration layer. The third intermediate pattern is formed in the etch stop layer by etching through the openings. The reason for retaining the etch penetration layer is that, during the formation of the third intermediate pattern, the etch stop layer is also used to stop the etching process, thereby improving the batch thickness (B / T) of the third intermediate pattern.

[0121] Similarly, since the thickness of the etch stop layer ranges from 25 nm to 35 nm, in order to stop the etching process at the etch stop layer, in some embodiments, the depth of the third intermediate pattern in the etch stop layer ranges from 10 nm to 30 nm.

[0122] Step S1033b: Etch the first hard mask layer and the etched layer through the first intermediate pattern to form a first target pattern in the etched layer, and simultaneously etch the first hard mask layer and the etched layer through the third intermediate pattern to form a second target pattern in the etched layer.

[0123] Here, as Figure 3DAs shown, step S1033b can be implemented by simultaneously etching the first hard mask layer 301 and the etched layer 101 through the first intermediate pattern 305 and the third intermediate pattern 306, so as to form a structure in the etched layer 101 as shown in the figure. Figure 2C The first target graphic 107 and the second target graphic 205 are shown.

[0124] This application provides an etching method for forming two target patterns on an etched layer, where a first hard mask layer, an etch stop layer, an etch penetration layer, and a second hard mask layer are formed sequentially on the etched layer. This method is well-suited for double-exposure processes. By forming a first intermediate pattern and a third intermediate pattern in the etch stop layer, the etch stop layer is used to stop the etching process during the formation of each target pattern, thereby improving the batch-to-trace (B / T) ratio of the first and third intermediate patterns and ultimately improving the B / T ratio of the final target pattern.

[0125] In some embodiments, the implementation of step S1032b, "forming a third intermediate pattern in the etch stop layer," may include:

[0126] Step S13b1: A third hard mask layer and a second photoresist layer with a third opening are sequentially formed on the etched penetration layer;

[0127] like Figure 3E As shown, a third hard mask layer 309 and a second photoresist layer 307 with a third opening 308 are sequentially formed on the etch penetration layer 303.

[0128] Here, the third hard mask layer may include a bottom anti-reflective layer and a spin-coated hard mask layer. The material of the third hard mask layer may be the same as or different from the material of the first hard mask layer.

[0129] In some embodiments, step S13b1 may be preceded by: removing all layers located above the etch-through layer.

[0130] Here, removing all layers above the etch-through layer is to form a new third hard mask layer and a second photoresist layer on the etch-through layer, thereby forming an opening on the second photoresist layer for etching to form the third intermediate pattern; in addition, retaining the etch-through layer allows the etch stop layer to be used to stop the etching process during the formation of the third intermediate pattern, thereby improving the B / T of the third intermediate pattern.

[0131] Step S13b2: Deposit a second protective layer on the sidewall of the third opening to form a second photoresist layer with a fourth opening;

[0132] like Figure 3E As shown, deposits are formed on the sidewall of the third opening 308 as follows. Figure 3FThe second protective layer 311 shown forms a second photoresist layer 307 with a fourth opening 310.

[0133] Step S13b3: Etch the third hard mask layer, the etching penetration layer and the etching stop layer through the fourth opening to form the third intermediate pattern in the etching stop layer.

[0134] like Figure 3F As shown, the third hard mask layer 309, the etch-through layer 303, and the etch stop layer 302 are etched through the fourth opening 310 to form a structure in the etch stop layer 302 as shown. Figure 3D The third intermediate graphic 306 is shown.

[0135] In this embodiment, a third intermediate pattern is formed in the etch stop layer by sequentially forming a third hard mask layer and a second photoresist layer with a third opening on the etch penetration layer; then a second protective layer is deposited on the sidewall of the third opening to form a second photoresist layer with a fourth opening; finally, the third hard mask layer, the etch penetration layer and the etch stop layer are etched through the fourth opening.

[0136] This application embodiment also provides an etching method for etching to form a first target pattern and a second target pattern, wherein the first target pattern and the second target pattern are used to form contact plugs in the peripheral region of a semiconductor structure, and the contact plugs are used to connect the source or drain of the transistor in the peripheral region to the metal interconnect layer of the peripheral region. The method includes the following steps S201 to S208:

[0137] Step S201: Sequentially form a fourth hard mask layer, a first hard mask layer, an etch stop layer, an etch penetration layer, a second hard mask layer, and a first photoresist layer with a first opening on the etch layer;

[0138] like Figure 4A As shown, a fourth hard mask layer 401, a first hard mask layer 301, an etch stop layer 302, an etch penetration layer 303, a second hard mask layer 304, and a first photoresist layer 102 with a first opening 103 are sequentially formed on the etch layer 101. The etch layer 101 is the layer containing the dielectric layer covering the peripheral transistor 402; the fourth hard mask layer 401 is a silicon nitride layer used to give the formed first target pattern the required size; the etch stop layer 302 is a silicon oxynitride layer, and the etch penetration layer 303 is an oxide layer, wherein the etch rate of the etch stop layer is less than the etch rate of the etch penetration layer; the second hard mask layer 304 includes a BARC layer 3042 and an SOH layer 3041, where the BARC layer is a silicon oxynitride layer and the SOH layer is a spin-coated carbon layer; the first opening is used to etch and form the first target pattern, and the first opening is formed by patterning the first photoresist layer.

[0139] Step S202: Deposit a first protective layer on the sidewall of the first opening to form a first photoresist layer with a second opening;

[0140] like Figure 4A As shown, the deposits on the sidewall of the first opening 103 are as follows Figure 4B The first protective layer 104 shown forms a first photoresist layer 102 with a second opening 105.

[0141] Step S203: Etch the second hard mask layer, the etching penetration layer and the etching stop layer through the second opening to form an etching stop layer with a first intermediate pattern;

[0142] like Figure 4B As shown, the second hard mask layer 304, the etching penetration layer 303, and the etching stop layer 302 are etched through the second opening 105 to form a layer as shown in the figure. Figure 4C The etch stop layer 302 shown has a first intermediate pattern 305.

[0143] Step S204: Remove all layers located above the etched penetration layer;

[0144] Remove all layers above the etch-through layer 303 to form a layer like Figure 4C The structure shown.

[0145] Step S205: A third hard mask layer and a second photoresist layer with a third opening are sequentially formed on the etched penetration layer;

[0146] like Figure 4D As shown, a third hard mask layer 309 and a second photoresist layer 307 with a third opening 308 are sequentially formed on the etch penetration layer 303. The third hard mask layer 309 includes a BARC layer 3092 and an SOH layer 3091.

[0147] Step S206: Deposit a second protective layer on the sidewall of the third opening to form a second photoresist layer with a fourth opening;

[0148] like Figure 4D As shown, deposits are formed on the sidewall of the third opening 308 as follows. Figure 4E The second protective layer 311 shown forms a second photoresist layer 307 with a fourth opening 310.

[0149] Step S207: Etch the third hard mask layer, the etching penetration layer and the etching stop layer through the fourth opening to form the third intermediate pattern in the etching stop layer;

[0150] like Figure 4EAs shown, the third hard mask layer 309, the etching penetration layer 303, and the etching stop layer 302 are etched through the fourth opening 310, forming a structure in the etching stop layer 302 as shown. Figure 4F The third intermediate figure 306 shown here, Figure 4F The structure obtained after removing all layers above the etch stop layer 302.

[0151] Step S208: Etch the first hard mask layer, the fourth hard mask layer, and the etched layer through the first intermediate pattern to form a first target pattern in the etched layer, and simultaneously etch the first hard mask layer, the fourth hard mask layer, and the etched layer through the third intermediate pattern to form a second target pattern in the etched layer.

[0152] like Figure 4F As shown, the first hard mask layer 301, the fourth hard mask layer 401, and the etched layer 101 are simultaneously etched through the first intermediate pattern 305 and the third intermediate pattern 306, forming a structure in the etched layer 101 as shown in the figure. Figure 4G The first target graphic 107 and the second target graphic 205 are shown.

[0153] Here, when the first and second target patterns are used to form contact plugs in the peripheral region of a semiconductor structure, insulating layers, buffer layers, and conductive layers can be deposited on the inner walls of both the first and second target patterns to form contact plugs in the peripheral region. Since one end of the contact plug is connected to the source or drain of the transistor in the peripheral region, and the other end is connected to the metal interconnect layer of the peripheral region, signal transmission and logic operations can be achieved.

[0154] This application also provides a semiconductor structure formed using the method described in any of the above embodiments.

[0155] The semiconductor structure provided in this application embodiment is similar to the method for forming the semiconductor structure provided in the above embodiments. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0156] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0157] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0158] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this application should be determined by the scope of the claims.

Claims

1. An etching method, characterized in that, include: A substrate is provided, the substrate comprising at least an etched layer and a first photoresist layer having a first opening on the etched layer; A first protective layer is deposited on the sidewall of the first opening to form a first photoresist layer with a second opening; The etching layer is etched through the second opening to form a first target pattern in the etching layer; A first protective layer is deposited on the sidewall of the first opening to form a first photoresist layer having a second opening, including: An initial first protective layer is deposited on the first photoresist layer; Remove the initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening, and retain the initial first protective layer on the sidewall of the first opening to form a first photoresist layer with a second opening; The provided substrate includes: The first photoresist layer is formed on the etched layer; The first photoresist layer is patterned to form a first photoresist layer having the first opening; Before forming the first photoresist layer on the etched layer, the method further includes: A first hard mask layer, an etch stop layer, an etch penetration layer, and a second hard mask layer are sequentially formed on the etched layer. Correspondingly, the step of etching the etched layer through the second opening to form a first target pattern in the etched layer includes: The second hard mask layer, the etching penetration layer, and the etching stop layer are etched through the second opening to form an etching stop layer with a first intermediate pattern. The first hard mask layer and the etched layer are etched using the first intermediate pattern to form the first target pattern in the etched layer.

2. The etching method according to claim 1, characterized in that, The step of etching the second hard mask layer, the etching penetration layer, and the etching stop layer through the second opening to form an etching stop layer with a first intermediate pattern includes: The first dry etching process is used to etch the second hard mask layer through the second opening to form a second hard mask layer with a second intermediate pattern. The second dry etching process is used to etch the etching penetration layer and the etching stop layer through the second intermediate pattern to form an etching stop layer with the first intermediate pattern.

3. The etching method according to claim 2, characterized in that, The process parameters for the second dry etching process include: carbon hexafluoride gas flow rate ranging from 22 to 26 sccm, argon gas flow rate ranging from 160 to 200 sccm, oxygen gas flow rate ranging from 20 to 24 sccm, gas pressure ranging from 13 to 17 mTorr, high-frequency power ranging from greater than 500W, low-frequency power ranging from greater than 2000W, and bias voltage ranging from greater than 450V.

4. The etching method according to claim 3, characterized in that, After forming the etch stop layer with the first intermediate pattern, the process also includes: A third intermediate pattern is formed in the etching stop layer; The first hard mask layer and the etched layer are etched using the first intermediate pattern to form a first target pattern in the etched layer, while the first hard mask layer and the etched layer are etched using the third intermediate pattern to form a second target pattern in the etched layer.

5. The etching method according to claim 4, characterized in that, A third intermediate pattern is formed in the etch stop layer, including: A third hard mask layer and a second photoresist layer with a third opening are sequentially formed on the etched penetration layer; A second protective layer is deposited on the sidewall of the third opening to form a second photoresist layer with a fourth opening; The third hard mask layer, the etching penetration layer, and the etching stop layer are etched through the fourth opening to form the third intermediate pattern in the etching stop layer.

6. The etching method according to claim 5, characterized in that, Before the third hard mask layer and the second photoresist layer with the third opening are sequentially formed on the etch-through layer, the method further includes: Remove all layers located above the etched penetration layer.

7. The etching method according to any one of claims 1 to 6, characterized in that, Under the same etching conditions, the etching rate of the etching stop layer is less than the etching rate of the etching penetration layer.

8. The etching method according to claim 1, characterized in that, The initial first protective layer located on the upper surface of the first photoresist layer and the bottom of the first opening is etched using a third dry etching process, while the initial first protective layer on the sidewall of the first opening is retained, to form a first photoresist layer with a second opening. The process parameters of the third dry etching process include: a trifluoromethane flow rate of 25 to 35 sccm, a helium flow rate of 90 to 110 sccm, a gas pressure of 4 to 6 mTorr, and a bias voltage greater than 200V.

9. The etching method according to any one of claims 1 to 6, characterized in that, The materials of the first protective layer and the etching penetration layer include oxides, and the material of the etching stop layer includes silicon oxynitride.

10. The etching method according to claim 4, characterized in that, The depth range of the first intermediate pattern and the third intermediate pattern in the etching stop layer is 10nm to 30nm, and the thickness range of the etching stop layer is 25nm to 35nm. The initial first protective layer is deposited using an atomic vapor deposition process, and the thickness of the initial first protective layer ranges from 5 nm to 10 nm.

11. The etching method according to any one of claims 1 to 6, characterized in that, The first target pattern is used to form a contact plug in the peripheral region of a semiconductor structure, and the contact plug is used to connect the source or drain of the transistor in the peripheral region to the metal interconnect layer of the peripheral region.

12. A semiconductor structure, characterized in that, Prepared by the etching method according to any one of claims 1 to 11.

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