Semiconductor structure

Abstract

The application provides a semiconductor structure, and relates to the technical field of semiconductors, which comprises a substrate, a dielectric layer on the substrate, a through hole penetrating through the dielectric layer and the substrate and filled with a first conductive material, and a buffer structure comprising a first buffer part arranged on the substrate outside the through hole, wherein the first buffer part comprises a honeycomb-arranged shallow trench isolation structure in the shape of a regular hexagon. The semiconductor structure provided by the application can buffer the expansion stress of the TSV acting on the outside, avoid affecting the components in the semiconductor structure, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] An integrated circuit (IC) chip is a chip made by placing a large number of microelectronic components (transistors, resistors, capacitors, etc.) on a substrate.

[0003] Currently, IC chip packaging technology is increasingly moving towards thinner and lighter designs and greater reliability. Taking memory chips as an example, by stacking at least two IC chips, semiconductor integration processes can produce chips with twice the memory capacity of traditional chips. Furthermore, chip stacking offers advantages such as increased mounting density and improved utilization of mounting area. Among IC chip stacking technologies, TSV (Through-Via) technology is becoming increasingly widely used. TSV technology establishes electrical connections from the active side of the chip to the back side by creating through-holes on a silicon wafer and filling these holes with conductive material. TSV provides the shortest interconnect path, creating a pathway for eventual 3D integration.

[0004] However, IC chips packaged using TSV technology are subject to thermal stress, which can affect the operating characteristics of the components within the IC chip. Summary of the Invention

[0005] To address at least one of the problems mentioned in the background art, the present invention provides a semiconductor structure capable of multiple buffering of the expansion stress exerted by TSV on the active region, thereby avoiding impact on the components in the semiconductor structure and improving the performance of the semiconductor structure.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a semiconductor structure, comprising:

[0008] Substrate;

[0009] The dielectric layer is located on the substrate;

[0010] A via, penetrating the dielectric layer and the substrate, and filled with a first conductive material;

[0011] A buffer structure includes a first buffer portion disposed on a substrate around a through hole;

[0012] The first buffer section includes a shallow groove isolation structure arranged in a honeycomb pattern of regular hexagons.

[0013] Optionally, in the semiconductor structure described above, the first buffer portion may further include:

[0014] The active region is located inside the shallow trench isolation structure and is closely adjacent to the shallow trench isolation structure.

[0015] In the semiconductor structure described above, optionally, the outer contour of the active region has a regular hexagonal structure.

[0016] In the semiconductor structure described above, optionally, the first buffer portion is an annular structure surrounding the periphery of the through hole.

[0017] In the semiconductor structure described above, optionally, the first buffer portion includes multiple buffer segments, which are spaced apart circumferentially along the via.

[0018] In the semiconductor structure described above, optionally, the buffer segment is an arc-shaped segment.

[0019] As described above, the semiconductor structure may optionally include a second buffer portion disposed within the dielectric layer. The second buffer portion includes a plurality of spaced-apart connecting pillars that extend along the thickness direction of the dielectric layer and whose bottoms are located on the active region.

[0020] In the semiconductor structure described above, optionally, the connecting pillars and the active region correspond one-to-one.

[0021] In the semiconductor structure described above, optionally, the projection of the connecting pillars onto the active region is entirely within the active region.

[0022] In the semiconductor structure described above, optionally, the center line of the connecting pillar coincides with the center line of the active region.

[0023] In the semiconductor structure described above, optionally, the dielectric layer includes multiple sub-dielectric layers stacked sequentially, and the connecting pillars include multiple sub-segments stacked sequentially, with each sub-dielectric layer and sub-segment corresponding to the other.

[0024] Optionally, the semiconductor structure may further include:

[0025] The connecting pad is located above the connecting post and makes direct contact with multiple connecting posts.

[0026] In the semiconductor structure described above, optionally, the connection pad is grounded.

[0027] Optionally, the semiconductor structure may further include:

[0028] A honeycomb-shaped hexagonal isolation structure is located in the sub-dielectric layer, with connecting pillars passing through the isolation structure;

[0029] In this case, the projection of the isolation structure onto the substrate is located inside the shallow trench isolation structure, and the material of the isolation structure is different from that of the dielectric layer.

[0030] In the semiconductor structure described above, optionally, at least one metal layer is disposed within the sub-dielectric layer, and the metal layer is made of the same material as the sub-segments within the sub-dielectric layer.

[0031] The semiconductor structure provided in this embodiment provides a buffer structure within the substrate and dielectric layer. The buffer structure includes a first buffer portion disposed on the substrate around the via. The first buffer portion is a honeycomb-shaped shallow trench isolation structure extending outward from the via in regular hexagonal shapes. The shallow trench isolation structure relies on its own regular hexagonal isolation walls. The honeycomb-shaped regular hexagonal shallow trench isolation structure has the largest number of distributions per unit area, which can effectively absorb and disperse the expansion stress from the first conductive material inside the via. By making the shallow trench isolation structure extend in a honeycomb shape from the outer edge of the via in a direction away from the via, multiple buffering of expansion stress can be achieved, protecting the substrate structure around the via and the characteristics of the components on the substrate. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a top view of a semiconductor substrate.

[0034] Figure 2 This is a schematic diagram of a longitudinal section of a semiconductor structure;

[0035] Figure 3 This is a schematic diagram of a longitudinal section of a semiconductor structure provided in an embodiment of the present invention;

[0036] Figure 4 A top view of the substrate of the semiconductor structure provided in an embodiment of the present invention;

[0037] Figure 5 for Figure 4 A partial structural diagram at point A in the middle;

[0038] Figure 6 This is a schematic diagram of the shallow trench isolation structure provided in an embodiment of the present invention;

[0039] Figure 7 A top view of another substrate for the semiconductor structure provided in an embodiment of the present invention;

[0040] Figure 8 A top view of a third type of substrate for a semiconductor structure provided in an embodiment of the present invention;

[0041] Figure 9 A schematic diagram of a longitudinal section of another semiconductor structure provided in an embodiment of the present invention;

[0042] Figure 10 This is a schematic diagram of a longitudinal section of a third semiconductor structure provided in an embodiment of the present invention;

[0043] Figure 11 This is a schematic diagram of a longitudinal section of a fourth semiconductor structure provided in an embodiment of the present invention;

[0044] Figure 12 This is a longitudinal cross-sectional schematic diagram of the fifth semiconductor structure provided in an embodiment of the present invention.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1-Through silicon via; 2-Silicon substrate; 3-Dielectric layer; 4-Guard ring; 5-Exclusion area; 6-Component;

[0047] 100 - Substrate; 200 - Dielectric layer; 300 - Through-hole; 301 - First conductive material;

[0048] 210 - Sub-dielectric layer; 410 - First buffer section; 420 - Second buffer section; 430 - Connecting pad; 440 - Metal layer;

[0049] 411-Shallow trench isolation structure; 412-Active area; 421-Connecting post; 422-Isolation structure;

[0050] 4211-sub-segment. Detailed Implementation

[0051] TSV (Through Silicon Vias) technology encapsulates multiple IC chips into a single unit by vertically creating through-silicon vias on at least two stacked IC chips and filling the vias with conductive material.

[0052] IC chips packaged using TSV technology are prone to expansion and contraction of the conductive material within the silicon through-hole due to thermal stress. This can cause stress deformation of the silicon substrate and dielectric layer around the silicon through-hole, affecting the operating characteristics of components on the silicon substrate surface and within the dielectric layer, and even causing structural damage to the components.

[0053] Figure 1 This is a top view of a substrate with a semiconductor structure. Figure 2 This is a schematic diagram of a longitudinal section of a semiconductor structure. (Refer to...) Figure 1 As shown, by arranging a protective ring 4 on the surface of the silicon substrate 2, the protective ring 4 surrounds the silicon via 1, thereby preventing the voltage of the conductive material inside the silicon via 1 from affecting the surrounding components 6.

[0054] Reference Figure 2 As shown in the figure, the direction indicated by the arrow is the direction in which the conductive material inside the silicon through-hole 1 releases thermal stress outward. Currently, it is also possible to reduce the impact of the thermal stress generated inside the silicon through-hole 1 on the component 6 by setting an exclusion zone 5 (KOZ) around the silicon through-hole 1. No component 6 is placed in the exclusion zone 5, that is, the component 6 is placed away from the silicon through-hole 1.

[0055] However, whether a protective ring 4 is set on the surface of the silicon substrate 2 or an exclusion area 5 is set around the silicon via 1, due to the high integrity of the silicon substrate 2 and the dielectric layer 3, the thermal stress generated in the silicon substrate 2 and the dielectric layer 3 cannot be effectively eliminated, and will still affect the characteristics of the components 6 in the silicon substrate 2 or the dielectric layer 3.

[0056] In view of this, embodiments of the present invention provide a semiconductor structure that, by providing a buffer structure within the semiconductor structure, at least reduces or eliminates thermal stress on the substrate surface, thereby protecting the characteristics of components on the substrate surface from damage. The semiconductor structure provided in this embodiment will be described in detail below.

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Figure 3 This is a schematic diagram of a longitudinal section of a semiconductor structure provided in an embodiment of the present invention; Figure 4 A top view of the substrate of the semiconductor structure provided in an embodiment of the present invention; Figure 5 for Figure 4 A partial structural diagram at point A in the middle; Figure 6 This is a schematic diagram of the shallow trench isolation structure provided in an embodiment of the present invention.

[0059] The semiconductor structure provided in this embodiment can be applied to IC chips. For example, the IC chip can be a dynamic random access memory chip or a logic chip, etc. This embodiment does not limit the IC chips to which the semiconductor structure can be applied.

[0060] Reference Figure 3As shown, the semiconductor structure provided in this embodiment includes a substrate 100 and a dielectric layer 200 located on the substrate 100. The material constituting the substrate 100 can be single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator (SOI) or other materials known to those skilled in the art.

[0061] In this embodiment, the substrate 100 may be a silicon substrate, and an active region 412 and a shallow trench isolation structure 411 (STI) are formed in the substrate 100 to isolate the active region 412.

[0062] The active region 412 may include a silicon substrate region doped with N-type or P-type ions.

[0063] The dielectric layer 200 disposed on the substrate 100 is typically an insulating layer. The dielectric layer 200 can be used to arrange components, or it can be used to arrange transistor traces. For example, the dielectric layer 200 contains transistor gate lines.

[0064] The material constituting the dielectric layer 200 is an insulating material. For example, the dielectric layer 200 is made of silicon nitride, silicon oxynitride, silicon carbide nitride, or other insulating materials known to those skilled in the art. Alternatively, the dielectric layer 200 can be deposited on the substrate 100 using a vapor deposition process, such as physical vapor deposition or chemical vapor deposition.

[0065] A through-hole 300 is provided in the dielectric layer 200 and the substrate 100. The through-hole 300 is filled with a first conductive material 301, which enables electrical connection between the semiconductor structure and other semiconductor structures. For example, the first conductive material 301 enables electrical connection between two stacked IC chips. Exemplarily, the first conductive material 301 can be a metal such as copper, aluminum, tungsten, or iron, or an alloy of these metals.

[0066] Because the coefficients of thermal expansion of the first conductive material 301 and the substrate 100 differ significantly, thermal stress will be generated around the via 300. For example, if the first conductive material 301 is copper and the substrate 100 is silicon, the coefficient of thermal expansion of copper is 16.4E. -6 The coefficient of thermal expansion of the silicon substrate is 2.6E at / ℃. 6 / ℃. The difference in the coefficient of thermal expansion between the first conductive material 301 and the substrate 100 will cause thermal stress to be generated on the substrate 100 around the via 300. The thermal stress will affect the characteristics of the components located on the substrate 100 around the via 300. For example, the thermal stress will affect the electron migration characteristics of the transistor.

[0067] To mitigate the impact of thermal stress on the first conductive material 301 on surrounding components and the substrate 100, the semiconductor structure provided in this embodiment further includes a buffer structure. (Refer to...) Figure 4 As shown, the buffer structure includes a first buffer section 410, which is disposed on the substrate 100 on the outer periphery of the through hole 300. The first buffer section 410 provides multiple buffers for the expansion stress generated by the first conductive material 301 on the outside of the through hole 300, thereby protecting the components outside the through hole 300.

[0068] The first buffer section 410 is disposed in a certain area around the outer periphery of the through hole 300, and buffers the expansion stress in the area it covers. It is understood that the coverage area of ​​the first buffer section 410 can be set according to actual needs, and this embodiment does not impose specific limitations on it.

[0069] Specifically, refer to Figure 5 As shown, the first buffer portion 410 includes a honeycomb-shaped shallow trench isolation structure 411 in the shape of regular hexagons. The shallow trench isolation structure 411 is, for example, the aforementioned STI. That is, the honeycomb-shaped shallow trench isolation structure 411 forms an isolation area around the through hole 300. In other words, the isolation area within the coverage area of ​​the first buffer portion 410 is a regular hexagonal shallow trench isolation structure 411.

[0070] Additionally, the first buffer section 410 also includes an active region 412 located within its coverage area. The active region 412 within the coverage area of ​​the first buffer section 410 is located within the area enclosed by the hexagonal shallow trench isolation structure 411. (See reference...) Figure 6 As shown, since the shallow trench isolation structure 411 is a regular hexagon, the area enclosed by the shallow trench isolation structure 411, that is, the area located within the shallow trench isolation structure 411, is also a regular hexagon. In other words, the outer contour of the active area 412 within the coverage area of ​​the first buffer part 410 has a regular hexagonal structure.

[0071] It should be noted that in this embodiment, the first buffer portion 410 may be located only in a certain area around the via 300. For example, the first buffer portion 410 may cover the area around the via 300 with large expansion stress; or, the first buffer portion 410 may cover the entire surface of the substrate 100, that is, the honeycomb-arranged regular hexagonal shallow trench isolation structure 411 covers the entire surface of the substrate 100, and the area enclosed by the shallow trench isolation structure 411 is the active region 412 with a regular hexagonal outer contour.

[0072] The shallow trench isolation structure 411, which is in the shape of a regular hexagon, can be filled with a material different from that of the substrate 100. Taking a silicon substrate as an example, the shallow trench isolation structure 411 can be filled with silicon oxide, for example. In this way, the material constituting the shallow trench isolation structure 411 is different from the material constituting the substrate 100. When the substrate 100 is subjected to the expansion stress of the first conductive material 301, the shallow trench isolation structure 411 has a different strength than the substrate 100, and can play a buffering role.

[0073] Reference Figure 6 As shown, by setting the shallow trench isolation structure 411 as a regular hexagon, the hexagonal shallow trench isolation structure 411 arranged in a honeycomb pattern forms the topology of the substrate 100 surface. The shallow trench isolation structure 411 absorbs and disperses the expansion stress from the first conductive material 301 by utilizing its regular hexagonal isolation wall. Furthermore, since the shallow trench isolation structure 411 extends outward in a honeycomb pattern around the through hole 300, when the expansion stress acts on the adjacent regular hexagonal shallow trench isolation structures 411, the stress generated on the adjacent shallow trench isolation structures 411 can partially cancel each other out.

[0074] Taking a regular hexagonal shallow trench isolation structure 411 as an example, when expansion stress is applied to the shallow trench isolation structure 411, the isolation walls on opposite sides of the regular hexagonal isolation wall of the shallow trench isolation structure 411 can partially cancel each other out, and the adjacent isolation walls can partially cancel out and disperse stress outward.

[0075] Because the shallow trench isolation structure 411 extends outward in a honeycomb shape, the expansion stress is offset and dispersed layer by layer, which can effectively reduce or even eliminate the expansion stress of the first conductive material 301. In addition, the hexagonal isolation walls of the shallow trench isolation structure 411 can improve the strength of the shallow trench isolation structure 411. After absorbing the expansion stress, the shallow trench isolation structure 411 has little impact on its own structure. In this way, the deformation of the substrate 100 around the via 300 can be reduced, protecting the characteristics of the components around the via 300.

[0076] Reference Figure 4 As shown, in this embodiment, the first buffer portion 410 surrounding the through hole 300 can be a ring structure, that is, each region of the through hole 300 in the circumferential direction is provided with a first buffer portion 410, and the hexagonal shallow groove isolation structure 411 forms a continuous ring structure along the circumferential direction of the through hole 300. Through the shallow groove isolation structure 411 extending outward in a honeycomb structure layer by layer, the expansion stress of each region of the through hole 300 in the circumferential direction can be effectively absorbed and buffered.

[0077] Specifically, in one embodiment, the outer contour of the first buffer portion 410 can be rectangular.

[0078] Figure 7 This is a top view of another substrate for a semiconductor structure provided in an embodiment of the present invention. (Refer to...) Figure 7 As shown, in another embodiment, the first buffer portion 410 can be a ring structure. The through hole 300 penetrating the dielectric layer 200 and the substrate 100 can be configured as a circular hole. The first conductive material 301 filled in the through hole 300 is cylindrical. The cylindrical first conductive material 301 uniformly releases expansion stress outward in its circumferential direction. By configuring the first buffer portion 410 as a ring structure, the first buffer portion 410 of the ring structure has the same extension width in each region in its circumferential direction. Therefore, the absorption and buffering effect of expansion stress in each region of the first conductive material 301 in the circumferential direction is more uniform.

[0079] Figure 8 This is a top view of a third type of substrate for a semiconductor structure provided in an embodiment of the present invention. (Refer to...) Figure 8 As shown, in other embodiments, the first buffer section 410 may further include multiple buffer segments, which are spaced apart circumferentially along the through hole 300. By providing multiple buffer segments spaced apart circumferentially around the through hole 300, each buffer segment can provide multiple buffers for the expansion stress in the corresponding coverage area. Furthermore, the segmented buffer segments can reduce the electromagnetic induction effect caused by the first buffer section 410 when the first conductive material 301 transmits signals, further reducing the impact on external components.

[0080] Reference Figure 8 As shown, for example, the buffer segment can be an arc-shaped segment, such as an arc-shaped segment that matches the outer contour of the through hole 300. The inner side of the buffer segment can be located at the outer edge of the through hole 300, and the buffer segment extends outward in a honeycomb shape along the radial direction of the through hole 300.

[0081] Alternatively, the buffer segment can be a straight line segment, with multiple straight buffer segments spaced circumferentially around the outer periphery of the through hole 300; or the buffer segment can be a broken line segment or other shapes, which are not specifically limited in this embodiment.

[0082] In summary, by providing a first buffer portion 410 on the substrate 100 around the via 300, the first buffer portion 410 surrounds the via 300. The first buffer portion 410 includes multiple hexagonal shallow trench isolation structures 411 that extend in a honeycomb arrangement. The hexagonal shallow trench isolation structures 411 diffuse or offset the expansion stress of the first conductive material 301 on the periphery of the via 300 by relying on their hexagonal isolation wall structure. Furthermore, the multiple honeycomb-shaped shallow trench isolation structures 411 arranged in layers provide multiple buffers for the expansion stress, thus protecting the components and the structure of the substrate 100 around the via 300.

[0083] In practical applications, the substrate 100 will be affected by the expansion stress of the first conductive material 301 in the via 300. At the same time, the dielectric layer 200 on the substrate 100 will also be affected by the expansion stress of the first conductive material 301. In this embodiment, in order to reduce or eliminate the effect of expansion stress on the dielectric layer 200, a second buffer portion 420 is also provided in the dielectric layer 200.

[0084] Reference Figure 3 As shown, the second buffer section 420 provided in the dielectric layer 200 may include a plurality of spaced connecting posts 421. The connecting posts 421 may extend along the thickness direction of the dielectric layer 200, and the bottom of the connecting posts 421 is located on the active region 412.

[0085] Specifically, multiple spaced contact holes can be formed within the dielectric layer 200. For example, multiple spaced contact holes can be formed by etching within the dielectric layer 200 using a photolithography process. The contact holes penetrate the dielectric layer 200, and then a second conductive material is filled into the contact holes to form multiple spaced connecting pillars 421. The second conductive material can be the same as or different from the first conductive material 301. For example, the second conductive material can be a metal such as copper, aluminum, tungsten, or iron, or an alloy of these metals.

[0086] The connecting post 421 penetrates the dielectric layer 200, and the bottom of the connecting post 421 is located inside the shallow trench isolation structure 411 of a regular hexagon. That is, the bottom end of the connecting post 421 is in contact with the active area 412 enclosed by the shallow trench isolation structure 411. By grounding the top end of the connecting post 421, the corresponding active area 412 can be grounded. This can reduce the electrical influence of the first conductive material 301 in the via 300 on the components around the via 300.

[0087] Specifically, taking a regular hexagonal shallow trench isolation structure 411 as an example, the active area 412 enclosed by the shallow trench isolation structure 411 can be connected to a connecting post 421, and the active area 412 is grounded through the connecting post 421; or, the active area 412 can be connected to two or more connecting posts 421, and the multiple connecting posts 421 connected in the active area 412 are arranged at intervals.

[0088] To avoid the influence of the connecting post 421 on the structure of the dielectric layer 200, one connecting post 421 can be connected within each active region 412, and each active region 412 is connected to one connecting post 421, that is, there is a one-to-one correspondence between the connecting post 421 and the active region 412. In this way, each active region 412 is grounded through the connecting post 421 connected to it, and all connecting posts 421 can ground all active regions 412 within the first buffer section 410, that is, the entire first buffer section 410 is grounded.

[0089] Furthermore, since the multiple connecting posts 421 correspond to the multiple active regions 412 within the first buffer section 410, the multiple connecting posts 421 surround the outer periphery of the through hole 300, and the multiple connecting posts 421 are spaced outwards and inwards from the outer edge of the through hole 300 in a direction away from the through hole 300. These multiple connecting posts 421 spaced outwards can disperse the expansion stress exerted outwards by the first conductive material 301 within the through hole 300 on the dielectric layer 200. The multiple connecting posts 421 play a role in multiple buffering of expansion stress, which can weaken or even avoid the influence of the expansion stress generated by the first conductive material 301 on the dielectric layer 200, protect the structure of the dielectric layer 200, and protect the electrical performance of the components located on the outer periphery of the through hole 300 within the dielectric layer 200.

[0090] Reference Figure 3 As shown, for each connecting post 421 connected within the active region 412, the projection of the connecting post 421 onto the active region 412 can be completely located within the active region 412. This ensures an effective electrical connection between the connecting post 421 and the active region 412, guaranteeing that the connecting post 421 effectively grounds the active region 412. It avoids the portion of the connecting post 421 located within the active region 412, i.e., the bottom portion of the connecting post 421 located on the hexagonal shallow trench isolation structure 411. This would affect the stability of the electrical connection between the connecting post 421 and the active region 412, and consequently, the connecting post 421 might not be able to effectively ground the active region 412, failing to effectively reduce the electrical impact on components surrounding the via 300.

[0091] Reference Figure 5 As shown, in one specific embodiment, the center line of the connecting post 421 can coincide with the center line of the active region 412, that is, the bottom of the connecting post 421 is located at the center of the active region 412. In the case of a one-to-one correspondence between the connecting post 421 and the active region 412, by connecting the bottom of the connecting post 421 to the center of the active region 412, it can be ensured that the bottom of the connecting post 421 is completely within the active region 412, thereby ensuring the stability of the electrical connection between the connecting post 421 and the active region 412, and ensuring that the connecting post 421 grounds the active region 412.

[0092] Furthermore, since each active region 412 is formed by a honeycomb-shaped shallow hexagonal trench isolation structure 411, the spacing between adjacent active regions 412 is consistent, and the shape and size of each hexagonal active region 412 are consistent. For the connecting posts 421 connected to the center of each active region 412, the spacing between multiple connecting posts 421 is consistent, and the multiple connecting posts 421 are evenly spaced from the outer edge of the through-hole 300 in a direction away from the through-hole 300. In this way, the multiple connecting posts 421 can evenly distribute the expansion stress within the dielectric layer 200, better protecting the characteristics of the components within the dielectric layer 200 and the structure of the dielectric layer 200.

[0093] Figure 9 This is a schematic longitudinal cross-sectional view of another semiconductor structure provided in an embodiment of the present invention. (Refer to...) Figure 9 As shown, in this embodiment, the dielectric layer 200 may include a plurality of sub-dielectric layers 210 stacked sequentially, and the connecting post 421 may include a plurality of sub-segments 4211 stacked sequentially, with the sub-dielectric layers 210 and sub-segments 4211 corresponding one-to-one.

[0094] In practical applications, multiple sub-dielectric layers 210 can be deposited sequentially on the substrate 100. Contact holes in the dielectric layer 200 can penetrate multiple sub-dielectric layers 210 along the thickness direction of the dielectric layer 200. One end of the connecting post 421 is connected to the active region 412 outside the via 300 on the substrate 100, and the other end of the connecting post 421 extends to the top of the dielectric layer 200.

[0095] When depositing multiple sub-dielectric layers 210 in sequence, after all the sub-dielectric layers 210 have been deposited to form a dielectric layer 200, contact holes can be etched in the dielectric layer 200, and a second conductive material can be filled into the contact holes to form a connecting post 421.

[0096] Alternatively, after depositing a sub-dielectric layer 210, contact holes can be etched within the sub-dielectric layer 210, and then a second conductive material can be filled into the contact holes to form segments 4211 of the connecting pillars 421. Then, another sub-dielectric layer 210 can be deposited. After the next sub-dielectric layer 210 is deposited, contact holes can be etched within it, and the contact holes can be filled with the second conductive material. The contact holes within the multiple sub-dielectric layers 210 are positioned correspondingly to form contact holes penetrating the dielectric layer 200.

[0097] Additionally, it should be noted that the second conductive material filling the contact hole segments of each sub-dielectric layer 210 can be consistent; or, for each sub-dielectric layer 210 deposited sequentially and the second conductive material being segmentally filled into the contact holes within each sub-dielectric layer 210, the second conductive material in each contact hole segment can be inconsistent.

[0098] To enhance the buffering effect on the expansion stress within the dielectric layer 200, refer to Figure 9 As shown, in one possible implementation, the sub-dielectric layer 210 may also be provided with a honeycomb-shaped hexagonal isolation structure 422, through which the connecting post 421 passes.

[0099] An isolation structure 422 is provided around the connecting pillars 421 in the sub-dielectric layer 210. The isolation structure 422 is similar to the shallow trench isolation structure 411 on the substrate 100. The isolation structure 422 is also a regular hexagonal structure. The isolation structures 422 around adjacent connecting pillars 421 are connected. All the isolation structures 422 around the connecting pillars 421 form a honeycomb-shaped ring structure.

[0100] Similar to the shallow trench isolation structure 411 on the substrate 100, the regular hexagonal isolation structure 422 can offset or disperse expansion stress by utilizing its own regular hexagonal isolation walls. The honeycomb-shaped inner and outer layers of the isolation structure 422 can effectively disperse and buffer the expansion stress in the dielectric layer 200, which will not be elaborated here.

[0101] The projection of the isolation structure 422 within the dielectric layer 200 onto the substrate 100 can be located inside the shallow trench isolation structure 411. In this way, the honeycomb-shaped isolation structure 422 is arranged more densely, which can enhance the buffering effect on the expansion stress within the dielectric layer 200.

[0102] In addition, similar to the fact that the material of the shallow trench isolation structure 411 is different from the material of the substrate 100, the material of the isolation structure 422 is different from the material of the dielectric layer 200.

[0103] Figure 10 This is a longitudinal cross-sectional schematic diagram of a third semiconductor structure provided in an embodiment of the present invention. (Refer to...) Figure 10 As shown, in one embodiment, a connecting pad 430 may also be provided in the dielectric layer 200. The connecting pad 430 is located above the connecting post 421 and is in direct contact with the multiple connecting posts 421. The multiple connecting posts 421 are grounded simultaneously through the connecting pad 430.

[0104] For example, the connecting pad 430 can be an insulator, and multiple connecting posts 421 can be grounded simultaneously by contacting the connecting pad 430; or, the connecting pad 430 can be a conductor, and multiple connecting posts 421 can be grounded simultaneously by grounding the connecting pad 430.

[0105] In the fabrication of the semiconductor structure, an insulating layer or a conductive layer can be deposited within the dielectric layer 200 as the substrate material for the connection pad 430. Then, the insulating layer or conductive layer is etched to form the connection pad 430 connected to multiple connection pillars 421. For example, the connection pad 430 can be an annular connection pad, which covers multiple connection pillars 421 arranged in a ring.

[0106] It should be noted that, in addition to grounding multiple connecting posts 421 simultaneously, the connecting pad 430 can also improve the overall strength and rigidity of the multiple connecting posts 421. When the multiple connecting posts 421 are subjected to thermal stress from the first conductive material 301 in the through hole 300, the connecting pad 430 connects the multiple connecting posts 421 to form an integral structure, which can prevent the connecting posts 421 from deforming or tilting, thereby reducing the impact of the connecting posts 421 on the dielectric layer 200.

[0107] Figure 11 This is a schematic diagram of a longitudinal section of a fourth semiconductor structure provided in an embodiment of the present invention; Figure 12 This is a longitudinal cross-sectional schematic diagram of the fifth semiconductor structure provided in an embodiment of the present invention. (Refer to...) Figure 11 and Figure 12 As shown in the figure, the dielectric layer 200 includes a sub-dielectric layer 210. It can be understood that the dielectric layer 200 may also include multiple stacked sub-dielectric layers 210.

[0108] At least one metal layer 440 may be disposed within the sub-dielectric layer 210. For example, the metal layer 440 within the sub-dielectric layer 210 may be used to form the gate of a transistor. The sub-segments 4211 of the connecting pillars 421 located within the metal layer 440 of the sub-dielectric layer 210 may be made of the same material.

[0109] As previously described, the connecting post 421 can be formed by etching contact holes within the dielectric layer 200 and filling the contact holes with a second conductive material. In this regard, when forming the metal layer 440 within the sub-dielectric layer 210, a segment 4211 of the connecting post 421 corresponding to the metal layer 440 can be formed simultaneously, and the portion of the metal layer 440 corresponding to the segment 4211 can serve as the segment 4211 of the connecting post 421.

[0110] Reference Figure 11 As shown, taking the metal layer 440 in the sub-dielectric layer 210 near the surface of the substrate 100 as an example, after depositing a portion of the sub-dielectric layer 210 on the surface of the substrate 100, contact holes are etched in the sub-dielectric layer 210, and then the metal layer 440 is deposited on the sub-dielectric layer 210. The portion of the metal layer 440 corresponding to the contact hole is filled into the contact hole. The metal layer 440 and the metal layer 440 material in the contact hole can be used as the sub-segment 4211 of the connecting post 421.

[0111] Reference Figure 12 As shown, more metal layers 440 can be added to the upper end of the connecting post 421 to increase the height of the connecting post 421, and each metal layer 440 at the upper end of the connecting post 421 serves as a segment 4211 of the connecting post 421.

[0112] In addition, the connecting pad 430 can be connected to the metal layer 440 at the upper end of the connecting post 421, that is, the connecting pad 430 is connected to the sub-segment 4211 at the top of the connecting post 421. The connecting pad 430 can ground each connecting post 421 and enhance the strength of each connecting post 421. On the other hand, the connecting pad 430 can increase the height of the connecting post 421 to match the height of the through hole 300.

[0113] The semiconductor structure provided in this embodiment provides a buffer structure within the substrate 100 and dielectric layer 200. This buffer structure includes a first buffer portion 410 disposed on the substrate 100 around the via 300. A honeycomb-shaped shallow trench isolation structure 411 extending outwards from the via 300 serves as the first buffer portion 410. The shallow trench isolation structure 411, relying on its hexagonal isolation walls, can effectively absorb and disperse the expansion stress from the first conductive material 301 within the via 300. By extending the shallow trench isolation structure 411 in a honeycomb shape from the outer edge of the via 300 away from the via 300, it can provide multiple buffers against expansion stress, protecting the substrate 100 structure around the via 300 and the components on the substrate 100. Furthermore, the honeycomb-shaped hexagonal shallow trench isolation structures have the highest distribution per unit area, effectively absorbing and dispersing the expansion stress from the first conductive material within the via, further enhancing the protection effect.

[0114] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0115] In the description of this invention, it should be understood that the terms “comprising” and “having” as used herein, and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or device.

[0116] Unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can be a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A dielectric layer is located on the substrate; A via extends through the dielectric layer and the substrate, and the via is filled with a first conductive material; A buffer structure includes a first buffer portion disposed on the substrate around the through hole; The first buffer section includes a shallow groove isolation structure in the shape of regular hexagons arranged in a honeycomb pattern. The first buffer section further includes: The active region is located inside the shallow trench isolation structure and is closely adjacent to the shallow trench isolation structure; The buffer structure further includes a second buffer section disposed within the dielectric layer. The second buffer section includes a plurality of spaced connecting posts, which extend along the thickness direction of the dielectric layer and have their bottoms located on the active region.

2. The semiconductor structure according to claim 1, characterized in that, The outer contour of the active region has a regular hexagonal structure.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The first buffer section is an annular structure surrounding the through hole.

4. The semiconductor structure according to claim 1 or 2, characterized in that, The first buffer section includes multiple buffer segments, which are spaced apart circumferentially along the through hole.

5. The semiconductor structure according to claim 4, characterized in that, The buffer section is an arc-shaped section.

6. The semiconductor structure according to claim 1, characterized in that, The connecting post and the active area correspond one-to-one.

7. The semiconductor structure according to claim 6, characterized in that, The projection of the connecting column onto the active region is entirely within the active region.

8. The semiconductor structure according to claim 7, characterized in that, The centerline of the connecting post coincides with the centerline of the active area.

9. The semiconductor structure according to claim 8, characterized in that, The dielectric layer comprises multiple sub-dielectric layers stacked sequentially, and the connecting post comprises multiple sub-segments stacked sequentially, with each sub-dielectric layer and each sub-segment corresponding to the other.

10. The semiconductor structure according to claim 9, characterized in that, Also includes: A connecting pad is located above the connecting posts and is in direct contact with the plurality of connecting posts.

11. The semiconductor structure according to claim 10, characterized in that, The connecting pad is grounded.

12. The semiconductor structure according to claim 9, characterized in that, Also includes: A honeycomb-shaped hexagonal isolation structure located in the sub-dielectric layer, through which the connecting posts pass; The projection of the isolation structure onto the substrate is located inside the shallow trench isolation structure, and the material of the isolation structure is different from the material of the dielectric layer.

13. The semiconductor structure according to claim 9, characterized in that, The sub-dielectric layer contains at least one metal layer, and the metal layer is made of the same material as the sub-segment within the sub-dielectric layer.

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