Method of manufacturing a semiconductor device

Abstract

The present application provides a semiconductor device manufacturing method, comprising: performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; performing a surface treatment on the planar surface layer to form a treated planar layer; and forming a second silicon oxide layer on the treated planar layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing a semiconductor device. Background Technology

[0002] Chemical mechanical polishing (CMP) is a crucial planarization technique in semiconductor manufacturing. However, after planarization, the adhesion between the dielectric layer and the overlying layer is often poor, frequently resulting in film cracking or delamination. Summary of the Invention

[0003] This invention relates to a method for manufacturing semiconductor devices, which can improve the adhesion between the planar surface layer and the overlayer after planarization by chemical mechanical polishing, thereby improving the problem of film cracking or delamination.

[0004] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; performing a surface treatment on the planar surface layer to form a treated planar layer; and forming a second silicon oxide layer on the treated planar layer.

[0005] In embodiments of the present invention, the surface treatment includes oxygen, hydrogen, or ammonia plasma treatment.

[0006] In an embodiment of the invention, the surface treatment of the flat surface layer and the formation of the second silicon oxide layer on the treated flat layer are performed in situ.

[0007] In an embodiment of the invention, the surface treatment of the flat surface layer and the formation of the second silicon oxide layer on the treated flat layer are performed in situ.

[0008] Another embodiment of the present invention relates to a method for manufacturing a semiconductor device, comprising forming an interconnect structure on a first substrate; forming a first material layer on the interconnect; forming a first dielectric layer on the first material layer; performing a planarization process on the first dielectric layer to form a planar surface layer; performing a first surface treatment on the planar surface layer to form a treated planarization layer; forming a second dielectric layer on the treated planarization layer, wherein the first substrate, the interconnect structure, the first material layer, the first dielectric layer, the treated planarization layer, and the second dielectric layer form a first semiconductor wafer; and bonding a second semiconductor wafer to the first semiconductor wafer.

[0009] In an embodiment of the invention, the planarization process comprises a chemical mechanical polishing process using tetramethylammonium hydroxide (TMAH) and an ammonia-rich slurry.

[0010] In an embodiment of the present invention, the first surface treatment includes oxygen, hydrogen, or ammonia plasma treatment.

[0011] In an embodiment of the present invention, the method of manufacturing the semiconductor device further includes performing a second surface treatment on the interconnect before forming the first material layer on the interconnect.

[0012] In an embodiment of the invention, the second surface treatment includes treatment with hydrogen plasma.

[0013] In an embodiment of the invention, bonding the second substrate to the first substrate includes bonding a second material layer on the second substrate to a second dielectric layer on the first substrate.

[0014] In an embodiment of the present invention, the first dielectric layer and the second dielectric layer comprise silicon oxide layers, and the first material layer and the second material layer comprise silicon carbonitride layers.

[0015] In an embodiment of the invention, the first surface treatment of the flat surface layer and the formation of the second silicon oxide layer on the treated flat layer are performed in situ.

[0016] In an embodiment of the invention, the first surface treatment of the flat surface layer and the formation of the second silicon oxide layer on the treated flat surface layer are performed in situ.

[0017] Based on the above, the semiconductor device manufacturing method of the present invention can improve the adhesion between the planar surface layer and the overlayer after planarization by chemical mechanical polishing, and avoid the problem of delamination. Attached Figure Description

[0018] Figures 1A to 1H This is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 This is a partial cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0020] Explanation of reference numerals in the attached figures

[0021] 10: Device Layer

[0022] 11: Contact components

[0023] 13: Inner dielectric layer

[0024] 12, 28: Conductors

[0025] 14, 18, 24: Interlayer dielectric layers

[0026] 16: Etching Stop Layer

[0027] 20, 22: Hard mask layers

[0028] 26: Interlayer window

[0029] 30, 32, 34: Barrier Layer

[0030] 100: Substrate

[0031] 102: Internal Structure

[0032] 103, 108: Surface treatment

[0033] 104, 114: Material layer

[0034] 106, 110: Dielectric layer

[0035] 106a: Flat surface layer

[0036] 106b: Surface

[0037] 106c: The treated planarization layer

[0038] 100W, 200W: Semiconductor chips

[0039] 100a, 200a: Core tube

[0040] 300: Stacked structure

[0041] 300a: Stacked dies Detailed Implementation

[0042] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0043] Please refer to Figure 1A and Figure 2 A substrate 100 is provided. The substrate 100 may be a doped silicon substrate, an undoped silicon substrate, a silicon-on-insulator (SOI) substrate, or an epitaxial substrate. The dopant in the silicon may be a P-type dopant, an N-type dopant, or a combination thereof. An isolation structure (not shown) may also be formed within the substrate 100 to define an active region within the substrate 100. A device layer 10 may be formed on or within the substrate 100. The device layer 10 may include active devices or passive devices. Active devices may be, for example, PMOS, NMOS, CMOS, JFET, BJT, or diodes. Passive devices may be, for example, inductors, capacitors, etc.

[0044] Please refer to Figure 1A and Figure 2An interconnect structure 102 is formed on the substrate 100. The interconnect structure 102 includes an inner dielectric layer 13, contacts 11, wires 12, an etch stop layer 16, interlayer dielectric layers 14, 18, and 24, a permeable window 26, a topmost wire 28, hard mask layers 20 and 22, etc. In some embodiments, the wires 12 and contacts 11 may also include other wires, interlayer dielectric layers, and permeable windows, but these are not shown. The contacts 11, wires 12, 28, and permeable windows 26 may be electrically connected to each other and to devices in the device layer 10. The materials of the wires 12, 28, and permeable windows 26 include doped polysilicon or metal. The metal is, for example, copper, tungsten, or a copper-aluminum alloy. In some embodiments, the wires 12, 28, contacts 11, and permeable windows 26 may also include barrier layers 30, 32, and 34. The wires 28 and permeable windows 26 may be formed via a double metal damascene process, but are not limited thereto. The inner dielectric layer 13 and the interlayer dielectric layers 14, 18, and 24 can be, for example, silicon oxide, and can be formed by methods such as chemical vapor deposition or spin coating. In some embodiments, the interlayer dielectric layer 14 can be made of a low dielectric constant material with a dielectric constant lower than 4. The inner dielectric layer 13 and the interlayer dielectric layers 14, 18, and 24 can be planarized by chemical mechanical polishing or etch-back. The etch stop layer 16 is, for example, silicon nitride or silicon oxynitride. The hard mask layer 20 is, for example, silicon oxynitride. The hard mask layer 22 is, for example, silicon nitride. The etch stop layer 16 and the hard mask layers 20 can be formed by chemical vapor deposition.

[0045] For the sake of brevity, Figures 1A to 1H Device layer 10 and some components of interconnect structure 102 are omitted. Figures 1A to 1H The diagram shows the topmost conductor 28 of the interconnect structure 102 and the interlayer dielectric layer 24.

[0046] Please refer to Figure 1B The inner structure 102 undergoes a surface treatment 103. Surface treatment 103 removes oxides, such as copper oxide, or impurities from the surface of the top layer 28. The gas used in surface treatment 103 includes hydrogen. Surface treatment 103 can be performed on a deposition or etching equipment. In one embodiment, surface treatment 103 is performed on a plasma-containing equipment, such as a plasma-enhanced chemical vapor deposition (PECVD) equipment. In an example embodiment, hydrogen is used as the plasma gas source, with a flow rate of 200 sccm to 500 sccm, a temperature of 350°C to 450°C, a pressure of 4 Torr to 7 Torr, and a reaction time of 5 to 30 seconds.

[0047] Please refer to Figure 1BA material layer 104 is formed on the interconnect structure 102. The material layer 104 includes a dielectric material, such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxynitride (SiON). The material layer 104 can be a single layer or multiple layers. The material layer 104 is formed, for example, by plasma-enhanced chemical vapor deposition. The material layer 104 and surface treatment 103 can be performed in situ on the same equipment or ex-situ on different equipment. The thickness of the material layer 104 is, for example, 200 angstroms to 500 angstroms.

[0048] Next, a dielectric layer 106 is formed on the material layer 104. The material of the dielectric layer 106 is different from that of the material layer 104. The dielectric layer 106 can be a single layer or multiple layers. The dielectric layer 106 is, for example, a silicon oxide layer, or undoped silicon glass (USG). The dielectric layer 106 is formed by, for example, plasma-enhanced chemical vapor deposition. The thickness of the dielectric layer 106 is, for example, 12,000 angstroms to 16,000 angstroms.

[0049] Please refer to Figure 1C A planarization process is performed on the dielectric layer 106 to form a planar surface layer 106a. In some embodiments, the thickness of the planar surface layer 106a is, for example, 6500 angstroms to 12500 angstroms. The planarization process is, for example, a chemical mechanical planarization process. In one embodiment, the chemical mechanical planarization process uses a slurry containing tetramethylammonium hydroxide (TMAH) and NH3-rich. In some cases, these slurries react with the dielectric layer 106, causing nitrogen to adsorb onto or react with the surface of the planar surface layer 106a to form a surface layer 106b. Therefore, the nitrogen content of the surface layer 106b of the planar surface layer 106a is higher than the nitrogen content of the inner layers of the planar surface layer 106a.

[0050] The surface layer 106b of the flat surface layer 106a has a high nitrogen content, which, if not removed, can easily cause nitrogen buildup in subsequent stacked structures. Figure 1G After formation, this leads to problems such as cracking and delamination. Therefore, in this embodiment of the invention, after the planarization process, a surface treatment 108 is performed to remove or reduce the nitrogen contained in the surface layer 106b of the planar surface layer 106a, to form a treated planar layer 106c, such as... Figure 1C As shown, the nitrogen content on the surface of the treated flattened layer 106c is lower than the nitrogen content on the surface layer 106b of the flattened surface layer 106a.

[0051] Surface treatment 108 can be performed on a deposition or etching apparatus. In one embodiment, surface treatment 108 is performed on a plasma-containing apparatus, such as a plasma-enhanced chemical vapor deposition apparatus or a plasma etching apparatus (e.g., an AIM apparatus). In an example embodiment, oxygen, hydrogen, or ammonia is used as the plasma gas source, with a gas flow rate of 500 sccm to 1000 sccm, a temperature of 350°C to 450°C, a pressure of 4 Torr to 7 Torr, and a reaction time of 5 seconds to 30 seconds. Surface treatment 108 can be subsequently used to form dielectric layer 110 (e.g., ...). Figure 1E The process can be performed in situ on the machine (as shown), or in non-situ on different machines.

[0052] Please refer to Figure 1E A dielectric layer 110 is formed on the treated planarization layer 106c. The material of the dielectric layer 110 can be a single layer or multiple layers. The dielectric layer 106 is, for example, a silicon oxide layer, or undoped silicon glass. The thickness of the dielectric layer 106 is, for example, 800 angstroms to 1200 angstroms. As described above, the dielectric layer 110 and the surface treatment 108 described above can be performed in situ on the same machine or off-site on different machines.

[0053] Please refer to Figure 1F A material layer 114 is formed on the dielectric layer 110. The material of the material layer 114 includes a dielectric material, such as silicon carbonitride (SiCN), silicon nitride (SiN), or silicon oxynitride (SiON). The material layer 114 can be a single layer or multiple layers. The method for forming the material layer 114 is, for example, plasma-enhanced chemical vapor deposition. The material of the material layer 114 is different from the material of the dielectric layer 110. The material layer 114 and the material layer 104 may have the same or different materials. The thickness of the material layer 114 is, for example, 200 angstroms to 500 angstroms.

[0054] Next, please refer to Figure 1G A semiconductor wafer 200W is provided. The semiconductor wafer 200W includes a substrate 200 and a material layer 204. The substrate 200 may include a doped silicon substrate, an undoped silicon substrate, a silicon-on-insulator (SOI) substrate, or an epitaxial substrate. The dopant of the silicon may be a P-type dopant, an N-type dopant, or a combination thereof. An isolation structure (not shown) may also be formed within the substrate 200 to define an active region within the substrate 200. A device layer (not shown) may be formed on or within the substrate 200. The device layer (not shown) may include active devices or passive devices. Active devices are, for example, PMOS, NMOS, CMOS, JFET, BJT, or diodes. Passive devices are, for example, inductors, capacitors, etc. The substrate 200 may also include interconnect structures (not shown). Interconnect structures include inner dielectric layers, contacts, wires, etch stop layers, interlayer dielectric layers, interlayer windows, top layer wires, hard mask layers, etc.

[0055] The semiconductor wafer 200W also includes a material layer 204 located on the interconnect structure of the substrate 200. The material of the material layer 204 includes dielectric materials, such as silicon carbonitride (SiCN), silicon nitride (SiN), silicon oxynitride (SiON), or silicon oxide. The material layer 204 can be a single layer or multiple layers. The material layer 204 can be formed by, for example, chemical vapor deposition. The material of the material layer 204 can be the same as or different from the material of the material layer 114.

[0056] Next, using material layer 204 and material layer 114 as bonding layers, the semiconductor wafer 200W and semiconductor wafer 100W (including substrate 100, interconnect structure 102, processed planarization layer 106c, dielectric layer 110, and material layer 114) are bonded through the bonding process of material layer 204 and material layer 114 to form a stacked structure 300.

[0057] Please refer to Figure 1H In some embodiments, the stacked structure 300 is further divided into multiple stacked dies 300a. The stacked dies 300a include dies 100a and dies 200a. Die 100a is, for example, a logic die, and die 200a is, for example, a sensing die or a memory die.

[0058] The above embodiments are illustrated using a wafer-to-wafer bonding method. However, the embodiments of the present invention are not limited thereto. Embodiments of the present invention may also include a die-to-wafer bonding method.

[0059] The semiconductor device manufacturing method of this invention, after planarization by chemical mechanical polishing, performs surface treatment on the planar surface layer, which can increase the adhesion between the treated planar layer and the overlying dielectric layer, and improve the problem of film cracking or delamination.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: The first silicon oxide layer is subjected to a chemical mechanical polishing process to form a flat surface layer; The flat surface layer is surface treated to form a treated flat layer, wherein the nitrogen content of the surface of the treated flat layer is lower than the nitrogen content of the surface of the flat surface layer; and A second silicon oxide layer is formed on the treated planar layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the chemical mechanical polishing process uses a slurry containing tetramethylammonium hydroxide and rich in ammonia.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the surface treatment includes oxygen, hydrogen, or ammonia plasma treatment.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the surface treatment of the flat surface layer and the formation of the second silicon oxide layer on the treated flat surface layer are performed in situ.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the surface treatment of the flat surface layer and the formation of the second silicon oxide layer on the treated flat surface layer are performed in situ.

6. A method for manufacturing a semiconductor device, characterized in that, The method includes: An interconnect structure is formed on the first substrate; A first material layer is formed on the interconnecting structure; A first dielectric layer is formed on the first material layer; The first dielectric layer is planarized to form a flat surface layer; The flat surface layer is subjected to a first surface treatment to form a treated flat layer, wherein the nitrogen content of the surface of the treated flat layer is lower than the nitrogen content of the surface of the flat surface layer. A second dielectric layer is formed on the processed planarization layer, wherein the first substrate, the interconnect structure, the first material layer, the processed planarization layer, and the second dielectric layer form a first semiconductor wafer; and The second semiconductor chip is bonded to the first semiconductor chip.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the planarization process includes a chemical mechanical polishing process using a slurry containing tetramethylammonium hydroxide and ammonia-rich material.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the first surface treatment includes oxygen, hydrogen, or ammonia plasma treatment.

9. The method of manufacturing a semiconductor device according to claim 8, further comprising performing a second surface treatment on the interconnect structure before forming the first material layer on the interconnect structure.

10. The method of manufacturing a semiconductor device according to claim 9, wherein the second surface treatment includes hydrogen plasma treatment.

11. The method of manufacturing a semiconductor device according to claim 10, wherein bonding a second substrate of the second semiconductor wafer to the first substrate comprises bonding a second material layer on the second substrate to a second dielectric layer on the first substrate.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide layers, and the first material layer and the second material layer comprise silicon carbonitride layers.

13. The method of manufacturing a semiconductor device according to claim 6, wherein the first surface treatment of the flat surface layer and the formation of the second dielectric layer on the treated flat surface layer are performed in situ.

14. The method of manufacturing a semiconductor device according to claim 6, wherein the first surface treatment of the flat surface layer and the formation of the second dielectric layer on the treated flat surface layer are performed in situ.

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