Semiconductor device and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor device and a forming method thereof. The method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of bit line structures arranged along a first direction; filling a conductive material on a surface of the bit line structure to form a conductive layer covering the surface of the bit line structure, wherein a top surface of the conductive layer is higher than a top surface of the bit line structure; and etching the conductive layer to form a plurality of first conductive layers and a second conductive layer on each of the first conductive layers. The present application can greatly simplify the manufacturing process of the semiconductor device and reduce the manufacturing cost of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The source of the transistor is connected to the capacitor through a node contact (NC) and a landing pad (LP), thereby enabling the reading of data stored in the capacitor or the writing of data to the capacitor for storage.

[0003] In related technologies, firstly, a contact hole is defined by forming two intersecting mask patterns, and conductive material is filled into the contact hole to form a memory node contact. Secondly, a landing pad is formed on the memory node contact using a patterning process. It is evident that the formation of the memory node contact and landing pad in these technologies requires advanced exposure techniques to create more intricate patterns, which poses a significant challenge to achieving high exposure rates. Furthermore, the formation process of the memory node contact and landing pad in these technologies involves numerous steps and is quite complex, resulting in high manufacturing costs for semiconductor devices. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor device and a method for forming the same, which can greatly simplify the fabrication process of semiconductor devices and reduce the manufacturing cost of semiconductor devices.

[0005] In a first aspect, embodiments of this application provide a method for forming a semiconductor device, the method comprising: A semiconductor substrate is provided, the semiconductor substrate including a plurality of bit line structures spaced apart along a first direction; A conductive material is filled on the surface of the bit line structure to form a conductive layer covering the surface of the bit line structure, wherein the top surface of the conductive layer extends beyond the top surface of the bit line structure. The conductive layer is etched to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers.

[0006] In some embodiments, the conductive material includes a first conductive material and a second conductive material; the conductive layer includes a first initial conductive layer and a second initial conductive layer; The step of filling the surface of the bit line structure with a conductive material to form a conductive layer covering the surface of the bit line structure includes: A first conductive material is filled on the surface of the bit line structure to form a first initial conductive layer covering the surface of the bit line structure; The first initial conductive layer is etched back to expose a portion of the bit line mask layer of the bit line structure; A second conductive material is filled on the surface of the first initial conductive layer after etch-back to form a second initial conductive layer covering the surface of the partial bit mask layer, wherein the top surface of the second initial conductive layer extends beyond the top surface of the bit mask layer.

[0007] In some embodiments, etching the conductive layer to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers includes: Along a third direction, the first initial conductive layer and the second initial conductive layer are sequentially subjected to a first etching process to form a first etched conductive layer and a second etched conductive layer that are independent of each other along the second direction. Along the third direction, the second etched conductive layer is subjected to a second etching process to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers; Wherein, the second direction is perpendicular to the first direction, the plane formed by the second direction and the first direction is parallel to the plane where the semiconductor substrate is located, and the third direction is perpendicular to the plane where the semiconductor substrate is located.

[0008] In some embodiments, the second etching process performed on the second etched conductive layer along the third direction to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers includes: Along the third direction, the second etched conductive layer above the bit line mask layer is partially etched to expose a portion of the bit line mask layer, forming a first conductive layer that is independent of each other along the first direction and a second conductive layer located above each first conductive layer.

[0009] In some embodiments, the first etching process includes: A first mask layer having a first mask pattern is formed on the surface of the second initial conductive layer; The first mask layer is used to sequentially etch the second initial conductive layer and the first initial conductive layer to transfer the first mask pattern to the second initial conductive layer and the first initial conductive layer, forming the first etched conductive layer and the second etched conductive layer that are independent of each other along the second direction.

[0010] In some embodiments, the first mask layer includes a first hard mask layer, a first anti-reflection layer, and a first photoresist layer stacked sequentially. The step of forming a first mask layer having a first mask pattern on the surface of the second initial conductive layer includes: A first hard mask layer, a first anti-reflection layer, and a first photoresist layer are formed on the surface of the second initial conductive layer; wherein the first photoresist layer has a first initial mask pattern; An isolation layer is formed on the surface of the first photoresist layer having the first initial mask pattern; The isolation layer and the first initial mask pattern are etched sequentially, retaining the isolation layer located on the sidewall of the first initial mask pattern to form an isolation sidewall pattern; The first anti-reflective layer and the first hard mask layer are etched using the isolation sidewall pattern to form the first mask layer having the first mask pattern.

[0011] In some embodiments, the method further includes: After forming the first etched conductive layer and the second etched conductive layer that are independent of each other along the second direction, and before the second etching process, storage contact isolation material is filled in the first etch trench between any two adjacent first etched conductive layers and the second etch trench between any two adjacent second etched conductive layers to form a storage contact isolation layer. The storage contact isolation layer is etched to remove the storage contact isolation layer located on the top surface of the second etched conductive layer.

[0012] In some embodiments, the method further includes: When the storage contact isolation material is filled into the first and second etched trenches, an air gap is formed at the center of the storage contact isolation layer.

[0013] In some embodiments, the storage contact isolation material comprises silicon nitride.

[0014] In some embodiments, the second etching process includes: A second mask layer having a second mask pattern is formed on the surface of the second etched conductive layer and the surface of the storage contact isolation layer; Using the second mask pattern, a portion of the second etched conductive layer located above the bit line mask layer is etched away, and the remaining second etched conductive layer forms the second conductive layer.

[0015] In some embodiments, the second mask layer includes a second hard mask layer, a second anti-reflection layer, and a second photoresist layer stacked sequentially. The step of forming a second mask layer having a second mask pattern on the surface of the second etched conductive layer and the surface of the storage contact isolation layer includes: On the surfaces of the second etched conductive layer and the storage contact isolation layer, a second hard mask layer, a second anti-reflection layer, and a second photoresist layer are sequentially deposited; wherein, the second photoresist layer has a second mask pattern; the second mask pattern includes a plurality of sub-patterns arranged parallel to the first direction; each of the sub-patterns extends in a plane parallel to the semiconductor substrate at an angle to the first direction, the angle being not equal to 90 degrees; The second anti-reflective layer and the second hard mask layer are sequentially etched through each of the sub-patterns to form the second mask layer having the second mask pattern.

[0016] Secondly, embodiments of this application provide a semiconductor device, which is formed by the above-described semiconductor device formation method, and the semiconductor device includes: A semiconductor substrate, wherein a plurality of active regions are formed on the semiconductor substrate at intervals; The bitline structure includes a bitline contact layer, a bitline metal layer, and a bitline mask layer; the bitline metal layer intersects with the active region through the bitline contact layer; the bitline structure is arranged at intervals along a first direction. A first conductive layer and a second conductive layer, wherein the first conductive layer is connected to the capacitor through the second conductive layer; The second conductive layer includes a first structure with a first preset height located above a portion of the first conductive layer and a second structure with a second preset height located above a portion of the bit line structure; the first preset height is greater than the second preset height.

[0017] In some embodiments, the semiconductor device further includes: a storage contact isolation layer; The storage contact isolation layer is located between any two adjacent first conductive layers and between any two adjacent second conductive layers.

[0018] In some embodiments, the semiconductor device further includes: an air gap; The air gap is located in the storage contact isolation layers arranged sequentially along the second direction; Wherein, the second direction is perpendicular to the first direction, and the plane formed by the second direction and the first direction is parallel to the plane in which the semiconductor substrate is located.

[0019] In some embodiments, the air gap consists of a first portion and a second portion; The first part of the air gap is located in the storage contact isolation layer between two adjacent first conductive layers, and the second part of the air gap is located in the storage contact isolation layer between two adjacent second conductive layers corresponding to the two adjacent first conductive layers.

[0020] In some embodiments, the air gap has a third preset height along a third direction; the storage contact isolation layer has a fourth preset height along the third direction; The fourth preset height is greater than the third preset height, and the difference between the fourth preset height and the third preset height is less than a preset difference. The third direction is perpendicular to the plane where the semiconductor substrate is located.

[0021] The semiconductor device and its formation method provided in this application include: providing a semiconductor substrate, the semiconductor substrate including a plurality of bit line structures spaced apart along a first direction; filling the surface of the bit line structures with a conductive material to form a conductive layer covering the surface of the bit line structures, the top surface of the conductive layer extending beyond the top surface of the bit line structures; etching the conductive layer to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers. In this application embodiment, since a semiconductor device can be formed by directly etching the conductive layer to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers, this greatly simplifies the semiconductor device fabrication process and reduces the manufacturing cost of the semiconductor device. Attached Figure Description

[0022] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0023] Figure 1 This is a schematic diagram of an optional process for forming a semiconductor device according to an embodiment of this application. Figures 2a-2e This is a schematic diagram of the process for forming a conductive layer provided in an embodiment of this application; Figures 3a-3k 4a~4g are schematic diagrams of the process for forming the first conductive layer and the second conductive layer provided in the embodiments of this application; Figure 5a and 5b This is a schematic diagram of an optional structure of a semiconductor device provided in an embodiment of this application; The annotations in the attached figures are explained as follows: 200 / 300—Semiconductor substrate; 201 / 301—Bit line structure; 2011 / 3011—Bit line contact layer; 2012 / 3012—Bit line metal layer; 2013 / 3013—Bit line mask layer; 2012-1—Tungsten metal layer; 2012-2—Multi-metal layer; 202—Second dielectric layer; 203—First initial conductive layer; 203-1—Top surface of the first initial conductive layer; 204—Second initial conductive layer; 204-1—Top surface of the second initial conductive layer; 205—First hard mask layer; 206—First anti-reflection layer; 207—First photoresist layer; 2071—Strip pattern; 208—Isolation layer; 2081—Isolation sidewall pattern; 203' —First etched conductive layer; 204'—Second etched conductive layer; 209 / 309—Storage contact isolation layer; 209-1—Top surface of storage contact isolation layer; 204'-1—Top surface of second etched conductive layer; 2091 / 3091—Air gap; 210—Second hard mask layer; 211—Second anti-reflection layer; 212—Second photoresist layer; 2121—Subpattern; 203'' / 303—First conductive layer; 204'' / 304—Second conductive layer; 30—Semiconductor device; 302—Dielectric layer; 305—Insulating layer; 306—First electrode layer; 307—Dielectric layer; 308—Second electrode layer; T1—First etched trench; T2—Second etched trench. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0025] In the following description, the use of suffixes such as "module" or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module" or "unit" may be used interchangeably.

[0026] This application provides a method for forming a semiconductor device. Figure 1 This is a schematic diagram of an optional process for forming a semiconductor device according to an embodiment of this application, such as... Figure 1 As shown, the method includes the following steps: Step S101: Provide a semiconductor substrate, the semiconductor substrate including a plurality of bit line structures spaced apart along a first direction.

[0027] Here, the semiconductor substrate material can be any one of silicon (Si), silicon-germanium alloy (SiGe), silicon carbide (SiC), aluminum oxide (Al2O3), aluminum nitride (AlN), zinc oxide (ZnO), gallium oxide (Ga2O3), or lithium aluminate (LiAlO2). Since Si substrates are inexpensive, easy to dopant, and readily react to form heterogeneous isolation layers, Si is chosen as the substrate in this embodiment.

[0028] The semiconductor substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, a direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction. In the direction of the top and bottom surfaces (i.e., the plane in which the substrate lies), two intersecting (e.g., perpendicular) directions are defined, such as a first direction and a second direction. For example, the arrangement direction of multiple bitline structures can be defined as the first direction. Based on the first and second directions, the planar orientation of the semiconductor substrate can be determined. Here, the first direction, the second direction, and the third direction are mutually perpendicular. In this embodiment, the first direction is defined as the X-axis direction, the second direction as the Y-axis direction, and the third direction as the Z-axis direction.

[0029] In some embodiments, the bit line structure includes a bit line contact layer, a bit line metal layer, and a bit line mask layer sequentially formed on the semiconductor substrate. In this embodiment, the semiconductor substrate includes at least one bit line structure.

[0030] Step S102: Fill the surface of the bit line structure with conductive material to form a conductive layer covering the surface of the bit line structure.

[0031] The top surface of the conductive layer extends beyond the top surface of the bit line structure.

[0032] Here, the conductive material can be any metal or semiconductor material, and can also be a mixture of multiple metals, multiple semiconductors, or a mixture of metals and semiconductors. In this embodiment, the conductive material includes a first conductive material and a second conductive material; the conductive layer includes a first initial conductive layer and a second initial conductive layer.

[0033] Step S103: Etch the conductive layer to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers.

[0034] In this embodiment of the application, the semiconductor device may be DRAM, the first conductive layer may be a memory node contact, and the second conductive layer may be a landing pad.

[0035] The semiconductor device formation method provided in this application embodiment can form a plurality of independent first conductive layers and a second conductive layer on each of the first conductive layers by directly etching the conductive layer, thereby forming a semiconductor device. This can greatly simplify the semiconductor device fabrication process and reduce the manufacturing cost of the semiconductor device.

[0036] Figures 2a-2e This is a schematic diagram of the process for forming a conductive layer provided in an embodiment of this application. Figures 3a-3k Figures 4a to 4g are schematic diagrams illustrating the process of forming the first conductive layer and the second conductive layer according to embodiments of this application. Please refer to the following... Figures 2a-2e , Figures 3a-3k and Figures 4a-4g The schematic diagram of the semiconductor device formation process in this application provides a more detailed description of the semiconductor device formation method provided in the embodiments of this application.

[0037] First, you can refer to Figure 2a Step S101 is executed: a semiconductor substrate is provided, the semiconductor substrate including a plurality of bit line structures spaced apart along a first direction.

[0038] Figure 2a A schematic cross-sectional view of a semiconductor substrate containing multiple bit line structures provided in an embodiment of this application is shown below. Figure 2a As shown, the semiconductor substrate 200 includes four bit line structures 201 arranged along the X-axis. Each bit line structure 201 includes a bit line contact layer 2011, a bit line metal layer 2012, and a bit line mask layer 2013 stacked sequentially along the Z-axis. The bit line mask layer 2013 is used as an etching mask to form the bit line metal layer 2012. The material of the bit line metal layer includes tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In this embodiment, the material of the bit line contact layer 2011 can be polysilicon, and the bit line metal layer 2012 includes a tungsten metal layer 2012-1 and a titanium-containing metal layer 2012-2. For example, the titanium-containing metal layer can be a composite layer of titanium nitride and titanium metal.

[0039] It should be noted that, Figure 2a The diagram only shows a limited number of bit line structures; in actual fabrication, the semiconductor substrate includes multiple bit line structures.

[0040] The positional relationship between the bit line structure and the semiconductor substrate is described below: Please continue reading Figure 2aThe semiconductor substrate 200 includes a plurality of spaced active regions (not shown in the figure), the bit line contact layer 2011 intersects with the active regions in the semiconductor substrate, and a bit line metal layer 2012 is formed above the bit line contact layer 2011, thereby realizing the electrical connection between the bit line metal layer and the active regions.

[0041] Next, the formation process of the bit line contact layer and the bit line metal layer in the bit line structure will be described as follows: In some embodiments, the active region includes at least a bit line contact region forming a bit line contact layer; the bit line contact layer and the bit line metal layer are formed in the following manner: Step S10: A first dielectric layer is formed on the surface of the semiconductor substrate, the first dielectric layer being used to protect the active region in the semiconductor substrate.

[0042] Here, the first dielectric layer can be a silicon dioxide layer.

[0043] Step S11: Etch the first dielectric layer and the active region to form a bit line contact hole in the bit line contact region.

[0044] Step S12: Fill the bit line contact hole with bit line contact material to form an initial bit line contact layer.

[0045] Step S13: Sequentially deposit a metal layer and a bit line mask layer on the surface of the first dielectric layer.

[0046] Step S14: Etch the metal layer and the initial bit line contact layer through the bit line mask layer to form the bit line contact layer and the bit line metal layer.

[0047] In some embodiments, please continue to see Figure 2a The semiconductor substrate 200 further includes a second dielectric layer 202 located on the surface of the bit line structure 201. The second dielectric layer 202 is used to isolate the bit line structure from other structures subsequently formed around the bit line structure, such as memory node contacts and landing pads. Here, the material of the second dielectric layer includes any one of the following: silicon nitride, silicon oxide, and silicon oxynitride.

[0048] Next, you can refer to Figures 2b-2e Step S102 is executed, where conductive material is filled onto the surface of the bit line structure to form a conductive layer covering the surface of the bit line structure.

[0049] In some embodiments, step S102 includes the following steps: Step S1021: Fill the surface of the bit line structure with a first conductive material to form the first initial conductive layer covering the surface of the bit line structure.

[0050] like Figure 2b As shown, a first conductive material is filled on the surface of the bit line structure 201 to form a first initial conductive layer 203 covering the surfaces of the bit line structure 201 and the second dielectric layer 202. Here, the first conductive material may be polysilicon, and the top surface 203-1 of the first initial conductive layer 203 extends beyond the top surface of the bit line structure 201.

[0051] Step S1022: Illustrate the first initial conductive layer back to expose a portion of the bit line mask layer of the bit line structure.

[0052] like Figure 2c As shown, the first initial conductive layer 203 is etched back using a dry etching process to reduce the height of the first initial conductive layer 203 in the Z-axis direction, thereby exposing part of the bit line mask layer 2013 of the bit line structure 201.

[0053] Here, the dry etching process includes plasma etching, reactive ion etching, or ion milling.

[0054] Step S1023: Fill the surface of the first initial conductive layer after the etch-back with a second conductive material to form a second initial conductive layer covering the surface of the partial bit line mask layer.

[0055] The top surface of the second initial conductive layer extends beyond the top surface of the bit line mask layer.

[0056] like Figure 2d As shown, a second conductive material is filled on the surface of the first initial conductive layer 203 to form a second initial conductive layer 204 covering a portion of the bit line mask layer 2013. Here, the second conductive material can be metal W, and the top surface 204-1 of the second initial conductive layer 204 extends beyond the top surface of the bit line mask layer 2013.

[0057] In some embodiments, after forming the second initial conductive layer, the method for forming the semiconductor device may further include: Step S1024: Perform chemical mechanical polishing or etch-back treatment on the second initial conductive layer.

[0058] In this embodiment, the purpose of performing chemical mechanical polishing (CMP) or etch-back treatment on the second initial conductive layer is to make the second initial conductive layer have a flat surface, which facilitates the subsequent growth of other structures or films on the second initial conductive layer.

[0059] like Figure 2eAs shown, after CMP or etch-back processing of the second initial conductive layer 204, the top surface 204-1 of the second initial conductive layer 204 still extends beyond the top surface of the bit line mask layer 2013, and there is a preset height difference between the top surface 204-1 of the second initial conductive layer 204 and the top surface of the bit line mask layer 2013. In some embodiments, the preset height difference may be 10~80 nanometers.

[0060] Next, you can refer to Figures 3a-3k , Figures 4a-4g Step S103 is executed to etch the conductive layer to form multiple independent first conductive layers and a second conductive layer located on each of the first conductive layers.

[0061] In some embodiments, step S103 may include the following steps: Step S1031: Along a third direction, the first initial conductive layer and the second initial conductive layer are sequentially subjected to a first etching process to form a first etched conductive layer and a second etched conductive layer that are independent of each other along the second direction.

[0062] Step S1032: Along the third direction, perform a second etching process on the second etched conductive layer to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers; wherein, the second direction is perpendicular to the first direction, the plane formed by the second direction and the first direction is parallel to the plane where the semiconductor substrate is located, and the third direction is perpendicular to the plane where the semiconductor substrate is located.

[0063] In some embodiments, the first etching process may include the following steps: Step S20: Form a first mask layer having a first mask pattern on the surface of the second initial conductive layer.

[0064] Here, the first mask layer comprises a first hard mask layer, a first anti-reflection layer, and a first photoresist layer stacked sequentially. Step S20 is formed through the following steps: Step S201: A first hard mask layer, a first anti-reflection layer, and a first photoresist layer are formed on the surface of the second initial conductive layer; wherein the first photoresist layer has a first initial mask pattern.

[0065] Here, the first hard mask layer can be a spin-coated carbon layer, and the first anti-reflection layer can be a silicon oxynitride layer. In the embodiments of this application, the first hard mask layer, the first anti-reflection layer, and the first photoresist layer can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0066] like Figure 3a and 3b As shown, a first hard mask layer 205, a first anti-reflection layer 206, and a first photoresist layer 207 are sequentially formed on the surface of the second initial conductive layer 204, constituting a first mask layer. The first photoresist layer 207 has a first initial mask pattern, which is composed of multiple strip patterns 2071 arranged parallel to each other along the Y-axis.

[0067] Step S202: An isolation layer is formed on the surface of the first photoresist layer having the first initial mask pattern.

[0068] like Figure 3c As shown, an isolation layer 208 is formed on the surface of a first photoresist layer 207 having a first initial mask pattern. Here, the isolation layer material may be silicon oxide.

[0069] Step S203: The isolation layer and the first initial mask pattern are etched sequentially to retain the isolation layer located on the sidewall of the first initial mask pattern, forming an isolation sidewall pattern.

[0070] like Figure 3d As shown, the isolation layer 208 and the first initial mask pattern are etched sequentially using a dry etching process, retaining the isolation layer 208 located on the sidewall of each strip pattern 2071 in the first initial mask pattern, thereby forming the isolation sidewall pattern 2081.

[0071] Step S204: Etch the first anti-reflective layer and the first hard mask layer through the isolation sidewall pattern to form the first mask layer having the first mask pattern.

[0072] In this embodiment of the application, the isolation sidewall pattern is the first mask pattern. After the isolation sidewall pattern is formed, the first mask layer with the first mask pattern is formed. The subsequent first etching process can be performed through the isolation sidewall pattern.

[0073] Step S21: Through the first mask layer, the second initial conductive layer and the first initial conductive layer are etched sequentially to transfer the first mask pattern to the second initial conductive layer and the first initial conductive layer, forming the first etched conductive layer and the second etched conductive layer that are independent of each other along the second direction.

[0074] Figure 3e This is a three-dimensional structural diagram illustrating the formation of the first etched conductive layer and the second etched conductive layer, provided as an embodiment of this application. Figure 3f for Figure 3e A schematic diagram of the cross-sectional structure along line A-A'. Figure 3g A top view showing the formation of the first and second etched conductive layers, combined with Figures 3e-3g As shown, after etching the second initial conductive layer 204 and the first initial conductive layer 203 through the first mask layer, a first etched conductive layer 203' and a second etched conductive layer 204' that are independent of each other along the Y-axis direction are formed.

[0075] In some embodiments, after forming a first etched conductive layer and a second etched conductive layer that are independent of each other along the Y-axis direction, a first etch trench is formed between any two adjacent first etched conductive layers, and a second etch trench is formed between any two adjacent second etched conductive layers. For example, please continue to see... Figure 3f A first etching trench T1 is formed between any two adjacent first etched conductive layers 203', and a second etching trench T2 is formed between any two adjacent second etched conductive layers 204'.

[0076] In some embodiments, after forming the first etched conductive layer and the second etched conductive layer which are independent of each other in the second direction, and before the second etching process, the method for forming the semiconductor device may further include: Step S30: Fill the first etching trench between any two adjacent first etched conductive layers and the second etching trench between any two adjacent second etched conductive layers with storage contact isolation material to form a storage contact isolation layer.

[0077] like Figure 3h and 3i As shown, a storage contact isolation layer 209 is formed by filling a first etching trench T1 between any two adjacent first etched conductive layers 203' and a second etching trench T2 between any two adjacent second etched conductive layers 204' with storage contact isolation material. The top surface 209-1 of the storage contact isolation layer 209 extends beyond the top surface 204'-1 of the second etched conductive layer.

[0078] Here, the storage contact isolation material can be silicon nitride.

[0079] In this embodiment, because the first etched trench T1 and the second etched trench T2 have a large aspect ratio (greater than 10:1), gaps will be generated during the filling process of the storage contact isolation material. These gaps can serve as air gaps between adjacent first conductive layers, thus reducing the critical dimension (CD) of the first etched trench. Consequently, the size of the first conductive layer will increase, resulting in lower resistance and reduced resistance-capacitance delay (Rc). For example, please refer to... Figure 3h and 3i When the storage contact isolation layer 209 is formed, an air gap 2091 is formed in the storage contact isolation layer.

[0080] Step S31: Etch the storage contact isolation layer to remove the storage contact isolation layer located on the top surface of the second etched conductive layer.

[0081] like Figure 3j and 3k As shown, a dry etching process is used to etch the storage contact isolation layer 209 along the Z-axis until the top surface 204'-1 of the second etched conductive layer is exposed.

[0082] In some embodiments, the second etching process performed on the second etched conductive layer along the third direction to form a plurality of mutually independent first conductive layers and a second conductive layer located on each of the first conductive layers includes: performing a partial etching process on the second etched conductive layer above the bit line mask layer along the third direction to expose a portion of the bit line mask layer, thereby forming a first conductive layer mutually independent along the first direction and a second conductive layer located on each of the first conductive layers.

[0083] In some embodiments, the second etching process may include the following steps: Step S22: A second mask layer with a second mask pattern is formed on the surface of the second etched conductive layer and the surface of the storage contact isolation layer.

[0084] Here, the second mask layer comprises a second hard mask layer, a second anti-reflection layer, and a second photoresist layer stacked sequentially. Step S22 can be formed through the following steps: Step S221: On the surfaces of the second etched conductive layer and the storage contact isolation layer, a second hard mask layer, a second anti-reflection layer and a second photoresist layer are sequentially deposited.

[0085] Here, the second hard mask layer is the same as the first hard mask layer, the second anti-reflection layer is the same as the first anti-reflection layer, and the second photoresist layer is the same as the first photoresist layer.

[0086] like Figures 4a-4c As shown, a second hard mask layer 210, a second anti-reflection layer 211, and a second photoresist layer 212 are sequentially deposited on the surface of the second etched conductive layer 204' and the surface of the storage contact isolation layer 209. The second photoresist layer 212 has a second mask pattern; the second mask pattern includes a plurality of sub-patterns 2121 arranged parallel to each other along the X-axis direction; each sub-pattern 2121 extends in a plane parallel to the semiconductor substrate at an angle B to the first direction, where the angle B is not equal to 90 degrees, for example, the angle B can be 60 degrees or 120 degrees.

[0087] In this embodiment, each sub-pattern has a diamond-shaped region that interrupts the second etched conductive layer, and this diamond-shaped region is used to form the subsequent second conductive layer. For example, Figure 4d Each of the sub-patterns 2121 has a cut-off rhomboid region C with the second etched conductive layer 204'.

[0088] Step S222: Through each of the sub-patterns, the second anti-reflective layer and the second hard mask layer are etched sequentially to form the second mask layer having the second mask pattern.

[0089] In this embodiment, a second mask pattern is used for the subsequent second etching process.

[0090] Step S23: Using the second mask pattern, a portion of the second etched conductive layer located above the bit line mask layer is etched away, and the remaining second etched conductive layer forms the second conductive layer.

[0091] like Figures 4e-4g As shown, the second conductive layer 204'' is formed on top of each first conductive layer 203'' by etching the second conductive layer 204 through the second mask pattern.

[0092] In some embodiments, the method for forming the semiconductor device may further include: forming a capacitor on the surface of the second conductive layer after forming the second conductive layer.

[0093] In some embodiments, forming a capacitor on the surface of the second conductive layer may include the following steps: Step S40: Fill the space between any two adjacent second conductive layers with insulating material to form an insulating layer.

[0094] Step S41: Sequentially deposit a first electrode layer, a dielectric layer, and a second electrode layer on the surface of the second conductive layer and the surface of the insulating layer to form the capacitor.

[0095] Here, the materials of the first electrode layer and the second electrode layer may include any of the following: metal, doped semiconductor, conductive metal oxide and conductive metal nitride.

[0096] In some embodiments, the method for forming the semiconductor device may further include: forming a word line structure located inside the active region before forming the bit line structure.

[0097] The semiconductor device provided in this application embodiment has a transistor formed in the active region. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line, or writing the data information into the capacitor for storage through the bit line.

[0098] This application provides a novel semiconductor device fabrication process. By directly etching conductive layers, multiple independent first conductive layers and a second conductive layer located on top of each first conductive layer are formed, thereby creating a semiconductor device. The method is simple and ingenious, greatly simplifying the process flow and reducing production costs. Furthermore, the semiconductor device fabrication method provided in this application does not require advanced exposure techniques, making the process simple and easy for large-scale production.

[0099] In addition, this application also provides a semiconductor device, which is formed by the semiconductor device formation method provided in the above embodiments. Figure 5a and 5b This is a schematic diagram of an optional structure of a semiconductor device provided in an embodiment of this application, such as... Figure 5a and 5b As shown, the semiconductor device 30 includes: a semiconductor substrate 300, a bit line structure 301, a first conductive layer 303, a second conductive layer 304, and a capacitor.

[0100] Semiconductor substrate 300, on which a plurality of active regions (not shown in the figure) are formed at intervals.

[0101] Bit line structure 301 includes a bit line contact layer 3011, a bit line metal layer 3012, and a bit line mask layer 3013; the bit line metal layer 3012 intersects with the active region through the bit line contact layer 3011; the bit line structure 301 is arranged at intervals along a first direction.

[0102] Here, the first direction can be the X-axis direction, and the bit line structure 301 is arranged at intervals along the X-axis direction.

[0103] In some embodiments, the semiconductor device 30 may further include a dielectric layer 302 located on the surface of the bit line structure 301, the dielectric layer 302 being used to protect the bit line structure 301.

[0104] A first conductive layer 303 and a second conductive layer 304 are connected to a capacitor through the second conductive layer 304.

[0105] In some embodiments, the first conductive layer may be a storage node contact, and the second conductive layer may be a landing pad.

[0106] Please continue reading Figure 5a The second conductive layer 304 includes a first structure having a first preset height h1 located above a portion of the first conductive layer 303 and a second structure having a second preset height h2 located above a portion of the bit line structure; the first preset height h1 is greater than the second preset height h2.

[0107] Please continue reading Figure 5b In some embodiments, the semiconductor device 30 further includes a storage contact isolation layer 309; the storage contact isolation layer 309 is located between any two adjacent first conductive layers 303 and between any two adjacent second conductive layers 304.

[0108] In some embodiments, please continue to see Figure 5b The semiconductor device 30 further includes an air gap 3091; the air gap 3091 is located in the storage contact isolation layers arranged sequentially along a second direction; wherein, the second direction is perpendicular to the first direction, and the plane formed by the second direction and the first direction is parallel to the plane where the semiconductor substrate 300 is located. Here, the second direction is the Y-axis direction.

[0109] In some embodiments, please continue to see Figure 5b The air gap 3091 is composed of a first part and a second part; the first part of the air gap 3091 is located in the storage contact isolation layer between two adjacent first conductive layers 303, and the second part of the air gap is located in the storage contact isolation layer between two adjacent second conductive layers 304 corresponding to the two adjacent first conductive layers.

[0110] In this embodiment, the first portion and the second portion are of equal size. In other embodiments, the first portion and the second portion may not be of equal size.

[0111] In this embodiment of the application, the height difference between the overlapping part of the first and second parts of the air gap and the tungsten layer in the bit line structure is less than a preset height value. In this way, the connection between adjacent first conductive layers and the connection between adjacent second conductive layers can be reduced.

[0112] In some embodiments, please continue to see Figure 5b The air gap 3091 has a third preset height h3 along a third direction; the storage contact isolation layer has a fourth preset height h4 along the third direction; the fourth preset height is greater than the third preset height, and the difference between the fourth preset height h4 and the third preset height h3 is less than a preset difference; wherein, the third direction is perpendicular to the plane where the semiconductor substrate is located. In this embodiment, the magnitude of the preset difference is not specifically limited.

[0113] Here, the third direction is perpendicular to both the first direction and the second direction, and the third direction is the Z-axis direction.

[0114] In some embodiments, please continue to see Figure 5a and 5b The semiconductor device 30 further includes an insulating layer 305 located between two adjacent second conductive layers 304. The insulating layer is used to give the second conductive layers a flat surface, facilitating the subsequent formation of a capacitor on the second conductive layers. The insulating layer 305 may be made of silicon dioxide.

[0115] In the embodiments of this application, please continue to refer to Figure 5a and 5b The capacitor includes a first electrode layer 306, a dielectric layer 307, and a second electrode layer 308. Here, the materials of the first electrode layer 306 and the second electrode layer 308 include any one of the following: metal, doped semiconductor, conductive metal oxide, and conductive metal nitride; the material of the dielectric layer 307 includes any one of the following: halogen oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, titanium dioxide, and perovskite structure materials.

[0116] The semiconductor device provided in this application embodiment is similar to the semiconductor device provided in the above embodiments in terms of the method of forming. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0117] This application provides a semiconductor device. Since the semiconductor device has an air gap located in the storage contact isolation layer between adjacent first conductive layers and in the storage contact isolation layer between adjacent second conductive layers, the critical size of the storage contact isolation layer between adjacent first conductive layers can be reduced, thereby increasing the size of the first conductive layer, which in turn reduces the resistance of the first conductive layer and reduces the resistance-capacitance delay, resulting in the fabricated semiconductor device having excellent electrical performance.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or they can be integrated into another system, or some features can be ignored or not executed.

[0119] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0120] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a plurality of bit line structures spaced apart along a first direction; A conductive material is filled on the surface of the bit line structure to form a conductive layer covering the surface of the bit line structure. The conductive layer includes a first initial conductive layer and a second initial conductive layer, and the top surface of the conductive layer extends beyond the top surface of the bit line structure. Etching the conductive layer to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers includes: Along a third direction, the first initial conductive layer and the second initial conductive layer are sequentially subjected to a first etching process to form a first etched conductive layer and a second etched conductive layer that are independent of each other along the second direction. Along the third direction, the second etched conductive layer is subjected to a second etching process to form a plurality of independent first conductive layers and a second conductive layer located on each of the first conductive layers; Wherein, the second direction is perpendicular to the first direction, the plane formed by the second direction and the first direction is parallel to the plane where the semiconductor substrate is located, and the third direction is perpendicular to the plane where the semiconductor substrate is located; The first etching process includes: A first hard mask layer, a first anti-reflection layer, and a first photoresist layer are formed on the surface of the second initial conductive layer; wherein the first photoresist layer has a first initial mask pattern; An isolation layer is formed on the surface of the first photoresist layer having the first initial mask pattern; The isolation layer and the first initial mask pattern are etched sequentially, retaining the isolation layer located on the sidewall of the first initial mask pattern to form an isolation sidewall pattern; The first anti-reflective layer and the first hard mask layer are etched using the isolation sidewall pattern to form a first mask layer with a first mask pattern. The first mask layer is used to sequentially etch the second initial conductive layer and the first initial conductive layer to transfer the first mask pattern to the second initial conductive layer and the first initial conductive layer, forming the first etched conductive layer and the second etched conductive layer that are independent of each other along the second direction.

2. The method according to claim 1, characterized in that, The conductive material includes a first conductive material and a second conductive material; The step of filling the surface of the bit line structure with a conductive material to form a conductive layer covering the surface of the bit line structure includes: A first conductive material is filled on the surface of the bit line structure to form a first initial conductive layer covering the surface of the bit line structure; The first initial conductive layer is etched back to expose a portion of the bit line mask layer of the bit line structure; A second conductive material is filled on the surface of the first initial conductive layer after etch-back to form a second initial conductive layer covering the surface of the partial bit mask layer, wherein the top surface of the second initial conductive layer extends beyond the top surface of the bit mask layer.

3. The method according to claim 2, characterized in that, The second etching process, performed along the third direction, on the second etched conductive layer to form multiple independent first conductive layers and a second conductive layer located on each of the first conductive layers, includes: Along the third direction, the second etched conductive layer above the bit line mask layer is partially etched to expose a portion of the bit line mask layer, forming a first conductive layer that is independent of each other along the first direction and a second conductive layer located above each first conductive layer.

4. The method according to claim 2, characterized in that, The method further includes: After forming the first etched conductive layer and the second etched conductive layer that are independent of each other along the second direction, and before the second etching process, storage contact isolation material is filled in the first etch trench between any two adjacent first etched conductive layers and the second etch trench between any two adjacent second etched conductive layers to form a storage contact isolation layer. The storage contact isolation layer is etched to remove the storage contact isolation layer located on the top surface of the second etched conductive layer.

5. The method according to claim 4, characterized in that, The method further includes: When the storage contact isolation material is filled into the first and second etched trenches, an air gap is formed at the center of the storage contact isolation layer.

6. The method according to claim 4, characterized in that, The storage contact isolation material includes silicon nitride.

7. The method according to claim 4, characterized in that, The second etching process includes: A second mask layer having a second mask pattern is formed on the surface of the second etched conductive layer and the surface of the storage contact isolation layer; Using the second mask pattern, a portion of the second etched conductive layer located above the bit line mask layer is etched away, and the remaining second etched conductive layer forms the second conductive layer.

8. The method according to claim 7, characterized in that, The second mask layer includes a second hard mask layer, a second anti-reflection layer, and a second photoresist layer stacked sequentially; The step of forming a second mask layer having a second mask pattern on the surface of the second etched conductive layer and the surface of the storage contact isolation layer includes: On the surfaces of the second etched conductive layer and the storage contact isolation layer, a second hard mask layer, a second anti-reflection layer, and a second photoresist layer are sequentially deposited; wherein, the second photoresist layer has a second mask pattern; the second mask pattern includes a plurality of sub-patterns arranged parallel to the first direction; each of the sub-patterns extends in a plane parallel to the semiconductor substrate at an angle to the first direction, the angle being not equal to 90 degrees; The second anti-reflective layer and the second hard mask layer are sequentially etched through each of the sub-patterns to form the second mask layer having the second mask pattern.

9. A semiconductor device, characterized in that, The semiconductor device is formed by the semiconductor device forming method provided by any one of claims 1 to 8, comprising: A semiconductor substrate, wherein a plurality of active regions are formed on the semiconductor substrate at intervals; The bitline structure includes a bitline contact layer, a bitline metal layer, and a bitline mask layer; the bitline metal layer intersects with the active region through the bitline contact layer; the bitline structure is arranged at intervals along a first direction. A first conductive layer and a second conductive layer, wherein the first conductive layer is connected to the capacitor through the second conductive layer; The second conductive layer includes a first structure with a first preset height located above a portion of the first conductive layer and a second structure with a second preset height located above a portion of the bit line structure; the first preset height is greater than the second preset height.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device further includes: a storage contact isolation layer; The storage contact isolation layer is located between any two adjacent first conductive layers and between any two adjacent second conductive layers.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: an air gap; The air gap is located in the storage contact isolation layers arranged sequentially along the second direction; Wherein, the second direction is perpendicular to the first direction, and the plane formed by the second direction and the first direction is parallel to the plane in which the semiconductor substrate is located.

12. The semiconductor device according to claim 11, characterized in that, The air gap consists of a first part and a second part; The first part of the air gap is located in the storage contact isolation layer between two adjacent first conductive layers, and the second part of the air gap is located in the storage contact isolation layer between two adjacent second conductive layers corresponding to the two adjacent first conductive layers.

13. The semiconductor device according to claim 11, characterized in that, The air gap has a third preset height along the third direction; the storage contact isolation layer has a fourth preset height along the third direction; The fourth preset height is greater than the third preset height, and the difference between the fourth preset height and the third preset height is less than a preset difference. The third direction is perpendicular to the plane where the semiconductor substrate is located.

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