Method for improving precision of integrated circuit and chip

By determining the current value of the metal wire and adjusting the connection point position, the process deviation problem caused by the metal wire wiring method was solved, the precision of integrated circuits was improved, and the high precision requirements in the chip manufacturing process were achieved.

CN115346978BActive Publication Date: 2026-05-29SG MICRO CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SG MICRO CORP
Filing Date
2022-07-19
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

In existing high-precision chip manufacturing technologies, process deviations caused by metal wire routing methods result in increased layout area and unreasonable arrangement, affecting chip precision.

Method used

By collecting the current values ​​of multiple metal lines, the chip error source is identified, and the connection points of other metal lines connected to the error source are adjusted so that they are directly connected to the component port, thereby reducing process deviations caused by metal line resistance.

Benefits of technology

It improves the precision of integrated circuits, reduces process deviations caused by metal line resistance, avoids mutual interference between metal lines, and improves chip output accuracy. At the same time, it does not require changes to the width, length, or shape of the metal lines, saving layout area.

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    Figure CN115346978B_ABST
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Abstract

The application discloses a method for improving the precision of an integrated circuit, and has the characteristics that the method comprises the following steps: step 1, collecting the current values of a plurality of metal wires connected to the same element port in a high-precision chip; step 2, when the current value of one of the plurality of metal wires exceeds a preset threshold, determining that the current metal wire is a chip error source; and step 3, adjusting the connection point positions of other metal wires connected to the chip error source to ensure that the voltages of the connection point positions of the other metal wires are not disturbed by the chip error source.
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