Integrated chip and method of forming the same

Abstract

In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and forming an unpatterned amorphous initial layer over the lower electrode layer. A layer of intermediate ferroelectric material having a substantially uniform amorphous phase is formed on the unpatterned amorphous initial layer. An annealing process is performed to change the layer of intermediate ferroelectric material to a layer of ferroelectric material having a substantially uniform orthorhombic phase. An upper electrode layer is formed over the layer of ferroelectric material. One or more patterning processes are performed on the upper electrode layer, the layer of ferroelectric material, the unpatterned amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device. Embodiments of the present disclosure also relate to an integrated chip.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and more specifically, to an integrated chip and a method for forming the same. Background Technology

[0002] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile memory stores data when power is applied, while non-volatile memory stores data when power is removed. Ferroelectric random access memory (FeRAM) devices are a promising candidate for next-generation non-volatile memory technology. This is because FeRAM devices offer many advantages, including fast write times, high robustness, low power consumption, and low sensitivity to radiation damage. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a method for forming an integrated chip is provided, comprising: forming a lower electrode layer over a substrate; forming an unpatterned amorphous initial layer over the lower electrode layer; forming an intermediate ferroelectric material layer on the unpatterned amorphous initial layer, wherein the intermediate ferroelectric material layer is formed having a substantially uniform amorphous phase; performing an annealing process configured to change the intermediate ferroelectric material layer into a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase; forming an upper electrode layer over the ferroelectric material layer; performing one or more patterning processes on the upper electrode layer, the ferroelectric material layer, the unpatterned amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device; forming an interlayer dielectric (ILD) layer over the ferroelectric memory device; and forming an upper interconnect extending through the upper ILD layer to contact the ferroelectric memory device.

[0004] According to another aspect of the embodiments of this application, a method for forming an integrated chip is provided, comprising: forming one or more lower interconnects within one or more lower interlayer dielectric (ILD) layers above a substrate; forming a lower insulating structure above the one or more lower ILD layers, wherein the lower insulating structure has sidewalls defining an opening extending through the lower insulating structure; forming a lower electrode layer above the lower insulating structure; forming an unpatterned amorphous initial layer above the lower electrode layer, wherein the unpatterned amorphous initial layer has an amorphous phase; and forming an intermediate ferroelectric material layer in contact with the upper surface of the unpatterned amorphous initial layer, wherein the unpatterned amorphous initial layer has an amorphous phase. The patterned amorphous initial layer is configured such that the intermediate ferroelectric material layer to be formed has a fundamental amorphous phase between the outermost walls of the intermediate ferroelectric material layer; an annealing process is performed, the annealing process being configured to transform the intermediate ferroelectric material layer from an amorphous phase to a ferroelectric material layer having a crystalline phase; an upper electrode layer is formed over the ferroelectric material layer; one or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the unpatterned amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device; an upper interlayer dielectric (ILD) layer is formed over the lower insulating structure; and an upper interconnect extending through the upper ILD layer to contact the ferroelectric memory device is formed.

[0005] According to another aspect of the embodiments of this application, an integrated chip is provided, comprising: a lower electrode including a first metal disposed above a substrate; an upper electrode including a second metal disposed above the lower electrode; and a ferroelectric data storage structure disposed between the lower electrode and the upper electrode, wherein the ferroelectric data storage structure includes a ferroelectric switching layer and an amorphous initial layer separating the ferroelectric switching layer from the lower electrode; wherein the amorphous initial layer has a structure configured to influence the crystalline phase of the ferroelectric switching layer; and wherein the ferroelectric switching layer includes a substantially uniform orthorhombic crystalline phase extending between the outermost surfaces of the ferroelectric switching layer. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 The illustration shows cross-sectional views of some embodiments of an integrated chip having a ferroelectric data storage structure, which includes an amorphous initial layer configured to improve the performance of the ferroelectric data storage structure.

[0008] Figure 2 The illustration shows cross-sectional views of some additional embodiments of an integrated chip having a ferroelectric data storage structure including an amorphous initial layer.

[0009] Figures 3A to 3BThe illustration shows cross-sectional views of some additional embodiments of an integrated chip having a ferroelectric data storage structure including an amorphous initial layer.

[0010] Figures 4A to 4C The illustration shows cross-sectional views of some additional embodiments of an integrated chip having a ferroelectric data storage structure including an amorphous initial layer.

[0011] Figures 5 to 7 The illustration shows cross-sectional views of some additional embodiments of an integrated chip having a ferroelectric data storage structure including multiple amorphous initial layers.

[0012] Figure 8 The illustration shows cross-sectional views of some additional embodiments of an integrated chip with a ferroelectric data storage structure, which includes multiple ferroelectric switching layers arranged on opposite sides of an amorphous initial layer.

[0013] Figure 9 The illustration shows graphs illustrating some embodiments of the ferroelectric response of ferroelectric memory devices with different sizes.

[0014] Figure 10 The illustration shows graphs illustrating some embodiments of the ferroelectric response ratios of ferroelectric memory devices with different sizes.

[0015] Figures 11A to 11B The illustration shows graphs illustrating some embodiments of the memory window of a ferroelectric memory device over time.

[0016] Figure 12 An exemplary schematic diagram of a memory circuit with a memory array is shown, the memory array including ferroelectric memory devices each having a ferroelectric data storage structure including an amorphous initial layer.

[0017] Figures 13 to 22 The illustration shows cross-sectional views of some embodiments of a method for forming an integrated chip having a ferroelectric data storage structure including an amorphous initial layer.

[0018] Figures 23 to 32 The illustration shows cross-sectional views of some additional embodiments of a method for forming an integrated chip having a ferroelectric data storage structure including an amorphous initial layer.

[0019] Figure 33 The illustration shows flowcharts of some embodiments of a method for forming an integrated chip having a ferroelectric data storage structure including an amorphous initial layer. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0022] Ferroelectric random access memory (FeRAM) devices have a lower electrode spaced from an upper electrode by a ferroelectric data storage structure comprising a ferroelectric material. The ferroelectric material has intrinsic electric dipoles that can be switched between opposite polarities by applying an external electric field. The different polarities provide different capacitances to the FeRAM device, which can be sensed by voltage on the bit lines during read operations. Different capacitances represent different data states (e.g., logic "0" or "1"), thus allowing the FeRAM device to store data digitally.

[0023] It has been recognized that some ferroelectric materials (e.g., hafnium zirconium oxide) used in ferroelectric data storage structures can be formed during manufacturing to have multiple different crystal phases (e.g., monoclinic, tetragonal, and / or orthorhombic phases) due to the influence of the lower electrode. It has further been recognized that multiple different crystal phases of the ferroelectric material will result in different ferroelectric memory devices within the memory array having different memory windows (e.g., voltage differences on bit lines between low data states (e.g., logic "0") and high data states (e.g., logic "1"). For example, a ferroelectric memory device having 78% monoclinic, 17% orthorhombic, and 5% tetragonal ferroelectric material may have a memory window of 0.2 volts (V), while a ferroelectric memory device having 16% monoclinic, 62% orthorhombic, and 22% tetragonal ferroelectric material may have a memory window of 0.7 V. Therefore, ferroelectric memory devices made of ferroelectric materials with low orthorhombic crystal phases can have relatively small memory windows, making it difficult to distinguish different data states during read operations.

[0024] As the size of FeRAM devices decreases, the variation in orthorhombic phase distribution within the ferroelectric data storage structure increases, resulting in greater device-to-device variability between different ferroelectric memory devices. For example, below a cell size of approximately 135 nm, the relatively large device-to-device variability of FeRAM devices reduces the memory window of the associated device, thereby reducing the ability of sensing circuitry (e.g., a sense amplifier) ​​to distinguish between low data states (e.g., logic "0") and high data states (e.g., logic "1") during read operations.

[0025] In some embodiments, this disclosure relates to an integrated chip having a ferroelectric data storage structure disposed between a lower electrode and an upper electrode. The ferroelectric data storage structure includes an amorphous initial layer and a ferroelectric switching layer. The amorphous initial layer is configured to influence the crystal phase of the ferroelectric switching layer. By influencing the crystal phase of the ferroelectric switching layer, the amorphous initial layer can cause the ferroelectric switching layer to form a substantially uniform orthorhombic crystal phase, thereby reducing device-to-device variations on the memory array and improving the reliability of read operations on the memory array.

[0026] Figure 1 The illustration shows cross-sectional views of some embodiments of an integrated chip 100 having a ferroelectric data storage structure including an amorphous initial layer.

[0027] The integrated chip 100 includes a ferroelectric memory device 104 (e.g., a FeRAM device) disposed within a dielectric structure 106 above a substrate 102. The ferroelectric memory device 104 includes a lower electrode 108 disposed above the substrate 102. A memory structure 109 is disposed between the lower electrode 108 and an upper electrode 114. The ferroelectric data storage structure 109 is configured to change polarization based on one or more voltages applied to the lower electrode 108 and / or the upper electrode 114. An upper interconnect 116 extends through the dielectric structure 106 to contact the upper electrode 114.

[0028] The ferroelectric data storage structure 109 includes an amorphous initial layer 110 and a ferroelectric switching layer 112. In some embodiments, the amorphous initial layer 110 may directly contact the ferroelectric switching layer 112. In some embodiments, the amorphous initial layer 110 may be disposed between the ferroelectric switching layer 112 and the lower electrode 108. In other embodiments (not shown), the amorphous initial layer 110 may be separated from the lower electrode 108 through the ferroelectric switching layer 112. In some embodiments, the amorphous initial layer 110 may include an amorphous phase.

[0029] The amorphous initial layer 110 is configured to influence the crystal phase (i.e., crystal structure) of the ferroelectric switch layer 112 during the fabrication of the ferroelectric memory device 104. For example, in some embodiments, the amorphous initial layer 110 may be configured to act as a nucleation site that influences the crystal phase of the ferroelectric switch layer 112 during the fabrication of the ferroelectric memory device 104 (e.g., during the epitaxial growth of the ferroelectric switch layer 112). In some embodiments, the amorphous initial layer 110 is configured to prevent interaction between the ferroelectric switch layer 112 and the lower electrode 108, thereby preventing the lower electrode 108 from influencing the crystal structure of the ferroelectric switch layer 112 and allowing the ferroelectric switch layer 112 to be formed having an amorphous phase (i.e., an amorphous structure). In some such embodiments, a subsequent annealing process is configured to transform the amorphous phase of the ferroelectric switch layer 112 into an orthorhombic crystal structure, thereby imparting a substantially uniform orthorhombic crystal phase to the ferroelectric switch layer 112 (e.g., imparting a significantly orthorhombic crystal phase to the ferroelectric switch layer 112).

[0030] By influencing the crystal phase of the ferroelectric switching layer 112, the amorphous initial layer 110 can result in the ferroelectric switching layer 112 having a substantially uniform crystal phase. In some embodiments, the substantially uniform orthorhombic crystal phase extends between the outermost surfaces of the ferroelectric switching layer 112 (e.g., the outermost outermost walls and / or the top and bottom surfaces). The substantially uniform crystal phase can reduce device-to-device variations that may occur on the crystal phase of the memory array. Reducing device-to-device variations mitigates the reduction in memory window size that results from the reduction in memory device dimensions, thereby improving the performance of the integrated chip 100 (e.g., read window).

[0031] Figure 2The illustration shows cross-sectional views of some additional embodiments of an integrated chip 200 having a ferroelectric data storage structure including an amorphous initial layer.

[0032] The integrated chip 200 includes a ferroelectric memory device 104 disposed within a dielectric structure 106, the dielectric structure 106 including a plurality of stacked interlayer dielectric (ILD) layers located above a substrate 102. In some embodiments, the plurality of stacked ILD layers may include one or more lower ILD layers 106L disposed between the ferroelectric memory device 104 and the substrate 102, and an upper ILD layer 106U surrounding the ferroelectric memory device 104. In some embodiments, the one or more lower ILD layers 106L surround one or more lower interconnects 204a-204c. In some embodiments, an upper interconnect 116 extends through the upper ILD layer 106U to contact the ferroelectric memory device 104.

[0033] In some embodiments, one or more lower interconnects 204a-204c may couple the ferroelectric memory device 104 to the access device 202. In various embodiments, the access device 202 may include a unipolar selector (e.g., a diode), a bipolar selector (e.g., a transistor device disposed within the substrate 102), or the like. In some embodiments, the access device 202 may include a planar FET, a FinFET, a gate-all-around (GAA) transistor, a nanosheet transistor, etc. In some such embodiments, one or more lower interconnects 204a-204c may couple the ferroelectric memory device 104 to the source line SL, the access device 202 may couple the ferroelectric memory device 104 to the word line WL, and the upper interconnect 116 may couple the ferroelectric memory device 104 to the bit line BL.

[0034] In some embodiments, one or more lower interconnects 204a-204c and / or upper interconnects 116 may include conductive contacts 204a, interconnect lines 204b, and / or interconnect vias 204c. In some embodiments, one or more lower interconnects 204a-204c and upper interconnects 116 may include tungsten, aluminum, copper, ruthenium, etc. In some embodiments, multiple stacked ILD layers may include nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or the like.

[0035] The ferroelectric memory device 104 includes a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. In some embodiments, the lower electrode 108 may include a first metal and the upper electrode 114 may include a second metal. In some embodiments, the first metal and / or the second metal may include tungsten, tantalum, titanium, tantalum nitride, titanium nitride, ruthenium, platinum, iridium, molybdenum, etc. In some embodiments, the lower electrode 108 and the upper electrode 114 may each have a thickness between about 10 nanometers (nm) and about 100 nm, between about 5 nm and about 50 nm, or other similar values.

[0036] The ferroelectric data storage structure 109 includes an amorphous initial layer 110 and a ferroelectric switching layer 112. In some embodiments, the amorphous initial layer 110 separates the ferroelectric switching layer 112 from the lower electrode 108. In some embodiments, the amorphous initial layer 110 may include silicon oxide (e.g., SiO2). x ), silicon nitride (e.g., Si) x N y ), tantalum oxide (e.g., TaO) x ), tantalum nitride (e.g., TaN), aluminum oxide (e.g., AlO) x ), aluminum nitride (e.g., AlN), yttrium oxide (e.g., YO) x ), gadolinium oxide (e.g., GdO) x ), lanthanum oxide (e.g., LaO) x ), Strontium oxide (e.g., SrO), x In some embodiments, the ferroelectric switching layer 112 may include a high-k dielectric material. For example, in some embodiments, the ferroelectric switching layer 112 may include hafnium oxide, hafnium zirconium oxide, zirconium oxide, etc.

[0037] In some embodiments, the amorphous initial layer 110 may have a thickness 208 between about 10 angstroms (Å) and about 30 Å. In other embodiments, the thickness 208 may be approximately... Peace Treaty Between, about Peace Treaty Between, or other similar values. If the thickness 208 of the amorphous initial layer 110 is greater than approximately The operating voltage of the ferroelectric switching layer 112 will then increase. In some embodiments, the ferroelectric switching layer 112 may have an operating voltage of approximately... Peace Treaty Between, in Peace Treaty Thickness 210 within the range of between or other similar values.

[0038] In some embodiments, the amorphous initial layer 110 may include and / or be a material having a relatively high crystallization temperature. The relatively high crystallization temperature allows the amorphous initial layer 110 to remain amorphous during high-temperature processes. By keeping the amorphous initial layer 110 amorphous during high-temperature processes, the amorphous initial layer 110 is able to remain amorphous and influence the phase of the overlying ferroelectric switching layer 112 to be amorphous. In some embodiments, the amorphous initial layer 110 may have a higher crystallization temperature than the ferroelectric switching layer 112, such that the amorphous initial layer 110 remains amorphous even when the ferroelectric switching layer 112 becomes a crystalline phase (e.g., an orthorhombic phase). In some embodiments, the amorphous initial layer 110 may include and / or be a material having a crystallization temperature greater than about 400 degrees Celsius (°C), greater than about 500°C, greater than about 750°C, or other similar values.

[0039] In some embodiments, the lower electrode 108 may be separated from one or more lower interconnects 204a-204b and / or one or more lower ILD layers 106L by a diffusion barrier layer 206. In some such embodiments, the diffusion barrier layer 206 may contact the lower surface of the lower electrode 108. In some embodiments, the diffusion barrier layer 206 may include tantalum nitride, titanium nitride, or the like.

[0040] Figure 3A The illustration shows cross-sectional views of some additional embodiments of an integrated chip 300 having a ferroelectric data storage structure including an amorphous initial layer.

[0041] The integrated chip 300 includes a memory region 302 and a logic region 304. The memory region 302 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 above a substrate 102. In some embodiments, the ferroelectric memory device 104 may be arranged in an array including a plurality of ferroelectric memory devices. The ferroelectric memory device 104 is coupled to the access device 202 via one or more lower interconnects 204 within one or more lower ILD layers 106L. In some embodiments, the access device 202 includes a gate electrode 202a disposed above the substrate 102 and disposed between source / drain regions 202b within the substrate 102. In some embodiments, the gate electrode 202a may be separated from the substrate 102 by a gate dielectric 202c. In some embodiments, one or more isolation structures 303 may be disposed within the substrate 102 along opposite sides of the access device 202. The one or more isolation structures 303 are configured to electrically isolate the access device 202 from adjacent devices. In some embodiments, one or more isolation structures 303 may include shallow trench isolation (STI) structures, the STI structures including one or more dielectric materials disposed within one or more trenches defined by the sidewalls of the substrate 102.

[0042] In some embodiments, a lower insulating structure 310 is disposed over one or more lower ILD layers 106L. The lower insulating structure 310 includes sidewalls defining openings disposed over one or more lower interconnects 204. A lower electrode via 306 extends through the openings defined by the sidewalls of the lower insulating structure 310. The lower electrode via 306 couples the ferroelectric memory device 104 to one or more lower interconnects 204.

[0043] The ferroelectric memory device 104 includes a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. The ferroelectric data storage structure 109 includes an amorphous initial layer 110 and a ferroelectric switching layer 112. In some embodiments, the lower electrode 108, the amorphous initial layer 110, the ferroelectric switching layer 112, and the upper electrode 114 may include substantially flat layers. In such embodiments, the lower electrode 108, the amorphous initial layer 110, the ferroelectric switching layer 112, and the upper electrode 114 may each have a substantially flat lower surface and a substantially flat upper surface extending laterally between the outermost outermost walls, respectively.

[0044] In some embodiments, a diffusion barrier layer 206 may be disposed between the lower electrode 108 and the lower insulating structure 310. In some embodiments, the diffusion barrier layer 206 may extend laterally beyond the outermost wall of the lower electrode via 306 to be located directly above the upper surface of the lower insulating structure 310. In some embodiments, the diffusion barrier layer 206 may also comprise a substantially flat layer. In some alternative embodiments (not shown), the diffusion barrier layer 206 may pave both the outer wall and the lower surface of the lower electrode via 306.

[0045] Logic region 304 includes logic devices 307 disposed on and / or within substrate 102. In some embodiments, logic devices 307 may include transistor devices (e.g., planar FETs, finFETs, gate-all-around (GAA) transistors, nanosheet transistors, etc.). In some embodiments, one or more isolation structures 303 may also be disposed within substrate 102 along opposite sides of logic devices 307. Logic devices 307 are coupled to one or more additional lower interconnects 308 disposed within one or more lower ILD layers 106L. One or more additional lower interconnects 308 are further coupled to interconnect vias 312 disposed within upper ILD layer 106U and extending through lower insulating structure 310.

[0046] Figure 3B The illustration shows cross-sectional views of some alternative embodiments of an integrated chip 314 having a ferroelectric data storage structure including an amorphous initial layer.

[0047] Integrated chip 314 includes a lower insulating structure 310 disposed above one or more lower ILD layers 106L, the lower ILD layers 106L surrounding one or more lower interconnects 204. Ferroelectric memory device 104 is disposed above the lower insulating structure 310. The lower insulating structure 310 includes one or more sidewalls 310s that define openings exposing one or more lower interconnects 204. In some embodiments, the one or more sidewalls 310s may be angled. In some such embodiments, the one or more sidewalls 310s may be spaced at an acute angle from the lower surface of the lower insulating structure 310, as measured by the lower insulating structure 310.

[0048] The ferroelectric memory device 104 includes a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. The ferroelectric data storage structure 109 includes an amorphous initial layer 110 and a ferroelectric switching layer 112. In some embodiments, the lower electrode 108, the amorphous initial layer 110, the ferroelectric switching layer 112, and the upper electrode 114 are conformal layers (e.g., each having a substantially V-shaped structure). In some such embodiments, the lower electrode 108 cushions one or more sidewalls 310s defining an opening in the lower insulating structure 310 and has angled inner sidewalls defining a first groove within the upper surface of the lower electrode 108. The amorphous initial layer 110 cushions the angled inner sidewalls of the lower electrode 108 and has angled inner sidewalls defining a second groove within the upper surface of the amorphous initial layer 110. The ferroelectric switching layer 112 cushions the angled inner sidewalls of the amorphous initial layer 110 and has angled inner sidewalls defining a third groove within the upper surface of the ferroelectric switching layer 112. The upper electrode 114 cushions the angled inner sidewalls of the ferroelectric switch layer 112. In some embodiments, the upper electrode 114 may completely fill the third recess.

[0049] Because the lower electrode 108, the amorphous initial layer 110, the ferroelectric switching layer 112, and the upper electrode 114 are conformal layers, they have surface regions extending in both the lateral and vertical directions. By extending in both directions, the layers have a larger effective width (i.e., the distance between the outermost walls of the layer measured along the upper surface of the layer). This larger effective width increases the size of the ferroelectric switching layer 112 without increasing the footprint of the ferroelectric memory device 104. By increasing the size of the ferroelectric switching layer 112, the probability of obtaining a more uniform crystalline phase (e.g., an orthorhombic phase) within the ferroelectric switching layer 112 increases, thereby improving the performance of the ferroelectric memory device 104.

[0050] Figure 4A The illustration shows cross-sectional views of some additional embodiments of an integrated chip 400 having a ferroelectric data storage structure including an amorphous initial layer.

[0051] The integrated chip 400 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 disposed above a substrate 102. In some embodiments, the dielectric structure 106 includes a plurality of stacked interlayer dielectric (ILD) layers 106a-106e. The plurality of stacked ILD layers 106a-106e include one or more lower ILD layers 106a-106d and an upper ILD layer 106e. The one or more lower ILD layers 106a-106d laterally surround one or more lower interconnects 204 configured to couple the ferroelectric memory device 104 to an access device 202.

[0052] In some embodiments, a lower insulating structure 310 is disposed above one or more lower ILD layers 106a-106d. The lower insulating structure 310 includes sidewalls forming openings extending through it. In various embodiments, the lower insulating structure 310 may include one or more of silicon nitride, silicon dioxide, silicon carbide, or the like. In some embodiments, an upper insulating structure 406 is disposed above the ferroelectric memory device 104 and on the lower insulating structure 310. The upper insulating structure 406 extends continuously from a first location directly above the ferroelectric memory device 104 to a second location adjacent to the upper surface of the lower insulating structure 310. The upper insulating structure 406 separates the ferroelectric memory device 104 from the upper ILD layer 106e. In some embodiments, the upper insulating structure 406 may include one or more of silicon nitride, silicon dioxide, silicon carbide, tetraethyl orthosilicate (TEOS), or the like.

[0053] A lower electrode via 306 extends through the lower insulating structure 310. In some embodiments, the lower electrode via 306 may include a diffusion barrier layer 306a and a lower electrode via layer 306b above the diffusion barrier layer 306a. A ferroelectric memory device 104 is disposed above the lower electrode via 306 and the lower insulating structure 310. In some embodiments, the ferroelectric memory device 104 includes a lower electrode 108 separated from the upper electrode 114 by a ferroelectric data storage structure 109. In some embodiments, the ferroelectric data storage structure 109 may include an amorphous initial layer 110 and a ferroelectric switching layer 112.

[0054] In some embodiments, a hard mask 402 may be disposed on the upper electrode 114. In some embodiments, one or more sidewall spacers 404 may be disposed on opposite sides of the upper electrode 114 and the hard mask 402. The hard mask 402 may include a metal (e.g., titanium, tantalum, or the like) and / or a dielectric (e.g., nitride, carbide, or the like). One or more sidewall spacers 404 may include oxides (e.g., silicon-rich oxides), nitrides (e.g., silicon nitride), carbides (e.g., silicon carbide), or the like. In some embodiments, an upper interconnect 116 extends through the upper ILD layer 106e and the hard mask 402 to electrically contact the upper electrode 114.

[0055] Figure 4B The illustration shows cross-sectional views of some alternative embodiments of an integrated chip 408 having a ferroelectric data storage structure including an amorphous initial layer.

[0056] Integrated chip 408 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 disposed above substrate 102. Ferroelectric memory device 104 includes a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. Ferroelectric data storage structure 109 includes an amorphous initial layer 110 and a ferroelectric switching layer 112. The lower electrode 108, amorphous initial layer 110, ferroelectric switching layer 112, and upper electrode 114 are conformal layers (e.g., each having a substantially V-shaped structure).

[0057] It should be understood that, in various embodiments, the disclosed ferroelectric data storage structure can be housed within different types of devices (e.g., FRAM, FTJ devices, MTJ devices, DRAM devices, FeFET devices, etc.). For example, Figure 4C The illustration shows cross-sectional views of some additional embodiments of an integrated chip 410 having a disclosed ferroelectric data storage structure arranged within a FeFET device 412.

[0058] The FeFET device 412 has a gate structure 414 disposed between source / drain regions 416 within a substrate 102. The gate structure 414 includes a gate dielectric 418 disposed on the substrate 102 and a conductive material 420 disposed on the gate dielectric 418. An amorphous initial layer 110 is disposed on the conductive material 420, and a ferroelectric switching layer 112 is disposed on the amorphous initial layer 110. A gate electrode 422 is disposed on the ferroelectric switching layer 112. One or more upper interconnects 424 are disposed within a dielectric structure 106 above the substrate 102. One or more upper interconnects 424 contact the gate electrode 422.

[0059] In some embodiments, the gate dielectric 418 may include oxides, such as silicon oxide, silicon oxynitride, or the like. In some embodiments, the conductive material 420 and / or the gate electrode 422 may include titanium nitride, tantalum nitride, tungsten, ruthenium, or the like. In some embodiments, the ferroelectric switching layer 112 may include hafnium oxide, hafnium zirconium oxide, zirconium oxide, lead zirconate titanate (PZT), or the like. In some embodiments, the conductive material 420 may include titanium nitride, tantalum nitride, tungsten, ruthenium, or the like.

[0060] In some alternative embodiments, the disclosed ferroelectric data storage structure can be used in a memory device that may include an FRAM device. In such embodiments, the upper and lower electrodes may each comprise one or more of titanium nitride, tantalum nitride, tungsten, ruthenium, or the like. In some such embodiments, the ferroelectric switching layer may comprise hafnium oxide, hafnium zirconium oxide, zirconium oxide, PZT, or the like.

[0061] In other alternative embodiments, the disclosed ferroelectric data storage structure can be used in a memory device that may include an FTJ device. In such embodiments, the upper and lower electrodes may each comprise one or more of titanium nitride, tantalum nitride, tungsten, ruthenium, platinum, niobium-doped strontium titanate (Nb:STO), or the like. In some such embodiments, the ferroelectric switching layer may comprise hafnium oxide, hafnium zirconium oxide, zirconium oxide, PZT, barium titanate, or the like.

[0062] In yet another alternative embodiment, the disclosed ferroelectric data storage structure can be used in a memory device that may include an MTJ device. In such an embodiment, the upper and lower electrodes may each comprise one or more of titanium nitride, tantalum nitride, tungsten, ruthenium, or the like. In some such embodiments, the ferroelectric switching layer may comprise hafnium oxide, hafnium zirconium oxide, zirconium oxide, or the like.

[0063] In other alternative embodiments, the disclosed ferroelectric data storage structure can be used in memory devices that may include DRAM devices. In such embodiments, the upper and lower electrodes may each comprise one or more of titanium nitride, tantalum nitride, tungsten, ruthenium, or the like. In some such embodiments, the ferroelectric switching layer may comprise hafnium oxide, hafnium zirconium oxide, aluminum hafnium zirconium oxide, niobium oxide, or the like.

[0064] Figure 5 The illustration shows some additional embodiments of an integrated chip 500 having a ferroelectric memory device including a ferroelectric data storage structure comprising multiple amorphous initial layers.

[0065] The integrated chip 500 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 above a substrate 102. The ferroelectric memory device 104 has a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. The data storage structure 109 includes an amorphous initial layer 110 disposed on the lower electrode 108, a ferroelectric switching layer 112 disposed on the amorphous initial layer 110, and a second amorphous initial layer 502 disposed on the ferroelectric switching layer 112. The amorphous initial layer 110 contacts the lower electrode 108, and the second amorphous initial layer 502 contacts the upper electrode 114. In some embodiments, the ferroelectric switching layer 112 may extend continuously from the lower surface contacting the amorphous initial layer 110 to the upper surface contacting the second amorphous initial layer 502.

[0066] In some embodiments, the amorphous initial layer 110 and the second amorphous initial layer 502 may comprise and / or be the same material. For example, in some embodiments, the amorphous initial layer 110 and the second amorphous initial layer 502 may comprise aluminum oxide. In other embodiments, the amorphous initial layer 110 may comprise a first material and the second amorphous initial layer 502 may comprise a second material different from the first material. For example, in some embodiments, the amorphous initial layer 110 may comprise tantalum nitride and the second amorphous initial layer 502 may comprise aluminum oxide.

[0067] Figure 6 The illustration shows some additional embodiments of an integrated chip 600 having a ferroelectric memory device including a ferroelectric data storage structure comprising multiple amorphous initial layers.

[0068] The integrated chip 600 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 above a substrate 102. The ferroelectric memory device 104 has a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. The data storage structure 109 includes an amorphous initial layer 110 disposed on the lower electrode 108, a ferroelectric switching layer 112 disposed on the amorphous initial layer 110, a second amorphous initial layer 502 disposed on the ferroelectric switching layer 112, and a second ferroelectric switching layer 602 disposed on the second amorphous initial layer 502. In some embodiments, the amorphous initial layer 110 contacts the lower electrode 108 and the second ferroelectric switching layer 602 contacts the upper electrode 114. In some embodiments, the ferroelectric switching layer 112 can continuously extend from the lower surface contacting the amorphous initial layer 110 to the upper surface contacting the second amorphous initial layer 502, and the second ferroelectric switching layer 602 can continuously extend from the lower surface contacting the second amorphous initial layer 502 to the upper surface contacting the upper electrode 114.

[0069] In some embodiments, the ferroelectric switching layer 112 and the second ferroelectric switching layer 602 may comprise and / or be the same material. For example, in some embodiments, the ferroelectric switching layer 112 and the second ferroelectric switching layer 602 may comprise hafnium zirconium oxide. In other embodiments, the ferroelectric switching layer 112 may comprise a first material and the second ferroelectric switching layer 602 may comprise a second material different from the first material. In some embodiments, both the ferroelectric switching layer 112 and the second ferroelectric switching layer 602 may have substantially orthorhombic phases.

[0070] Figure 7 The illustration shows some additional embodiments of an integrated chip 700 having a ferroelectric memory device including a ferroelectric data storage structure comprising multiple amorphous initial layers.

[0071] The integrated chip 700 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 above a substrate 102. The ferroelectric memory device 104 has a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. The data storage structure 109 includes an amorphous initial layer 110 disposed on the lower electrode 108, a ferroelectric switching layer 112 disposed on the amorphous initial layer 110, a second amorphous initial layer 502 disposed on the ferroelectric switching layer 112, a second ferroelectric switching layer 602 disposed on the second amorphous initial layer 502, and a third amorphous initial layer 702 disposed on the second ferroelectric switching layer 602. In some embodiments, the amorphous initial layer 110 contacts the lower electrode 108 and the third amorphous initial layer 702 contacts the upper electrode 114. In some embodiments, the ferroelectric switching layer 112 may extend continuously from the lower surface of the contact amorphous initial layer 110 to the upper surface of the contact second amorphous initial layer 502, and the second ferroelectric switching layer 602 may extend continuously from the lower surface of the contact second amorphous initial layer 502 to the upper surface of the contact third amorphous initial layer 702.

[0072] In some embodiments, the amorphous initial layer 110, the second amorphous initial layer 502, and the third amorphous initial layer 702 may comprise and / or be the same material. For example, in some embodiments, the amorphous initial layer 110, the second amorphous initial layer 502, and the third amorphous initial layer 702 may comprise aluminum oxide. In other embodiments, one or more of the amorphous initial layer 110, the second amorphous initial layer 502, and the third amorphous initial layer 702 may comprise and / or be different materials. For example, in some embodiments, the amorphous initial layer 110 may comprise tantalum nitride, and the second amorphous initial layer 502 and the third amorphous initial layer 702 may comprise aluminum oxide.

[0073] Figure 8The illustration shows some additional embodiments of an integrated chip 800 having a ferroelectric memory device including a ferroelectric data storage structure comprising multiple ferroelectric switching layers separated by an amorphous initial layer.

[0074] The integrated chip 800 includes a ferroelectric memory device 104 disposed within a dielectric structure 106 above a substrate 102. The ferroelectric memory device 104 has a ferroelectric data storage structure 109 disposed between a lower electrode 108 and an upper electrode 114. The data storage structure 109 includes a ferroelectric switching layer 112 disposed on the lower electrode 108, an amorphous initial layer 110 disposed on the ferroelectric switching layer 112, and a second ferroelectric switching layer 602 disposed on the amorphous initial layer 110. In some embodiments, the ferroelectric switching layer 112 contacts the lower electrode 108, and the second ferroelectric switching layer 602 contacts the upper electrode 114. In some embodiments, the amorphous initial layer 110 may extend continuously from the lower surface contacting the ferroelectric switching layer 112 to the upper surface contacting the second ferroelectric switching layer 602.

[0075] In some embodiments, the ferroelectric switching layer 112 and the second ferroelectric switching layer 602 may comprise and / or be the same material. For example, in some embodiments, the ferroelectric switching layer 112 and the second ferroelectric switching layer 602 may comprise hafnium zirconium oxide. In other embodiments, the ferroelectric switching layer 112 and the second ferroelectric switching layer 602 may comprise and / or be different materials. In some embodiments, the second ferroelectric switching layer 602 may have a substantially orthorhombic phase. In some embodiments, the ferroelectric switching layer 112 may have multiple different phases.

[0076] Figure 9 The figure 900 illustrates the ferroelectric response of ferroelectric memory devices of different sizes without an amorphous initial layer in some embodiments.

[0077] Graph 900 shows the capacitance (y-axis) of the ferroelectric material as a function of the applied voltage (x-axis). As graph 900 shows, the charge stored in the ferroelectric material changes with the applied voltage. The ferroelectric response corresponds to the difference between the maximum and minimum charge on the ferroelectric material. The difference in charge stored in the ferroelectric material corresponds to different data states stored in the ferroelectric material. For example, if the ferroelectric material stores a charge with a first value, it will store a first data state (e.g., logic "0"), while if it stores a charge with a second value, it will store a second data state (e.g., logic "1").

[0078] As shown in graph 900, the ferroelectric response dimensions of ferroelectric memory devices of different sizes are different. For example, line 902 shows the ferroelectric response of ferroelectric memory devices associated with cell sizes having a large width (e.g., between about 500 nm and about 550 nm), line 906 shows the ferroelectric response of ferroelectric memory devices associated with cell sizes having a medium width (e.g., between about 250 nm and about 300 nm) smaller than the large width, and line 910 shows the ferroelectric response of ferroelectric memory devices associated with cell sizes having a small width (e.g., between about 100 nm and about 150 nm) smaller than the medium width.

[0079] As shown in line 902, for ferroelectric memory devices associated with a large cell size, the ferroelectric response has a first value 904 corresponding to a first memory window (e.g., the difference between a high data state and a low data state). The relatively large first value 904 allows for relatively easy differentiation between high and low data states. However, as shown in line 906, for ferroelectric memory devices associated with a medium cell size, the ferroelectric response has a second value 908 smaller than the first value 904. The second value 908 makes it more difficult to distinguish between high and low data states. Furthermore, as shown in line 910, for ferroelectric memory devices associated with a small cell size, the ferroelectric response has a third value 912 smaller than the second value 908. The third value 912 makes it even more difficult to distinguish between high and low data states.

[0080] Figure 10 The figure shows a bar chart 1000 illustrating some embodiments of ferroelectric response ratios of ferroelectric memory devices with different sizes.

[0081] Bars 1002a-1002b illustrate the ratio of ferroelectric response between ferroelectric memory devices of different sizes without an amorphous initial layer (AIL). Bar 1002a illustrates ferroelectric memory devices associated with small cell sizes (e.g., with...). Figure 9 (associated with line 910) and ferroelectric memory devices associated with large cell sizes (e.g., with...). Figure 9 The ratio of the ferroelectric response (as associated with line 902). Bar 1002b illustrates the ratio of the ferroelectric response of a ferroelectric memory device associated with a medium cell size (e.g., with...). Figure 9 (associated with line 906) and ferroelectric memory devices associated with large cell sizes (e.g., with...). Figure 9The ratio of the ferroelectric response (as associated with line 902). As can be seen from bars 1002a-1002b, the width difference of the ferroelectric memory devices leads to significant differences in their ferroelectric responses. For example, the ferroelectric response of a ferroelectric memory device associated with a small cell size is approximately 20% of that associated with a large cell size, while the ferroelectric response of a ferroelectric memory device associated with a medium cell size is approximately 40% of that associated with a large cell size.

[0082] Columnar images 1004a-1004b illustrate the ferroelectric response ratios between ferroelectric memory devices of different sizes with an amorphous initial layer, which is separated from the lower and upper electrodes by a ferroelectric switching layer (e.g., as shown in the image). Figure 8 (As shown). Bar 1004a illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with small cell sizes to those associated with large cell sizes. Bar 1004b illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with medium cell sizes to those associated with large cell sizes. As can be seen from bars 1004a-1004b, in some embodiments, the ferroelectric response of ferroelectric memory devices associated with small cell sizes is approximately 40% of that associated with large cell sizes, while the ferroelectric response of ferroelectric memory devices associated with medium cell sizes is approximately 90% of that associated with large cell sizes. Therefore, as the size of the ferroelectric memory device decreases, the amorphous initial layer reduces the degradation of the memory window.

[0083] Columnar images 1006a-1006b illustrate the ferroelectric response ratios between ferroelectric memory devices of different sizes, which have an amorphous initial layer (e.g., as shown in the image) that is in contact with the lower electrode and separated from the upper electrode by a ferroelectric switching layer. Figure 1 (As shown in the diagram). Bar 1006a illustrates the ratio of the ferroelectric response of a ferroelectric memory device associated with a small cell size to that associated with a large cell size. Bar 1006b illustrates the ratio of the ferroelectric response of a ferroelectric memory device associated with a medium cell size to that associated with a large cell size. As can be seen from bars 1006a-1006b, in some embodiments, the ferroelectric response of a ferroelectric memory device associated with a small cell size is approximately 100% of the ferroelectric response of a ferroelectric memory device associated with a large cell size, while the ferroelectric response of a ferroelectric memory device associated with a medium cell size is approximately 100% of the ferroelectric response of a ferroelectric memory device associated with a large cell size.

[0084] Bar charts 1008a-1008b show the ratio of ferroelectric responses among ferroelectric memory devices of different sizes (e.g., as shown in the figure). Figure 5 (As shown). Bar 1008a illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with small cell sizes to those associated with large cell sizes. Bar 1008b illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with medium cell sizes to those associated with large cell sizes. As can be seen from bars 1008a-1008b, in some embodiments, the ferroelectric response of ferroelectric memory devices associated with small cell sizes is approximately 100% of that of ferroelectric memory devices associated with large cell sizes, while the ferroelectric response of ferroelectric memory devices associated with medium cell sizes is approximately 100% of that of ferroelectric memory devices associated with large cell sizes.

[0085] Bar charts 1010a-1010b show the ratio of ferroelectric responses between ferroelectric memory devices of different sizes, having an amorphous initial layer on the lower electrode, a ferroelectric switching layer on the amorphous initial layer, a second amorphous initial layer on the ferroelectric switching layer, and a second ferroelectric switching layer on the second amorphous initial layer (e.g., as shown in Figure 1010a-1010b). Figure 6 (As shown). Bar 1010a illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with small cell sizes to those associated with large cell sizes. Bar 1010b illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with medium cell sizes to those associated with large cell sizes. As can be seen from bars 1010a-1010b, in some embodiments, the ferroelectric response of ferroelectric memory devices associated with small cell sizes is approximately 100% of that of ferroelectric memory devices associated with large cell sizes, while the ferroelectric response of ferroelectric memory devices associated with medium cell sizes is approximately 90% of that of ferroelectric memory devices associated with large cell sizes.

[0086] Bar charts 1012a-1012b show the ratio of ferroelectric responses between ferroelectric memory devices of different sizes, the ferroelectric memory devices having an amorphous initial layer on the lower electrode, a ferroelectric switching layer on the amorphous initial layer, a second amorphous initial layer on the ferroelectric switching layer, a second ferroelectric switching layer on the second amorphous initial layer, and a third amorphous initial layer on the second ferroelectric switching layer (e.g., as shown in the figure). Figure 7(As shown). Bar 1012a illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with small cell sizes to those associated with large cell sizes. Bar 1012b illustrates the ratio of the ferroelectric response of ferroelectric memory devices associated with medium cell sizes to those associated with large cell sizes. As can be seen from bars 1012a-1012b, in some embodiments, the ferroelectric response of ferroelectric memory devices associated with small cell sizes is approximately 100% of that of ferroelectric memory devices associated with large cell sizes, while the response of ferroelectric memory devices associated with medium cell sizes is approximately 90% of that of ferroelectric memory devices associated with large cell sizes.

[0087] Therefore, as shown in bar chart 1000, the degradation of the memory window is reduced by one or more amorphous initial layers of the disclosed ferroelectric data storage structure as the size of the ferroelectric memory device decreases, thereby allowing for the miniaturization of the ferroelectric memory device while maintaining good performance.

[0088] It has been recognized that the disclosed amorphous initial layer is also configured to reduce the time-varying memory window of the ferroelectric data storage structure. For example, Figure 11A Figure 1100 illustrates some embodiments of the memory window (y-axis) of ferroelectric memory devices with different sizes over multiple read / write cycles (x-axis). The memory window shown in Figure 1100 is associated with ferroelectric memory devices that do not have the disclosed amorphous initial layer.

[0089] As shown in graph 1100, the memory windows of ferroelectric memory devices associated with a first cell size (line 1102), ferroelectric memory devices associated with a second cell size smaller than the first cell size (line 1104), and ferroelectric memory devices associated with a third cell size smaller than the second cell size (line 1106) are illustrated. Due to defect redistribution, the memory window of a ferroelectric memory device typically increases over time. However, as the size of the ferroelectric memory device decreases, the memory window variation increases within a first range 1108. As the first range increases, controlling the reliability of the ferroelectric memory device becomes more difficult.

[0090] Figure 11B Figure 1110 illustrates some embodiments of the memory window (y-axis) of a ferroelectric memory device over multiple read / write cycles (x-axis) of ferroelectric memory devices with different sizes. The memory window shown in Figure 1110 is associated with a ferroelectric memory device having the disclosed amorphous initial layer.

[0091] As shown in graph 1110, the memory windows of ferroelectric memory devices associated with a first cell size (line 1112), ferroelectric memory devices associated with a second cell size smaller than the first cell size (line 1114), and ferroelectric memory devices associated with a third cell size smaller than the second cell size (line 1116) are illustrated. Due to defect redistribution, the memory window of the ferroelectric memory device typically increases over time. However, as the size of the ferroelectric memory device decreases, the memory window changes within a range smaller than the first range (line 1112). Figure 11A The second range 1118 of (1108) has been increased. Small changes in the memory window for different sized devices improve the reliability of the memory devices.

[0092] Figure 12 An exemplary schematic diagram of a ferroelectric memory circuit 1200 having ferroelectric memory devices, each including an amorphous initial layer, is shown.

[0093] Ferroelectric memory circuit 1200 includes ferroelectric memory array 1202, which includes multiple ferroelectric memory cells 1204. 1,1 -1204 n,m Multiple ferroelectric memory cells 1204 1,1 -1204 n,m Arranged in rows and / or columns within the ferroelectric memory array 1202. Multiple ferroelectric memory cells 1204 within a row. 1,x -1204 n,x Operable grounding to word line WL x (x = 1 - m). Multiple ferroelectric devices 1204 in the column. x,1 -1204 x,m Operable ground coupling to bit line BL x (x = 1 - n) and source line SL x (x = 1 - n). In some embodiments, a plurality of ferroelectric memory cells 1204 1,1 -1204 n,m Each can have a cell size (e.g., width) of less than about 135 nm. At this cell size, the disclosed amorphous initial layer is configured to significantly mitigate the performance degradation effect caused by the shrinkage of memory cells.

[0094] Word line WL l -WL m Bitline BL l -BL n and source polar line SL l -SL n Coupled to control circuit 1206. In some embodiments, control circuit 1206 includes components coupled to word lines WL1-WL mThe word line decoder 1210 is coupled to the bit lines BL1-BL1. n The bit line decoder 1208, and the source lines SL1-SL n The source-line decoder 1212. In some embodiments, the control circuit 1206 further includes a source-line decoder coupled to bit lines BL1-BL2. n or source line SL1-SL n The sensing amplifier 1214. In some embodiments, the control circuit 1206 further includes a control unit 1216, which is configured to transmit address information S ADR The signal is sent to word line decoder 1210, bit line decoder 1208, and / or source line decoder 1212 to enable control circuitry 1206 for selective access to multiple ferroelectric memory cells 1204. 1,1 -1204 n,m One or more of them.

[0095] For example, during operation, the control unit 1216 is configured to transfer address information S ADR Provided to word line decoder 1210, bit line decoder 1208, and source line decoder 1212. Based on address information S ADR The word line decoder 1210 is configured to selectively decode word lines WL1-WL m A bias voltage is applied to one of the bit lines BL1-BL2. Simultaneously, the bit line decoder 1208 is configured to selectively apply a bias voltage to the bit lines BL1-BL2. n One of them applies a bias voltage and / or the source line decoder 1212 is configured to selectively apply a bias voltage to the source lines SL1-SL1. n Apply a bias voltage to one of the word lines WL1-WL. m Bit line BL1-BL n and / or source lines SL1-SL n By applying a bias voltage to one of the selected ferroelectric memory cells 1204, the ferroelectric memory circuit 1200 can be operated to write different data states into multiple ferroelectric memory cells 1204. 1，1 -1204 n，m And / or from multiple ferroelectric memory cells 1204 1,1 -1204 n,m Read data status.

[0096] Figures 13 to 22 Cross-sectional views 1300 to 2200 illustrate some embodiments of a method for forming an integrated chip having a ferroelectric data storage structure including an amorphous initial layer. Although Figures 13 to 22 It describes the method, but it should be understood that... Figures 13 to 22 The structures disclosed herein are not limited to this method, but can exist independently of this method.

[0097] like Figure 13 As shown in cross-sectional view 1300, a substrate 102 is provided. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, and any other type of associated semiconductor and / or epitaxial layer. In some embodiments, the substrate 102 may include a memory region 302 and a logic region 304. In some embodiments, an access device 202 is formed on and / or within the substrate 102 within the memory region 302. In some embodiments, a logic device 307 is formed on and / or within the substrate 102 within the logic region 304. In some embodiments, the access device 202 and / or the logic device 307 may include transistors. In some such embodiments, the access device 202 and / or the logic device 307 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric (e.g., 202c) and a gate electrode (e.g., 202a). Substrate 102 may then be implanted to form source / drain regions (e.g., 202b) on opposite sides of the gate electrode (e.g., 202a). In some embodiments, one or more isolation structures 303 may be formed within substrate 102 along opposite sides of access device 202 and / or logic device 307.

[0098] like Figure 14 As shown in cross-sectional view 1400, one or more lower ILD layers 106L are formed over substrate 102. In some embodiments, one or more lower interconnects 204 are formed within one or more lower ILD layers 106L in memory region 302, and one or more additional lower interconnects 308 are formed within one or more lower ILD layers 106L in logic region 304. In some embodiments, one or more lower interconnects 204 and / or one or more additional lower interconnects 308 may include conductive contacts, interconnects, and / or interconnect vias. In some embodiments, one or more lower ILD layers 106L may include one or more stacked interlayer dielectric (ILD) layers. One or more lower interconnects 204 and / or one or more additional lower interconnects 308 can be formed by: forming a lower ILD layer (e.g., oxide, low-k dielectric, or ultra-low-k dielectric) over the substrate 102, selectively etching the lower ILD layer to form vias and / or trenches within the lower ILD layer, forming conductive material (e.g., copper, aluminum, etc.) within the dielectric and / or trenches, and performing a planarization process (e.g., chemical mechanical planarization) to remove excess conductive material from over the lower ILD layer.

[0099] like Figure 15As shown in cross-sectional view 1500, a lower insulating structure 310 is formed over one or more lower interconnects 204 and / or one or more lower ILD layers 106L. In some embodiments, the lower insulating structure 310 comprises one or more of silicon-rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, the lower insulating structure 310 can be formed by one or more deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), etc.).

[0100] In some embodiments, the lower insulating structure 310 may be selectively etched to form an opening 1502 extending through the lower insulating structure 310 to expose the upper surface of one or more lower interconnects 204. In some embodiments, the opening 1502 may then be filled with a conductive material to form a lower electrode via 306 extending through the lower insulating structure 310. In some embodiments, the lower electrode via 306 may include a metal, a metal nitride, and / or the like. For example, the lower electrode via 306 may include tungsten, tantalum nitride, titanium nitride, ruthenium, platinum, iridium, or the like. In some embodiments, the conductive material may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, or the like).

[0101] In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP) process) may be performed to remove excess conductive material from above the lower insulating structure 310.

[0102] like Figure 16 As shown in cross-sectional view 1600, a diffusion barrier layer 1602 is formed over the lower insulating structure 310. In some embodiments, the diffusion barrier layer 1602 may include a metal nitride, such as titanium nitride, tantalum nitride, or the like. A lower electrode layer 1604 is formed over the diffusion barrier layer 1602. In some embodiments, the lower electrode layer 1604 may include tungsten, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, platinum, iridium, or the like. In some embodiments, the diffusion barrier layer 1602 and the lower electrode layer 1604 may be formed by a deposition process (e.g., PVD process, CVD process, PE-CVD process, etc.). In other embodiments (not shown), an opening (e.g., Figure 15 Before depositing conductive material in the lower electrode via 306 to form the lower electrode via 1502), a diffusion barrier layer 1602 is formed in the opening in the lower insulating structure 310.

[0103] An unpatterned amorphous initial layer 1606 is formed above the lower electrode layer 1604. In various embodiments, the unpatterned amorphous initial layer 1606 may comprise zirconium oxide (e.g., ZrO). x ), hafnium oxide (e.g., HfO) x), silicon dioxide (e.g., SiO2) x ), tantalum oxide (e.g., TaO) x ), aluminum oxide (e.g., AlO) x ), titanium dioxide (e.g., TiO2) x ), Yttrium oxide (e.g., YO) x ), gadolinium oxide (e.g., GdO) x ), lanthanum oxide (e.g., LaO) x ), Strontium oxide (e.g., SrO), x (and / or similar). In some embodiments, the unpatterned amorphous initial layer 1606 may be formed by an atomic layer deposition (ALD) process. In other embodiments, the unpatterned amorphous initial layer 1606 may be formed by a high-temperature oxidation process in a furnace. In some embodiments, the unpatterned amorphous initial layer 1606 may be formed having an amorphous phase.

[0104] In some embodiments, the unpatterned amorphous initial layer 1606 may include and / or be a material having a relatively high crystallization temperature. The relatively high crystallization temperature allows the unpatterned amorphous initial layer 1606 to remain amorphous during subsequent high-temperature processes. By allowing the unpatterned amorphous initial layer 1606 to remain amorphous during high-temperature processes, the unpatterned amorphous initial layer 1606 can influence the subsequently formed intermediate ferroelectric material layer (e.g., Figure 17 Phase 1702). In some embodiments, the unpatterned amorphous initial layer 1606 may include a first material having a higher elevation than the subsequently formed intermediate ferroelectric material layer (e.g., 1702). Figure 17 The first crystallization temperature of the second crystallization temperature of the second material (1702) is such that the amorphous initial layer 110 remains amorphous even when the subsequently formed intermediate ferroelectric material layer becomes a crystalline phase (e.g., an orthorhombic phase). In some embodiments, the unpatterned amorphous initial layer 1606 may include and / or a material having a crystallization temperature greater than about 400°C, greater than about 500°C, greater than about 750°C, or other similar values.

[0105] like Figure 17 As shown in cross-sectional view 1700, an intermediate ferroelectric material layer 1702 is formed on an unpatterned amorphous initial layer 1606. In some embodiments, the intermediate ferroelectric material layer 1702 may be formed having a substantially uniform amorphous phase. In some embodiments, the intermediate ferroelectric material layer 1702 may include hafnium oxide, hafnium zirconium oxide (HZO), lead zirconate titanate (PZT), or the like. In some embodiments, the intermediate ferroelectric material layer 1702 may be formed by an atomic layer deposition (ALD) process. In other embodiments, the intermediate ferroelectric material layer 1702 may be formed by a PVD process, a CVD process, a PE-CVD process, or the like.

[0106] In some additional embodiments, one or more additional unpatterned amorphous initial layers and / or one or more intermediate ferroelectric material layers may be formed above the lower electrode layer 1604. One or more additional unpatterned amorphous initial layers and / or one or more intermediate ferroelectric material layers may correspond to... Figures 5 to 8 The embodiments shown. For example, in some embodiments, a second unpatterned amorphous initial layer (e.g., corresponding to) can be formed on the intermediate ferroelectric material layer. Figure 5 The second amorphous initial layer 502). In some other embodiments, the second intermediate ferroelectric material layer (e.g., corresponding to the second amorphous initial layer 502). Figure 6 The second ferroelectric switching layer 602 can be formed on the second amorphous initial layer. In another embodiment, a third amorphous initial layer (e.g., corresponding to the second intermediate ferroelectric material layer) can be formed on the second intermediate ferroelectric material layer. Figure 7 The third amorphous initial layer 702).

[0107] like Figure 18 As shown in the cross-sectional diagram 1800, an intermediate ferroelectric material layer can be deposited ( Figure 17 After annealing (1702), annealing process 1802 is performed. Annealing process 1802 changes the intermediate ferroelectric material layer ( Figure 17 The phase of (1702) is used to form the ferroelectric material layer 1804. For example, the annealing process 1802 can change the amorphous phase of the intermediate ferroelectric material layer to a substantially uniform orthorhombic phase in the ferroelectric material layer 1804, such that the ferroelectric material layer 1804 has a significantly orthorhombic phase. In some embodiments, the annealing process 1802 can be performed at temperatures between about 200°C and about 700°C, between about 200°C and about 500°C, between about 250°C and about 400°C, between about 300°C and about 400°C, or other similar values.

[0108] like Figure 19 As shown in cross-sectional view 1900, an upper electrode layer 1902 is formed over a ferroelectric material layer 1804. The upper electrode layer 1902 may include a metal, a metal nitride, or the like. In some embodiments, the upper electrode layer 1902 may include tungsten, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, platinum, iridium, or the like. In some embodiments, the upper electrode layer 1902 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, or the like). In some alternative embodiments, an annealing process may be performed after depositing the upper electrode layer 1902.

[0109] like Figure 20 As shown in the cross-sectional diagram 2000, in the upper electrode layer ( Figure 19 1902), ferroelectric material layer ( Figure 19 1804), unpatterned amorphous initial layer ( Figure 19 1606), lower electrode layer ( Figure 19 1604) and diffusion barrier layer ( Figure 19 One or more patterning processes 2002 are performed on the upper electrode (1602) to form a ferroelectric memory device 104 having a ferroelectric switching layer 112 and an amorphous initial layer 110 disposed between the lower electrode 108 and the upper electrode 114. One or more patterning processes 2002 remove portions of the upper electrode layer (1602). Figure 19 (1902) to form the upper electrode 114, removing part of the ferroelectric material layer ( Figure 19 (1804) to form ferroelectric switching layer 112, removing part of the unpatterned amorphous initial layer ( Figure 19 (1606) to form an amorphous initial layer 110, removing part of the lower electrode layer ( Figure 19 (1604) to form the lower electrode 108, and remove part of the diffusion barrier layer ( Figure 19 1602) to form a diffusion barrier layer 206.

[0110] In some embodiments, one or more patterning processes 2002 may include a patterning process configured to pattern the upper electrode layer (based on a mask layer) Figure 19 The mask layer 2004 (1902) is selectively exposed to the etchant. In various embodiments, the mask layer 2004 may include a metal (e.g., titanium, titanium nitride, tantalum, or the like), a dielectric material (e.g., silicon nitride, silicon carbide, or the like), a photosensitive material (e.g., photoresist), or the like. In some additional embodiments, one or more patterning processes 2002 may include a first patterning process configured to pattern the upper electrode layer (1902) according to the mask layer. Figure 19 The ferroelectric material layer (1902) is selectively exposed to the first etchant to form the upper electrode 114. In some embodiments, after the first patterning process is completed, one or more sidewall spacers may be formed along the opposite sides of the upper electrode 114 and the mask layer. In some embodiments, one or more patterning processes 2002 may further include a second patterning process performed after the formation of one or more sidewall spacers. The second patterning process is configured to selectively expose the ferroelectric material layer (1902) to the first etchant to form the upper electrode 114. Figure 19 1804), amorphous initial layer ( Figure 19 1606) and the lower electrode layer ( Figure 19 1604) and diffusion barrier layer ( Figure 19 The 1602) is exposed to a second etchant in the area not covered by the mask layer and one or more sidewall spacers.

[0111] like Figure 21As shown in cross-sectional view 2100, an upper ILD layer 106U is formed over the ferroelectric memory device 104. In some embodiments, the upper ILD layer 106U can be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the upper ILD layer 106U may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), silicon phosphosilicate glass (PSG), borosilicate phosphorus (BPSG), fluorosilicone glass (FSG), undoped silicate glass (USG), porous dielectric material, or the like.

[0112] like Figure 22 As shown in cross-sectional view 2200, an upper interconnect 116 is formed on the upper electrode 114. The upper interconnect 116 extends through the upper ILD layer 106U to the upper electrode 114. In some embodiments, the upper interconnect 116 can be formed by selectively etching the upper ILD layer 106U to form an opening extending from the top surface of the upper ILD layer 106U to expose the upper surface of the upper electrode 114. In some embodiments, the opening can be formed by a third patterning process using a third etchant to selectively etch the upper ILD layer 106U according to a mask layer (e.g., photoresist). A conductive material (e.g., copper, aluminum, etc.) is formed within the opening. In some embodiments, after forming the conductive material within the opening, a planarization process (e.g., CMP process) is performed to remove excess conductive material from above the top of the upper ILD layer 106U. In some embodiments, interconnect vias 312 can also be formed within logic regions 304. Interconnect vias 312 are formed to extend from the top surface of the upper ILD layer 106U to one or more additional lower interconnects 308.

[0113] Figures 23 to 32 Cross-sectional views 2300-3200 illustrate some alternative embodiments of a method for forming an integrated chip having a ferroelectric data storage structure including an amorphous initial layer. Although regarding... Figures 23 to 32 The method has been described, but it should be understood that... Figures 23 to 32 The structure disclosed in the method may not be limited to this method, but may exist independently of this method.

[0114] like Figure 23 As shown in cross-sectional view 2300, a substrate 102 is provided. In some embodiments, the substrate 102 may include a memory region 302 and a logic region 304. In some embodiments, an access device 202 is formed on and / or within the substrate 102 within the memory region 302. In some other embodiments, a logic device 307 is formed on and / or within the substrate 102 within the logic region 304. In some embodiments, the access device 202 and / or the logic device 307 may be as described regarding... Figure 13 It forms as described.

[0115] like Figure 24 As shown in cross-sectional view 2400, one or more lower ILD layers 106L are formed over substrate 102. In some embodiments, one or more lower interconnects 204 are formed within one or more lower ILD layers 106L within memory region 302, and one or more additional lower interconnects 308 are formed within one or more lower ILD layers 106L within logic region 304. In some embodiments, one or more lower interconnects 204 and / or one or more additional lower interconnects 308 may be as described regarding Figure 14 It forms as described.

[0116] like Figure 25 As shown in cross-sectional view 2500, a lower insulating structure 310 is formed over one or more lower ILD layers 106L and / or one or more lower interconnects 204. In some embodiments, the lower insulating structure 310 may be selectively etched to form one or more sidewalls 310s of the lower insulating structure 310, the sidewalls 310s defining openings 2502 extending through the lower insulating structure 310 to expose the upper surfaces of one or more lower interconnects 204.

[0117] like Figure 26 As shown in cross-sectional view 2600, a diffusion barrier layer 2602 is formed above the lower insulating structure 310. The diffusion barrier layer 2602 extends from above the lower insulating structure 310 into the opening 2502 and along one or more sidewalls 310s of the lower insulating structure 310. The diffusion barrier layer 2602 is formed with angled inner sidewalls that define a first groove within the upper surface of the diffusion barrier layer 2602. A lower electrode layer 2604 is formed above the diffusion barrier layer 2602. The lower electrode layer 2604 extends from above the diffusion barrier layer 2602 into the opening 2502 and along the angled inner sidewalls of the diffusion barrier layer 2602. The lower electrode layer 2604 is formed with angled inner sidewalls that define a second groove within the upper surface of the lower electrode layer 2604. An unpatterned amorphous initial layer 2606 is formed above the lower electrode layer 2604. An unpatterned amorphous initial layer 2606 extends from above the lower electrode layer 2604 into the opening 2502 and along the angled inner sidewall of the lower electrode layer 2604. The unpatterned amorphous initial layer 2606 is formed with angled inner sidewalls that define a third groove within the upper surface of the unpatterned amorphous initial layer 2606.

[0118] like Figure 27As shown in cross-sectional view 2700, an intermediate ferroelectric material layer 2702 is formed over an unpatterned amorphous initial layer 2606. In some embodiments, the intermediate ferroelectric material layer 2702 may be formed having a substantially uniform amorphous phase. The intermediate ferroelectric material layer 2702 extends over the unpatterned amorphous initial layer 2606 into the opening 2502 and along the angled inner sidewalls of the unpatterned amorphous initial layer 2606. The intermediate ferroelectric material layer 2702 is formed with angled inner sidewalls that define a fourth groove within the upper surface of the intermediate ferroelectric material layer 2702.

[0119] like Figure 28 As shown in cross-sectional diagram 2800, an intermediate ferroelectric material layer can be deposited ( Figure 27 After annealing process 2802, the intermediate ferroelectric material layer (2702) is then subjected to annealing process 2802. Annealing process 2802 changes the intermediate ferroelectric material layer ( Figure 27 The phase of the ferroelectric material layer 2702). For example, annealing process 2802 can change the amorphous phase of the intermediate ferroelectric material layer into a ferroelectric material layer 2804 having a substantially uniform orthorhombic crystalline phase. In some embodiments, annealing process 2802 can be performed at temperatures within the range of about 200°C and about 700°C, about 200°C and about 500°C, about 250°C and about 400°C, about 300°C and about 400°C, or other similar values.

[0120] like Figure 29 As shown in cross-sectional view 2900, an upper electrode layer 2902 is formed above the ferroelectric material layer 2804. The upper electrode layer 2902 extends from above the ferroelectric material layer 2804 into the fourth groove and along the inner sidewall of the ferroelectric material layer 2804.

[0121] like Figure 30 As shown in the cross-sectional view 3000, in the upper electrode layer ( Figure 29 2902), ferroelectric material layer ( Figure 29 2804), unpatterned amorphous initial layer ( Figure 29 2606), lower electrode layer ( Figure 29 2604) and diffusion barrier layer ( Figure 29 One or more patterning processes 3004 are performed on the mask layer 3002. The one or more patterning processes 3004 form a ferroelectric memory device 104, the ferroelectric memory device 104 having a ferroelectric switching layer 112 and an amorphous initial layer 110 disposed between a lower electrode 108 and an upper electrode 114. The one or more patterning processes 3004 remove a portion of the upper electrode layer (…). Figure 29 (2902) to form the upper electrode 114, removing part of the ferroelectric material layer ( Figure 29 (2804) to form ferroelectric switching layer 112, removing part of the unpatterned amorphous initial layer ( Figure 29(2606) to form an amorphous initial layer 110, removing part of the lower electrode layer ( Figure 29 2604) to form the lower electrode 108, and remove part of the diffusion barrier layer ( Figure 29 2602) to form a diffusion barrier layer 206.

[0122] like Figure 31 As shown in cross-sectional view 3100, an upper ILD layer 106U is formed above the ferroelectric memory device 104. In some embodiments, the upper ILD layer 106U can be as described regarding... Figure 21 It forms as described.

[0123] like Figure 32 As shown in cross-sectional view 3200, an upper interconnect 116 is formed on the upper electrode 114. The upper interconnect 116 extends through the upper ILD layer 106U to the upper electrode 114. In some embodiments, the upper interconnect 116 may be as described regarding Figure 22 As described. In some embodiments, interconnect vias 312 may also be formed within logic region 304 to extend through upper ILD layer 106U to one or more additional lower interconnects 308.

[0124] Figure 33 The illustration shows flowcharts of some embodiments of a method 3300 for forming an integrated chip having a ferroelectric data storage structure including an amorphous initial layer.

[0125] Although the methods are illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those illustrated and / or described herein. Furthermore, not all illustrated actions may be required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and / or phases.

[0126] At action 3302, access devices may be formed on and / or within the substrate. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of action 3302 is shown. Figure 23 A cross-sectional view 2300 corresponding to an alternative embodiment of action 3302 is shown.

[0127] At action 3304, one or more lower interconnects are formed within one or more inter-layer dielectric (ILD) layers above the substrate. Figure 14 A cross-sectional view 1400 is shown corresponding to some embodiments of action 3304. Figure 24 A cross-sectional view 2400 corresponding to an alternative embodiment of action 3304 is shown.

[0128] At action 3306, a lower insulation structure is formed over one or more lower ILD layers and one or more lower interconnects. Figure 15 A cross-sectional view 1500 corresponding to some embodiments of action 3306 is shown. Figure 25 A cross-sectional view 2500 corresponding to an alternative embodiment of action 3306 is shown.

[0129] At action 3308, a diffusion barrier layer is formed on the lower insulation layer and / or within an opening extending through the lower insulation structure to one or more lower interconnects. Figure 16 A cross-sectional view 1600 corresponding to some embodiments of action 3308 is shown. Figure 26 A cross-sectional view 2600 corresponding to an alternative embodiment of action 3308 is shown.

[0130] At action 3310, a lower electrode layer is formed on the diffusion barrier layer. Figure 16 A cross-sectional view 1600 is shown corresponding to some embodiments of action 3310. Figure 26 A cross-sectional view 2600 corresponding to an alternative embodiment of action 3310 is shown.

[0131] At action 3312, an unpatterned amorphous initial layer is formed on the lower electrode layer. Figure 16 A cross-sectional view 1600 corresponding to some embodiments of action 3312 is shown. Figure 26 A cross-sectional view 2600 corresponding to an alternative embodiment of action 3312 is shown.

[0132] At action 3314, an intermediate ferroelectric switch layer with a substantially uniform amorphous phase is formed on the unpatterned amorphous initial layer. Figure 17 A cross-sectional view 1700 is shown, corresponding to some embodiments of action 3314. Figure 27 A cross-sectional view 2700 corresponding to an alternative embodiment of action 3314 is shown.

[0133] At action 3316, an annealing process is performed to change the intermediate ferroelectric switch layer with a substantially uniform amorphous phase into a ferroelectric switch layer with a substantially uniform orthorhombic phase. Figure 18 A cross-sectional view 1800 is shown corresponding to some embodiments of action 3316. Figure 28 A cross-sectional view 2800 corresponding to an alternative embodiment of action 3316 is shown.

[0134] At action 3318, an upper electrode layer is formed on the ferroelectric switch layer. Figure 19 A cross-sectional view 1900 is shown, corresponding to some embodiments of action 3318. Figure 29 A cross-sectional view 2900 corresponding to an alternative embodiment of action 3318 is shown.

[0135] At action 3320, one or more patterning processes are performed to form a ferroelectric memory device. Figure 20 A cross-sectional view 2000 corresponding to some embodiments of action 3320 is shown. Figure 30 A cross-sectional view 3000 corresponding to an alternative embodiment of action 3320 is shown.

[0136] At action 3322, an upper ILD layer is formed above the ferroelectric memory device. Figure 21 A cross-sectional view 2100 is shown corresponding to some embodiments of action 3322. Figure 31 A cross-sectional view 3100 corresponding to an alternative embodiment of action 3322 is shown.

[0137] At action 3324, an upper interconnect is formed to extend through the upper ILD layer to the upper electrode of the ferroelectric memory device. Figure 22 A cross-sectional view 2200 is shown, corresponding to some embodiments of action 3324. Figure 32 A cross-sectional view 3200 corresponding to an alternative embodiment of action 3324 is shown.

[0138] Therefore, in some embodiments, this disclosure relates to an integrated chip having a ferroelectric memory device, the ferroelectric memory device including a ferroelectric data storage structure having an amorphous initial layer configured such that an overlying ferroelectric switching layer is formed having a substantially uniform orthorhombic crystalline phase. The substantially uniform orthorhombic crystalline phase improves the ferroelectric response of the ferroelectric switching layer, thereby improving the performance of the ferroelectric memory device.

[0139] In some embodiments, this disclosure relates to a method of forming an integrated chip. The method includes: forming a lower electrode layer over a substrate; forming an unpatterned amorphous initial layer over the lower electrode layer; forming an intermediate ferroelectric material layer on the unpatterned amorphous initial layer, wherein the intermediate ferroelectric material layer is formed having a substantially uniform amorphous phase; performing an annealing process configured to transform the intermediate ferroelectric material layer into a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase; forming an upper electrode layer over the ferroelectric material layer; performing one or more patterning processes on the upper electrode layer, the ferroelectric material layer, the unpatterned amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device; forming an interlayer dielectric (ILD) layer over the ferroelectric memory device; and forming an upper interconnect extending through the upper ILD layer to contact the ferroelectric memory device. In some embodiments, the method further includes forming the upper electrode layer after performing the annealing process. In some embodiments, the annealing process is performed at a temperature in the range of about 250 degrees Celsius (°C) and about 400 degrees Celsius. In some embodiments, the unpatterned amorphous initial layer comprises an oxide or a nitride. In some embodiments, the method further includes: forming a second unpatterned amorphous initial layer on an intermediate ferroelectric material layer; and patterning the second unpatterned amorphous initial layer to form a ferroelectric memory device. In some embodiments, the second unpatterned amorphous initial layer is made of the same material as the unpatterned amorphous initial layer. In some embodiments, the second unpatterned amorphous initial layer is made of a different material than the unpatterned amorphous initial layer. In some embodiments, the method further includes: forming a second intermediate ferroelectric material layer on the second unpatterned amorphous initial layer; and patterning the second intermediate ferroelectric material layer to form a ferroelectric memory device. In some embodiments, the method further includes: forming a third unpatterned amorphous initial layer on the second intermediate ferroelectric material layer; and patterning the third unpatterned amorphous initial layer to form a ferroelectric memory device.

[0140] In other embodiments, this disclosure relates to a method of forming an integrated chip. The method includes: forming one or more lower interconnects within one or more lower interlayer dielectric (ILD) layers above a substrate; forming a lower insulating structure above the one or more lower ILD layers, wherein the lower insulating structure has sidewalls defining openings extending through the lower insulating structure; forming a lower electrode layer above the lower insulating structure; forming an unpatterned amorphous initial layer above the lower electrode layer, wherein the unpatterned amorphous initial layer has an amorphous phase; and forming an intermediate ferroelectric material layer in contact with an upper surface of the unpatterned amorphous initial layer, wherein the unpatterned amorphous initial layer is configured to... The formed intermediate ferroelectric material layer has a substantially amorphous phase between its outermost outermost walls; an annealing process is performed, configured to transform the intermediate ferroelectric material layer from an amorphous phase to a ferroelectric material layer having a crystalline phase; an upper electrode layer is formed over the ferroelectric material layer; one or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the unpatterned amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device; an upper interlayer dielectric (ILD) layer is formed over a lower insulating structure; and an upper interconnect extending through the upper ILD layer to contact the ferroelectric memory device is formed. In some embodiments, the crystalline phase is an orthorhombic phase. In some embodiments, the unpatterned amorphous initial layer comprises a first material having a first crystallization temperature, and the intermediate ferroelectric material layer comprises a second material having a second crystallization temperature lower than the first crystallization temperature. In some embodiments, the method further includes forming a lower electrode layer, an unpatterned amorphous initial layer, and an intermediate ferroelectric material layer along the sidewalls of the lower insulating structure. In some embodiments, the unpatterned amorphous initial layer comprises silicon oxide, tantalum oxide, aluminum oxide, yttrium oxide, gadolinium oxide, lanthanum oxide, or strontium oxide. In some embodiments, the unpatterned amorphous initial layer comprises silicon nitride, tantalum nitride, or aluminum nitride. In some embodiments, the unpatterned amorphous initial layer extends continuously from the lower surface of the contact lower electrode layer to the upper surface of the contact intermediate ferroelectric material layer. In some embodiments, the unpatterned amorphous initial layer is formed to a thickness of less than or equal to about 30 angstroms.

[0141] In other embodiments, this disclosure relates to an integrated chip. The integrated chip includes: a lower electrode including a first metal disposed above a substrate; an upper electrode including a second metal disposed above the lower electrode; and a ferroelectric data storage structure disposed between the lower and upper electrodes, wherein the ferroelectric data storage structure includes a ferroelectric switching layer and an amorphous initial layer separating the ferroelectric switching layer from the lower electrode; wherein the amorphous initial layer has a structure configured to influence a crystalline phase of the ferroelectric switching layer; and wherein the ferroelectric switching layer includes a substantially uniform orthorhombic crystalline phase extending between the outermost surfaces of the ferroelectric switching layer. In some embodiments, the integrated chip further includes: one or more lower interconnects disposed within one or more lower interlayer dielectric (ILD) layers above the substrate; and a lower insulating structure disposed above the one or more lower ILD layers, wherein the lower insulating structure includes one or more sidewalls defining openings extending through the lower insulating structure; wherein the amorphous initial layer is directly disposed between the one or more sidewalls of the lower insulating structure. In some embodiments, the ferroelectric data storage structure includes a second amorphous initial layer separated from the amorphous initial layer by the ferroelectric switching layer.

[0142] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A method for forming an integrated chip, comprising: A lower electrode layer comprising a first metal, namely ruthenium, is formed above the substrate; An unpatterned amorphous initial layer is formed above the lower electrode layer; An intermediate ferroelectric material layer is formed on the unpatterned amorphous initial layer, wherein the intermediate ferroelectric material layer is formed having a substantially uniform amorphous phase; An annealing process is performed, the annealing process being configured to change the intermediate ferroelectric material layer into a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase; An upper electrode layer is formed above the ferroelectric material layer; One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the unpatterned amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device. The ferroelectric memory device has a first amorphous initial layer and a ferroelectric switching layer located between the lower electrode and the upper electrode. The first amorphous initial layer contacts the bottom of the ferroelectric switching layer, wherein a second amorphous initial layer contacts the top of the ferroelectric switching layer. The second amorphous initial layer is a different material from the first amorphous initial layer. The first amorphous initial layer includes tantalum nitride, and the second amorphous initial layer includes aluminum oxide. An interlayer dielectric layer is formed above the ferroelectric memory device; and An upper interconnect is formed that extends through the upper interlayer dielectric layer to contact the ferroelectric memory device.

2. The method according to claim 1, further comprising: The upper electrode layer is formed after the annealing process is performed.

3. The method according to claim 1, wherein, The annealing process is performed at a temperature between 250°C and 400°C.

4. The method according to claim 1, wherein, The unpatterned amorphous initial layer includes oxides or nitrides.

5. The method according to claim 1, further comprising: A second unpatterned amorphous initial layer is formed on the intermediate ferroelectric material layer; and The second unpatterned amorphous initial layer is patterned to form the ferroelectric memory device.

6. The method according to claim 1, wherein, The intermediate ferroelectric material layer includes hafnium oxide.

7. The method according to claim 1, wherein, The ferroelectric switch layer comprises a high-k dielectric material.

8. The method according to claim 5, further comprising: A second intermediate ferroelectric material layer is formed on the second unpatterned amorphous initial layer; and The second intermediate ferroelectric material layer is patterned to form the ferroelectric memory device.

9. The method according to claim 8, further comprising: A third unpatterned amorphous initial layer is formed on the second intermediate ferroelectric material layer; and The third unpatterned amorphous initial layer is patterned to form the ferroelectric memory device.

10. A method for forming an integrated chip, comprising: One or more lower interconnects are formed within one or more lower interlayer dielectric layers above the substrate; A lower insulating structure is formed above one or more lower interlayer dielectric layers, wherein the lower insulating structure has sidewalls defining an opening extending through the lower insulating structure; A lower electrode layer comprising a first metal, namely ruthenium, is formed above the lower insulating structure; An unpatterned first amorphous initial layer is formed above the lower electrode layer, wherein the unpatterned first amorphous initial layer has an amorphous phase and the unpatterned first amorphous initial layer includes tantalum nitride; An intermediate ferroelectric material layer is formed in contact with the upper surface of the unpatterned first amorphous initial layer, wherein the unpatterned first amorphous initial layer is configured such that the intermediate ferroelectric material layer to be formed has a substantially amorphous phase between the outermost walls of the intermediate ferroelectric material layer; An annealing process is performed, the annealing process being configured to transform the intermediate ferroelectric material layer from the amorphous phase into a ferroelectric material layer having a crystalline phase; A second amorphous initial layer is formed above the ferroelectric material layer, the second amorphous initial layer is in contact with the top of the ferroelectric material layer, and the second amorphous initial layer is a different material from the first amorphous initial layer, the second amorphous initial layer comprising aluminum oxide; An upper electrode layer is formed above the second amorphous initial layer; One or more patterning processes are performed on the upper electrode layer, the second amorphous initial layer, the ferroelectric material layer, the unpatterned first amorphous initial layer, and the lower electrode layer to form a ferroelectric memory device; An upper interlayer dielectric layer is formed above the lower insulating structure; and An upper interconnect is formed that extends through the upper interlayer dielectric layer to contact the ferroelectric memory device.

11. The method according to claim 10, wherein, The crystal phase is an orthorhombic crystal phase.

12. The method according to claim 10, wherein, The unpatterned first amorphous initial layer comprises a first material having a first crystallization temperature, and the intermediate ferroelectric material layer comprises a second material having a second crystallization temperature lower than the first crystallization temperature.

13. The method of claim 10, further comprising: The lower electrode layer, the unpatterned first amorphous initial layer, and the intermediate ferroelectric material layer are formed along the sidewall of the lower insulating structure.

14. The method of claim 10, wherein, The intermediate ferroelectric material layer includes hafnium oxide.

15. The method according to claim 10, wherein, The intermediate ferroelectric material layer is formed by atomic layer deposition.

16. The method of claim 10, wherein, The unpatterned first amorphous initial layer extends continuously from the lower surface of the contacting lower electrode layer to the upper surface of the contacting intermediate ferroelectric material layer.

17. The method according to claim 10, wherein, The unpatterned first amorphous initial layer is formed to a thickness of less than or equal to 30 angstroms.

18. An integrated chip, comprising: The lower electrode includes a first metal disposed above the substrate, wherein the first metal is ruthenium; The upper electrode includes a second metal disposed above the lower electrode; A ferroelectric data storage structure is disposed between a lower electrode and an upper electrode. The ferroelectric data storage structure includes a ferroelectric switching layer located between the upper electrode and the lower electrode, and a first amorphous initial layer separating the ferroelectric switching layer from the lower electrode. The first amorphous initial layer contacts the bottom of the ferroelectric switching layer. A second amorphous initial layer is located between the ferroelectric switching layer and the upper electrode, and contacts the top of the ferroelectric switching layer. The second amorphous initial layer is made of a different material than the first amorphous initial layer. The first amorphous initial layer includes tantalum nitride, and the second amorphous initial layer includes aluminum oxide. Wherein, the first amorphous initial layer has a structure configured to influence the crystalline phase of the ferroelectric switching layer; and The ferroelectric switch layer comprises a substantially uniform orthorhombic crystalline phase extending between the outermost surfaces of the ferroelectric switch layer.

19. The integrated chip according to claim 18, further comprising: One or more lower interconnects are disposed within one or more lower interlayer dielectric layers above the substrate; A lower insulating structure disposed above the one or more lower interlayer dielectric layers, wherein the lower insulating structure includes one or more sidewalls defining an opening extending through the lower insulating structure; and The first amorphous initial layer is directly disposed between the one or more sidewalls of the lower insulating structure.

20. The integrated chip according to claim 18, wherein, The ferroelectric switch layer comprises a high-k dielectric material.

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