integrated circuit

Abstract

The application discloses an integrated circuit, comprising: a plurality of function blocks, each of the plurality of function blocks comprising a hardware circuit, wherein the plurality of function blocks comprises: a first function block comprising: a first macro circuit located in a first sub-region of the first function block, wherein among a plurality of sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first function block; wherein a first intermediate sub-region of the first function block is located between the first side of the first sub-region and the boundary of the first function block, and there is no tapping unit in the first intermediate sub-region of the first function block. The application omits the tapping unit within the function block, and after the tapping unit within the function block is omitted, normal power supply to the macro circuit can be continued, meanwhile, the number of parts is reduced, the area of the integrated circuit is reduced, and therefore, the process is simplified and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an integrated circuit. Background Technology

[0002] According to existing technology, control circuits in electronic devices can be fabricated using integrated circuits (ICs). For example, design companies can design control circuits and other circuits according to certain design rules, while the manufacturing process can take place in one or more highly specialized semiconductor manufacturing plants, which can be called foundries or wafer fabs. In the mass production stage of integrated circuits, the number of dies obtainable from a wafer may depend on the die size, and the total cost may depend on the number of functional dies out of all dies obtained from the wafer. Although related technologies may have strived to improve yield, it seems that further cost reduction is impossible due to bottlenecks. Therefore, a novel approach and related architecture are needed to save the overall circuit area of ​​the IC without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0003] In view of this, the present invention provides an integrated circuit to solve the above problems.

[0004] According to a first aspect of the present invention, an integrated circuit is disclosed, comprising:

[0005] Multiple functional blocks, each of which includes hardware circuitry, wherein the multiple functional blocks include:

[0006] A first functional block includes: a first macro circuit located in a first sub-region of the first functional block, wherein among the plurality of sides of the first sub-region, the first side of the first sub-region is closest to the boundary of the first functional block;

[0007] The first intermediate sub-region of the first functional block is located between the first side of the first sub-region and the boundary of the first functional block, and there is no tapping unit in the first intermediate sub-region of the first functional block.

[0008] The integrated circuit of the present invention includes: a plurality of functional blocks, each of which includes hardware circuitry; wherein the plurality of functional blocks includes: a first functional block, comprising: a first macro circuit located within a first sub-region of the first functional block; wherein, among the plurality of sides of the first sub-region, a first side of the first sub-region is closest to the boundary of the first functional block; wherein a first intermediate sub-region of the first functional block is located between the first side of the first sub-region and the boundary of the first functional block, and no tapping unit is present in the first intermediate sub-region of the first functional block. The present invention omits tapping units within functional blocks. By omitting tapping units within functional blocks, normal power supply to the macro circuit can be maintained, while reducing components and the area of ​​the integrated circuit, thus simplifying the manufacturing process and reducing costs. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of an IC according to an embodiment of the present invention.

[0010] Figure 2 The right half of the diagram illustrates an embodiment of the IC (such as...) according to an invention. Figure 1 The diagram shows a compact layout control scheme for the IC method, for better understanding. Figure 2 The left half shows the non-compact layout control scheme.

[0011] Figure 3 The right half of the illustration shows an embodiment of the invention. Figure 2 The diagram illustrates some implementation details of the compact layout control scheme for better understanding. Figure 3 The left half shows some implementation details of the non-compact layout control scheme.

[0012] Figure 4 The right half of the illustration shows another embodiment of the invention. Figure 2 The diagram illustrates some implementation details of the compact layout control scheme for better understanding. Figure 4 The left half shows some implementation details of the non-compact layout control scheme.

[0013] Figure 5 The right half of the illustration shows an embodiment of the invention. Figure 2 The diagram illustrates some implementation details of the compact layout control scheme for better understanding. Figure 5 The right half shows some implementation details of the non-compact layout control scheme.

[0014] Figure 6 The right half of the illustration shows another embodiment of the invention. Figure 2The diagram illustrates some implementation details of the compact layout control scheme. For better understanding, Figure 6 The right half shows some implementation details of the non-compact layout control scheme.

[0015] Figure 7 This is a diagram illustrating an improvement achieved using a method according to an embodiment of the present invention. Detailed Implementation

[0016] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0017] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0019] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0020] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0021] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0022] Figure 1 This is a schematic diagram of IC 100 according to an embodiment of the present invention. IC 100 may include multiple functional blocks, such as functional blocks 110_1, 110_2, etc., and each of the multiple functional blocks may include hardware circuitry, such as multiple macro circuits. Examples of any macro circuitry among the multiple macro circuits may include, but are not limited to, static random access memory (SRAM), intellectual property (IP) modules, etc. For better understanding, IC 100 may represent circuitry controlling an electronic device, and more specifically, may represent processing circuitry including at least one processor / microprocessor, etc., but the present invention is not limited thereto.

[0023] like Figure 1As shown, in any one of the multiple functional blocks (e.g., each functional block), such as functional block 110_i in functional blocks 110_1, 110_2, etc. (e.g., the functional block index i can represent a positive integer), the distance DL1 between the first boundary line (e.g., the left boundary line) of any functional block and the macrocircuit adjacent to the first boundary line (e.g., the left boundary line) of any functional block is less than 4.488 micrometers (μm), and the distance DR1 between another boundary line (e.g., the right boundary line) (or second boundary line) of any functional block and the macrocircuit adjacent to the other boundary line (e.g., the right boundary line) (or second boundary line) of any functional block is less than 4.488 μm. A boundary can also be called an edge, and a boundary line can also be called an edge line. A boundary line can be simply referred to as a boundary.

[0024] based on Figure 1 The architecture shown allows for a compact layout of IC 100. Compared to existing technologies, IC 100 can operate correctly under various conditions, while its overall circuit area is further reduced. Consequently, the associated costs can be further reduced.

[0025] Figure 2 The right half of the illustration shows an embodiment of the invention for implementing, such as Figure 1 The diagram shown illustrates a compact layout control scheme for IC 100. For better understanding, Figure 2 The left half shows a non-compact layout control scheme (e.g.) Figure 2 The left half is the traditional approach). According to... Figure 2 In the IC implemented by the non-compact layout control scheme shown in the left half, each intermediate sub-region between the boundary of the functional block in the IC and the intermediate sub-region of the macro circuit in the functional block may include multiple tap cells (labeled "intermediate sub-region with tap cells" for simplicity), and more specifically, includes a first one-dimensional (1D) array of boundary cells located on one side of the multiple tap cells (such as the left side) (e.g., tap cells of the first one-dimensional array on the left side), and further includes a second one-dimensional array of boundary cells located on the other side of the multiple tap cells (such as the right side) (e.g., tap cells of the second one-dimensional array on the right side). Therefore, the distance DL0 between the left boundary line of the functional block (e.g., the left boundary line) and the macro circuit near the left boundary line is typically greater than or equal to 4.488 μm (denoted as "DL0≥4.488 μm" for simplicity), and the distance DR0 between the right boundary line of the functional block (e.g., the right boundary line) and the macro circuit near the right boundary line is typically greater than or equal to 4.488 μm (denoted as "DR0≥4.488 μm" for simplicity).

[0026] According to such Figure 2 In the IC 100 implemented with a compact layout control scheme shown in the right half, each intermediate sub-region between the boundary of the first functional block 110 (labeled "functional block" for simplicity) and the macro circuitry within functional block 110 does not include any tap units (labeled "intermediate sub-region without any tap units" for simplicity). The first functional block 110 can represent any one of the multiple functional blocks, such as functional block 110_i among functional blocks 110_1, 110_2, etc. The first functional block 110 may include a first group of macrocircuits ML(1), ML(2), ..., and ML(N) near a first boundary line (e.g., the left boundary line) of the first functional block 110, and the first functional block 110 may further include a second group of macrocircuits MR(1), MR(2), ..., and MR(M) near another boundary line (e.g., the right boundary line, also referred to as the second boundary line) of the first functional block 110. The number of macrocircuits N in the first group of macrocircuits ML(1), ML(2), ..., and ML(N) and the number of macrocircuits M in the second group of macrocircuits MR(1), MR(2), ..., and MR(M) can be any positive integer greater than 2, more specifically, it can be a positive integer much greater than 2, but the invention is not limited thereto. For example, the first functional block 110 may further include one or more groups of macrocircuits, such as other groups of macrocircuits located between the first group of macrocircuits ML(1), ML(2), ..., and ML(N) and the second group of macrocircuits MR(1), MR(2), ..., and MR(M). The intermediate sub-region is located in the space between the boundary line of the functional block and one side or side of the macro circuit closest to that boundary line, for example... Figure 2 The region on the right half that is between DL1 and DR1. For example... Figure 2 In the right half, three intermediate sub-regions are shown on the left side of the function block, and three intermediate sub-regions are shown on the right side of the function block.

[0027] Taking the nth macro circuit in the first group of macro circuits ML(1), ML(2), ..., ML(N) as an example, the first functional block 110 may include the first macro circuit ML(n), which is located in the first sub-region of the first functional block 110, where the macro circuit index n can be a positive integer falling within the interval [1, N]. Among the multiple edges or sides of the first sub-region, for example, among the four edges of the sub-region where the first macro circuit ML(n) is located, the first edge or side (e.g., the left side) of the first sub-region is closest to the boundary of the first functional block 110. In addition, the first intermediate sub-region of the first functional block 110 is located between the first side (e.g., the left side) of the first sub-region (e.g., the sub-region where the first macro circuit ML(n) is located) and the boundary of the first functional block 110 (e.g., the left boundary of the first functional block 110, or referred to as the first boundary line), and there is no tap unit in the first intermediate sub-region of the first functional block 110. Therefore, the distance between the first edge (or first side) of the first sub-region and the boundary of the first functional block 110, for example, the distance DL1 between the first macro circuit ML(n) and the first boundary line (e.g., the left boundary line) of the first functional block 110, is less than 4.488 μm (for simplicity, it is labeled "DL1<4.488 μm"). The first sub-region may be the region where the first macro circuit ML(n) is located. In this embodiment of the invention, the first group of macro circuits has multiple macro circuits, so it may also have a second sub-region. For example, the second sub-region may be the region where the second macro circuit ML(n-1), ML(n-2), or ML(n+1) is located. Of course, other sub-regions may also exist, which will not be listed here for the sake of brevity; in one embodiment, the second intermediate sub-region of the first functional block 110 is located between the first side (e.g., the left side) of the second sub-region (e.g., the sub-region where the first macro circuit ML(n-1) is located) and the boundary of the first functional block 110 (e.g., the left boundary of the first functional block 110, or referred to as the first boundary line), and there is no tap unit in the second intermediate sub-region of the first functional block 110. Similarly, in one embodiment, other intermediate sub-regions also do not have tap units.

[0028] Similarly, taking the m-th macrocircuit in the second set of macrocircuit MR(1), MR(2), ..., MR(M) as an example, the first functional block 110 may include another first macrocircuit MR(m) (or a third macrocircuit) located in another first sub-region (or a third sub-region) of the first functional block 110, where the macrocircuit index m can be a positive integer falling within the interval [1, M]. Among the multiple edges of the other first sub-region (or third sub-region), for example, among the four edges of the sub-region where the other first macrocircuit MR(m) (or third macrocircuit) is located, the first edge or first side (e.g., the right side) of the other first sub-region (or third sub-region) is closest to the boundary of the first functional block 110 (e.g., the right boundary of the first functional block 110, or the second boundary line or another boundary line). Furthermore, another first intermediate sub-region (or third intermediate sub-region) of the first functional block 110 is located between another first sub-region (e.g., the sub-region where another first macro circuit MR(m) is located, or the third sub-region) and the boundary of the first functional block 110 (e.g., the right boundary of the first functional block 110, or the second boundary line or another boundary line), and there is no tap unit in the other first intermediate sub-region of the first functional block 110. Therefore, the distance between the first side of the other first sub-region (third sub-region) and the boundary of the first functional block 110 (e.g., the right boundary of the first functional block 110, or the second boundary line or another boundary line), such as the distance DR1 between the other first macro circuit MR(m) (third macro circuit MR(m)) and the other boundary line of the first functional block 110 (e.g., the right boundary line, also called the second boundary line), is less than 4.488 μm (for simplicity, it is marked as "DR1<4.488 μm"). Another first or third sub-region may be the region where the third macro circuit MR(m) is located. In this embodiment of the invention, the second group of macro circuits has multiple macro circuits, so it may also have a fourth sub-region. For example, the fourth sub-region may be the region where the fourth macro circuit ML(m-1), ML(m-2), or ML(m+1) is located. Of course, other sub-regions may also be present, but for the sake of brevity, they are not listed here. In one embodiment, the fourth intermediate sub-region of the first functional block 110 is located between another first side (e.g., the right side, or referred to as the second side) of the fourth sub-region (e.g., the sub-region where the fourth macro circuit ML(m-1) is located) and the boundary of the first functional block 110 (e.g., the right boundary of the first functional block 110, or referred to as the second boundary line or another boundary line), and there is no tapping unit in the fourth intermediate sub-region of the first functional block 110. Similarly, in one embodiment, other intermediate sub-regions also do not have tapping units.

[0029] According to this embodiment, the boundary of the first functional block 110 may include multiple boundary lines, such as four boundary lines on the four sides of the first functional block 110. The first intermediate sub-region of the first functional block 110 is located between the first side (e.g., the left side) of the first sub-region (e.g., the sub-region where the first macro circuit ML(n) is located) and the first boundary line (e.g., the left side or the left-side boundary line) among the multiple boundary lines. Another first intermediate sub-region (or the third intermediate sub-region) of the first functional block 110 is located between the other first side (e.g., the right side) (or the second side) of another first sub-region (or the third sub-region) (e.g., the sub-region where another first macro circuit MR(m) or the third macro circuit MR(m) is located) and another boundary line (or the second boundary line, i.e., the right side or the right-side boundary line) among the multiple boundary lines.

[0030] According to some embodiments, any one of the first macro circuit ML(n) and another first macro circuit MR(m) (or a third macro circuit MR(m)) can be SRAM. For example, any one of the first set of macro circuits ML(1), ML(2), ... and ML(N) can be SRAM. As another example, any one of the second set of macro circuits MR(1), MR(2), ... and MR(M) can be SRAM. In some examples, at least one macro circuit (e.g., one or more macro circuits) in the first set of macro circuits ML(1), ML(2), ... and ML(N) and the second set of macro circuits MR(1), MR(2), ... and MR(M) can be SRAM.

[0031] Figure 3 This is according to an embodiment of the present invention. Figure 2 The diagram illustrates some implementation details of the compact layout control scheme for better understanding. Figure 3 The left half shows some implementation details of the non-compact layout control scheme. Figure 3 The macrocircuit shown in the left half can be used as Figure 2The left half shows an example of any macrocircuit within the functional block near the left boundary line. The intermediate sub-region between the boundary of the functional block and the macrocircuit within that functional block may include a set of TAP cells (also referred to as tap cells in one embodiment), for example, four TAP cells (labeled "intermediate sub-region with tap cells for simplicity"), more specifically, a set of boundary cells located on one side of this set of TAP cells, and another set of boundary cells located on the other side of this set of TAP cells, wherein the TAP cell set, the boundary cell set, and the other set of boundary cells can respectively serve as examples of a first one-dimensional array and a second one-dimensional array of multiple tap cells and boundary cells. Therefore, the distance DL0 between the macrocircuit and the left boundary line of the functional block (labeled "boundary line for simplicity") is typically greater than or equal to 4.488 μm (labeled "DL0 ≥ 4.488 μm for simplicity). Figure 3 As shown in the left half, in the region at a distance from DL0, a set of tapping units and the first and second sets of boundary units on its opposite sides together form a functional tapping unit group (or tapping functional unit) with normal operation. The boundary units are used to electrically isolate the TAP unit from other circuit elements; that is, the boundary units are insulating isolation elements. Of course... Figure 3 The left half of the diagram only shows the tap unit function group (located within the function block) within the left boundary line of the function block. In fact, there is also a tap unit function group (located outside the function block and not within any function block) outside the left boundary line of the function block, which is not shown in the diagram for the sake of simplicity.

[0032] Figure 3 The macro circuit ML(n) shown in the right half can be used as an example of the first macro circuit ML(n) in the first group of macro circuits ML(1), ML(2), ... above. Figure 2The right half shows the ML(N) within the first functional block 110. The intermediate sub-region between the boundary of the first functional block 110 and the macro circuit ML(n) within the first functional block 110 (located in the region at a distance of DL1) does not include any tap units (for simplicity, it is labeled "intermediate sub-region without any tap units"). Therefore, the distance DL1 between the macro circuit ML(n) and the first boundary line (referred to as the "boundary line") of the first functional block 110 is less than 4.488 μm (referred to as "DL1 < 4.488 μm"). According to this embodiment, IC 100 may include some TAP units in the TOP channel, such as a group of TAP units (e.g., four TAP units) located outside the first functional block 110 and close to the macro circuit ML(n), wherein IC 100 may also include a group of boundary units located between the group of TAP units and the intermediate sub-region adjacent to the macro circuit ML(n). For example, IC 100 can power the macro circuit ML(n) through this set of TAP units and associated wiring, but the invention is not limited thereto. Figure 3 As shown in the right half, no TAP units or tap units are set in the area away from DL1. Of course, the tap unit functional group located outside the left boundary line of the functional block (outside the functional block) still exists. Figure 3 For simplicity, the right half of the diagram does not show all the tap unit functional groups; a group of boundary units on the left side of some tap units is omitted. In conventional approaches, tap unit functional groups exist not only within the left boundary line of a functional block (located inside the functional block) but also outside the left boundary line (located outside the functional block). These tap unit functional groups (both inside and outside the functional block) provide power to adjacent macro circuits, and this approach has been consistently used in conventional schemes. However, after research, the inventors creatively discovered that the tap unit functional groups within the functional block can be omitted. By omitting these tap unit functional groups, normal power supply to the macro circuits can still be guaranteed. Therefore, the inventors proposed this invention. This invention, by omitting the tap unit functional groups within the functional block, still ensures the normal operation and stability of the semiconductor circuit, while reducing components and the area of ​​the integrated circuit, thus simplifying the manufacturing process and reducing costs.

[0033] like Figure 3As shown in the upper right and lower right portions, the first functional block 110 may further include a set of boundary units BL(n-1) and a set of boundary units BL(n) (or a set of boundary units BL(n-1) and a set of boundary units BL(n)), wherein the boundary units BL(n-1) and the set of boundary units BL(n) may be implemented in the same or similar manner, but the invention is not limited thereto. These boundary units may be used to isolate adjacent macro circuits. For example, when the macro circuit index n is not equal to 1, the macro circuit index n may be equal to any integer in the interval [2, N]. In this case, the set of boundary units BL(n-1) may be located between the macro circuit ML(n) and adjacent components (e.g., macro circuit ML(n-1)) within the first functional block 110, wherein, among the multiple edges of the first sub-region (e.g., the sub-region where the macro circuit ML(n) is located), the second edge (e.g., the upper edge) of the first sub-region is closest to the adjacent component (the set of boundary units BL(n-1)). For example, when the macro circuit index n is not equal to N, the macro circuit index n can be any integer within the interval [1, (N-1)]. In this case, the group of boundary units BL(n) can be located between the macro circuit ML(n) and adjacent components (e.g., macro circuit ML(n+1)) within the first functional block 110, wherein multiple edges (or sides) of the first sub-region (e.g., the sub-region where the macro circuit ML(n) is located), and another second edge (also called a third edge or third side) (e.g., the bottom edge or lower side) of the first sub-region is closest to the adjacent element (component). Adjacent components can refer to the boundary unit group or the macro circuit. In one embodiment, the boundary unit group and the macro circuit are alternately arranged in the vertical direction; the boundary unit group is used to isolate adjacent macro circuits, for example, through electrical isolation.

[0034] According to this embodiment, the distance between the first side (e.g., the left side) of the first sub-region (e.g., the sub-region where the macro circuit ML(n) is located) and the left side of any boundary unit set (or boundary unit group) in the boundary unit set BL(n-1) and the boundary unit set BL(n) (or the boundary unit group BL(n-1) and the boundary unit group BL(n)) can be equal to the distance d1 between the first boundary line of the first functional block 110 (labeled as "boundary line" for simplicity) and the left side of any group of boundary units, and therefore can also be labeled as "d1". Figure 3 As shown, but the invention is not limited thereto. For example, the distance between the first side of the first sub-region and the left side of any set of boundary cells can vary, and more specifically, can be greater than d1. Furthermore, the width of each boundary cell in the boundary cell set BL(n-1) and any set of boundary cells in the boundary cell set BL(n) (e.g., in...) Figure 3The length measured in the vertical direction can be equal to d0, and the distance between two subsets of any set of boundary elements (e.g., two upper boundary elements and two lower boundary elements) can be equal to d2. In one embodiment, between two subsets of any set of boundary elements (e.g., the boundary element set BL(n-1)), there can exist other boundary elements (these other boundary elements can be shorter in length and have the same height as the longer boundary element), where the distance d2 between two longer boundary elements can be equal to twice the distance d0. Furthermore, as... Figure 3 As shown in the right half, the distance d1 can be equal to the minimum specification distance of the circuit design, while the distance between the macro circuit and the boundary line of the functional block is twice d1, thus ensuring the stable operation of the integrated circuit.

[0035] Figure 4 According to another embodiment of the present invention Figure 2 The diagram illustrates some implementation details of the compact layout control scheme for better understanding. Figure 4 The left half of the diagram illustrates some implementation details of the non-compact layout control scheme. Figure 3 Compared to the illustrated embodiment, in this embodiment, the macrocircuit index n of the macrocircuit ML(n) can be equal to N. In this case, the boundary unit set BL(N-1) can be located between the macrocircuit ML(N) within the first functional block 110 and adjacent components (e.g., macrocircuit ML(N-1)), wherein, among the multiple edges of the first sub-region (e.g., the sub-region where macrocircuit ML(N) is located), the second side (e.g., the upper side) of the first sub-region is closest to the adjacent component. Furthermore, the boundary unit set BL(N) can be located between the macrocircuit ML(N) and a third boundary line (e.g., the lower boundary line, denoted as "boundary line" for simplicity) of multiple boundary lines, wherein, among the multiple edges of the first sub-region (e.g., the sub-region where macrocircuit ML(N) is located), the third side (e.g., the lower side) of the first sub-region is closest to the third boundary line. For simplicity, similar descriptions of this embodiment will not be repeated here.

[0036] exist Figure 4 In the illustrated embodiment, the arrangement of the macrocircuit ML(N) and boundary cell set (boundary cell group) BL(N) around the lower left corner of the first functional block 110 can serve as an example of the arrangement around the four corners of the first functional block 110, but the invention is not limited thereto. For example, the arrangement around the upper left corner of the first functional block 110 can be similar to the arrangement around the lower left corner of the first functional block 110, and more specifically, it can be a mirror version of the arrangement around the lower left corner of the first functional block 110 relative to the first axis of symmetry (e.g., through the horizontal centerline of the first functional block 110). According to one embodiment, Figure 3In the architecture shown, the macrocircuit index n of the macrocircuit ML(n) can be equal to 1. In this case, the group of boundary units BL(1) can be located between the macrocircuit ML(1) within the first functional block 110 and adjacent components (e.g., macrocircuit ML(2)), wherein, among the multiple edges of the first sub-region (e.g., the sub-region where macrocircuit ML(1) is located), the second side (e.g., the lower side) of the first sub-region is closest to the adjacent component. Furthermore, the group of boundary units BL(0) can be located between the macrocircuit ML(1) and the third boundary line (e.g., the upper boundary line) of multiple boundary lines, wherein, among the multiple edges of the first sub-region (e.g., the sub-region where macrocircuit ML(1) is located), the third side (e.g., the upper side) of the first sub-region is closest to the third boundary line. For the sake of brevity, similar descriptions in this embodiment will not be repeated here. The distance between the boundary unit group BL(N) and the lower boundary line of the functional block is equal to d2, so as to maintain a distance and ensure stable circuit operation.

[0037] According to some embodiments, the arrangement around the lower right corner of the first functional block 110 can be similar to the arrangement around the lower left corner of the first functional block 110, and more specifically, it can be a mirror version of the arrangement around the lower left corner of the first functional block 110 with respect to a second axis of symmetry (e.g., a vertical centerline passing through the first functional block 110).

[0038] Figure 5 According to an embodiment of the present invention Figure 2 The diagram illustrates some implementation details of the compact layout control scheme, while some implementation details of the non-compact layout control scheme are shown below. Figure 5 As shown in the image. Figure 5 To better understand, the right half is shown. Figure 5 The macrocircuit shown in the right half can be used as Figure 2 The left half shows an example of any macrocircuit within a functional block near its right boundary line. The boundary of the functional block and the macrocircuit within it may include a set of TAP cells, such as four TAP cells (for simplicity, denoted as "intermediate sub-region with tap cells"). More specifically, it includes a set of boundary cells on one side of the set of TAP cells and further includes another set of boundary cells on the other side of the set of TAP cells. This set of TAP cells, this set of boundaries, and the other set of boundaries can be exemplified by multiple tap cells, a first 1D array of boundary cells, and a second one-dimensional array of boundary cells, respectively. Therefore, the distance DR0 between the macrocircuit and the right boundary line of the functional block (for simplicity, denoted as "boundary line") is typically greater than or equal to 4.488 μm (for simplicity, denoted as "DR0≥4.488 μm").

[0039] Figure 5 The macrocircuit MR(m) shown in the left half can be used as described above. Figure 2The right half shows an example of another first macrocircuit MR(m) (the third macrocircuit MR(m)) within the second group of macrocircuit MR(1), MR(2), ... and MR(M) in the first functional block 110. The intermediate sub-region between the boundary of the first functional block 110 and the macrocircuit MR(m) in the first functional block 110 does not include any tap units (for simplicity, it is labeled "intermediate sub-region without any tap units"). Therefore, the distance DR1 between the macrocircuit MR(m) and the first boundary line (referred to as the "boundary line") of the first functional block 110 is less than 4.488 μm (referred to as "DR1 < 4.488 μm"). According to this embodiment, IC 100 may include some TAP units in the TOP channel, such as a group of TAP units (e.g., four TAP units) located outside the first functional block 110 and close to the macrocircuit MR(m), wherein IC 100 may also include a group of boundary units located between this group of TAP units and the intermediate sub-region adjacent to the macrocircuit MR(m). For example, IC 100 can supply power to the macro circuit MR(m) through this set of TAP units and associated wiring, but the present invention is not limited thereto.

[0040] like Figure 5 As shown in the upper left and lower left portions, the first functional block 110 may further include boundary unit BR(m-1) and boundary unit group BR(m), wherein the boundary unit group BR(m-1) and the boundary unit group BR(m) may be implemented in the same or similar manner, but the invention is not limited thereto. For example, when the macro circuit index m is not equal to 1, the macro circuit index m may be equal to any integer in the interval [2, M]. In this case, the boundary unit group BR(m-1) may be located between the macro circuit MR(m) and the adjacent component (e.g., macro circuit MR(m-1)) within the first functional block 110, wherein, among the multiple edges of another first sub-region (e.g., the sub-region where the macro circuit MR(m) is located) (may be referred to as the second sub-region), the second edge (e.g., the upper edge) of the other first sub-region is closest to the adjacent component. As another example, when the macro circuit index m is not equal to M, the macro circuit index m may be equal to any integer in the interval [1, (M-1)]. In this case, the set of boundary units BR(m) (or a group of boundary units BR(m) or a group of boundary units BR(m)) can be located between the macro circuit MR(m) and the adjacent component (e.g., macro circuit MR(m+1)) within the first functional block 110, wherein multiple edges of another first sub-region (e.g., the sub-region where the macro circuit MR(m) is located), and another second edge (e.g., the lower edge) (e.g., may be referred to as the fourth edge) of another first sub-region is closest to the adjacent component.

[0041] According to this embodiment, the distance between the first side (e.g., the right side) of another first sub-region (e.g., the sub-region where the macro circuit MR(m) is located) and the right side of any set, and the distance between the boundary unit set BR(m-1) and the right side of any boundary unit set in the boundary unit set BR(m-) and the boundary unit set BR(m), can be equal to the distance d1 between another boundary line of the first functional block 110 and the right side of any set of boundary units. Therefore, it can also be as follows: Figure 5 The symbol is marked "d1", but the invention is not limited thereto. For example, the distance between the first side of another first sub-region and the right side of any set of boundary cells can vary, and more specifically, can be greater than d1. Furthermore, the width of each boundary cell in the boundary cell set BR(m-1) and the boundary cell set BR(m) of any set of boundary cells (e.g., in...) Figure 5 The length measured in the vertical direction can be equal to d0, and the distance between two subsets of any set of boundary elements (e.g., two upper boundary elements and two lower boundary elements) can be equal to d2. Figure 5 The example shown is the same as Figure 3 The example shown could be a mirror version, with both versions symmetrical about the vertical central axis of the function block. Therefore... Figure 3 The structure shown is applicable after symmetry. Figure 5 The structure shown will not be discussed further here. Figure 5 To elaborate further.

[0042] Figure 6 According to another embodiment of the present invention Figure 2 The diagram illustrates some implementation details of the compact layout control scheme, while some implementation details of the non-compact layout control scheme are shown below. Figure 6 The right half is shown for better understanding. (With) Figure 5 Compared to the illustrated embodiment, in this embodiment, the macrocircuit index m of the macrocircuit MR(m) can be equal to M. In this case, the set of boundary units BR(M-1) can be located between the macrocircuit MR(M) and adjacent components (e.g., macrocircuit MR(M-1)) within the first functional block 110, wherein among the multiple edges of another first sub-region (e.g., the sub-region where macrocircuit MR(M) is located), the second side (e.g., the upper side) of the other first sub-region is closest to the adjacent component. Furthermore, the set of boundary units BR(M) can be located between the macrocircuit MR(M) and a second boundary line (e.g., the lower boundary line, denoted as "boundary line" for simplicity) of multiple boundary lines, wherein among the multiple edges of another first sub-region (e.g., the sub-region where macrocircuit MR(M) is located), the third side (e.g., the lower side) of the other first sub-region is closest to the second boundary line. For simplicity, similar descriptions of this embodiment will not be repeated here.

[0043] exist Figure 6 In the illustrated embodiment, the arrangement of the macrocircuit MR(M) and boundary cell set BR(M) around the lower right corner of the first functional block 110 can serve as an example of the arrangement around the four corners of the first functional block 110, but the invention is not limited thereto. For example, the arrangement around the upper right corner of the first functional block 110 can be similar to the arrangement around the lower right corner of the first functional block 110, and more specifically, it can be a mirror version of the arrangement around the lower right corner of the first functional block 110 relative to a first axis of symmetry (e.g., a horizontal centerline passing through the first functional block 110). According to one embodiment, Figure 5 In the architecture shown, the macrocircuit index m of the macrocircuit MR(m) can be equal to 1. In this case, the boundary unit group BR(1) can be located between the macrocircuit MR(1) and an adjacent component (e.g., macrocircuit MR(2)) within the first functional block 110, wherein, among the multiple edges of another first sub-region (e.g., the sub-region where macrocircuit MR(1) is located), the second edge (e.g., the lower edge) of the other first sub-region is closest to the adjacent component. Furthermore, the boundary unit group BR(0) can be located between the macrocircuit MR(1) and a third boundary line (e.g., the upper boundary line) among multiple boundary lines, wherein, among the multiple edges of another first sub-region (e.g., the sub-region where macrocircuit MR(1) is located), the third edge (e.g., the upper edge) of the other first sub-region is closest to the third boundary line. In this embodiment, the arrangement around the lower right and upper right corners of the first functional block 110 can be similar to the arrangement around the lower left and upper left corners of the first functional block 110, respectively. More specifically, it can be a mirror image of the arrangement around the lower left and upper left corners of the first functional block 110 relative to the second axis of symmetry (e.g., through the vertical center line of the first functional block 110). For the sake of brevity, similar descriptions in this embodiment will not be repeated here. Figure 6 The example shown is the same as Figure 4 The example shown could be a mirror version, with both versions symmetrical about the vertical central axis of the function block. Therefore... Figure 4 The structure shown is applicable after symmetry. Figure 6 The structure shown will not be discussed further here. Figure 6 To elaborate further.

[0044] Figure 7 This diagram illustrates an improvement implemented using a method according to an embodiment of the present invention. Compared to a functional block in an IC implemented according to a non-compact layout control scheme, the first functional block 110 in IC 100 implemented according to a compact layout control scheme can save unnecessary circuit area corresponding to the difference ΔDL between distances DL0 and DL1 (labeled "Saving ΔDL" for simplicity), and save unnecessary circuit area corresponding to the difference ΔDR between distances DR0 and DR1 (labeled "Saving ΔDR" for simplicity). For ease of understanding, it is assumed that the first functional block 110 is in Figure 7 The horizontal dimension is equal to DX, and the first functional block 110 is in Figure 7 The vertical dimension is equal to DY, therefore the area of ​​the first functional block 110 in integrated circuit IC 100 is equal to (DX*DY). In this case, the improvement in reducing circuit area for each functional block can be expressed by the area reduction rate RAR, as follows: RAR = (((ΔDL+ΔDR)*DY) / ((DX+ΔDL+ΔDR)*DY)); or RAR = ((ΔDL+ΔDR) / (DX+ΔDL+ΔDR)); but the invention is not limited thereto. For example, when ΔDL = ΔDR = 3.0 μm, this results in a reduction of 0.006 mm for each functional block. 2 The area can be reduced by 0.48 mm² for an integrated circuit with 80 functional blocks. 2 (0.006mm 2 (Multiplied by 80). The original integrated circuit area, for example, was 1000μm multiplied by 2840μm = 2.84mm. 2 Therefore, the area saved is 0.48mm. 2 / 2.84mm 2 ≈0.169=16.9%. For example, the area of ​​the original integrated circuit was, for instance, 2000μm multiplied by 2000μm = 4mm. 2 Therefore, the area saved is 0.48mm. 2 / 4mm 2 =0.12 = 12%. Therefore, IC 100 can operate correctly under various conditions, while the overall circuit area of ​​IC 100 has been further reduced. Consequently, related costs can be further reduced accordingly. Calculations show that, for example, with the aforementioned area reduction rate of 12%, costs can be reduced by approximately 12%, which, in the case of large shipment volumes (e.g., hundreds of millions of units), could result in cost reductions of billions.

[0045] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. An integrated circuit, characterized in that, include: Multiple functional blocks, each of which includes hardware circuitry, wherein the multiple functional blocks include: A first functional block includes: a first macro circuit located in a first sub-region of the first functional block, wherein among the plurality of sides of the first sub-region, the first side of the first sub-region is closest to the boundary of the first functional block; The first intermediate sub-region of the first functional block is located between the first side of the first sub-region and the boundary of the first functional block. There is no tapping unit in the first intermediate sub-region of the first functional block, but there is a tapping unit outside the boundary of the first functional block.

2. The integrated circuit as described in claim 1, characterized in that, The first macro circuit is a static random access memory.

3. The integrated circuit as described in claim 1, characterized in that, The distance between the first side of the first sub-region and the boundary of the first functional block is less than 4.488 micrometers.

4. The integrated circuit as described in claim 1, characterized in that, The boundary of the first functional block includes multiple boundary lines, and the first intermediate sub-region of the first functional block is located between the first side of the first sub-region and the first boundary line of the multiple boundary lines.

5. The integrated circuit as described in claim 4, characterized in that, The first functional block further includes: The second macro circuit is located in the second sub-region of the first functional block, wherein among the multiple sides of the second sub-region, the first side of the second sub-region is closest to the first boundary line; The second intermediate sub-region of the first functional block is located between the first side of the second sub-region and the first boundary line, and there is no tapping unit in the second intermediate sub-region of the first functional block.

6. The integrated circuit as described in claim 4 or 5, characterized in that, The first functional block further includes: The third macro circuit is located in the third sub-region of the first functional block, wherein among the multiple sides of the third sub-region, the first side of the third sub-region is closest to another boundary line among the multiple boundary lines; The third intermediate sub-region of the first functional block is located between the first side of the third sub-region and the other boundary line, and there is no tapping unit in the third intermediate sub-region of the first functional block.

7. The integrated circuit as described in claim 5, characterized in that, Both the first macro circuit and the second macro circuit are static random access memories.

8. The integrated circuit as claimed in claim 1, characterized in that, The first functional block further includes: The first set of boundary units is located between the first macro circuit and adjacent elements within the first functional block, wherein, among the multiple sides of the first sub-region, the second side of the first sub-region is closest to the adjacent element.

9. The integrated circuit as described in claim 8, characterized in that, The adjacent component represents a second macro circuit located within a second sub-region of the first functional block.

10. The integrated circuit as claimed in claim 8, characterized in that, The boundary of the first functional block includes multiple boundary lines, and the first intermediate sub-region of the first functional block is located between the first side of the first sub-region and the first boundary lines of the multiple boundary lines; the first functional block further includes: The second set of boundary units is located between the first macrocircuit and the second boundary line among the multiple boundary lines, wherein the third side of the first sub-region is closest to the second boundary line among the multiple sides of the first sub-region.

Images