A light emitting diode chip and a method of manufacturing the same

Abstract

The application provides a light emitting diode chip and a preparation method thereof, and relates to the technical field of semiconductors. The method comprises the following steps: providing an epitaxial structure, wherein the epitaxial structure comprises a substrate, a first N-type cladding layer, a tunnel layer, a P-type cladding layer, a quantum well layer, a second N-type cladding layer and an N-type window layer which are stacked in sequence; inverting the epitaxial structure, and bonding a heat dissipation substrate at the N-type window layer; removing the substrate; and forming N-type contact layers on the first N-type cladding layer and the heat dissipation substrate, respectively. The formed BTJ LED epitaxial structure is provided with a TJ structure, so that the material is easy to reach a high-concentration and high-quality N-windowg epitaxial layer, the difficulty of epitaxy can be effectively reduced, and the carrier transport efficiency and heat dissipation can be improved. Moreover, the prepared light emitting diode chip has N-type contact layers on the top layer and the bottom layer, so that the process flow of the subsequent preparation of the coplanar light emitting diode chip can be completed at one time.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a light-emitting diode chip and its fabrication method. Background Technology

[0002] With the rapid development of the LED (Light Emitting Diode) industry, LEDs are increasingly used in lighting. As high-power LED chips are widely used in lighting, the requirements for their luminous efficiency are growing daily. Existing LED chip structures can no longer meet market demands, primarily because the hole conductivity of the P-cladding layer in existing LEDs is inferior to its electron conductivity, and their heat dissipation efficiency is low, affecting the LED chip's performance. Summary of the Invention

[0003] The purpose of this application is to provide a light-emitting diode chip and its fabrication method, which can improve carrier transport efficiency and heat dissipation efficiency, and enhance working performance.

[0004] One aspect of this application provides a method for fabricating a light-emitting diode chip, comprising providing an epitaxial structure, the epitaxial structure comprising a substrate, a first N-type cladding layer, a tunneling layer, a P-type cladding layer, a quantum well layer, a second N-type cladding layer, and an N-type window layer stacked sequentially; flipping the epitaxial structure; bonding a heat dissipation substrate to the N-type window layer; removing the substrate; and forming N-type contact layers on the first N-type cladding layer and the heat dissipation substrate, respectively.

[0005] Optionally, the provided extensional structure includes: the tunneling layer includes an N-type tunneling layer and a P-type tunneling layer formed sequentially on the first N-type cladding layer.

[0006] Optionally, the tunneling layer includes an N-type tunneling layer and a P-type tunneling layer sequentially formed on the first N-type cladding layer, wherein the N-type tunneling layer is heavily doped with tellurium, and the P-type tunneling layer is heavily doped with carbon, and the doping concentration of the doping materials in both the N-type and P-type tunneling layers is greater than 10. 19 cm -3 .

[0007] Optionally, the epitaxial structure includes: the quantum well layer comprising a first water-blocking layer, a sub-quantum well layer, and a second water-blocking layer sequentially formed on the P-type cladding layer.

[0008] In another aspect of this application, a light-emitting diode (LED) chip is provided, which is fabricated using the above-described LED chip fabrication method, comprising an N-type contact layer, a heat dissipation substrate, an N-type window layer, a second N-type cladding layer, a quantum well layer, a P-type cladding layer, a tunneling layer, a first N-type cladding layer, and an N-type contact layer stacked sequentially.

[0009] Optionally, the thickness of the tunneling layer is between 5 nm and 25 nm.

[0010] Optionally, the tunneling layer includes an N-type tunneling layer and a P-type tunneling layer sequentially disposed on the first N-type cladding layer.

[0011] Optionally, the N-type tunneling layer is heavily doped with tellurium, the P-type tunneling layer is heavily doped with carbon, and the doping concentration of the doped materials in both the N-type and P-type tunneling layers is greater than 10. 19 cm -3 .

[0012] The light-emitting diode (LED) chip and its fabrication method provided in this application form a BTJ LED epitaxial structure. A first N-type cladding layer, a tunneling layer, a P-type cladding layer, a quantum well layer, a second N-type cladding layer, and an N-type window layer are sequentially formed on a substrate. The BTJ LED epitaxial structure, through its TJ structure, facilitates the formation of a high-concentration, high-quality N-window epitaxial layer. Compared to existing LED epitaxial structures using GaP structures (which require a lattice matching degree of 3.6% with the GaAs substrate) or depositing a GaP-window layer after stacking the TJ structure, which is a highly challenging epitaxial structure, this application effectively reduces the epitaxial difficulty through the BTJ LED epitaxial structure. The BTJ LED epitaxial structure improves carrier transport efficiency and heat dissipation. Furthermore, the LED chip formed using the above fabrication method has N-type contact layers on both its top and bottom layers, allowing for one-step deposition in subsequent coplanar LED chip fabrication processes, resulting in high efficiency and good performance. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the epitaxial structure of the light-emitting diode chip provided in this embodiment;

[0015] Figure 2This is one of the schematic diagrams illustrating the formation process of the light-emitting diode chip fabrication method provided in this embodiment;

[0016] Figure 3 This is the second schematic diagram of the formation process of the light-emitting diode chip fabrication method provided in this embodiment;

[0017] Figure 4 This is the third schematic diagram of the formation process of the light-emitting diode chip fabrication method provided in this embodiment;

[0018] Figure 5 This is a schematic diagram of the LED chip structure provided in this embodiment.

[0019] Icons: 101-Substrate; 102-First N-type cladding layer; 103-Tunneling layer; 104-P-type cladding layer; 105-Quantum well layer; 106-Second N-type cladding layer; 107-N-type window layer; 108-Heat dissipation substrate; 109-N-type contact layer. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0021] In the description of this application, it should be noted that the terms "inner" and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] It should also be noted that, unless otherwise explicitly specified and limited, the terms "setup" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] This application provides a method for fabricating a light-emitting diode chip, the method comprising:

[0024] Please refer to Figure 1 As shown, S100: Provides an epitaxial structure, the epitaxial structure including a substrate 101, a first N-type cladding layer 102, a tunneling layer 103, a P-type cladding layer 104, a quantum well layer 105, a second N-type cladding layer 106 and an N-type window layer 107 stacked sequentially.

[0025] The epitaxial structure includes a substrate 101, which may be a gallium arsenide substrate 101. Then, a first N-type cladding layer 102, a tunneling layer 103, a P-type cladding layer 104, a quantum well layer 105, a second N-type cladding layer 106, and an N-type window layer 107 are sequentially formed on the substrate 101.

[0026] The tunneling layer 103 comprises an N-type tunneling layer 103 and a P-type tunneling layer 103 sequentially formed on the first N-type cladding layer 102. Both the N-type tunneling layer 103 and the P-type tunneling layer 103 are heavily doped layers. Specifically, the N-type tunneling layer 103 is heavily doped with tellurium, and the P-type tunneling layer 103 is heavily doped with carbon. The doping concentration of the doped materials in both the N-type tunneling layer 103 and the P-type tunneling layer 103 is greater than 10. 19 cm -3 .

[0027] The tunneling layer 103 is heavily doped with tellurium to form an N-type tunneling layer 103, and heavily doped with carbon to form a P-type tunneling layer 103. The tunneling layer 103 is formed by heavy doping with both N-type and P-type tunneling layers 103. The original material of the tunneling layer 103 can be one of GaP, GaAs, AlGaAs, InGaP, AlInP, or AlGaInP.

[0028] The quantum well layer 105 includes a first water-blocking layer, a sub-quantum well layer 105, and a second water-blocking layer formed sequentially on the P-type coating layer 104.

[0029] Except for the tunneling layer 103, which is heavily doped, all other layers are conventionally doped, with doping concentrations greater than 10. 18 cm -3 The materials and doping at each level are shown in Table 1, thus forming the epitaxial structure. It should be understood that the materials and doping materials at each level in Table 1 are merely examples provided in this application, and not the only supported solutions. The parameters of each level and doping material in the specific epitaxial structure are set according to specific needs and are not limited to the above.

[0030] Table 1

[0031]

[0032]

[0033] The substrate and buffer layer in Table 1 form substrate 101. This application sets up a BTJ (Bottom Tunnel Junction) LED epitaxial structure. By using the TJ (Tunnel Junction) structure, most of the P-cladding in the existing LED structure can be converted into N-cladding, thereby optimizing the P-cladding layer in the existing LED, improving carrier transport efficiency and heat dissipation.

[0034] The main advantage of the BTJ LED epitaxial structure is that the TJ structure makes it easy to achieve a high-concentration, high-quality N-window epitaxial layer. In the existing LED epitaxial structure, the TJ structure uses GaP structure, which has a lattice matching degree of 3.6% with the epitaxial material GaAs substrate 101, or after stacking the TJ structure, a GaP-window layer will be deposited. This is a high-difficulty structure in epitaxial technology. This application converts to the BTJ LED epitaxial structure, which will effectively reduce the difficulty of epitaxy.

[0035] S110: Flipped epitaxial structure, with heat dissipation substrate 108 bonded to N-type window layer 107.

[0036] After the above-mentioned extensional structure is formed, such as Figure 2 As shown, the epitaxial structure is flipped so that the substrate 101, originally located at the bottom layer, is now located at the top layer, and the N-type window layer 107, originally located at the top layer, is now located at the bottom layer; then, a heat dissipation substrate 108 is bonded below the N-type window layer 107 at the bottom layer, as shown. Figure 3 As shown, the heat dissipation substrate 108 is made of metal or semiconductor substrate and has the function of heat dissipation.

[0037] like Figure 4 As shown, S120: Remove substrate 101.

[0038] The top substrate 101 is removed by grinding, exposing the first N-type cladding layer 102 below the substrate 101, so that the first N-type cladding layer 102 is located on the top layer.

[0039] S130: An N-type contact layer 109 is formed on the first N-type covering layer 102 and the heat dissipation substrate 108, respectively.

[0040] An N-type contact layer 109 is formed above the top N-type cladding layer 102 and below the bottom heat dissipation substrate 108. Specifically, the N-type contact layer 109 is a metal ohmic contact layer to form... Figure 5 The LED chip shown.

[0041] The light-emitting diode chip formed by the above-described preparation method has N-type contact layers 109 on both its top and bottom layers, so that it can be deposited in one step when a coplanar light-emitting diode chip is subsequently fabricated.

[0042] The method for fabricating a light-emitting diode (LED) chip provided in this application provides a BTJ LED epitaxial structure. A first N-type cladding layer 102, a tunneling layer 103, a P-type cladding layer 104, a quantum well layer 105, a second N-type cladding layer 106, and an N-type window layer 107 are sequentially formed on a substrate 101. The BTJ LED epitaxial structure, through its TJ structure, facilitates the achievement of a high-concentration, high-quality N-window epitaxial layer. Compared to existing LED epitaxial structures that use GaP structures for the TJ structure (which requires a lattice matching degree of 3.6% with the GaAs substrate 101) or require the deposition of a GaP-window layer after stacking the TJ structure, which is a highly challenging epitaxial structure, this application effectively reduces the epitaxial difficulty through the BTJ LED epitaxial structure. The BTJ LED epitaxial structure used in this application improves carrier transport efficiency and heat dissipation. The fabrication process using the above method is simple, and the resulting product quality is guaranteed. Furthermore, the light-emitting diode chip formed by the above preparation method has N-type contact layers 109 on both the top and bottom layers, so that it can be deposited in one step when fabricating coplanar light-emitting diode chips in the future, which is efficient and effective.

[0043] On the other hand, such as Figure 5 As shown in the figure, this application also discloses a light-emitting diode chip, which is fabricated using any of the above-mentioned light-emitting diode chip fabrication methods. The light-emitting diode chip includes an N-type contact layer 109, a heat dissipation substrate 108, an N-type window layer 107, a second N-type cladding layer 106, a quantum well layer 105, a P-type cladding layer 104, a tunneling layer 103, a first N-type cladding layer 102, and an N-type contact layer 109 stacked sequentially.

[0044] The thickness of the tunneling layer 103 is between 5 nm and 25 nm. The thickness of the tunneling layer 103 can be controlled within a range of >5 nm, which is the minimum controllable range for high concentration. If the thickness of the tunneling layer 103 is greater than 25 nm, the tunneling effect is difficult to form. Therefore, this application sets the thickness of the tunneling layer 103 between 5 nm and 25 nm. Specifically, the tunneling layer 103 includes an N-type tunneling layer 103 and a P-type tunneling layer 103 sequentially disposed on the first N-type cladding layer 102. The tunneling layer 103 is composed of two heavily doped layers: an N-type tunneling layer 103 and a P-type tunneling layer 103. The N-type tunneling layer 103 is heavily doped with tellurium, and the P-type tunneling layer 103 is heavily doped with carbon. The doping concentration of both the N-type and P-type tunneling layers is greater than 10. 19 cm -3Other layers are conventionally doped, as detailed in Table 1 above, and will not be repeated here.

[0045] This light-emitting diode (LED) chip has the same structure and beneficial effects as the LED chip fabrication method described in the foregoing embodiments. The structure and beneficial effects of the LED chip fabrication method have been described in detail in the foregoing embodiments and will not be repeated here.

[0046] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a light-emitting diode chip, characterized in that, include: An epitaxial structure is provided, the epitaxial structure comprising a substrate, a first N-type cladding layer, a tunneling layer, a P-type cladding layer, a quantum well layer, a second N-type cladding layer, and an N-type window layer stacked sequentially; Flip the epitaxial structure and bond a heat dissipation substrate to the N-type window layer; Remove the substrate; An N-type contact layer is formed on the first N-type coating layer and the heat dissipation substrate, respectively.

2. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The provided epitaxial structure includes: The tunneling layer includes an N-type tunneling layer and a P-type tunneling layer formed sequentially on the first N-type cladding layer.

3. The method for fabricating a light-emitting diode chip according to claim 2, characterized in that, The tunneling layer includes an N-type tunneling layer and a P-type tunneling layer sequentially formed on the first N-type cladding layer, comprising: The N-type tunneling layer is heavily doped with tellurium, and the P-type tunneling layer is heavily doped with carbon, wherein the doping concentration of the doped materials in both the N-type and P-type tunneling layers is greater than 10. 19 cm -3 .

4. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The provided epitaxial structure includes: The quantum well layer includes a first water-blocking layer, a sub-quantum well layer, and a second water-blocking layer formed sequentially on the P-type coating layer.

5. A light-emitting diode chip, fabricated using the method for fabricating a light-emitting diode chip as described in any one of claims 1 to 4, characterized in that, It includes an N-type contact layer, a heat dissipation substrate, an N-type window layer, a second N-type cladding layer, a quantum well layer, a P-type cladding layer, a tunneling layer, a first N-type cladding layer, and an N-type contact layer stacked in sequence.

6. The light-emitting diode chip according to claim 5, characterized in that, The thickness of the tunneling layer is between 5 nm and 25 nm.

7. The light-emitting diode chip according to claim 5, characterized in that, The tunneling layer includes an N-type tunneling layer and a P-type tunneling layer sequentially disposed on the first N-type cladding layer.

8. The light-emitting diode chip according to claim 7, characterized in that, The N-type tunneling layer is heavily doped with tellurium, and the P-type tunneling layer is heavily doped with carbon. The doping concentration of both the N-type and P-type tunneling layers is greater than 10. 19 cm -3 .

Images