An energy storage inverter parallel system, time base synchronization control method and system

Abstract

The application discloses a time base synchronization control method, relates to the field of energy storage inverters, and comprises the following steps: a controller outputs PWM waves to a master and a slave, and when the PWM waves are output, timers in the master and the slave are used to respectively acquire real-time counting points corresponding to the current counting periods of the PWM waves of the master and the slave; when the real-time counting point of the master reaches the highest point of the upper edge, a single-chip microcomputer outputs a high-level signal to a first output circuit of the master; and when the slave receives the high-level signal, the real-time counting point of the counting period of the slave is adjusted according to the counting direction of the slave, so that after a preset counting period, the difference between the real-time counting point corresponding to the counting period of the slave and the highest point of the upper edge of the master is within a preset range when the master corresponds to the highest point of the upper edge, and the problem of overcurrent of the parallel energy storage inverters caused by the current mutual infusion among the energy storage inverters is avoided.

Description

Technical Field

[0001] This invention relates to the field of energy storage inverters, and more particularly to a parallel system of energy storage inverters, a time-base synchronization control method and system. Background Technology

[0002] With major global economies reaching a consensus on carbon neutrality, the vast majority of countries worldwide have proposed "zero-carbon" climate goals to drive energy structure transformation. In the future, the importance of energy storage inverters will be further highlighted in the energy sector. Currently, the output power of a single energy storage inverter is relatively small, and its off-grid output is unstable. When multiple energy storage inverters are connected in parallel (one master energy storage inverter and one slave energy storage inverter or several slave energy storage inverters), noise interference on the communication line causes the time base corresponding to the PWM waves of the master and slave energy storage inverters to be inconsistent and the difference is large. This leads to current mutual injection between the master and slave energy storage inverters, which in turn causes the problem of parallel overcurrent of energy storage inverters. Summary of the Invention

[0003] To ensure that the time base difference between the PWM waves of the master and slave energy storage inverters is within a standard range, thus avoiding current leakage between the inverters, this invention proposes a parallel energy storage inverter system, comprising a master unit and several slave units, both of which are energy storage inverters. The positive terminals of the power supplies of the master and slave units are connected in parallel to a battery pack, and the negative terminals are also connected in parallel to the battery pack to maintain consistent DC bus voltages between the master and slave units. The master and slave units are connected via a SYNC interface. Both the master and slave units include a time base communication circuit. This time base communication circuit includes a first output circuit and a second output circuit with unidirectional output. The first and second output circuits of the master unit are connected to the SYNC bus. The first and second output circuits of each slave unit are also connected to the SYNC bus.

[0004] Furthermore, the first phase line of the host is connected in parallel with the first phase line of the slave; the second phase line of the host is connected in parallel with the second phase line of the slave; and the neutral line of the host is connected in parallel with the neutral line of the slave and then grounded.

[0005] Furthermore, the first output circuit specifically includes: The fourth optocoupler has its second pin connected to one end of a second 221 resistor, a second 228 resistor, and the collector of a third transistor. The other end of the second 221 resistor is connected to both the positive power supply and one end of a second 57 capacitor. The other end of the second 57 capacitor is grounded. The third pin of the fourth optocoupler is connected to both the other end of the second 228 resistor and one end of a second 229 resistor. The other end of the second 229 resistor is grounded. The emitter of the third transistor is grounded and connected to one end of a second 60 capacitor. The other end of the second 60 capacitor is connected to one end of a second 227 resistor, the cathode of a first diode, and the base of the third transistor. The other end of the second 227 resistor is connected to a first microcontroller, one end of a fourth 5 resistor, and the first port of a seventh connector. The anode of the first diode is connected to the other end of the fourth 5 resistor. The second port of the seventh connector is grounded. The second 26 resistor has one end connected to the power supply, and simultaneously connected to one end of the second 25 resistor and one end of the second 58 capacitor. After being connected to one end of the second 225 resistor, it is connected to the eighth pin of the fourth 4 optocoupler. The other end of the second 58 capacitor is grounded. The other end of the second 225 resistor is simultaneously connected to the seventh pin of the fourth 4 optocoupler and one end of the third 1 capacitor. The other end of the third 1 capacitor is connected to the fifth pin of the fourth 4 optocoupler, and simultaneously connected to one end of the third 2 capacitor, the collector of the second transistor, and grounded. The other end of the second 26 resistor is simultaneously connected to the sixth pin of the fourth 4 optocoupler, the other end of the third 2 capacitor, and the base of the second transistor. The emitter of the second transistor is connected to the second output circuit.

[0006] Furthermore, the second output circuit specifically includes: The second 32 resistor has one end connected to the emitter of the second transistor in the first output circuit; the other end of the second 32 resistor is connected to one end of the fifth 9 capacitor and the fourth 7 resistor, and then connected to the third pin of the fourth 5 optocoupler; the other end of the fourth 7 resistor is simultaneously connected to the other end of the fifth 9 capacitor, the second pin of the fourth 5 optocoupler, and the power supply terminal. The second 31 resistor has one end connected to the positive power supply, and simultaneously connected to one end of the second 30 resistor and the eighth pin of the fourth 5 optocoupler; the other end of the second 30 resistor is connected to the sixth pin of the fourth 5 optocoupler, and simultaneously connected to the second microcontroller, and then connected to the third port of the seventh connector after being connected to the second microcontroller; the other end of the second 31 resistor is also connected to the seventh pin of the fourth 5 optocoupler and one end of the sixth 2 capacitor; the other end of the sixth 2 capacitor is connected to the fifth pin of the fourth 5 optocoupler and then grounded.

[0007] This invention also proposes a time-base synchronization control method, applied to the above-described parallel energy storage inverter system, comprising the following steps: S1: The controller outputs PWM waves to the master and slave devices. When outputting PWM waves, the timers in the master and slave devices respectively obtain the real-time count points corresponding to the current counting cycle of the PWM wave. When the real-time count point of the master device reaches the highest point of the upper edge, the microcontroller outputs a high-level signal to the first output circuit of the master device. At this time, the slave device receives the high-level signal through the second output circuit. One PWM wave corresponds to one counting cycle. One counting cycle includes a rising counting segment and a falling counting segment. The rising counting segment corresponds to a highest point of the upper edge, and the falling counting segment corresponds to a lowest point of the lower edge. S2: When the slave receives a high-level signal, obtain the current counting direction of the slave and adjust the real-time counting point of the slave counting cycle according to the counting direction, so that after a preset number of counting cycles, when the master is at the highest point of the upper edge, the difference between the real-time counting point of the slave counting cycle and the highest point of the master upper edge is within a preset range.

[0008] Further, step S2 specifically includes: S21: When the slave device receives a high-level signal, determine whether the current counting direction of the slave device is an upward counting segment. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device corresponding to the counting cycle and the highest point of the master device's upper edge is within a preset range; if not, proceed to the next step. S22: Determine whether the real-time count point corresponding to the slave device when it receives a high-level signal is greater than the set value. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually decrease the real-time count point of each PWM wave corresponding to the counting cycle, so that after preset number of counting cycles, when the master device is at the highest point of the rising edge, the difference between the real-time count point of the slave device corresponding to the counting cycle and the highest point of the master device's rising edge is within the preset range. If not, proceed to the next step. S23: Under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within the preset range.

[0009] This invention also proposes a time-base synchronization control system, applied to the above-described parallel energy storage inverter system, comprising: The counting module is used to output PWM waves to the master and slave devices through the controller. When outputting PWM waves, the timers in the master and slave devices respectively obtain the real-time counting points corresponding to the current counting cycle of the PWM wave. When the real-time counting point of the master device reaches the highest point of the upper edge, the microcontroller outputs a high-level signal to the first output circuit of the master device. At this time, the slave device receives the high-level signal through the second output circuit. One PWM wave corresponds to one counting cycle, and one counting cycle includes a rising counting segment and a falling counting segment. The rising counting segment corresponds to a highest point of the upper edge, and the falling counting segment corresponds to a lowest point of the lower edge. The time base synchronization module is used to obtain the current counting direction of the slave device when the slave device receives a high-level signal, and adjust the real-time counting point of the slave device's counting cycle according to the counting direction, so that after a preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range.

[0010] Furthermore, the time base synchronization module specifically includes a first synchronization unit, a second synchronization unit, and a third synchronization unit, wherein: The first synchronization unit is used to determine whether the current counting direction of the slave device is an upward counting segment when the slave device receives a high-level signal. If so, it gradually increases the real-time counting point of each PWM wave corresponding to the counting cycle under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range; if not, it enters the second synchronization unit. The second synchronization unit is used to determine whether the real-time count point corresponding to the slave device when it receives a high-level signal is greater than a set value. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, the real-time count point of each PWM wave corresponding to the counting cycle is gradually reduced so that after preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time count point of the slave device corresponding to the counting cycle and the highest point of the master device's upper edge is within a preset range. If not, the process proceeds to the third synchronization unit. The third synchronization unit is used to gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle under the current PWM wave of the slave and under the subsequent preset number of PWM waves, so that after the preset number of counting cycles, when the master is at the highest point of the upper edge, the difference between the real-time counting point of the slave counting cycle and the highest point of the upper edge of the master is within a preset range.

[0011] Compared with the prior art, the present invention has at least the following beneficial effects: (1) Both the host and slave of the present invention include a time base communication circuit; the time base communication circuit includes a first output circuit and a second output circuit with unidirectional output; the first output circuit and the second output circuit of the host are connected to the SYNC bus; the first output circuit and the second output circuit of each slave are connected to the SYNC bus. Since the first output circuit and the second output circuit are both unidirectional output, the fourth optocoupler in the slave does not work. Through the unidirectional first output circuit and the second output circuit, the problem of low output power of a single energy storage inverter is solved, and the time for the slave to receive the signal is obtained, that is, the time for adjusting the slave counting cycle is obtained. (2) The present invention outputs PWM waves to the master and slave devices through the controller, and when outputting PWM waves, the real-time counting points corresponding to the current counting cycle of the PWM waves of the master and slave devices are obtained by the timers in the master and slave devices respectively; when the real-time counting point of the master device reaches the highest point of the upper edge, the microcontroller outputs a high-level signal to the first output circuit of the master device; when the slave device receives the high-level signal, it adjusts the real-time counting point of the counting cycle of the slave device according to the counting direction of the slave device, so that after a preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device and the highest point of the upper edge of the master device is within a preset range. By adjusting the real-time counting point of the slave device when the master device is at the highest point of the upper edge in multiple counting cycles of the slave device, the time base difference between the slave device and the master device is within a preset range, which avoids the problem of parallel overcurrent of energy storage inverters caused by current mutual injection between the various energy storage inverters. Attached Figure Description

[0012] Figure 1 Wiring diagram for a parallel energy storage inverter system; Figure 2 This is a circuit diagram for time-based communication. Figure 3 This is the overall wiring diagram for the master and slave devices; Figure 4 Here is a flowchart of the time-base synchronization control method; Figure 5 This is a flowchart of a time-base synchronization control system. Detailed Implementation

[0013] The following are specific embodiments of the present invention, which are described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0014] Example 1 To address the issue of inconsistencies in the time bases of the PWM waves corresponding to the master and slave energy storage inverters due to noise interference on the communication line, which leads to current leakage between the master and slave energy storage inverters and consequently, parallel overcurrent problems, such as... Figures 1 to 3As shown, this invention proposes a parallel energy storage inverter system, including a master unit and several slave units, both of which are energy storage inverters. The positive terminals of the power supplies of the master and slave units are connected in parallel and then connected to a battery pack, and the negative terminals of the power supplies of the master and slave units are also connected in parallel and then connected to the battery pack to ensure that the DC bus voltages of the master and slave units are kept consistent. The master and slave units are connected via a SYNC interface. Both the master and slave units include a time base communication circuit. The time base communication circuit includes a first output circuit and a second output circuit with unidirectional output. The first output circuit and the second output circuit of the master unit are connected and then connected to the SYNC bus. The first output circuit and the second output circuit of each slave unit are connected and then connected to the SYNC bus.

[0015] The first phase line of the host is connected in parallel with the first phase line of the slave; the second phase line of the host is connected in parallel with the second phase line of the slave; the neutral line of the host is connected in parallel with the neutral line of the slave and then grounded.

[0016] like Figure 2 As shown, the first output circuit specifically includes: The fourth optocoupler U44 has its second pin connected to one end of the second 221 resistor R221, the second 28 resistor R228, and the collector of the third transistor Q3. The other end of the second 221 resistor R221 is connected to both the positive power supply 3.3VDC and one end of the second 57 capacitor C257. The other end of the second 57 capacitor C257 is grounded. The third pin of the fourth optocoupler U44 is connected to both the other end of the second 28 resistor R228 and one end of the second 29 resistor R229. The other end of the second 29 resistor R229 is grounded. The emitter of the third transistor Q3 is grounded and connected to one end of the second 60-cell capacitor C260; the other end of the second 60-cell capacitor C260 is simultaneously connected to one end of the second 27-cell resistor R227, the cathode of the first diode D11, and the base of the third transistor Q3; the other end of the second 27-cell resistor R227 is connected to the first microcontroller EPWMSYNCO, one end of the fourth 5-cell resistor R45, and the first port of the seventh connector P7; the anode of the first diode D11 is connected to the other end of the fourth 5-cell resistor R45; the second port of the seventh connector P7 is grounded. The second 226 resistor R226 has one end connected to the power supply terminal VDD_2, and simultaneously connected to one end of the second 225 resistor R225 and one end of the second 58 capacitor C258. After being connected to one end of the second 225 resistor R225, it is connected to the eighth pin of the fourth four-electrocoupler U44. The other end of the second 58 capacitor C258 is grounded. The other end of the second 225 resistor R225 is simultaneously connected to the seventh pin of the fourth four-electrocoupler U44 and one end of the third one capacitor C31. The other end of the third one capacitor C31 is connected to the fifth pin of the fourth four-electrocoupler U44, and simultaneously connected to one end of the third two capacitor C32, the collector of the second transistor Q2, and grounded. The other end of the second 226 resistor R226 is simultaneously connected to the sixth pin of the fourth four-electrocoupler U44, the other end of the third two capacitor C32, and the base of the second transistor Q2. The emitter of the second transistor Q2 is connected to the second output circuit.

[0017] like Figure 2 As shown, the second output circuit specifically includes: The second resistor R232 has one end connected to the emitter of the second transistor Q2 in the first output circuit; the other end of the second resistor R232 is connected to one end of the fifth capacitor C59 and the fourth resistor R47, and then connected to the third pin of the fourth optocoupler U45; the other end of the fourth resistor R47 is simultaneously connected to the other end of the fifth capacitor C59, the second pin of the fourth optocoupler U45, and the power supply terminal VDD_2. The second resistor R231 has one end connected to the positive power supply (3.3VDC) and simultaneously connected to one end of the second resistor R230 and the eighth pin of the fourth optocoupler U45. The other end of the second resistor R230 is connected to the sixth pin of the fourth optocoupler U45 and to the second microcontroller EPWMSYNCI, and then connected to the third port of the seventh connector P7 after connecting to the second microcontroller. The other end of the second resistor R231 is also connected to the seventh pin of the fourth optocoupler U45 and one end of the sixth capacitor C62. The other end of the sixth capacitor C62 is connected to the fifth pin of the fourth optocoupler U45 and then grounded.

[0018] This embodiment Figure 1 This diagram shows the wiring between one master unit and one slave unit, where N represents the neutral wire; This embodiment Figure 3 It shows the wiring diagram of 1 master unit and 3 slave units.

[0019] Both the host and slave units of this invention include a time base communication circuit; the time base communication circuit includes a first output circuit and a second output circuit with unidirectional output; the first output circuit and the second output circuit of the host are connected to the SYNC bus; the first output circuit and the second output circuit of each slave unit are connected to the SYNC bus. Since the first output circuit and the second output circuit are both unidirectional, the fourth optocoupler in the slave unit does not work. Through the unidirectional first output circuit and the second output circuit, the problem of low output power of a single energy storage inverter is solved, and the time for the slave unit to receive the signal is obtained, that is, the time for adjusting the slave unit's counting cycle is obtained.

[0020] Example 2 like Figure 4 As shown, this invention also proposes a time-base synchronization control method, applied to the above-described parallel energy storage inverter system, comprising the following steps: S1: The controller outputs PWM waves to the master and slave devices. While outputting the PWM waves, the timers in the master and slave devices respectively acquire the real-time count points corresponding to the current counting cycle of the PWM waves. When the real-time count point of the master device reaches its highest point, the microcontroller outputs a high-level signal to the first output circuit of the master device. Specifically, at this time, the first diode is forward-biased, the third transistor is turned on, pulling the fourth optocoupler input port CA low, the optocoupler output port VO is pulled high, the second transistor is turned off, the SYNC bus is raised, the slave device's fourth optocoupler pin CA is pulled high (since the fourth optocoupler in the first output circuit is unidirectional, the fourth optocoupler in the slave device does not work), the optocoupler output is turned off, the optocoupler output port VO is pulled high, and the microcontroller's EPWMSYNCI level is pulled high. At this time, the slave device receives a high-level signal through the second output circuit. One PWM wave corresponds to one counting cycle, and one counting cycle includes a rising counting segment and a falling counting segment. The rising counting segment corresponds to a highest point, and the falling counting segment corresponds to a lowest point. S2: When the slave receives a high-level signal, obtain the current counting direction of the slave and adjust the real-time counting point of the slave counting cycle according to the counting direction, so that after a preset number of counting cycles, when the master is at the highest point of the upper edge, the difference between the real-time counting point of the slave counting cycle and the highest point of the master upper edge is within a preset range.

[0021] Step S2 specifically includes: S21: When the slave device receives a high-level signal, determine whether the current counting direction of the slave device is an upward counting segment. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device corresponding to the counting cycle and the highest point of the master device's upper edge is within a preset range; if not, proceed to the next step. S22: Determine whether the real-time count point corresponding to the slave device when it receives a high-level signal is greater than the set value. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually decrease the real-time count point of each PWM wave corresponding to the counting cycle, so that after preset number of counting cycles, when the master device is at the highest point of the rising edge, the difference between the real-time count point of the slave device corresponding to the counting cycle and the highest point of the master device's rising edge is within the preset range. If not, proceed to the next step. S23: Under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within the preset range.

[0022] This invention outputs PWM waves to both the master and slave devices via a controller. During PWM wave output, timers in both the master and slave devices acquire the real-time count points corresponding to the current counting cycle of the PWM wave. When the master device's real-time count point reaches its upper limit, a high-level signal is output to the master device's first output circuit via a microcontroller. Upon receiving the high-level signal, the slave device adjusts its real-time count point according to its counting direction. This ensures that after a preset number of counting cycles, the difference between the slave device's real-time count point and the master device's upper limit when the master device reaches its upper limit is within a preset range. By adjusting the slave device's real-time count point when the master device reaches its upper limit over multiple counting cycles, the time base difference between the slave and master devices remains within a preset range. This avoids the problem of large AC current waveform differences between the master and slave devices due to excessive time base differences, thus preventing the parallel overcurrent problem in the energy storage inverter caused by current mutual injection between the master and slave devices due to large AC current waveform differences.

[0023] Example 3 like Figure 5 As shown, this invention also proposes a time-base synchronization control system, applied to the above-described parallel energy storage inverter system, comprising: The counting module is used to output PWM waves to the master and slave devices through the controller. When outputting PWM waves, the timers in the master and slave devices respectively obtain the real-time counting points corresponding to the current counting cycle of the PWM wave. When the real-time counting point of the master device reaches the highest point of the upper edge, the microcontroller outputs a high-level signal to the first output circuit of the master device. At this time, the slave device receives the high-level signal through the second output circuit. One PWM wave corresponds to one counting cycle, and one counting cycle includes a rising counting segment and a falling counting segment. The rising counting segment corresponds to a highest point of the upper edge, and the falling counting segment corresponds to a lowest point of the lower edge. The time base synchronization module is used to obtain the current counting direction of the slave device when the slave device receives a high-level signal, and adjust the real-time counting point of the slave device's counting cycle according to the counting direction, so that after a preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range.

[0024] The time base synchronization module specifically includes a first synchronization unit, a second synchronization unit, and a third synchronization unit, wherein: The first synchronization unit is used to determine whether the current counting direction of the slave device is an upward counting segment when the slave device receives a high-level signal. If so, it gradually increases the real-time counting point of each PWM wave corresponding to the counting cycle under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range; if not, it enters the second synchronization unit. The second synchronization unit is used to determine whether the real-time count point corresponding to the slave device when it receives a high-level signal is greater than a set value. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, the real-time count point of each PWM wave corresponding to the counting cycle is gradually reduced so that after preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time count point of the slave device corresponding to the counting cycle and the highest point of the master device's upper edge is within a preset range. If not, the process proceeds to the third synchronization unit. The third synchronization unit is used to gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range.

[0025] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of the components in a specific posture (as shown in the attached figures). If the specific posture changes, the directional indication will also change accordingly. Furthermore, descriptions involving "first," "second," or "a" in the present invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. In the description of the present invention, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly defined. In the present invention, unless otherwise explicitly specified and defined, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise explicitly defined. For those skilled in the art, the specific meanings of the above terms in this invention can be understood according to the specific circumstances. Furthermore, the technical solutions of the various embodiments of this invention can be combined with each other, but only on the basis that those skilled in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

Claims

1. A parallel energy storage inverter system, characterized in that, The system includes a master unit and several slave units, both of which are energy storage inverters. The positive terminals of the power supplies of the master and slave units are connected in parallel and then connected to a battery pack. The negative terminals of the power supplies of the master and slave units are also connected in parallel and then connected to the battery pack to ensure that the DC bus voltages of the master and slave units are consistent. The master and slave units are connected via a SYNC interface. Both the master and slave units include a time base communication circuit. The time base communication circuit includes a first output circuit and a second output circuit with unidirectional output. The first and second output circuits of the master unit are connected to the SYNC bus. The first and second output circuits of each slave unit are also connected to the SYNC bus. The first phase line of the host is connected in parallel with the first phase line of the slave. The second phase line of the host is connected in parallel with the second phase line of the slave. The neutral wire of the host and the neutral wire of the slave are connected in parallel and then grounded; The first output circuit specifically includes: The fourth optocoupler has its second pin connected to one end of a second 221 resistor, a second 228 resistor, and the collector of a third transistor. The other end of the second 221 resistor is connected to both the positive power supply and one end of a second 57 capacitor. The other end of the second 57 capacitor is grounded. The third pin of the fourth optocoupler is connected to both the other end of the second 228 resistor and one end of a second 229 resistor. The other end of the second 229 resistor is grounded. The emitter of the third transistor is grounded and connected to one end of a second 60 capacitor. The other end of the second 60 capacitor is connected to one end of a second 227 resistor, the cathode of a first diode, and the base of the third transistor. The other end of the second 227 resistor is connected to a first microcontroller, one end of a fourth 5 resistor, and the first port of a seventh connector. The anode of the first diode is connected to the other end of the fourth 5 resistor. The second port of the seventh connector is grounded. The second 26 resistor has one end connected to the power supply, and simultaneously connected to one end of the second 25 resistor and one end of the second 58 capacitor. After being connected to one end of the second 225 resistor, it is connected to the eighth pin of the fourth 4 optocoupler. The other end of the second 58 capacitor is grounded. The other end of the second 225 resistor is simultaneously connected to the seventh pin of the fourth 4 optocoupler and one end of the third 1 capacitor. The other end of the third 1 capacitor is connected to the fifth pin of the fourth 4 optocoupler, and simultaneously connected to one end of the third 2 capacitor, the collector of the second transistor, and grounded. The other end of the second 26 resistor is simultaneously connected to the sixth pin of the fourth 4 optocoupler, the other end of the third 2 capacitor, and the base of the second transistor. The emitter of the second transistor is connected to the second output circuit.

2. The parallel system of energy storage inverters according to claim 1, characterized in that, The second output circuit specifically includes: The second 32 resistor has one end connected to the emitter of the second transistor in the first output circuit; the other end of the second 32 resistor is connected to one end of the fifth 9 capacitor and the fourth 7 resistor, and then connected to the third pin of the fourth 5 optocoupler; the other end of the fourth 7 resistor is simultaneously connected to the other end of the fifth 9 capacitor, the second pin of the fourth 5 optocoupler, and the power supply terminal. The second 31 resistor has one end connected to the positive power supply, and simultaneously connected to one end of the second 30 resistor and the eighth pin of the fourth 5 optocoupler; the other end of the second 30 resistor is connected to the sixth pin of the fourth 5 optocoupler, and simultaneously connected to the second microcontroller, and then connected to the third port of the seventh connector after being connected to the second microcontroller; the other end of the second 31 resistor is also connected to the seventh pin of the fourth 5 optocoupler and one end of the sixth 2 capacitor; the other end of the sixth 2 capacitor is connected to the fifth pin of the fourth 5 optocoupler and then grounded.

3. A time-base synchronization control method, applied to the parallel energy storage inverter system according to any one of claims 1 to 2, characterized in that, Including the following steps: S1: The controller outputs PWM waves to the master and slave devices. When outputting PWM waves, the timers in the master and slave devices respectively obtain the real-time count points corresponding to the current counting cycle of the PWM wave. When the real-time count point of the master device reaches the highest point of the upper edge, the microcontroller outputs a high-level signal to the first output circuit of the master device. At this time, the slave device receives the high-level signal through the second output circuit. One PWM wave corresponds to one counting cycle. One counting cycle includes a rising counting segment and a falling counting segment. The rising counting segment corresponds to a highest point of the upper edge, and the falling counting segment corresponds to a lowest point of the lower edge. S2: When the slave receives a high-level signal, obtain the current counting direction of the slave and adjust the real-time counting point of the slave counting cycle according to the counting direction, so that after a preset number of counting cycles, when the master is at the highest point of the upper edge, the difference between the real-time counting point of the slave counting cycle and the highest point of the master upper edge is within a preset range.

4. The time base synchronization control method according to claim 3, characterized in that, Step S2 specifically includes: S21: When the slave device receives a high-level signal, determine whether the current counting direction of the slave device is an upward counting segment. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device corresponding to the counting cycle and the highest point of the master device's upper edge is within a preset range; if not, proceed to the next step. S22: Determine whether the real-time count point corresponding to the slave device when it receives a high-level signal is greater than the set value. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually decrease the real-time count point of each PWM wave corresponding to the counting cycle, so that after preset number of counting cycles, when the master device is at the highest point of the rising edge, the difference between the real-time count point of the slave device corresponding to the counting cycle and the highest point of the master device's rising edge is within the preset range. If not, proceed to the next step. S23: Under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within the preset range.

5. A time-base synchronization control system, applied to the parallel energy storage inverter system according to any one of claims 1 to 2, characterized in that, include: The counting module is used to output PWM waves to the master and slave devices through the controller. When outputting PWM waves, the timers in the master and slave devices respectively obtain the real-time counting points corresponding to the current counting cycle of the PWM wave. When the real-time counting point of the master device reaches the highest point of the upper edge, the microcontroller outputs a high-level signal to the first output circuit of the master device. At this time, the slave device receives the high-level signal through the second output circuit. One PWM wave corresponds to one counting cycle. One counting cycle includes a rising counting segment and a falling counting segment. The rising counting segment corresponds to a highest point of the upper edge, and the falling counting segment corresponds to a lowest point of the lower edge. The time base synchronization module is used to obtain the current counting direction of the slave device when the slave device receives a high-level signal, and adjust the real-time counting point of the slave device's counting cycle according to the counting direction, so that after a preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range.

6. A time-base synchronization control system according to claim 5, characterized in that, The time base synchronization module specifically includes a first synchronization unit, a second synchronization unit, and a third synchronization unit, wherein: The first synchronization unit is used to determine whether the current counting direction of the slave device is an upward counting segment when the slave device receives a high-level signal. If so, it gradually increases the real-time counting point of each PWM wave corresponding to the counting cycle under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, so that after the preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time counting point of the slave device's counting cycle and the highest point of the master device's upper edge is within a preset range; if not, it enters the second synchronization unit. The second synchronization unit is used to determine whether the real-time count point corresponding to the slave device when it receives a high-level signal is greater than a set value. If so, under the current PWM wave of the slave device and under the subsequent preset number of PWM waves, the real-time count point of each PWM wave corresponding to the counting cycle is gradually reduced so that after preset number of counting cycles, when the master device is at the highest point of the upper edge, the difference between the real-time count point of the slave device corresponding to the counting cycle and the highest point of the master device's upper edge is within a preset range. If not, the process proceeds to the third synchronization unit. The third synchronization unit is used to gradually increase the real-time counting point of each PWM wave corresponding to the counting cycle under the current PWM wave of the slave and under the subsequent preset number of PWM waves, so that after the preset number of counting cycles, when the master is at the highest point of the upper edge, the difference between the real-time counting point of the slave counting cycle and the highest point of the upper edge of the master is within a preset range.

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