An integrated circuit having a fault reporting structure

Abstract

An integrated circuit (IC) having a fault reporting structure includes at least one power metal oxide semiconductor field effect transistor (MOSFET). The at least one power MOSFET includes a plurality of MOSFET cells, each MOSFET cell including a drain metal and a source metal, the IC including a power MOSFET region for routing of the plurality of drain metals and the plurality of source metals of the plurality of MOSFET cells. The fault reporting structure includes a metal mesh within or above or below the power MOSFET region or within or above or below a routing of the power MOSFET region. The fault reporting structure further includes a fault reporting pin coupled to the metal mesh, providing a fault signal to indicate whether the IC is in a normal state or a fault state. The fault reporting structure is capable of reporting catastrophic failures such as burnout occurring inside the IC.

Description

Technical Field

[0001] Embodiments of the present invention relate to an electronic circuit, and more specifically, to a fault reporting structure. Background Technology

[0002] In highly integrated power solutions, integrated circuits (ICs) typically include fault reporting structures to report fault events. However, in some cases, such as when a catastrophic failure occurs, like a region within the IC burning out (e.g., due to excessive electrical stress), meaning a burn-out point forms within the IC, the fault event cannot be reported. For example, fault reporting functionality can be implemented by coupling a fault reporting pin to an open-drain metal-oxide-semiconductor field-effect transistor (MOSFET). When the open-drain MOSFET is pulled up to a bias voltage VDD, the fault reporting pin provides a fault signal to indicate the occurrence of the fault. However, if the bias voltage VDD, or even the open-drain MOSFET itself, is damaged, the fault cannot be reported.

[0003] Therefore, a method is needed that can at least solve the above problems. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an integrated circuit and its fault reporting structure.

[0005] According to embodiments of the present invention, a fault reporting structure is provided for an integrated circuit (IC) having at least one power metal-oxide-semiconductor field-effect transistor (MOSFET), wherein the at least one power MOSFET comprises a plurality of MOSFET cells, each MOSFET cell comprising drain metal and source metal, and the IC includes a power MOSFET region for wiring of a plurality of drain metals and a plurality of source metals of the plurality of MOSFET cells. The fault reporting structure includes a metal mesh and fault reporting pins. The metal mesh is located within or above or below the power MOSFET region, and the fault reporting pins are coupled to the metal mesh to provide a fault signal indicating whether the IC is in a normal state or a fault state.

[0006] According to an embodiment of the present invention, an IC is provided, including a first fault reporting structure and a second fault reporting structure. The first fault reporting structure includes a first fault reporting pin, providing a first fault reporting signal to indicate whether the IC is in a first fault state. The second fault reporting structure includes a second fault reporting pin, providing a second fault reporting signal to indicate whether the IC is in a second fault state.

[0007] According to an embodiment of the present invention, a fault reporting structure for an IC is provided, wherein the IC includes at least one metal layer, and the fault reporting structure includes: a metal mesh embedded within the at least one metal layer and fault reporting pins coupled to the metal mesh. The fault reporting pins provide a fault signal to indicate whether the IC is in a normal state or a fault state. When the IC is operating normally, the metal mesh floats inside the IC.

[0008] The fault reporting structure according to an embodiment of the present invention can report catastrophic faults such as burn-out inside the IC. Attached Figure Description

[0009] To better understand this invention, it will be described in detail with reference to the following drawings. Identical or similar elements are referred to by the same reference numerals.

[0010] Figure 1 A plan view of a portion of an integrated circuit (IC) 100 according to an embodiment of the present invention is shown.

[0011] Figure 2 An embodiment of the present invention is shown. Figure 1 An exemplary block diagram of IC100.

[0012] Figure 3 A cross-sectional view of a portion of an exemplary layout of an IC100 having multiple metal layers according to an embodiment of the present invention is shown.

[0013] Figure 4 An embodiment of the present invention is shown. Figure 2 An exemplary layout of a portion of IC100.

[0014] Figure 5 A plan view of a partial layout of IC200 according to an embodiment of the present invention is shown.

[0015] Figure 6 An embodiment of the present invention is shown. Figure 2 An exemplary layout plan of a portion of IC200.

[0016] Figure 7 Another IC300 according to an embodiment of the present invention is shown.

[0017] Figure 8 An IC400 according to an embodiment of the present invention is shown. Detailed Implementation

[0018] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0019] Figure 1 A plan view of a portion of an integrated circuit (IC) 100 according to an embodiment of the present invention is shown. IC 100 includes at least one power metal-oxide-semiconductor field-effect transistor (MOSFET), each power MOSFET including a plurality of MOSFET cells, each MOSFET cell including a drain metal D and a source metal S. Those skilled in the art will understand that, for clarity of description, Figure 1 Only a portion of each MOSFET cell is shown.

[0020] Those skilled in the art will understand that at least one power MOSFET in IC100 may include one, two, four, or any number of power MOSFETs, depending on the topology and specific design of IC100. For example, in one embodiment, IC100 includes a power IC, which includes, for example, drive circuitry and power metal-oxide-semiconductor field-effect transistors, having a synchronous buck converter topology. The at least one power MOSFET may include a high-side power MOSFET for receiving an input voltage, and the at least one power MOSFET may further include a low-side power MOSFET coupled to a power ground.

[0021] Those skilled in the art will understand that, in one embodiment, the MOSFET described in this invention can be a MOSFET capable of handling large currents (e.g., amperes) compared to other MOSFETs with weaker current handling capabilities (e.g., microamps or milliamps).

[0022] Figure 2 An embodiment of the present invention is shown. Figure 1 An exemplary block diagram of IC100 is shown below. Figure 2 As shown, IC100 may include an output stage 101, a driver stage 102, and a control circuit 103. The output stage 101 includes at least one MOSFET coupled to the input voltage Vin or power ground PGND. The driver stage 102 drives at least one MOSFET of the output stage 101. In such an embodiment, the power MOSFET in this invention may refer to at least one MOSFET of the output stage 101, and other MOSFETs may refer to the MOSFETs of the control circuit 103 and / or the driver stage 102.

[0023] Furthermore, in one embodiment, Figure 2 IC100 may include a power IC with a synchronous Buck converter topology, and output stage 101 may include a high-side MOSFET and a low-side MOSFET. Both the high-side and low-side MOSFETs have a first terminal, a second terminal, and a control terminal, wherein the first terminal of the high-side MOSFET receives the input signal Vin, the first terminal of the low-side MOSFET is coupled to the second terminal of the high-side MOSFET, and the second terminal of the low-side MOSFET is coupled to power ground PGND. The control terminals of the high-side and low-side MOSFETs are driven by driver stage 102. In such an embodiment, the power MOSFET of the present invention may refer to the high-side MOSFET and / or low-side MOSFET of output stage 101 in the power IC, and other MOSFETs may refer to the MOSFETs of control circuit 103 and driver stage 102 in the power IC.

[0024] In one embodiment, Figure 1 The drain metal D in the illustrated IC100 can be routed within multiple metal layers of the IC100. The portions of the drain metal D routed within different metal layers can be coupled vias or other conductive coupling structures. Further, in one embodiment, the multiple metal layers may include a redistribution layer (RDLLayer) and / or an under-bump metallization layer (UBM layer), and the drain metal D may include portions routed within the redistribution layer and / or the UBM layer. Similarly, in one embodiment, the source metal S can be routed within multiple metal layers of the IC100. The portions of the source metal S routed within different metal layers of the IC100 can be coupled vias or other conductive coupling structures. Further, in one embodiment, the source metal S may include portions routed within the redistribution layer and / or the UBM layer.

[0025] Continue to refer to Figure 1 IC100 includes a power MOSFET region for wiring the drain and source metals of multiple MOSFET cells. In one embodiment, the power MOSFET region may refer to a portion of a larger region for wiring all the power MOSFETs of IC100. In another embodiment, the drain metal D and source metal S of each MOSFET cell are wired within the plurality of metal layers, and the power MOSFET region may refer to a region of a single metal layer among the plurality of metal layers for wiring corresponding portions of the plurality of drain metals and plurality of source metals in the plurality of MOSFET cells.

[0026] Figure 3 A cross-sectional view of a portion of an exemplary layout of an IC100 having multiple metal layers according to an embodiment of the present invention is shown. Figure 3 As shown, IC100 includes multiple metal layers M1, M2, M3, and M4, where metal layer M4 is a redistribution layer. Multiple drain metals and multiple source metals of the multiple MOSFET cells are routed within the multiple metal layers M1, M2, M3, and M4. Portions of the drain metals and source metals within metal layers M1, M2, M3, and M4 are coupled through one or more vias. In such an embodiment, the power MOSFET region may refer to the region within metal layers M1, M2, M3, and M4 where corresponding portions of the multiple drain metals and multiple source metals of the multiple MOSFET cells are routed.

[0027] In one embodiment, in Figure 2 In the IC100 shown, the drain and source metals of the plurality of MOSFET units of at least one power MOSFET of the output stage 101 are wired in the power MOSFET region, but the drain and source metals of the MOSFETs of the control circuit 103 and the drive stage 102 in the IC100 are not wired in the power MOSFET region. Figure 4 An embodiment of the present invention is shown. Figure 2 An exemplary layout of a portion of IC100. (e.g.) Figure 4 As shown, IC100 includes a first region AD for wiring of the driver stage 102, a second region AC for wiring of the control circuit 103, and a third region AO for wiring of the output stage 101. In such an embodiment, the power MOSFET region refers to the third region AO or a portion of the third region AO.

[0028] Furthermore, in one embodiment, Figure 4 IC100 may further include additional regions for wiring of output stage 101 or other portions of IC100. For example, in one embodiment, IC100 includes a power IC comprising a synchronous buck converter topology, and IC100 may include a third region AO for high-side MOSFET wiring and a fourth region AO' for low-side MOSFET wiring. Those skilled in the art will understand that: Figure 4 The layout of IC100 is for illustrative purposes only. Areas AD, AC, AO and / or AO' can be arranged in different ways, depending on the specific design of IC100.

[0029] Continue to refer to Figure 1IC100 includes a fault reporting structure. The fault reporting structure includes a metal mesh NT and a fault reporting pin FLT. The metal mesh NT is routed within the power MOSFET region. The fault reporting pin FLT is coupled to the metal mesh NT to provide a fault signal SFLT, indicating whether IC100 is in a normal or fault state. In one embodiment, the fault reporting pin FLT is coupled to the metal mesh NT via a via, solder joint, or any other conductive coupling structure or combination thereof. In another embodiment, the fault state refers to a catastrophic failure such as a region burn-out within IC100 (e.g., caused by excessive electrical stress), or the formation of a burn-out point in IC100. In other words, the fault state refers to a catastrophic failure of IC100, whereby IC100 burns out. In yet another embodiment, the metal mesh NT is electrically isolated from the drain metal and source metal of multiple MOSFET cells of at least one power MOSFET.

[0030] In another embodiment, the metal mesh NT can be routed in an area above or below the power MOSFET region. In another embodiment, the metal mesh NT can be routed in an area directly above or below the power MOSFET region. In yet another embodiment, the metal mesh NT can be routed within a single metal layer or more, said metal layers being used solely for the routing of the metal mesh NT.

[0031] exist Figure 1 In the IC100 shown, the metal mesh NT has a finger-like structure, wherein multiple fingers F1, ..., F5 are parallel to multiple drain metals and multiple source metals of multiple MOSFET units. Figure 1 In this configuration, a finger of the metal mesh NT is placed every other pair of drain and source metals. For example... Figure 5 As shown, in another embodiment, a finger of the metal mesh NT is placed every two or more pairs of drain metal and source metal.

[0032] Figure 6 An embodiment of the present invention is shown. Figure 2 An exemplary layout plan of a portion of IC200 is shown below. In IC200, the metal mesh NT has a serpentine structure, and the fault reporting pin FLT can be connected to any location on the metal mesh NT, depending on design requirements. In another embodiment, the metal mesh NT is in a grid shape.

[0033] Those skilled in the art should understand that: Figure 1 and Figure 6 The diagram shows an exemplary shape of the metal mesh NT. However, other shapes of metal mesh NTs can also be used, as long as the structure of the metal mesh NT meets the following condition: when a burn-out point occurs in IC100, at least a portion of the metal mesh NT is burned out, thereby short-circuiting the metal mesh NT to ground.

[0034] Using the fault reporting structure of this invention, when IC100 is operating, the fault reporting pin FLT of IC100 is externally coupled to the fault detection pin of the control IC, thereby reporting the status of IC100 through the fault signal SFLT. The control IC injects current from the fault monitoring pin to the impedance formed between the fault reporting pin FLT and ground. When IC100 is in a normal state, current flows into the impedance, and the voltage on the fault reporting pin FLT is high; however, when IC100 is in a fault state and a burnt-out point appears within IC100, at least a portion of the metal mesh NT of the fault reporting structure is also burned out, thus short-circuiting the metal mesh NT to ground, causing the voltage on the fault reporting pin FLT to be low. In this way, the fault reporting structure of this invention can report whether IC100 is in a normal state or a fault state.

[0035] Figure 7 Another IC300 according to an embodiment of the present invention is shown. For example... Figure 7 As shown, IC300 includes a first fault reporting structure, which includes a first fault reporting pin FLT and provides a first fault signal SFLT to indicate whether IC300 is in a first fault state. IC300 further includes a second fault reporting structure, which includes a second fault reporting pin FLT' and provides a second fault signal SFLT' to indicate whether IC300 is in a second fault state.

[0036] In one embodiment, the first fault state refers to a burn-out point within IC300. In other words, the first fault state refers to a catastrophic failure where IC300 burns out. The second fault state refers to an overcurrent event, overvoltage event, or overtemperature event occurring within IC300. In one embodiment, the second fault state may indicate any one of the overcurrent event, overvoltage event, or overtemperature event. In another embodiment, the second fault state may indicate multiple of the overcurrent event, overvoltage event, and overtemperature event.

[0037] like Figure 7 As shown, the first fault report structure further includes a metal mesh NT embedded within the metal layer of IC300, and the first fault report pin FLT is coupled to the metal mesh NT. Those skilled in the art will understand that... Figure 7In the illustrated embodiment, the metal mesh NT can be implemented using the metal mesh in any embodiment of the present invention, which will not be repeated here for clarity. The second fault reporting structure may further include a switch SW. The switch SW includes a first terminal and a second terminal, and the second fault reporting pin FLT' is coupled to the first terminal of the switch SW. Further, in one embodiment, the switch SW may be a MOSFET, including a drain metal coupled to the first terminal of the switch SW and a source metal coupled to the second terminal of the switch SW. In another embodiment, the first terminal of the switch SW is coupled to a bias voltage VDD, and the second terminal of the switch SW is coupled to signal ground SGND. In one embodiment, when IC300 is in the second fault state, the second fault signal SFLT' is high, and when IC300 is not in the second fault state, the second fault signal SFLT' is low. In another embodiment, when IC300 is in the second fault state, the second fault signal SFLT' is low, and when IC300 is not in the second fault state, the second fault signal SFLT' is high. In one embodiment, the metal mesh NT is electrically isolated from the first and second terminals of the switch SW.

[0038] In one embodiment, IC300 may be the power IC described in the above embodiments of the present invention.

[0039] The IC 300 of this invention has a first fault reporting structure and a second fault reporting structure. Therefore, it can report not only second fault states such as overcurrent, overvoltage, or overtemperature, but also the first fault state where a burn-out point has occurred within the IC 300. Specifically, when the second fault reporting structure is implemented by an open-drain MOSFET (a MOSFET with an open drain), whose drain is metal-coupled to the second fault reporting pin and the bias voltage VDD, and the second fault signal is high when the IC 300 is in the second fault state, if the bias voltage VDD is shorted to ground or the open-drain MOSFET is damaged due to a burn-out point, the second fault reporting structure cannot be used to report catastrophic faults. Using the first fault reporting structure of this invention, even if the second fault reporting structure within the IC is damaged, catastrophic faults can still be reported.

[0040] Figure 8 An IC 400 according to an embodiment of the present invention is shown. The IC 400 includes a fault reporting structure and at least one metal layer. The fault reporting structure of the IC 400 includes a metal mesh NT embedded within the at least one metal layer, wherein the metal mesh NT floats within the IC 400 when the IC 400 is operating normally. The IC 400 further includes a fault reporting pin FLT coupled to the metal mesh NT for providing a fault signal SFLT to indicate whether the IC 400 is in a normal or faulty state.

[0041] Those skilled in the art will understand that "the metal mesh NT is floating inside the IC400" means that the metal mesh NT is not coupled to any voltage level inside the IC400. Figure 8 As shown, in one embodiment, the fault reporting pin FLT is coupled to the fault detection pin DFLT of the control IC CIC, and IC400 provides a fault signal SFLT to the control IC CIC. In such an embodiment, the control IC CIC provides a current I to the fault reporting pin FLT of IC400 through the fault detection pin DFLT, thereby coupling the metal mesh NT to the level of the fault reporting pin FLT. In this case, although the metal mesh NT is coupled to the level of the fault reporting pin FLT when current I flows into the fault reporting pin FLT, it is still considered to be floating inside IC400 because the metal mesh NT is not coupled to any level inside IC400. In one embodiment, the fault detection pin of the control IC CIC is a general purpose input / output pin that can be used for general analog voltage sampling.

[0042] like Figure 8 As shown, IC400 may further include a MOSFET M, which includes drain metal and source metal. The drain metal of MOSFET M is coupled to another fault reporting pin FLT' and the bias voltage VDD. The fault reporting pin FLT' is used to report another fault condition. The source metal of MOSFET M is coupled to signal ground SGND. The other fault reporting pin FLT' is also coupled to the control IC CIC to report another fault condition. Comparing the metal mesh NT and MOSFET M, it can be found that the metal mesh NT is floating inside IC400, while MOSFET M is coupled to the bias voltage VDD inside IC400.

[0043] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A fault reporting structure for an IC including at least one power MOSFET, wherein the at least one power MOSFET includes a plurality of MOSFET cells, each MOSFET cell including a drain metal and a source metal, the IC including a power MOSFET region, and wiring for a plurality of drain metals and a plurality of source metals of the plurality of MOSFET cells, the fault reporting structure comprising: A metal mesh is routed within or above or below the power MOSFET region, such that the metal mesh can at least partially burn out and short-circuit to ground in the event of a burn-out point within the IC. as well as A fault reporting pin, coupled to the metal mesh, provides a fault signal to indicate whether the IC is in a normal or faulty state.

2. The fault reporting structure as claimed in claim 1, wherein the metal mesh is electrically isolated from the plurality of drain metals and the plurality of source metals.

3. The fault reporting structure as claimed in claim 1, wherein the metal mesh includes a finger structure, the finger structure including a plurality of metal fingers parallel to the plurality of drain metals and the plurality of source metals.

4. The fault reporting structure as claimed in claim 1, wherein the metal mesh comprises a serpentine structure.

5. The fault reporting structure as claimed in claim 1, wherein the IC includes a plurality of metal layers, the drain metal and source metal of each MOSFET unit are wired within the plurality of metal layers, and the power MOSFET region includes a region of a single metal layer among the plurality of metal layers for wiring of corresponding portions of the plurality of drain metals and the plurality of source metals.

6. The fault reporting structure of claim 1, wherein the power MOSFET region includes a portion of a larger region for wiring all power MOSFETs within the IC.

7. The fault reporting structure of claim 1, wherein the IC further includes an open-drain MOSFET, the open-drain MOSFET including drain metal and source metal, the drain metal of the open-drain MOSFET being coupled to a bias voltage for reporting another fault state of the IC, the source metal of the open-drain MOSFET being coupled to a signal ground, wherein the power MOSFET region is not used for wiring the drain metal and source metal of the open-drain MOSFET.

8. An IC, comprising: A first fault reporting structure includes a metal mesh and a first fault reporting pin coupled to the metal mesh, the first fault reporting pin providing a first fault reporting signal to indicate whether the IC is in a first fault state, wherein the metal mesh is configured to at least partially burn out and short-circuit to ground when there is a burn-out point in the IC. as well as The second fault reporting structure includes a second fault reporting pin, which provides a second fault reporting signal to indicate whether the IC is in a second fault state.

9. The IC of claim 8, wherein the IC includes at least one metal layer, the metal mesh is embedded in the at least one metal layer, and the second fault reporting structure further includes a switch, the switch including a first terminal and a second terminal, wherein the first terminal is coupled to a bias voltage, the second terminal is coupled to a signal ground, and the second fault reporting pin is coupled to the first terminal of the switch.

10. The IC of claim 9, wherein the switch comprises a MOSFET having a drain metal coupled to a first terminal and a source metal coupled to a second terminal.

11. The IC of claim 9, wherein the metal mesh is electrically isolated from the first and second terminals of the switch.

12. The IC of claim 8, wherein the first fault condition indicates a burnt-out point within the IC.

13. The IC of claim 12, wherein the second fault state indicates that an overcurrent, overvoltage, or overtemperature has occurred within the IC.

14. The IC of claim 8, including a power IC.

15. A fault reporting structure for an IC, wherein the IC includes at least one metal layer, the fault reporting structure comprising: A metal mesh embedded within the at least one metal layer; as well as The first fault reporting pin is coupled to the metal mesh and provides a fault signal to indicate whether the IC is in a normal or faulty state. in When the IC is working normally, the metal mesh floats inside the IC; as well as When there is a burnt point in the IC, at least a portion of the metal mesh is burned out, and the metal mesh is short-circuited to ground.

16. The fault reporting structure as described in claim 15, wherein the first fault reporting pin is externally connected to a fault detection pin of a control IC to control the IC.

17. The fault reporting structure of claim 16, wherein the control IC provides a current to the first fault reporting pin via a fault detection pin.

18. The fault reporting structure as described in claim 16, wherein the fault detection pin is a general purpose input / output pin.

19. The fault reporting structure of claim 15, wherein the IC further includes a second fault reporting pin and a MOSFET, the MOSFET including drain metal and source metal, the drain metal of the MOSFET being coupled to the second fault reporting pin to report another fault state of the IC, the drain metal of the MOSFET being further coupled to a bias voltage, and the source metal of the MOSFET being coupled to signal ground.

Images