An ots gating device silicon equivalent circuit

Abstract

The application relates to an OTS gating device silicon equivalent circuit, which comprises a state control module and a gating module; the state control module is used for comparing a voltage difference between a positive electrode and a negative electrode of the OTS gating device silicon equivalent circuit and an externally input OTS threshold voltage or holding voltage according to a current state of the OTS gating device silicon equivalent circuit, and judging the state of the OTS gating device silicon equivalent circuit at the next moment according to a comparison result; and the gating module is used for realizing simulation of an OTS gating device switching process through two MOS devices according to an output of the state control module. The application can simulate the working state of the OTS gating device in a circuit.

Description

Technical Field

[0001] This invention relates to the field of microelectronics, and in particular to a silicon equivalent circuit for an OTS gating device. Background Technology

[0002] OTS (Optical Switching Transistor) is a gating device used in high-density new memory. It has advantages such as high integration, large switching ratio, long lifespan, and strong driving capability, making it an indispensable component for realizing high-density storage, especially new three-dimensional memory. However, the integration process of OTS is quite difficult, and process development requires a long time. Before the device process matures, the related circuit design cannot be verified through tape-out, which seriously restricts the synchronous development of device process and circuit, and prolongs the product development cycle. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a silicon equivalent circuit for an OTS gating device that can simulate the working state of the OTS gating device in the circuit.

[0004] The technical solution adopted by this invention to solve its technical problem is as follows: An OTS gating device silicon equivalent circuit is provided, including a state control module and a gating module. The state control module is used to compare the voltage difference between the positive and negative terminals of the OTS gating device silicon equivalent circuit with an externally input OTS threshold voltage or holding voltage based on the current state of the OTS gating device silicon equivalent circuit, and determine the state of the OTS gating device silicon equivalent circuit at the next moment based on the comparison result. The gating module is used to simulate the switching process of the OTS gating device through two MOS devices based on the output of the state control module.

[0005] The state control module includes an analog switch selector, a comparator, and a D flip-flop. The two inputs of the analog switch selector are connected to the OTS threshold voltage and the holding voltage, respectively. Its output is connected to the inverting input of the comparator, and its selection input is connected to the output of the D flip-flop. The non-inverting input of the comparator is connected to the positive terminal of the silicon equivalent circuit of the OTS gating device. Its output is divided into two paths: one path is connected to the clock input of the D flip-flop via a first inverter, and the other path is connected to the reset input of the D flip-flop via a falling edge detection module. The input of the D flip-flop is connected to the power supply voltage, and its output serves as the output of the state control module, connected to the gating module.

[0006] The falling edge detection module includes a third inverter, a delay, an XOR gate, an AND gate, and an OR gate. The input of the third inverter is connected to the output of the comparator. The first input of the XOR gate is connected to the output of the third inverter through the delay, and the second input is directly connected to the output of the third inverter. The first input of the AND gate is connected to the output of the XOR gate, and the second input is connected to the output of the third inverter. The first input of the OR gate is connected to an external reset signal, the second input is connected to the output of the AND gate, and the output of the OR gate is connected to the reset terminal of the D flip-flop.

[0007] When the silicon equivalent circuit of the OTS gate device is currently in the off state, the output of the D flip-flop is low, and the analog switch selector transmits the OTS threshold voltage to the inverting input of the comparator. When the voltage difference between the positive and negative terminals of the silicon equivalent circuit of the OTS gate device rises above the OTS threshold voltage, the comparator output changes from low to high, and a falling edge is generated by the first inverter. The D flip-flop outputs a high level, and the silicon equivalent circuit of the OTS gate device enters the on state.

[0008] When the silicon equivalent circuit of the OTS gate device is in the on state, the output of the D flip-flop is high, and the analog switch selector transmits the holding voltage to the inverting input of the comparator. When the voltage difference between the positive and negative terminals of the silicon equivalent circuit of the OTS gate device drops below the holding voltage, the comparator output changes from high to low, and a brief voltage pulse is generated by the falling edge detection module to reset the D flip-flop to low, and the silicon equivalent circuit of the OTS gate device enters the off state.

[0009] The gating module includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the output terminal of the state control module, the source serves as the negative terminal of the silicon equivalent circuit of the OTS gating device, and the drain is connected to one end of a first resistor, the other end of which serves as the positive terminal of the silicon equivalent circuit of the OTS gating device. The gate of the second MOS transistor is connected to the output terminal of the state control module through a second inverter, the source is connected to the negative terminal of the silicon equivalent circuit of the OTS gating device, and the drain is connected to one end of a second resistor, the other end of which is connected to the positive terminal of the silicon equivalent circuit of the OTS gating device. The resistance of the first resistor is greater than the resistance of the second resistor.

[0010] The OTS drive capability of the silicon equivalent circuit of the OTS gate device is adjusted by adjusting the size of the first MOSFET and the resistance value of the first resistor; the OTS leakage current of the silicon equivalent circuit of the OTS gate device is adjusted by adjusting the size of the second MOSFET and the resistance value of the second resistor.

[0011] The resistance value of the first resistor is set to the OTS equivalent on-state resistance, and the resistance value of the second resistor is set to the OTS equivalent off-state resistance.

[0012] Beneficial effects

[0013] By adopting the above-mentioned technical solution, this invention has the following advantages and positive effects compared with the prior art: This invention uses traditional MOS circuit technology, and can simulate the working state of the OTS gating device in the circuit by simulating a switch selector, comparator, D flip-flop, and combinational logic circuit module. Before the integration technology of the OTS gating device matures, the OTS silicon equivalent circuit of this invention can be used to perform tape-out verification of novel memory circuits, realizing the simultaneous development of device technology and circuits, and shortening the R&D cycle of products using OTS gating devices. This invention also incorporates an automatic shutdown function, taking into account the leakage current in the shutdown state. Attached Figure Description

[0014] Figure 1 This is a circuit diagram of an embodiment of the present invention;

[0015] Figure 2 These are simulation results obtained using the embodiments of the present invention;

[0016] Figure 3 This is a simulation environment diagram of the silicon equivalent circuit of the OTS gating device according to the embodiments of the present invention. Detailed Implementation

[0017] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0018] Embodiments of the present invention relate to a silicon equivalent circuit for an OTS gating device, such as... Figure 1As shown, it includes a state control module and a gating module. The state control module is used to compare the voltage difference Vdevice between the positive and negative terminals of the OTS gating device silicon equivalent circuit with the externally input OTS threshold voltage Vth or holding voltage Vhold based on the current state of the OTS gating device silicon equivalent circuit, and determine the state of the OTS gating device silicon equivalent circuit at the next moment based on the comparison result. The gating module is used to simulate the switching process of the OTS gating device through two MOS devices based on the output of the state control module.

[0019] The state control module includes an analog switch selector MUX, a comparator Comp, and a D flip-flop D1. The two inputs of the analog switch selector MUX are connected to the OTS threshold voltage Vth and the holding voltage Vhold, respectively. Its output is connected to the inverting input of the comparator Comp, and its selection terminal s is connected to the output of the D flip-flop D1. The non-inverting input of the comparator Comp is connected to the positive terminal VP of the silicon equivalent circuit of the OTS gate device. Its output is divided into two paths: one path is connected to the clock terminal of the D flip-flop D1 via a first inverter INV1, and the other path is connected to the reset terminal of the D flip-flop D1 via a falling edge detection module. The input of the D flip-flop D1 is connected to the power supply voltage V. DD The output terminal is connected to the gating module, serving as the output terminal of the state control module.

[0020] The analog switch selector MUX transmits the externally input threshold voltage Vth or holding voltage Vhold to the comparator Comp based on the current state of the OTS. The comparator Comp compares the voltage difference Vdevice between the positive terminal VP and the negative terminal VN of the OTS with the voltage output by the analog switch selector MUX. The comparison result of Comp is processed by combinational logic circuitry to control the output of D flip-flop D1, thereby controlling the switching of the selection module.

[0021] The falling edge detection module includes a third inverter INV3, a delay, an XOR gate XOR1, an AND gate AND1, and an OR gate OR1. The input of the third inverter INV3 is connected to the output of the comparator Comp. The first input of the XOR gate XOR1 is connected to the output of the third inverter INV3 through the delay, and the second input is directly connected to the output of the third inverter INV3. The first input of the AND gate AND1 is connected to the output of the XOR gate XOR1, and the second input is connected to the output of the third inverter INV3. The first input of the OR gate OR1 is connected to an external reset signal, the second input is connected to the output of the AND gate AND1, and the output of the OR gate OR1 is connected to the reset terminal of the D flip-flop D1.

[0022] When the silicon equivalent circuit of the OTS gating device is currently in the off state, the output of the D flip-flop D1 is low, and the analog switch selector MUX transmits the OTS threshold voltage Vth to the inverting input of the comparator Comp. When the voltage difference Vdevice between the positive terminal VP and the negative terminal VN of the silicon equivalent circuit of the OTS gating device rises above the OTS threshold voltage Vth, the output of the comparator Comp changes from low to high, and a falling edge is generated through the first inverter INV1. The D flip-flop D1 outputs a high level, and the silicon equivalent circuit of the OTS gating device enters the on state.

[0023] When the silicon equivalent circuit of the OTS gate device is in the ON state, the output of the D flip-flop D1 is high, and the analog switch selector MUX transmits the holding voltage Vhold to the inverting input of the comparator Comp. When the voltage difference Vdevice between the positive terminal VP and the negative terminal VN of the silicon equivalent circuit of the OTS gate device drops below the holding voltage Vhold, the output of the comparator Comp changes from high to low, and a brief voltage pulse is generated by the falling edge detection module to reset the D flip-flop D1 to low, and the silicon equivalent circuit of the OTS gate device enters the OFF state.

[0024] The gating module in this embodiment includes a first MOSFET NM1 and a second MOSFET NM2. The gate of the first MOSFET NM1 is connected to the output terminal of the state control module, the source serves as the negative terminal VN of the silicon equivalent circuit of the OTS gating device, and the drain is connected to the first resistor R. on One end is connected, the first resistor R on The other end serves as the positive terminal VP of the silicon equivalent circuit of the OTS gate device; the gate of the second MOS transistor NM2 is connected to the output terminal of the state control module through a second inverter INV2, the source is connected to the negative terminal VN of the silicon equivalent circuit of the OTS gate device, and the drain is connected to the second resistor R. off One end is connected, and the second resistor R off The other end is connected to the positive terminal VP of the silicon equivalent circuit of the OTS gating device. The first resistor R... on The resistance value is greater than that of the second resistor R. off The resistance value of the first resistor R on The resistance value is set to the OTS equivalent on-state resistance, and the second resistor R off The resistance value is set to the OTS equivalent off-state resistance.

[0025] When the silicon equivalent circuit of the OTS gate device is in the ON state, the first MOSFET NM1 is turned on, the second MOSFET NM2 is turned off, and the current flows through the first resistor R. ON The first MOSFET NM1 flows through the silicon equivalent circuit of the OTS gating device, and the size of the first MOSFET NM1 and the first resistor R are adjusted. ON The resistance value can be used to adjust the OTS drive capability of the silicon equivalent circuit of the OTS gate device; when the silicon equivalent circuit of the OTS gate device is in the off state, the first MOSFET NM1 is off, the second MOSFET NM2 is on, and the current flows through the second resistor R. OFF The second MOSFET NM2 flows through the silicon equivalent circuit of the OTS gating device, and the flow is adjusted by modifying the size of the second MOSFET NM2 and the second resistor R. OFF The leakage current of the OTS can be adjusted by changing the resistance value.

[0026] Figure 2 The diagram shows the simulation environment and results obtained using the embodiment of the present invention, where a represents the voltage curve and b represents the current curve. Figure 3 This is a diagram of the specific simulation environment. Through this... Figure 2 It can be seen that the silicon equivalent circuit of the OTS gating device in the embodiments of the present invention is basically the same as that of the real device.

[0027] In addition, this embodiment also includes a Set control signal terminal and a Reset control signal terminal. The Set control signal terminal is connected to the setting terminal of the D flip-flop D1, and the Reset control signal terminal is connected to the first input terminal of the OR gate OR1. The Set control signal terminal and the Reset control signal terminal can force the silicon equivalent circuit of the OTS gating device to enter the on or off state.

[0028] It is easy to see that this invention uses traditional MOS circuit technology to simulate the operating state of the OTS gating device in a circuit by simulating a switch selector, comparator, D flip-flop, and combinational logic circuit modules. Before the integration technology of the OTS gating device matures, the OTS silicon equivalent circuit of this invention can be used to perform tape-out verification of novel memory circuits, achieving simultaneous development of device technology and circuits, and shortening the R&D cycle of products using OTS gating devices. This invention also incorporates an automatic shutdown function, taking into account leakage current in the shutdown state.

Claims

1. A silicon equivalent circuit for an OTS gating device, characterized in that, The device includes a state control module and a gating module. The state control module compares the voltage difference between the positive and negative terminals of the OTS gating device's silicon equivalent circuit with an externally input OTS threshold voltage or holding voltage based on the current state of the OTS gating device's silicon equivalent circuit, and determines the state of the OTS gating device's silicon equivalent circuit at the next moment based on the comparison result. The gating module simulates the switching process of the OTS gating device using two MOS devices based on the output of the state control module. The state control module includes an analog switch selector, a comparator, and a D flip-flop. The two inputs of the analog switch selector are connected to the OTS threshold voltage and the holding voltage, respectively. Its output is connected to the inverting input of the comparator, and its selection input is connected to the output of the D flip-flop. The non-inverting input of the comparator is connected to the positive terminal of the silicon equivalent circuit of the OTS gating device. Its output is divided into two paths: one path is connected to the clock input of the D flip-flop via a first inverter, and the other path is connected to the reset input of the D flip-flop via a falling edge detection module. The input of the D flip-flop is connected to the power supply voltage, and its output serves as the output of the state control module, connected to the gating module. The gating module includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the output terminal of the state control module, the source serves as the negative terminal of the silicon equivalent circuit of the OTS gating device, and the drain is connected to one end of a first resistor, the other end of which serves as the positive terminal of the silicon equivalent circuit of the OTS gating device. The gate of the second MOS transistor is connected to the output terminal of the state control module through a second inverter, the source is connected to the negative terminal of the silicon equivalent circuit of the OTS gating device, and the drain is connected to one end of a second resistor, the other end of which is connected to the positive terminal of the silicon equivalent circuit of the OTS gating device. The resistance of the first resistor is greater than the resistance of the second resistor.

2. The silicon equivalent circuit of the OTS gating device according to claim 1, characterized in that, The falling edge detection module includes a third inverter, a delay, an XOR gate, an AND gate, and an OR gate. The input of the third inverter is connected to the output of the comparator. The first input of the XOR gate is connected to the output of the third inverter through the delay, and the second input is directly connected to the output of the third inverter. The first input of the AND gate is connected to the output of the XOR gate, and the second input is connected to the output of the third inverter. The first input of the OR gate is connected to an external reset signal, the second input is connected to the output of the AND gate, and the output of the OR gate is connected to the reset terminal of the D flip-flop.

3. The silicon equivalent circuit of the OTS gating device according to claim 1, characterized in that, When the silicon equivalent circuit of the OTS gate device is currently in the off state, the output of the D flip-flop is low, and the analog switch selector transmits the OTS threshold voltage to the inverting input of the comparator. When the voltage difference between the positive and negative terminals of the silicon equivalent circuit of the OTS gate device rises above the OTS threshold voltage, the comparator output changes from low to high, and a falling edge is generated by the first inverter. The D flip-flop outputs a high level, and the silicon equivalent circuit of the OTS gate device enters the on state.

4. The silicon equivalent circuit of the OTS gating device according to claim 1, characterized in that, When the silicon equivalent circuit of the OTS gate device is in the on state, the output of the D flip-flop is high, and the analog switch selector transmits the holding voltage to the inverting input of the comparator. When the voltage difference between the positive and negative terminals of the silicon equivalent circuit of the OTS gate device drops below the holding voltage, the comparator output changes from high to low, and a brief voltage pulse is generated by the falling edge detection module to reset the D flip-flop to low, and the silicon equivalent circuit of the OTS gate device enters the off state.

5. The silicon equivalent circuit of the OTS gating device according to claim 1, characterized in that, The OTS drive capability of the silicon equivalent circuit of the OTS gate device is adjusted by adjusting the size of the first MOSFET and the resistance value of the first resistor; the OTS leakage current of the silicon equivalent circuit of the OTS gate device is adjusted by adjusting the size of the second MOSFET and the resistance value of the second resistor.

6. The silicon equivalent circuit of the OTS gating device according to claim 1, characterized in that, The resistance value of the first resistor is set to the OTS equivalent on-state resistance, and the resistance value of the second resistor is set to the OTS equivalent off-state resistance.

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