Readout control method for SRAM in low noise image sensor

Abstract

A readout control method for SRAM in a low-noise image sensor, wherein the decoder used comprises: a decoder clock signal generating circuit composed of triggers and gate logic; three triggers connected in sequence and a plurality of decoding units composed of triggers, wherein the three triggers and the plurality of decoding units generate all control signals required for the continuous readout mode of the SRAM according to the clock signal and the read start signal. The present invention simplifies the signals required for readout, and only needs to read out the clock, the read start signal and the read pause signal to generate all control signals required for the continuous readout mode and the intermittent readout mode, without the need for long-distance transmission of the address signal; at the same time, the intermittent readout mode proposed by the present invention significantly reduces the influence of the SRAM read operation on the image noise of the CMOS image sensor.

Description

Technical Field

[0001] The present invention relates to a technology in the semiconductor field, in particular to a readout control method for SRAM in a low-noise image sensor. Background Art

[0002] Most of the existing CMOS image sensors first convert analog signals into digital signals through column-parallel ADC and store the data in SRAM, and then read out the data in sequence for processing. However, CMOS image sensors require high gain in many scenarios. For example, in dark scenes in monitoring, in order to see the dark scenes clearly, high gain must be added to the image sensor. However, under high gain, while the signal is amplified, the noise is also inevitably amplified, so low noise has always been a very important indicator of CMOS image sensors.

[0003] In order to increase the readout speed, the SRAM storage array is usually divided into several small storage arrays. Traditional decoders use binary address decoding, so each small storage array of SRAM needs to correspond to an integer power of 2 word line signals. Since the number of word lines of the storage array required by the CMOS image sensor is a fixed value determined by the number of columns of the image array, the use of traditional binary decoders may cause a large difference in the number of SRAMs at a certain level and other levels, resulting in differences in the writing and reading of the SRAMs of each storage array, which is ultimately converted into image noise.

[0004] In addition, the traditional CMOS image sensor SRAM adopts a continuous readout mode. After the read starts, the address line generates a word line signal after passing through the decoder to control the continuous readout of each word of the SRAM. In order to improve the frame rate of the image sensor, the read process and the signal transmission and the analog-to-digital conversion process of the column parallel ADC are carried out simultaneously. The power supply fluctuation caused by the read process affects the signal transmission and the power supply-sensitive moments in the analog-to-digital conversion process through power supply crosstalk. Summary of the invention

[0005] Aiming at the influence of power supply fluctuation caused by the readout of existing SRAM on the image of CMOS image sensor, the present invention proposes a readout control method for SRAM in low-noise image sensor. By simplifying the signals required for readout, only a readout clock, a read start signal and a read pause signal are required to generate all control signals required for continuous readout mode and intermittent readout mode, without long-distance transmission of address signals. At the same time, the intermittent readout mode proposed by the present invention significantly reduces the influence of SRAM read operation on the image noise of CMOS image sensor.

[0006] The present invention is achieved through the following technical solutions:

[0007] The present invention relates to a decoder, comprising: a decoder clock signal generating circuit composed of a trigger and an AND gate logic; three triggers connected in sequence and a plurality of decoding units composed of the triggers, the three triggers and the plurality of decoding units generating all control signals required for a continuous read mode of an SRAM according to a clock signal and a read start signal.

[0008] Preferably, the decoder further generates all control signals required for the SRAM intermittent read mode according to the read pause signal, the clock signal and the read start signal.

[0009] The present invention relates to a readout control method for SRAM in a low-noise CMOS image sensor based on the above decoder. By controlling the readout timing of the SRAM in the image sensor, the image noise caused by power supply crosstalk is reduced by avoiding power supply-sensitive moments during signal transmission and analog-to-digital conversion in a continuous readout mode or an intermittent readout mode.

[0010] Technical Effects

[0011] Compared with the prior art, the decoder of the present invention can generate all the control signals required for the SRAM continuous read mode and intermittent read mode only through the clock signal, the read start signal and the read pause signal, without providing the address line, thus eliminating the problem of long-distance transmission of the address line; the number of storage cells in each level can be allowed to be set arbitrarily, so the number of storage cells in each level can be guaranteed to be consistent, thus eliminating the errors in the SRAM read and write operations caused by the different numbers of storage cells between levels caused by the use of a binary address decoder.

[0012] The intermittent readout mode of the present invention can suspend the reading operation at any time during the reading process and continue the reading operation at any subsequent position, avoiding the sensitive time period during the analog-to-digital conversion process of the CMOS image sensor and reducing image noise caused by mutual interference of power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a structural diagram of a storage array including a decoder of the present invention;

[0014] Figure 2a and Figure 2b This is a schematic diagram of the decoder of the present invention;

[0015] In the figure: Figure 2b for Figure 2a Magnified partial view;

[0016] Figure 3 is a timing diagram of the decoder of the present invention;

[0017] Figure 4 To read out the data transmission principle diagram;

[0018] Figure 5 This is the timing diagram for the continuous readout mode;

[0019] Figure 6 It is a segmented diagram of the intermittent readout mode line signal processing proposed by the present invention;

[0020] Figure 7 The schematic diagram of the clock generation circuit of the present invention;

[0021] Figure 8 This is the timing diagram of the intermittent readout mode. DETAILED DESCRIPTION

[0022] like Figure 1 As shown in the figure, the decoder 33 of this embodiment and the CMOS image sensor storage array 31 including n rows and m columns of storage cells connected thereto are shown, wherein: the decoder 33 generates the word line signal WL required for reading through the clock signal, the read start signal and the read pause signal <0> ~WL <m>and other control signals 32, the word line signal WL<0~WL <m>When any word line is valid, the n-bit storage unit controlled by the word line will output data 30Data <0> ~Data <n>.

[0023] In order to increase the readout speed, the storage array is usually divided into several small storage arrays and read out in sequence. Using a binary decoder, the corresponding word line signal in each small storage array must be an integer power of 2. Since the number of storage units required by the image sensor is determined by the number of row pixel units, which is mostly a fixed value, it is inevitable that a small storage array will be different from other small storage arrays, introducing read and write errors. In addition, the decoder used in the traditional readout method requires corresponding address lines according to the number of word lines. The address lines need to drive all decoding units, and the address lines need to be transmitted over long distances, which will increase power consumption, area and errors.

[0024] like Figure 2a As shown in the figure, a decoder 49 involved in this embodiment can generate all control signals required for the continuous read mode and the intermittent read mode of the storage array 31 without an address signal. The decoder specifically includes: three triggers 40-42 connected in sequence and a plurality of decoding units 46-48 for generating word line signals, wherein: the input end of the first trigger 40 receives a read start signal, and the output end is connected to the input end of the second trigger 41, the output end of the second trigger 41 is connected to the input end of the third trigger 42, the clock ends of the first trigger 40, the second trigger 41 and the third trigger 42 receive positive, negative and positive clock signals respectively, and the output end of the third trigger 42 is inverted and then performs an AND gate logic with the output end of the first trigger to generate a first word line signal WL <0> , W.L. <0> As the input of the first decoding unit 46, the output of the first decoding unit is the second word line signal WL <1> , and so on, each decoding unit generates a word line signal.

[0025] like Figure 2b As shown, each decoding unit includes two flip-flops 44 and 45 connected in sequence, and the two flip-flops receive positive and negative clock signals respectively.

[0026] like Figure 3 As shown, when the continuous read mode is used, the decoder 33 only needs to input the clock signal clk and the read start signal Read_en. The read start signal Read_en is first sampled by the first trigger 40 at the rising edge of clk to obtain the signal a. The signal a is sampled by the second trigger 41 at the rising edge of clkb to obtain the signal b. The signal b is sampled by the third trigger 42 at the rising edge of clk and then inverted to obtain the signal c. The signal a and the signal c are passed through the AND gate circuit 43 to obtain the word line signal WL. <0> ;WL <0> The signal is sampled by the trigger 44 of the first decoding unit at the rising edge of clkb to obtain the signal d, and the signal d is sampled by the trigger 45 of the first decoding unit at the rising edge of clk to obtain the word line WL <1> Similarly, each decoding unit can generate a word line signal, which eventually makes the word line signal WL <0> ~WL <m>Valid in sequence.

[0027] The storage unit will output data 30Data <0> ~Data <n>Further adoption Figure 4 The 2-stage DFF50-51 shown in the figure performs synchronous processing. The continuous readout mode data processing waveform is as follows Figure 5 As shown Figure 1 Read data in Data <0> In WL <0> ~WL <m>When the sequence is valid, the data read out in sequence are d0~dm, then Figure 4 The inputs of signal e are d0~dm in sequence. Signal e is sampled by DFF50 at the rising edge of clkb to obtain signal f. Signal f is sampled by DFF51 at the rising edge of clk to obtain signal g. Signal g is the output read data.

[0028] like Figure 6 As shown in the figure, time period 1, that is, when the RST signal is at a low level, is the entire row signal processing time. In order to improve the frame rate of the image sensor, the storage unit read processing and the analog-to-digital conversion processing are carried out simultaneously, wherein: the time period for the analog-to-digital conversion processing includes the first analog-to-digital conversion time period 2, the signal transmission time period 3 and the second analog-to-digital conversion time period 4, and the time period for the storage unit read processing includes the reading time period 5, the read suspension time period 6 and the reading time period 7.

[0029] The signal transmission period 3 is very sensitive to power supply noise, so power supply fluctuations should be minimized during this period; when the intermittent readout mode is used, the signal transmission period 3 that is sensitive to power supply corresponds to the read pause period 6, during which no read operation is performed to reduce power supply fluctuations and ensure low-noise transmission of the signal. After the signal transmission is completed, the read operation period 7 is continued.

[0030] When the intermittent read mode is used, the decoder is further provided with a clock generating circuit 62, which receives a read pause signal h and an input clock signal clkin. When the read pause signal h is at a high level, the read operation is performed, and when h is at a low level, the read operation is suspended.

[0031] like Figure 7 and Figure 8 As shown, the clock generating circuit 62 includes: a trigger unit 60 and an AND gate unit 61, wherein: the input end of the trigger 60 receives a pause signal, and the clock signal end receives an inverted signal clkinb of the input clock signal clkin. The pause signal h is sampled by the trigger unit 60 at the rising edge of the clkinb signal to obtain an output signal j, which is then ANDed with the input clock signal clkin through the AND gate unit 61 to generate a decoder clock signal clk.

[0032] The clock signal clk is Figure 2a and Figure 2b The decoder input clock signal clk is as follows: Figure 8 As shown, when the word line signal WL is expected <4> At the time when the read is suspended for a period of time, h is at a low level during this period, and the clock signal clk and its inverted signal clkb have no rising edge in period a, so WL <4> The signal remains high during this period, and the read signals e, f, g maintain data d4, f and g during this period, and each data is sampled only once by the clock signal. After the read pause signal h changes from low to high, the output j of the flip-flop 60 changes from low to high, and the read operation continues.

[0033] Preferably, by setting the read pause signal h to be always high, the output clock signal clk of the clock generating circuit 62 is a continuous clock signal, which is applicable to the continuous read mode.

[0034] In summary, the decoder of the present invention has a simplified structure and only needs to read the start signal, clock signal and read pause signal to generate all the control signals required for the continuous read mode and the intermittent read mode; the intermittent read mode of the present invention can further effectively reduce the impact of the SRAM read on the sensitive signals in the entire analog-to-digital conversion process, thereby realizing low-noise transmission of the signal.

[0035] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.< / m> < / n> < / m> < / n> < / m> < / m>

Claims

1. A decoder, characterized in that: include: A decoder clock signal generating circuit composed of a flip-flop and an AND gate logic; Three flip-flops and a plurality of decoding units composed of the flip-flops connected in sequence, the three flip-flops and the plurality of decoding units generate all control signals required for the SRAM continuous read mode according to the clock signal and the read start signal; The decoder specifically comprises: three triggers connected in sequence and a plurality of decoding units for generating word line signals, wherein: the input end of the first trigger receives a read start signal, the output end is connected to the input end of the second trigger, the output end of the second trigger is connected to the input end of the third trigger, the clock ends of the first trigger, the second trigger and the third trigger receive positive, negative and positive clock signals respectively, the output end of the third trigger is inverted and then performs AND gate logic with the output end of the first trigger to generate the first word line signal WL <0> As the input of the first decoding unit, the output of the first decoding unit is the second word line signal WL <1> , and so on, each decoding unit generates a word line signal; each decoding unit includes two flip-flops connected in sequence, and the two flip-flops receive positive and negative clock signals respectively.

2. The decoder according to claim 1, characterized in that: The decoder further generates all control signals required for the SRAM intermittent read mode according to the read pause signal, the clock signal and the read start signal.

3. A readout control method for SRAM in a low-noise CMOS image sensor based on the decoder according to claim 1 or 2, characterized in that: By controlling the read timing of the SRAM in the image sensor, the image noise caused by power supply crosstalk can be reduced by using a continuous readout mode or an intermittent readout mode to avoid power supply-sensitive moments during signal transmission and analog-to-digital conversion.

4. The readout control method according to claim 3, characterized in that: When using the continuous read mode, the decoder only needs to input the clock signal clk and the read start signal Read_en. The read start signal Read_en is sampled for the first time by the first trigger at the rising edge of clk to obtain signal a. Signal a is sampled by the second trigger at the rising edge of clkb to obtain signal b. Signal b is sampled by the third trigger at the rising edge of clk and then inverted to obtain signal c. Signal a and signal c are passed through the AND gate circuit to obtain the word line signal WL. <0> ;WL <0> The signal is sampled by the trigger of the first decoding unit at the rising edge of clkb to obtain the signal d, and the signal d is sampled by the trigger of the first decoding unit at the rising edge of clk to obtain the word line WL <1> Similarly, each decoding unit can generate a word line signal, which eventually makes the word line signal WL <0> ~WL <m> Valid in sequence.< / m> 5. The readout control method according to claim 3, characterized in that: When the intermittent read mode is used, the decoder generates all control signals required for the SRAM intermittent read mode according to the read pause signal, the clock signal and the read start signal; in the entire row signal processing time period, the storage unit read processing and the analog-to-digital conversion processing are performed simultaneously, wherein: the time period of the analog-to-digital conversion processing includes the first analog-to-digital conversion time period, the signal transmission time period and the second analog-to-digital conversion time period, and the time period of the storage unit read processing includes the reading time period, the read pause time period and the reading time period; The signal transmission period is very sensitive to power supply noise, so power supply fluctuations should be minimized during this period; when using the intermittent read mode, for the storage unit reading period, the signal transmission period that is sensitive to power supply corresponds to the read pause period, during which no read operation is performed to reduce power supply fluctuations and ensure low-noise transmission of the signal, and the read operation period is continued after the signal transmission is completed.

6. The readout control method according to any one of claims 3 to 5, characterized in that: When the intermittent read mode is used, the decoder is further provided with a clock generating circuit, which receives a read pause signal h and an input clock signal clkin. When the read pause signal h is at a high level, the read operation is performed, and when h is at a low level, the read operation is suspended.

7. The readout control method according to claim 6, characterized in that: The clock generating circuit comprises: a trigger unit and an AND gate unit, wherein: the input end of the trigger receives a pause signal, the clock signal end receives an inverted signal clkinb of the input clock signal clkin, the pause signal h is sampled by the trigger unit at the rising edge of the clkinb signal to obtain an output signal j, and the output signal j and the input clock signal clkin are ANDed by the AND gate unit and logic to generate a decoder clock signal clk.

8. The readout control method according to claim 6, wherein: By setting the read pause signal h to be always high, the output clock signal clk of the clock generating circuit is a continuous clock signal, that is, suitable for the continuous read mode.

9. A control system for implementing the readout control method according to any one of claims 3 to 8, comprising: A decoder and a CMOS image sensor storage array including n rows and m columns of storage cells connected thereto, wherein: the decoder generates a word line signal WL required for reading through a clock signal, a read start signal and a read pause signal <0> ~WL <m>And other control signals, the word line signal WL<0~WL when the storage array is read <m>When any word line is valid, the n-bit storage unit controlled by the word line will output data Data <0> ~Data <n> 。< / n> < / m> < / m>

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