Reference bit testing and repair using memory built-in self-test

Abstract

A memory test circuit configured to perform a test of reference bits in a memory. In a read operation, the output of a column of data bits is compared to one or more columns of reference bits. The memory test circuit includes a test controller and an association adjustment circuit configurable by the test controller to associate another one or more columns of reference bits or one or more columns of data bits with the column of data bits in the read operation. The test controller can determine whether the original one or more columns of reference bits are defective based on results from the two different associations.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 000,517, filed on March 27, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed herein relates to memory testing. Various embodiments of the disclosed technology can be particularly useful for improving the manufacturing yield of embedded memories using reference bits. Background Technology

[0004] Magnetoresistive random access memory (MRAM) has become an attractive non-volatile memory solution due to its small size, fast operating speed, and good durability. MRAM devices can store data in magnetic domains, for example, as the spin polarity of magnets in their free layers. MRAM devices can write data into magnetic domains by setting the spin polarity of magnets in their free layers, for example, by providing a spin-polarized current through a magnetic tunnel junction (MTJ), which applies a torque to the local magnetization in the free layers; this is commonly referred to as spin torque transfer (STT). The electron spin polarity of these layers switches based on the direction of the write current. Therefore, an MRAM cell can be switched to either a high-resistivity state (anti-parallel spin polarity, RAP) or a low-resistivity state (parallel spin polarity, RP).

[0005] To read stored data, an MRAM device determines the spin polarity of a magnet in its free layer relative to a pinned reference layer below the corresponding free layer. When the spin polarity is parallel to the pinned reference layer, the resistance on the accessed data bit line (column) of the MRAM device can be considered low, thus corresponding to a data value "0". When the spin polarity is antiparallel to the pinned reference layer, the resistance on the accessed data bit line of the MRAM device can be considered high, thus corresponding to a data value "1". The MRAM device may include sensing circuitry that detects the resistance on the accessed data bit line of the MRAM device relative to the resistance of the reference bit line to determine whether the detected resistance is considered low corresponding to a data value "0" or high corresponding to a data value "1". Resistance detection can be performed by current measurement or voltage measurement.

[0006] Typically, a reference bit line is paired with multiple data bit lines for read operations. A reference bit line can be written to zero or one. Two reference bit lines storing different values ​​can be used to provide a reference resistance value for the read operation. Therefore, each read operation on one of the data bit lines involves an operation on the reference bit line. Frequent operations can make the reference bit line susceptible to failure. If the reference bit fails, it can cause read operations involving not only one data bit but also multiple data bits to fail.

[0007] Current high-density semiconductors often include embedded memories. If designed strictly to meet technological constraints, memories are more prone to failure than other circuitry, adversely impacting yield. Built-in self-test (BIST) technology is used to identify defects and problems in memories. Furthermore, these circuits typically include built-in self-repair (BISR) circuitry for performing repair analysis (BIRA) and replacing faulty components with spares. However, conventional test schemes can only functionally access data bits and cannot determine whether the failure is caused by a defect in the data bits or a defect in the reference bits.

[0008] Error-correcting code (ECC) technology is frequently used in MRAM products. ECC is not only a good solution for permanent bit failures in memory, but it can also be used to overcome weak bit aging failures that occur early in the memory's lifespan. For low manufacturing failure rates (e.g., one or two bits failing in a word), ECC can even eliminate the need for repair circuitry. However, using ECC to detect and resolve defects associated with reference bits is very challenging because reference bit failures typically involve multiple bits and complex ECC coding. Summary of the Invention

[0009] Various aspects of the disclosed technology relate to testing and repairing reference bits in a memory. In one aspect, a memory test circuit exists in a circuit configured to perform tests on a memory in the circuit, the memory including: a data bit column configured to store data bits, a reference bit column configured to store reference bits, and a column association circuit configured to associate one or more reference bit columns with data bit columns in the data bit column. The memory test circuit includes: a test controller; and an association adjustment circuit coupled to the column association circuit and the test controller, the association adjustment circuit being configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the data bit column, wherein the memory test includes: based on the association by the column association circuit... One or more reference bit columns perform one or more read operations to generate one or more outputs; compare the one or more outputs with corresponding good machine values ​​to determine whether any of the one or more outputs is incorrect; if at least one of the one or more outputs is incorrect, repeat at least one of the one or more read operations to generate at least one second output, wherein the one or more read operations generate at least one of the one or more outputs based on another one or more reference bit columns or one or more data bit columns associated by the associated adjustment circuitry; and compare the at least one second output with corresponding good machine values ​​to determine whether the one or more reference bit columns associated by the column association circuitry are defective.

[0010] The memory test circuit may further include a repair circuit configured to replace defective reference bits detected by the memory test circuit with additional reference bits. The repair circuit may include: a register coupled to the associated adjustment circuit and configured to load repair information for one or more defective reference bits; an address comparison device configured to compare a data bit address used for a read operation with one or more addresses used to associate data bits with one or more defective reference bits; and a multiplexing device controlled by the output of the address comparison device and configured to select an output signal from a signal from the register and a signal from the column association circuit.

[0011] The column association circuit can be a decoder, which is configured to generate signals for selecting one or more reference bit columns based on the address signals used for read operations.

[0012] The memory may be a magnetoresistive random access memory (MRAM), and read operations on the memory may include: comparing the output from the data column with the outputs from two reference columns (which store “0” and “1”) associated with the data column, respectively, or comparing the output from the data column with half the sum of the outputs from the two reference columns (which store “0” and “1”) associated with the data column.

[0013] The correlation adjustment circuit may include a multiplexing circuit configured to select between an output signal from the column correlation circuit and a signal directly from the test controller or a signal generated by a device in the correlation adjustment circuit. This device may be configured to add one bit to the address of one or more reference bit columns associated with the column correlation circuit to generate the address of another one or more reference bit columns.

[0014] On the other hand, there exists one or more computer-readable media storing computer-executable instructions for causing a computer to perform a method comprising: creating a memory test circuit in a circuit design including a memory, the memory test circuit being configured to perform a test of the memory, the memory including: a data bit column configured to store data bits, a reference bit column configured to store reference bits, and a column association circuit configured to associate one or more reference bit columns with data bit columns in the data bit column, the memory test circuit including: a test controller; and an association adjustment circuit coupled to the column association circuit and the test controller, the association adjustment circuit being configurable by the test controller to associate another one or more reference bit columns in the reference bit column or one or more data bit columns in the data bit column with the data bit columns in the data bit column. The memory test includes: performing one or more read operations based on one or more reference bits in a reference bit column associated by a column association circuit to generate one or more outputs; comparing the one or more outputs with a corresponding good machine value to determine whether any of the one or more outputs is incorrect; if at least one of the one or more outputs is incorrect, repeating at least one of the one or more read operations to generate at least one second output, wherein the one or more read operations generate at least one of the one or more outputs based on another one or more reference bits in a reference bit column associated by an association adjustment circuit or one or more data bits in a data bit column; and comparing the at least one second output with a corresponding good machine value to determine whether the one or more reference bits in the reference bit column associated by the column association circuit are defective.

[0015] Certain aspects of the invention are set forth in the appended independent and dependent claims. Features of the dependent claims may be appropriately combined with features of the independent claims and other dependent claims, and not merely as expressly set forth in the claims.

[0016] Certain objects and advantages of various aspects of the present invention have been described above. It should be understood, of course, that not all of these objects or advantages must be achieved according to any particular embodiment of the disclosed technology. Therefore, for example, those skilled in the art will recognize that the disclosed technology may be embodied or carried out in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objects or advantages as taught or suggested herein. Attached Figure Description

[0017] Figure 1 An example block diagram of a typical memory is shown.

[0018] Figure 2 An example of the resistance distribution of an MRAM array for the "1" and "0" states is shown.

[0019] Figure 3 An example is shown of multiple data columns associated with a pair of reference columns, both of which reside in memory.

[0020] Figure 4 Examples of two sense amplifiers are shown, which can be used in magnetoresistive random access memory.

[0021] Figure 5 Examples of block diagrams illustrating a memory test circuit capable of testing reference bits in a memory according to various embodiments of the disclosed technology are provided.

[0022] Figure 6 Two examples of a memory having a reference bit column associated with certain data bit columns are shown.

[0023] Figure 7 An example of a decoder is shown.

[0024] Figure 8 Examples are illustrated of how a memory test circuit according to some embodiments of the disclosed technology tests a reference bit in a memory.

[0025] Figure 9 Examples of repair circuits that may be included in memory test circuits according to various embodiments of the disclosed technology are illustrated.

[0026] Figure 10 Examples of programmable computer systems that can be used in conjunction with various embodiments of the disclosed technology are illustrated. Detailed Implementation

[0027] Various aspects of the disclosed techniques relate to testing and repairing reference bits in memory. Numerous details are set forth in the following description for purposes of explanation. However, those skilled in the art will recognize that the disclosed techniques can be practiced without using these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the techniques disclosed herein.

[0028] Some of the techniques described herein can be implemented as software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. For example, some of the disclosed techniques can be implemented as part of an electronic design automation (EDA) tool. These methods can be executed on a single computer or a networked computer.

[0029] Although the operations of the disclosed methods are described in a specific order for ease of presentation, it should be understood that this descriptive approach encompasses rearrangement unless the specific language used in the following description requires a particular order. For example, in some cases, the operations described in sequence may be rearranged or performed concurrently. Moreover, for simplicity, the disclosed flowcharts and block diagrams generally do not show the various ways in which a particular method can be used in conjunction with other methods.

[0030] Detailed descriptions of methods or apparatus sometimes use terms like "associated," "compared," and "performed" to describe the disclosed method or apparatus functionality / structure. These terms are high-level descriptions. The actual operation or functionality / structure corresponding to these terms will vary depending on the specific implementation and is readily discernible to those skilled in the art.

[0031] As used herein, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly indicates otherwise. Additionally, the term “comprising” means “including.” Furthermore, unless the context otherwise specifies, the term “coupled” means an electrical or electromagnetic connection or link, and includes both direct connections or links and indirect connections or links made through one or more intermediate elements that do not affect the intended operation of the circuit.

[0032] Memory forms a large part of the system-on-a-chip circuitry. Embedded memory can provide higher bandwidth and consume less power than discrete memory. Figure 1An example block diagram of a typical memory 100 is illustrated. Memory 100 includes memory cells 110, column address decoders 120, row address decoders 130, driver circuitry 150, and sense amplifiers 160. The memory cells 110 are connected in a two-dimensional array. Each memory cell 110 can store one bit of binary information. The memory cells 110 can be grouped into memory words of fixed word lengths (e.g., 1, 2, 4, 8, 16, 32, 64, or 128 bits). Each memory cell has two basic components: a memory node and a selection device. The memory node stores the data bits used for the memory cell, and the selection device component facilitates addressing the memory cell for reading / writing within the array.

[0033] Row address decoder 130 and column address decoder 120 determine the address of the cell to be accessed. Based on the addresses on row address decoder 130 and column address decoder 120, one or more corresponding rows and one or more columns are selected and connected to sense amplifier 160. Each sense amplifier 160 amplifies and sends out data bits. Similarly, the desired cell for which data bits need to be written is selected by the addresses on row address decoder 130 and column address decoder 120. However, driver 150 is used to write the data bits into the memory cell. Address information is supplied via address bus 140.

[0034] For a magnetoresistive random access memory (MRAM), the sense amplifier 160 determines whether a data bit stores a "0" or a "1" by comparing the output from the data bit with a reference value. Due to process variations, the "1" and "0" states of MRAM have a resistance distribution within a certain range that resembles a normal distribution. Figure 2 An example of the resistance distribution of an MRAM array for "1" states 210 / 215 and "0" states 220 / 225 is illustrated. In the figure, the vertical axis represents probability, and the horizontal axis represents read characteristics. Read characteristics can be resistance, current associated with a read operation, or voltage of the bit line associated with a read operation. It has been reported that the resistance value of the "1" state decreases with increasing temperature. In one report, the resistance value of the "0" state 220 remained at ~10 (arbitrary units) and did not change much with temperature, while the resistance value of the "1" state changed from 30 to 22 (arbitrary units) as the temperature increased. Figure 2In the memory, state 210 is at a high temperature, and state 215 is at a low temperature. If a fixed reference level 230 is used, some memory cells with resistance values ​​in state "1" in region 245 will cause read operation output errors. To mitigate this problem, some columns in the magnetoresistive random access memory are dedicated to establishing reference resistors 235. These columns are called reference bit columns or reference bit lines. The reference resistance of the reference bits will vary with temperature in a manner similar to that of the data bits, thereby reducing the chance of errors caused by environmental factors. Moreover, when the data bits and reference bits share the same word line, errors caused by process variations and errors caused by parasitic effects can also be reduced.

[0035] Figure 3 An example of multiple data bit columns associated with a pair of reference bit columns 312 and 313 is illustrated, both of which reside in memory bank 300. The value "1" is written to a row of data bit cells 310 in memory bank 300. The corresponding bit in reference bit column 312 stores "0", while the corresponding bit in reference bit column 313 stores "1". The average of their resistance values ​​sets a reference resistance value 320. During a read operation, the resistance value of the data bit cell selected from data bit cell 310 is compared to the reference resistance value 320 to determine the output of the read operation. Figure 3 The resistance values ​​of the selected data bit cells are all greater than the reference resistance value of 320, therefore the output of the read operation is set to "1" for each selected data bit cell.

[0036] Similarly, the value "0" is written into a row of data bit cells 330 in memory bank 300. Likewise, the corresponding bit in reference bit column 312 stores "0", and the corresponding bit in reference bit column 313 stores "1". The average of their resistance values ​​sets a reference resistance value 320. During a read operation, the resistance value of the selected data bit cell from data bit cell 330 is compared with the reference resistance value 320 to determine the output of the read operation. Figure 3 The resistance values ​​of the selected data bit cells are all less than the reference resistance value of 320, therefore the output of the read operation is set to "0" for each selected data bit cell.

[0037] Figure 4 Examples of two sense amplifiers 410 and 420 are illustrated, which can be used in a magnetoresistive random access memory. Sensing amplifier 410 has two inputs 412 and 414. Input 412 is coupled to a current or voltage level corresponding to the resistor of the selected data bit. Input 414 is coupled to a reference voltage / current level corresponding to half the sum of the resistors of the reference "0" bit and the reference "1" bit. Sensing amplifier 410 compares the two inputs 412 and 414 to determine its output.

[0038] Unlike the single-stage sense amplifier 410, the sense amplifier 420 has two stages: two sensing devices 422 and 424 in the first stage, and a sensing device 426 in the second stage. First, sensing device 422 compares the current or voltage level of the resistor corresponding to the selected data bit with the current or voltage level corresponding to the reference "1" bit to generate a first intermediate comparison result; and sensing device 424 compares the current or voltage level of the resistor corresponding to the selected data bit with the current or voltage level corresponding to the reference "0" bit to generate a second intermediate comparison result. Then, sensing device 426 compares the first intermediate comparison result with the second intermediate comparison result to generate the final output.

[0039] For both sense amplifiers 410 and 420, at least one of the reference "0" bit and the reference "1" bit is derived from a reference bit column, while the other can be set to a fixed level. Alternatively, a pair of reference bit columns can be used for each of the reference "0" bit and the reference "1" bit.

[0040] Figure 5 An example block diagram of a memory test circuit 500 capable of testing reference bits in memory 510 according to various embodiments of the disclosed technology is illustrated. Memory 510 includes a data bit column configured to store data bits and a reference bit column 520 configured to store reference bits. The reference bit column 520 may be grouped together or divided into multiple subsets, each subset being grouped with some of the data bit columns. Memory 510 also includes column association circuitry 530 and sense amplifier circuitry 540. In a read operation, the column association circuitry 530 is configured to associate one or more reference bit columns 520 with one of the data bit columns selected by the column address of the read operation based on data bit column address information 535, and the sense amplifier circuitry 540 is configured to compare the output from the selected data bit column with the output from the associated reference bit column to determine an output. An example of memory 510 is a magnetoresistive random access memory (MRAM).

[0041] Figure 6Examples of memories 610 and 620 with reference bit columns associated with specific data bit columns are illustrated. Memory 610 is divided into three segments, the outputs of which are coupled to three multiplexers 630, 640, and 650, respectively. The outputs of the three multiplexers 630, 640, and 650 are coupled to the input of a sense amplifier 660. Three pairs of reference bit columns 635, 645, and 655 are located in the three segments coupled to the three multiplexers 630, 640, and 650, respectively. It should be noted that each of the three segments may have more than one pair of reference bit columns. In a read operation, for example, data bit column 637 is selected by multiplexer 630, one reference bit column from a pair of reference bit columns 645 is selected by multiplexer 640, and one reference bit column from a pair of reference bit columns 655 is selected by multiplexer 650. The sense amplifier 660 can be used... Figure 4 The settings of the sensing amplifier 420 shown are based on the outputs of the three multiplexers to determine its output.

[0042] Memory 620 is divided into four segments 622, 624, 626, and 628, whose outputs are coupled to four multiplexers 672, 674, 676, and 678, respectively. Sensing amplifier 680 couples its input to the outputs of multiplexers 672, 676, and 678. Another sensing amplifier 690 couples its input to the outputs of multiplexers 674, 676, and 678. Within memory 620, data bit columns and reference bit columns are grouped separately: memory segments 622 and 624 store data bits, while memory segments 626 and 628 store reference bits, one for "0" and the other for "1". In a read operation, for example, multiplexers 672 and 674 select data bit column 623 in segment 622 and data bit column 625 in segment 624, respectively, and multiplexers 676 and 678 select reference bit column 627 in segment 626 and reference bit column 629 in segment 628, respectively. Sensing amplifiers 680 and 690 can be used. Figure 4 The amplifier 410 shown is configured to compare the corresponding multiplexer outputs to determine its output.

[0043] Return to reference Figure 5 The column association circuit 530 can be a decoder configured to generate a signal for selecting one or more reference bit columns from the column address signal used for the read operation. Figure 7 An example of decoder 700 is illustrated. Decoder 700 includes logic gates. The inputs of decoder 700 receive six address bits 710 (BL_ADD<0:5>), which are used to select a data bit column. These input address bits 710 can select one of 64 data bit columns in various I / O units. The three output signals 720 of decoder 700 can be used to select a reference bit column.

[0044] Return to reference Figure 5 The memory test circuit 500 includes a test controller 550 and an association adjustment circuit 560. The test controller 550 can be implemented using a conventional memory BIST controller. The test controller 550 can be programmed by signals sent via a TAP (Test Access Port) and performs tests by applying read and write sequences to memory cells in the memory 510 via a test interface. These read and write sequences are commonly referred to as memory test algorithms. The association adjustment circuit 560 is coupled to both the column association circuit 530 and the test controller 550. Based on control signals from the test controller 550, the association adjustment circuit 560 can allow signals output from the column association circuit 530 to pass through during read operations to select a reference bit column, or output signals to associate different reference bit columns or data bit columns with the selected data bit column. It should be noted that the association adjustment circuit 560 can be considered a device internal to the memory 510.

[0045] During testing, test controller 550 can perform several write and read operations on memory 510. Read operations generate outputs based on reference bit columns associated with column association circuitry 530. The outputs are compared to corresponding good machine values ​​(expected values) to determine if any one or more outputs are incorrect. If at least one of the outputs is incorrect for a test row associated with a particular reference bit or bit pair, test controller 550 repeats at least one of the read operations. However, the output of at least one of the read operations is not obtained based on the original associated reference bit columns, but rather on reference bit columns or even data bit columns associated with association adjustment circuitry 560. The new outputs are again compared to corresponding good machine values. These newly associated reference bit columns or data bit columns can be selected from known non-defective reference bit columns or data bit columns. Therefore, test controller 550 can determine that if the new output matches the corresponding good machine value, the original associated reference bit column is defective, or if the new output does not match the corresponding good machine value, the data bit is defective.

[0046] Figure 8An example is illustrated of how a memory test circuit 800, according to some embodiments of the disclosed technology, tests reference bits in a memory 810. The memory 810 groups columns into four segments 812, 814, 816, and 818. Segments 812 and 814 are configured to store data bits, thus including data bit columns, and segments 816 and 818 are configured to store reference bits, thus including reference bit columns. Multiplexers 822, 824, 826, and 828 select column outputs from the four segments 812, 814, 816, and 818, respectively. Multiplexers 822 and 824 use a column address signal 830 to select the data bit column. A decoder 840 generates a reference column selection signal 850 based on the column address signal 830. The reference column selection signal 850 controls multiplexers 826 and 828 to select the reference bit column. The memory 810 also has two sense amplifiers 865 and 875, which use a combination of the outputs of multiplexers 826 and 828 as a reference to derive their outputs. This combination can be half the sum of the outputs of multiplexers 826 and 828. Sensing amplifier 865 compares the output of multiplexer 822 with a reference level obtained based on the combination of the outputs of multiplexers 826 and 828 to derive its output, and sensing amplifier 875 compares the output of multiplexer 824 with a reference level obtained based on the combination of the outputs of multiplexers 826 and 828 to derive its output.

[0047] The memory test circuit 800 includes a selection device 860, an address adjustment device 870, and a test controller 880. The selection device 860 and the address adjustment device 870 can be considered as... Figure 5 This is part of the associated adjustment circuitry 560. Address adjustment device 870 is configured to shift reference column select signal 850 by one bit to generate a new reference column select signal 890. Test controller 880 can control selection device 860, thereby instructing whether to allow reference column select signal 850 or the new reference column select signal 890 to control multiplexers 826 and 828. During testing, if the output of one or more read operations based on reference column select signal 850 has an error, but the output of the same one or more read operations based on the new reference column select signal 890 has no error, test controller 880 will determine that the reference column selected by reference column select signal 850 may be defective. Shifting the reference column address by one bit is only one of many ways to generate a new reference column address 890. Test controller 880 can directly supply the new reference column address 890.

[0048] Figure 9Examples of repair circuitry 900, which may be included in a memory test circuit according to various embodiments of the disclosed technology, are illustrated. Repair circuitry 900 includes address comparison device 910, multiplexing device 920, and repair register 930. Repair solutions for reference bits are typically stored together with other repair solutions in repair information storage device 960. Repair information storage device 960 may be a fuse array, a one-time programmable memory, or other non-volatile memory. To save space, these repair solutions are typically stored in compressed form. Upon circuit power-on or reset, the compressed repair solutions are automatically decompressed and scanned into repair register 930 via a scan chain. Address comparison device 910 is configured to compare a reference data bit address signal output from decoder 940 with one or more addresses supplied by repair register 930 during a read operation. Figure 5 Similar to the column association circuit 530, the decoder 940 is configured to generate a reference data column address signal based on the data column address signal 950 to associate one or more reference columns with the data columns selected by the data column address signal 950.

[0049] If address comparison device 910 does not find a match between the reference data bit column address signal from decoder 940 and one or more addresses from repair register 930, the former is allowed to pass through multiplexing device 920. Otherwise, a different reference bit column address supplied by repair register 930 is allowed to pass through multiplexing device 920. The different reference bit column address can be an address of a redundant reference bit column dedicated to repair.

[0050] Various examples of the disclosed technology can be implemented by executing software instructions using a computing device such as a programmable computer. Therefore, Figure 10 An illustrative example of a computing device 1001 is shown. As seen in the figure, the computing device 1001 includes a computing unit 1003 having a processing unit 1005 and a system memory 1007. The processing unit 1005 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 1007 may include a read-only memory (ROM) 1009 and a random access memory (RAM) 1011. As will be understood by those skilled in the art, both the read-only memory (ROM) 1009 and the random access memory (RAM) 1011 can store software instructions for execution by the processing unit 1005.

[0051] Processing unit 1005 and system memory 1007 are directly connected or indirectly connected to one or more peripheral devices via bus 1013 or alternative communication structures. For example, processing unit 1005 or system memory 1007 may be directly or indirectly connected to one or more additional storage devices, such as a hard disk drive 1015, a removable disk drive 1017, an optical disk drive 1019, or a flash memory card 1021. Processing unit 1005 and system memory 1007 may also be directly or indirectly connected to one or more input devices 1023 and one or more output devices 1025. Input devices 1023 may include, for example, a keyboard, pointing devices (e.g., a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. Output devices 1025 may include, for example, a monitor, a printer, and speakers. For various examples of computer 1001, one or more peripheral devices 1015-1025 may be housed internally with computing unit 1003. Alternatively, one or more peripheral devices 1015-1025 may be located outside the housing of computing unit 1003 and connected to bus 1013 via, for example, a Universal Serial Bus (USB) connection.

[0052] In some implementations, computing unit 1003 may be directly or indirectly connected to one or more network interfaces 1027 for communication with other devices comprising the network. Network interface 1027 converts data and control signals from computing unit 1003 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). Furthermore, interface 1027 may employ any suitable connection proxy (or combination of proxies) to connect to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in further detail here.

[0053] It should be understood that computer 1001 is merely an example and is not intended to be limiting. Various embodiments of the disclosed technology can be implemented using one or more computing devices, which include… Figure 10 The components of the computer 1001 illustrated herein include only... Figure 10 A subset of the components illustrated, or including alternative combinations of components, including Figure 10 Components not shown. For example, various embodiments of the disclosed technology may be implemented using a multiprocessor computer, multiple single-processor and / or multiprocessor computers arranged in a network, or some combination of both.

[0054] in conclusion

[0055] The principles of the disclosed technology have been illustrated and described. It will be apparent to those skilled in the art that modifications in arrangement and detail may be made to the disclosed embodiments without departing from these principles. Given the many possible embodiments to which the principles of the disclosed technology can be applied, it should be understood that the illustrated embodiments are merely preferred examples of the technology and should not be considered as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the appended claims and their equivalents. Therefore, we claim protection for all technologies falling within the scope and spirit of these claims as the technology we have disclosed.

Claims

1. A memory test circuit in a circuit, the memory test circuit being configured to perform a test on a memory in the circuit, the memory comprising: The memory test circuit includes: a data bit column configured to store data bits, a reference bit column configured to store reference bits, and a column association circuit configured to associate one or more of the reference bit columns with the data bit columns in the data bit column. Test controller; An association adjustment circuit, coupled to the column association circuit and the test controller, the association adjustment circuit being configurable by the test controller to associate one or more reference columns in the reference bit columns or one or more data columns in the data bit columns with the data columns in the data bit columns, and A repair circuit, configured to replace a defective reference bit column detected by the memory test circuit with an additional reference bit column, the repair circuit comprising: A register, coupled to the associated adjustment circuitry and configured to load repair information for one or more defective reference columns; An address comparison device is configured to compare a data bit column address used for a read operation with one or more addresses used to associate a data bit column with one or more defective reference bit columns; and The multiplexing device, controlled by the output of the address comparison device, is configured to select an output signal from between a signal from the register and a signal from the column association circuit. The testing of the memory includes: One or more read operations are performed based on one or more reference bit columns associated with the column association circuit to generate one or more outputs; The one or more outputs are compared with the corresponding good machine value to determine whether any of the one or more outputs is incorrect; If at least one of the one or more outputs is incorrect, then at least one of the one or more read operations is repeated to generate at least one second output, wherein the one or more read operations generate the at least one of the one or more outputs based on another one or more reference bit columns or one or more data bit columns of the data bit columns associated with the associated adjustment circuit; and The at least one second output is compared with the corresponding good machine value to determine whether one or more reference bit columns in the reference bit columns associated with the column association circuit are defective.

2. The memory test circuit according to claim 1, wherein, The column association circuit is a decoder configured to generate signals for selecting one or more reference bit columns based on address signals used for read operations.

3. The circuit according to claim 1, wherein, The memory is a magnetoresistive random access memory (MRAM), and the read operation of the memory includes: comparing the output from the data bit column with the output from two reference bit columns associated with the data bit column that store "0" and "1" respectively, or comparing the output from the data bit column with half the sum of the outputs from the two reference bit columns associated with the data bit column that store "0" and "1" respectively.

4. The circuit according to claim 1, wherein, The correlation adjustment circuit includes a multiplexing circuit configured to select between the output signal of the correlation circuit and a signal directly from the test controller or a signal generated by a device in the correlation adjustment circuit.

5. The circuit according to claim 4, wherein, The device is configured to add a bit to the address of one or more reference bit columns in the reference bit columns associated with the column association circuitry to generate the address of the other one or more reference bit columns in the reference bit columns.

6. One or more computer-readable media storing computer-executable instructions, the computer-executable instructions being configured to cause a computer to perform a method, the method comprising: A memory test circuit is created in a circuit design, the circuit design including a memory, the memory test circuit being configured to perform tests on the memory, the memory including: a data bit column configured to store data bits, a reference bit column configured to store reference bits, and a column association circuit configured to associate one or more of the reference bit columns with the data bit columns, the memory test circuit including: Test controller; and An association adjustment circuit, coupled to the column association circuit and the test controller, the association adjustment circuit being configurable by the test controller to associate one or more reference columns in the reference bit columns or one or more data columns in the data bit columns with the data columns in the data bit columns, and A repair circuit, configured to replace a defective reference bit column detected by the memory test circuit with an additional reference bit column, the repair circuit comprising: A register, coupled to the associated adjustment circuitry and configured to load repair information for one or more defective reference columns; An address comparison device is configured to compare a data bit column address used for a read operation with one or more addresses used to associate a data bit column with one or more defective reference bit columns; and The multiplexing device, controlled by the output of the address comparison device, is configured to select an output signal from between a signal from the register and a signal from the column association circuit. The testing of the memory includes: One or more read operations are performed based on one or more reference bit columns associated with the column association circuit to generate one or more outputs; The one or more outputs are compared with the corresponding good machine value to determine whether any of the one or more outputs is incorrect; If at least one of the one or more outputs is incorrect, then at least one of the one or more read operations is repeated to generate at least one second output, wherein the one or more read operations generate the at least one of the one or more outputs based on another one or more reference bit columns or one or more data bit columns of the data bit columns associated with the associated adjustment circuit; and The at least one second output is compared with the corresponding good machine value to determine whether one or more reference bit columns in the reference bit columns associated with the column association circuit are defective.

7. The one or more computer-readable media according to claim 6, wherein, The column association circuit is a decoder configured to generate signals for selecting one or more reference bit columns based on address signals used for read operations.

8. The one or more computer-readable media according to claim 6, wherein, The memory is a magnetoresistive random access memory (MRAM), and the read operation of the memory includes: comparing the output from the data bit column with the output from two reference bit columns associated with the data bit column that store "0" and "1" respectively, or comparing the output from the data bit column with half the sum of the outputs from the two reference bit columns associated with the data bit column that store "0" and "1" respectively.

9. One or more computer-readable media according to claim 6, wherein, The correlation adjustment circuit includes a multiplexing circuit configured to select between the output signal of the correlation circuit and a signal directly from the test controller or a signal generated by a device in the correlation adjustment circuit.

10. One or more computer-readable media according to claim 9, wherein, The device is configured to add a bit to the address of one or more reference bit columns in the reference bit columns associated with the column association circuitry to generate the address of the other one or more reference bit columns in the reference bit columns.

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