一种时钟监控电路及时钟监控方法
By designing in-phase and out-of-phase reference clock generation modules and adjusting the delay time of the delay unit, two detection modes are provided, which solves the problems of complexity and high power consumption of existing clock monitoring circuits and realizes low power consumption and high precision clock monitoring.
CN115357094BActive Publication Date: 2026-07-17INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-09-15
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing clock monitoring circuits are complex in design, consume a lot of power, and have uncontrollable detection accuracy, making it difficult to expand the system.
Method used
The design includes a co-phase reference clock generation module and an anti-phase reference clock generation module. The duty cycle of the reference clock is adjusted by regulating the delay time of the delay unit, providing two detection modes to achieve clock monitoring for different accuracy requirements.
Benefits of technology
A simple, low-power clock monitoring circuit was developed, capable of acquiring multiple types of clock monitoring results and quickly identifying clock problems under test, making it worthy of widespread application.
✦ Generated by Eureka AI based on patent content.
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Figure CN115357094B_ABST
Abstract
本发明涉及一种时钟监控电路及时钟监控方法，属于电子电路技术领域，解决了现有时钟监控方式存在的电路结构复杂、检测精度不可控等问题。一种时钟监控电路，包括：同相位参考时钟生成模块，用于生成与所述低频时钟的相位相同的同相位参考时钟；反相位参考时钟生成模块，用于生成与所述低频时钟的相位相反的反相位参考时钟；异常检测模块，用于以所述同相位参考时钟为参考，对待测时钟进行上升沿检测及下降沿计数，并根据上升沿检测及下降沿计数的结果生成所述待测时钟的时钟监控结果；或者，用于以所述反相位参考时钟为参考，对所述待测时钟进行上升沿计数及下降沿检测，并根据上升沿计数及下降沿检测的结果生成所述待测时钟的时钟监控结果。
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