Object management in a tiered memory system

Abstract

This invention discusses systems, devices, and methods for object management in hierarchical memory systems. An example method may include writing a memory object to a first memory device of a first type of memory medium. The example method may include determining that the size of the memory object meets or exceeds a threshold data size. The example method may also include writing the memory object to a second memory device comprising a second type of memory medium different from the first type. The first memory medium may be a non-volatile memory including phase-change memory or resistive random access memory (RAM), and the second memory medium may be NAND flash or NOR flash.

Description

Technical Field

[0001] This disclosure generally relates to memory objects, and more specifically, to devices, systems, and methods for object management in hierarchical memory systems. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during operation of the computing or other electronic system. Summary of the Invention

[0004] One aspect of this disclosure relates to a method comprising: writing a memory object to a first memory device including a first type of memory medium; determining that the size of the memory object satisfies or exceeds a threshold data size; and writing the memory object to a second memory device including a second type of memory medium different from the first type, wherein the first memory medium is a non-volatile memory including phase-change memory or resistive random access memory (RAM), and the second memory medium includes NAND flash or NOR flash.

[0005] Another aspect of this disclosure relates to a system comprising: a first memory device including a first type of memory medium, the first type of memory medium being a non-volatile memory including phase-change memory or resistive random access memory (RAM); a second memory device including a second type of memory medium, the second type of memory medium including NAND flash or NOR flash; and a controller coupled to the first memory device and the second memory device, the controller being configured to: write a plurality of memory objects to the first memory device; determine that the data size of any of the plurality of memory objects exceeds a threshold data size; and, in response to the corresponding size of the data of the corresponding plurality of memory objects being less than the threshold data size, write the corresponding memory object to the second memory device.

[0006] Another aspect of this disclosure relates to a system comprising: a first memory device including a first type of memory medium; a second memory device including a second type of memory medium; and a controller coupled to the first device and the second memory device and configured to: write each of a plurality of memory objects to the first memory device; and write the specific memory object to the second memory device in response to the size of a particular of the plurality of memory objects reaching the page size of the second memory device; wherein: the first type of memory medium is a non-volatile memory including phase-change memory or resistive random access memory (RAM); and the second type of memory medium includes NAND flash or NOR flash. Attached Figure Description

[0007] Figure 1A This is a block diagram of a computing system including a controller and a corresponding memory device, according to several embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a computing system including a controller and a memory device, according to several embodiments of the present disclosure.

[0009] Figure 2 This is a block diagram illustrating object management in a hierarchical memory system according to several embodiments of the present disclosure.

[0010] Figure 3 This is a flowchart illustrating an instance method for object management in a hierarchical memory system according to several embodiments of the present disclosure.

[0011] Figure 4 This is a flowchart illustrating an example of object management in a hierarchical memory system according to several embodiments of the present disclosure. Detailed Implementation

[0012] This describes systems, devices, and methods relating to object management in a hierarchical memory system. An example method may include writing a memory object to a first memory device of a first type of memory medium. The example method may include determining that the size of the memory object meets or exceeds a threshold data size. The example method may also include writing the memory object to a second memory device comprising a second type of memory medium different from the first type. The first memory medium may be a non-volatile memory including phase-change memory or resistive random access memory (RAM), and the second memory medium may be NAND flash or NOR flash.

[0013] In some embodiments, the first memory device may include a first type of memory medium, including, for example, emerging memory devices such as three-dimensional (3D) cross-point memory, phase-change memory, resistive random access memory (RAM), etc. The second memory device may include a second type of memory medium, including NAND flash or NOR flash. The memory system may include an address space partitioned between the first and second memory devices or contiguous across both the first and second memory devices. As an example, the address space may span both the first and second memory devices. Memory objects stored in the memory system may be associated with a specific address location in the address space, regardless of which of the first and second memory devices the memory object is stored in.

[0014] The embodiments described herein may further include writing each of a plurality of memory objects to one of a first memory device and a second memory device. A particular memory object may be written (e.g., transferred) to the other of the second memory device or the first memory device in response to the size of a particular memory object being a threshold data size. As an example, data associated with a memory object may be written to the first memory device, such as an emerging memory device. When the data of a memory object reaches a threshold data size, for example, the page size of a flash-based memory device, the memory object and data may be transferred to a non-volatile memory device. In this way, a smaller portion of the data may be initially written to the emerging memory device, and when the smaller portion of the data can be combined to form a full flash-based page size (e.g., a NAND page size), the combined data may be transferred to the flash-based memory device.

[0015] In this example, data associated with a memory object can be written to a second memory device, such as a non-volatile memory device that may contain a flash-based memory device. When data for a memory object is requested by a host from a flash-based (e.g., NOR or NAND) memory device, the data can be accessed from the flash-based memory device if the data is the same size as the page size or within a threshold of the page size. Furthermore, when data is requested by the host, if the data is smaller than the page size or the threshold data size, the data can be written to (e.g., transferred to) an emerging memory device before being accessed by the host. In this way, smaller data sizes can be accessed from the emerging memory device, where a smaller portion of the data can be accessed without accessing the full page size. In methods where data is held in a flash-based memory device, the host may be accessing the full page size of data in order to access a portion of data smaller than the full page size, thereby transferring data that has not yet been requested by the host and consuming unnecessary resources of the memory system.

[0016] As used herein, the term "memory object" and variations thereof generally refer to a contiguously addressed area of ​​data on a device that is uniquely identified and can be read or written. As used herein, "semantics" generally refers to the format of a memory object, instruction, command, or signal that refers to its meaning. For example, a memory object or instruction that can be understood by a first memory device may not be understood by a second memory device, and vice versa. By configuring the semantics associated with a memory object to be understood by either the first or second memory device, the memory object can be selectively written to either the first or second memory device.

[0017] As described herein, embodiments may include a memory system comprising a host and a memory device using a key-value database system. A key-value database is a data storage method and data structure, which may be referred to as a dictionary or hash table, for storing, retrieving, and managing associative arrays, wherein the dictionary may contain memory objects. These memory objects can be stored and retrieved using keys that uniquely identify records and can be used to look up data within the database, as will be described below. Figure 2 More detailed description.

[0018] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form part of this disclosure and illustrate by description how one or more embodiments of this disclosure can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice embodiments of this disclosure, and it should be understood that other embodiments may be utilized and process, electrical, and structural changes may be made without departing from the scope of this disclosure.

[0019] It should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a / an” and “the” may include both singular and plural indicators unless the context clearly indicates otherwise. Additionally, “a number,” “at least one,” and “one or more,” for example, a number of memory banks, may refer to one or more memory banks, while “more” is intended to refer to more than one such thing.

[0020] Furthermore, the word "can / may" is used throughout this application in a permissive (e.g., possible, able) rather than mandatory (e.g., required) sense. The term "comprising" and its derivatives mean "including (but not limited to)". Depending on the context, the terms "coupled" and "coupled" mean physically connected, directly or indirectly, or used for accessing and moving (transmitting) commands and / or data.

[0021] The figures in this document follow a numbering convention, where the first one or a few digits correspond to the figure number, and the remaining digits identify the elements or components within the figure. Similar elements or components between different figures can be identified by using similar digits. For example, 120 could refer to... Figure 1A Component "20" in the text, and similar components in Figure 2 The reference numeral 220 may be used. Generally, a single element number may be used herein to refer to a group or plurality of similar elements or components. For example, multiple reference elements 117-1 to 117-2 may be collectively referred to as 117. It should be understood that the elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of this disclosure and should not be construed as limiting.

[0022] Figure 1A This is a block diagram of a computing system 100 comprising a host 120 and a device including a memory system 110, according to several embodiments of the present disclosure. As used herein, "device" may refer to (but is not limited to) any of a variety of structures or combinations thereof, such as (for example) a circuit or circuit system, one or more dies, one or more modules, one or more devices, or one or more systems. The memory system 110 may include a storage class memory ("SCM") controller 115-1, a storage device controller 115-2, an emerging memory device 130, and a non-volatile ("NV") memory device 140, which includes flash-based memory devices, as will be described below.

[0023] SCM controller 115-1 may include a processor 117-1 (e.g., a processing device or processing unit) configured to execute instructions stored in local memory 119-1. Similarly, storage device controller 115-2 may include a processor 117-2 (e.g., a processing device or processing unit) configured to execute instructions stored in local memory 119-2. In the illustrated example, the local memories 119-1 and 119-2 of the SCM controllers / storage device controllers 115-1 and 115-2 each include embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of memory system 110, including processing communication between memory system 110 and host 120. Host 120 can communicate with memory system 110 via kernel 121, as will be further described below.

[0024] In some embodiments, local memories 119-1 and 119-2 may include memory registers storing memory pointers, fetched data, etc. Local memories 119-1 and 119-2 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1A The instance memory subsystem 110 is described as including controllers 115-1 and 115-2, but in another embodiment of this disclosure, the memory system 110 does not include a memory system controller and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0025] Generally, controllers 115-1 and 115-2 can receive commands or operations from host 120 and can translate these commands or operations into instructions or appropriate commands to achieve desired access to emerging memory device 130 and / or NV memory device 140. Controllers 115-1 and 115-2 may be responsible for other operations, such as wear leveling operations, discarded item collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with memory devices 130 and 140. Controllers 115-1 and 115-2 may further include features for accessing physical host interfaces (e.g., ...). Figure 1BThe host interface circuitry (HIP) communicates with host 120 via host interface 111. The HIP circuitry can translate commands received from the host into command instructions to access memory devices 130 and / or 140, and can also translate responses associated with memory devices 130 and / or 140 into information for host 120. Host 120 can specify a location in the address space for memory objects to be stored in memory system 110. Memory system 110 can use an address space partitioned between first memory device 130 and second memory device 140. As an example, the address space can span both first memory device 130 and second memory device 140.

[0026] Host 120 may be a host system, such as a personal laptop computer, vehicle, desktop computer, digital camera, smartphone, or Internet of Things (IoT) enabled device or memory card reader, graphics processing unit (e.g., video card), and various other types of host. Host 120 may include a system motherboard and / or backplane and may include several memory access devices, such as several processing resources, such as one or more processors, microprocessors, image processors, or some other type of control circuitry system. Those skilled in the art will understand that "processor" may mean one or more processors, such as a parallel processing system, several coprocessors, etc. Host 120 may be coupled to the host interface of memory system 110 (e.g., [missing information]) via communication channel 103. Figure 1B The host interface 111 in the host 120). The kernel 121 of the host 120 can be connected to the host interface (e.g., Figure 1B Communication via host interface 111).

[0027] As used herein, "IoT-enabled device" can refer to a device embedded with electronic components, software, sensors, actuators, and / or network connectivity that enable such device to connect to a network and / or exchange data. Examples of IoT-enabled devices include mobile phones, smartphones, tablet computers, phablets, computing devices, implantable devices, vehicles, home appliances, smart home devices, monitoring devices, wearable devices, devices enabling smart shopping systems, and other cyber-physical systems.

[0028] Host 120 may be responsible for executing an operating system for computing system 100, which includes memory system 110. Therefore, in some embodiments, host 120 may be responsible for controlling the operation of memory system 110. For example, host 120 may execute instructions for managing the hardware of computing system 100 (e.g., scheduling tasks, executing applications, controlling peripheral devices, etc.), for example, in the form of an operating system.

[0029] Emerging memory device 130 may include three-dimensional (3D) crosspoint memory, phase-change memory, and resistive random access memory (RAM), and NV memory device 140 may include NAND or NOR memory devices. As used herein, the term "emerging memory device" generally refers to resistive variable memory, such as 3-D crosspoint (crosspoint memory device, 3D XP device, etc.), phase-change memory, resistive RAM, memory devices containing arrays of self-select memory (SSM), ferroelectric random access memory (FeRAM), etc., or any combination thereof. Memory system 110 may be located remotely from the host (e.g., as part of a cloud database) and / or remotely from the location of the user accessing memory system 110.

[0030] Non-limiting examples of multiple memory devices of various types in Figure 1A As described in the text. A variable-resistance memory device can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Therefore, compared to many flash-based memories, variable-resistance non-volatile memories can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing. Compared to flash-based memories and variable-resistance memories, self-selecting memory cells can comprise memory cells having a single chalcogenide material serving as both a switch and a storage element for the memory cell.

[0031] In one example, emerging memory device 130 is not used as a cache for the memory system, and emerging memory device 130 is not used as a cache for NV memory device 140. In one example, the address space of each of the plurality of objects written to the first memory device or the second memory device may be a contiguous address space across the first memory device and the second memory device. That is, the address spaces of both emerging memory device 130 and NV memory device 140 may form a total address space and be used seamlessly as if the two memory devices were the same memory device. Although two memory device types (e.g., emerging memory and NAND) have been described, the embodiments are not limited thereto, and more or fewer memory media types may exist. For example, several embodiments assume the use of memory devices that include different types of emerging memory and / or different types of non-volatile or volatile memory. That is, for example, other types of volatile and / or non-volatile memory media devices are considered.

[0032] like Figure 1A As described herein, in several embodiments, controllers 115-1, 115-2, memory devices 130, 140, and / or host interfaces ( Figure 1BThe memory device 111) can be physically located on a single die or within a single package, for example, in a managed memory application. Furthermore, in several embodiments, multiple memory devices 130, 140 may be included on a single memory system 110. Moreover, in some embodiments, more than one memory device may include an array of memory cells of the same type.

[0033] Figure 1B This is a block diagram of a computing system 100, comprising a host 120 and a device including a memory system 110, according to several embodiments of the present disclosure. The computing system 101 may be similar to... Figure 1A The computing system 100 includes a single memory controller 115 that can communicate with each of the emerging memory device 130 and the non-volatile (“NV”) memory device 140. For example, the memory controller 115 can generate commands and / or signals to read data from and write data to each of the emerging memory device 130 and the NV memory device 140. The memory controller 115 may be able to communicate with both emerging memory cells (e.g., 3D cross-point memory cells, phase-change memory cells, resistive RAM memory cells) and NV memory cells (e.g., NAND memory cells).

[0034] Furthermore, memory devices 130 and 140 may each include a corresponding control circuitry system, with memory controller 115 communicating with the control circuitry system to perform memory read and write operations within each of memory devices 130 and 140. However, embodiments are not limited thereto. For example, embodiments assume that several memory devices include control circuitry systems, while several different memory devices do not. The operations discussed herein may be performed by a controller, a control circuitry system, or a combination thereof.

[0035] Figure 2 This is a block diagram 202 illustrating object management in a hierarchical memory system according to several embodiments of the present disclosure. Block diagram 202 includes a host 220 and a memory system 210. The host 220 may be similar to... Figure 1A and 1B The host 120 is located in the memory system 210, which may be similar to the host 120. Figure 1A and 1B The memory system 110 is included. Host 220 includes host application 231, mapped file system 233, and kernel 235. Host application 231 may use key-value database methods, as described below, to read or request data from memory devices 230, 240 and to send or store data in memory devices 230, 240. Memory system 210 includes emerging memory device 230 and non-volatile (“NV”) memory device 240.

[0036] Key-value databases are a type of non-relational database that uses a key-value approach to store data. They store data as a collection of key-value pairs, where the key serves as a unique identifier. Key-value databases associate values ​​(which can be anything from numbers or simple strings to complex objects) with keys, which are used to track objects. They can use compact, efficient index structures to locate values ​​by their keys, making them useful for systems that look up and retrieve data in constant time. Both keys and values ​​can be anything, ranging from simple objects to complex composite objects. Key-value databases are partitionable and allow for horizontal scaling to scales that other types of databases might not be able to achieve.

[0037] A key-value database allows a program or its user to retrieve data by a key pointing to a stored value, where the key is essentially a name or identifier. A key-value database can be associated with a set of operations including: retrieving a stored value associated with a given key (if a value exists), deleting a stored value associated with a given key (if a value exists), and setting, updating, and replacing a value associated with a given key (if a value exists).

[0038] The host application 231 can request to store data or retrieve data from a memory device, such as emerging memory device 230 or NV memory device 240. The mapped file system 233 can assign keys to specific memory objects and indicate the location where that memory object will be stored or retrieved. A first mapping list 243 can be used to specify that a memory object is stored in emerging memory device 230, and a second mapping list 245 can be used to specify that a memory object is stored in NV memory device 240.

[0039] As an example, such as Figure 2The description states that the first key in the first mapping list 243 (e.g., "file 45") can be specified as stored as logical address 8 (e.g., "LA8"). The second key in the first mapping list 243 (e.g., "file 5") can be specified as stored as logical address 10 (e.g., "LA10"), and the third key (e.g., "file 9") can be specified as stored as logical address 234 (e.g., "LA234"). Furthermore, the first key (e.g., "file 0"), the second key (e.g., "file 1"), and the third key (e.g., "file 2") in the second mapping list 245 can be specified as stored as logical block addresses 0, 1, and 2 (e.g., "LBA0", "LBA 1", and "LBA 2" respectively). The "LA" portion can indicate that the memory object will be located in the emerging memory device 230 (stored at or retrieved from the emerging memory device 230), and the "LBA" portion can indicate that the memory object will be located in the NV memory device 240. Each of these key values ​​(e.g., "file45", "file5", "file9", "file0", "file1", "file2") can be sent to the host (e.g., Figure 1A and 1B The kernel 235 of the host 120 is used to retrieve or store associated memory objects.

[0040] Although "LA" can specify the first memory device 230 and "LBA" can specify the second memory device 240, the address space used to address the location of a memory object can be divided between or span both the first memory device 230 and the second memory device 240. For example, when using a total user-addressable space of 1 gigabit (GB), a memory object can be divided into 300 megabytes (MB) in the first memory device 230 and 700 MB in the second memory device, 250 MB in the first memory device and 750 MB in the second memory device, 900 MB in the first memory device and 100 MB in the second memory device, or any ratio. Furthermore, for a given percentage of small data-sized memory objects, a certain percentage of the address space can be allocated to the first memory device, and the remaining data can be allocated to the second memory device.

[0041] Kernel 235 may be software and / or code that performs operations (e.g., low-level operations) and interacts with the hardware and / or software components of the operating system (OS) and is controlled and / or executed by the computing system. Kernel 235 may coordinate memory, peripheral devices, and input / output (I / O) requests from software, translating them into data processing instructions for the central processing unit and enabling application software to be connected to the computer's hardware. Kernel 235 may perform tasks such as running processes, managing hardware devices such as hard disks, and handling interrupts. The interface of kernel 235 may be a low-level abstraction layer.

[0042] Core 235 can communicate with emerging memory device 230 using Double Data Rate (DDR) software protocol 237 for communicating with emerging memory. Core 235 can communicate with NV memory device 240 using Non-Volatile Memory High Speed ​​(NVMe) software protocol 239. NVMe software protocol 239 is an open logic device interface specification for accessing non-volatile memory media attached via the PCI Express (PCIe) bus.

[0043] In some embodiments, the determination of whether to store the key and associated data in emerging memory device 230 or NV memory device 240 may be based on the type of feature set. Embodiments assume that a feature set may include one or more features, including (but not limited to) access frequency, memory access size (e.g., the number of bits associated with a memory object), and / or whether memory access includes sequential or non-sequential access. For example, a memory object accessed during a specific time period at a first access frequency greater than a second access frequency during that specific time period may be stored in emerging memory device 230. As examples, a higher access frequency may include several times a day, several times a week, etc. A lower access frequency may include once a month, once a year, etc. A more frequently accessed memory object may be referred to as "hot" and may refer to a memory object that is updated more frequently by the host and / or other external devices. A memory object accessed at a second access frequency may be stored in NV memory device 240. A memory object with a second access frequency may be referred to as "cold" and may refer to a memory object that is updated less frequently by the host and / or external devices. In this way, the access frequency can be used to specify whether the key-value pair of the memory object indicates "LA" (and is stored in the emerging memory device 230) or "LBA" (and is stored in the NV memory device 240).

[0044] Furthermore, access frequency can indicate how frequently the associated address space is accessed during a specific time interval. The embodiments assume that for a first set of characteristics, the specific time interval may be smaller than the time interval for a second set of characteristics, i.e., a shorter period of time. The specific time interval may have various values, for example, depending on the application. As an example, a stock account database may be frequently updated or accessed because the data can change rapidly. A health database may be updated or accessed less frequently because the data may be updated when patients visit healthcare facilities, etc. In one example, such as an aviation database, a mixture of small, frequently updated memory objects (e.g., data associated with flight tracking coordinates) and large, less frequently updated memory objects (e.g., maintenance data) may be accessed.

[0045] As another example, the specific time interval can be 5 microseconds, 10 microseconds, 1 second, 1 minute, 1 day, 1 month, 1 year, and other values. Furthermore, the embodiments assume that the specific time interval can change over time, for example, based on changing workloads, baseline and / or host data traffic behavior. Generally, a higher access frequency will make a memory object "hotter" compared to another memory object that may be "colder" with a lower access frequency. In other words, a memory object with a higher or maximum access frequency will typically have a first designation (and be stored in emerging memory device 230), and a memory object with a lower or minimum access frequency will typically be stored in NV memory device 240.

[0046] The embodiments assume that a set of characteristics may include one or more characteristics, including (but not limited to) the size of the memory object, access frequency, a type of key-value data, etc. For example, a memory object with a first data size greater than the second data size may be stored in emerging memory device 230. As an example, the smaller data size may include 1 kilobyte (KB), 2KB, 4KB, 16KB. As an example, the larger data size may include data sizes ranging from 16KB to several gigabytes (GB). Memory objects accessed with the second data size may be stored in NV memory device 240. This can be particularly useful when using hybrid workloads that can operate more efficiently when optimized for both large data blocks (e.g., written to NAND memory devices in the description herein) and smaller data segments (e.g., written to emerging memory devices in the description herein). In this way, the data size can be used to specify whether the key-value pair of the memory object indicates "LA" (and is stored in emerging memory device 230) or "LBA" (and is stored in NV memory device 240). Although the example descriptions are initially stored in emerging memory device 230 or NV memory device 240, the embodiments are not limited thereto.

[0047] For example, a memory object may initially be stored in emerging memory device 230 and sent to the host, then expanded to contain a larger memory object (but still associated with the same key) and subsequently stored in NV memory device 240. Similarly, a memory object may initially be stored in emerging memory device 230 and sent to the host, then accessed at a lower frequency and subsequently stored in NV memory device 240. The size of a memory object may correspond to the number of bits or other information contained within the memory object. Generally, a smaller size will make a memory object "hotter" compared to another memory object of a larger size, because if the memory object is smaller, it can also be accessed more frequently.

[0048] The embodiments assume that the specifications of a memory object can change over time. Over time, the type of the set of characteristics associated with the memory object can change. In other words, one or more characteristics associated with the memory object can change over time. For example, the access frequency of the memory object over short time intervals can decrease over time, or the data size of the memory object can increase or decrease over time. As an example, a decrease in access frequency can make the memory object less "hot" compared to a memory object before the access frequency decreases. Therefore, this decrease can cause the memory object to be moved from one memory device type to another.

[0049] This embodiment assumes a set of characteristics that may include one or more characteristics, including (but not limited to) the size of the memory object, access frequency, and / or the type of key-value data. For example, the key of the memory object may be stored in emerging memory device 230, and the data associated with the key may be stored in NV memory device 240. In this instance, the key-value data may no longer be the memory object itself, because the memory object in the key-value database contains both the key and the data associated with it. In this way, the key-value data type can be used to specify whether a key-value pair indicates "LA" (and is stored in emerging memory device 230) or "LBA" (and is stored in NV memory device 240). The hash table used to associate the key with the data may also be stored in emerging memory device 230. In this way, the determination of whether to locate data in NV memory device 240 can be performed quickly.

[0050] Furthermore, updates to the key can be stored in a cache update table in the emerging memory device 230 during foreground operations, for example, when the memory system is performing additional operations. Updates to data in the NV memory device 240 associated with the updated key (stored in the emerging memory device 230) can be performed in the background using the cache update table, for example, when the memory device is not performing additional operations, is in sleep mode, or is in another reduced power state. In this way, memory resources can be saved for currently executing operations and used to update data to the NV memory device 240 when the operations are completed.

[0051] Figure 3 This is a flowchart 351 illustrating an example method for object management in a hierarchical memory system according to several embodiments of the present disclosure. Method 351 can be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions running or executed on a processing means) or a combination thereof. In some embodiments, method 351 is performed by… Figure 1A The method 351 is executed by the processor of host 120. In some embodiments, the method 351 is performed by... Figure 1A The control circuitry of the host 120 described herein is executed. Although shown in a specific order or sequence, the order of the processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0052] In box 353, method 351 may include writing a memory object to a first memory device. The first memory device may be similar to those described in [the respective boxes]. Figure 1A The first memory devices 130 and 230 in / 1B and 2. The first memory device may be a memory medium of a first type, including emerging memories such as crosspoint memory, phase-change memory, and resistive RAM. The second memory device may be similar to those in / 1B and 230 respectively. Figure 1A The second memory devices 140 and 240 in / 1B and 2. The second memory device may be a second type of memory medium comprising non-volatile memory including NAND flash or NOR flash. The flash-based memory device may be a NAND memory device or a NOR memory device. In some instances, writing a memory object may involve initially writing the memory object to an emerging memory device.

[0053] In box 355, method 351 may include determining that the size of the memory object is equal to or exceeds a threshold data size. As an example, the threshold data size may be a page size (e.g., a NAND page size or a NOR page size). Then, it may be determined that the size of the memory object is equal to or greater than (exceeds) the page size.

[0054] In box 357, method 351 may include writing a memory object to a second memory device. For example, data stored in a first memory device may be written to (or transferred to) the second memory device. The memory object may be written in response to a data size equal to or greater than a threshold data size. As an example, the memory object may be written from the first memory device to the second memory device in response to a memory object equal to or greater than 16 kilobytes (KB) (in some instances, this may refer to a page size). In other words, data may be written to the first memory device (e.g., a cross-point memory device) until the data reaches a data size equal to the page size of the second memory device (e.g., a flash-based memory device), at which point the data may be written to (or transferred to) the second memory device (e.g., a flash-based memory device).

[0055] In another instance, a particular memory object can be transferred from a second memory device to a first memory device in response to the data associated with that particular memory object being less than 16KB. The transfer of data from a flash-based memory device to a cross-point memory device allows a host requesting access to the data to access a data size smaller than a full page size. In response to the data equaling the page size, the data can remain in the flash-based memory device and be accessed by the host from the flash-based memory device.

[0056] Figure 4 This is a flowchart 471 illustrating an example of object management in a hierarchical memory system according to several embodiments of the present disclosure. The operation of flowchart 471 can be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method is... Figure 1A The method is executed by the processor of host 120. In some embodiments, the method is performed by... Figure 1A The control circuitry of the host 120 described herein is executed. Although shown in a specific order or sequence, the order of the processes is modifiable unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0057] In operation 473, multiple memory objects can be written to the flash-based memory device. In operation 475, a request to access data of the memory objects in the flash-based memory device can be received. The request can be sent by the host to the controller of the memory system containing the flash-based memory device. The instance data size can include 1 kilobyte (KB), 2KB, 4KB, 16KB, and its range can also be from 16KB to several gigabytes (GB).

[0058] In operation 477, it can be determined whether the data size is less than a threshold data size. In response to the data size being less than the threshold data size (indicated by "YES"), as described in operation 479, the memory object can be transferred to the crosspoint memory device. The data transferred to the crosspoint memory device can be accessed by the host in the crosspoint memory device. The host can request access to a portion of the data that could be a full page size. The data accessed by the host can be a portion of the data that would otherwise be accessed if the data were held in a flash-based memory device, as it would likely have been a full page size. That is, the host can access the data that is requested to be accessed without accessing a portion of the data that would have been a full page size if the data were held in a flash-based memory device. In response to the data size being equal to or greater than the threshold data size (indicated by "NO"), as described in operation 481, the memory object can be read from the flash-based memory device. In this example, the memory object can be read from the flash-based memory device without transferring the memory object to the crosspoint memory device.

[0059] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description is illustrative rather than restrictive. Those skilled in the art will understand, upon review of the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications in which the foregoing structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims and the full scope of their equivalents.

[0060] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. The method of this disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than are expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is considered an independent, separate embodiment.

Claims

1. A method comprising: The memory object is written to a first memory device (130, 230) including a memory medium of the first type, wherein: The memory object is associated with a first key in a key-value database structure, and the key-value database structure is associated with the first memory device; and The first key is stored in the first memory device; Sure: Does the size of the memory object meet or exceed the threshold data size? Whether the access frequency of the memory object is lower than the threshold access frequency; In response to determining that the size of the memory object meets or exceeds the threshold data size or that the access frequency of the memory object is lower than the threshold access frequency, the memory object is written to a second memory device (140, 240) comprising a second type of memory media different from the first type of memory media by the following operations: Retrieve the first key from the first memory device to locate the memory object in the first memory device; The first key is updated, and the updated first key is associated with the second memory device; and The memory object is associated with the updated first key, and the updated first key is stored in the first memory device, wherein the updated first key indicates the storage location of the memory object in the second memory device. in: The first memory device and the second memory device are external to the host computer; and The first type of memory medium is a non-volatile memory including phase-change memory or resistive random access memory (RAM), and the second type of memory medium includes NAND flash or NOR flash.

2. The method of claim 1, wherein the address spaces of the first memory device and the second memory device are contiguous across both the first memory device and the second memory device.

3. The method according to claim 1, wherein: Writing the memory object includes initially writing the memory object to the first memory device; and Writing the memory object to the second memory device includes writing the memory object to the second memory device in response to a particular memory object reaching the page size associated with the second memory device.

4. The method of claim 3, wherein the page size is a NAND page.

5. The method of claim 3, wherein the page size is 16 kilobytes (KB).

6. The method of claim 1, wherein the memory object is written to the second memory device in response to the host writing data exceeding the threshold data size to the first memory device.

7. The method of claim 1, wherein the threshold data size is based on the data size of a flash memory page.

8. A system comprising: A first memory device (130, 230) includes a first type of memory medium, which is a non-volatile memory including phase-change memory or resistive random access memory (RAM). The second memory device (140, 240) includes a second type of memory medium, which includes NAND flash or NOR flash. The first memory device and the second memory device are located outside the host computer; and A controller (115), coupled to the first memory device and the second memory device, is configured to: Multiple memory objects are written to the first memory device, wherein each of the multiple memory objects is associated with a first set of keys of a key-value database structure, the key-value database structure being associated with the first memory device, and the first set of keys being stored in the first memory device; Sure: Whether the data size of any of the plurality of memory objects exceeds the threshold data size; or Whether the access frequency of any of the plurality of memory objects exceeds the threshold access frequency; In response to a situation where the size of the data for a given plurality of memory objects is less than the threshold data size or the access frequency of the given plurality of memory objects is greater than the threshold access frequency, the given plurality of memory objects are maintained in the first memory device. In response to the fact that the corresponding size of the data of the corresponding plurality of memory objects is greater than the threshold data size or the corresponding access frequency of the corresponding plurality of memory objects is less than the threshold access frequency, the corresponding plurality of memory objects are written to the second memory device by the following operation: Update the corresponding key in the first set of keys associated with the respective plurality of memory objects, and the updated corresponding key is associated with the second memory device; Associate the respective plurality of memory objects with the updated corresponding keys; and The updated corresponding key is stored in the first memory device.

9. The system of claim 8, wherein the address space for storing each of the plurality of memory objects spans continuously across the second memory device and the first memory device.

10. The system of claim 8, wherein in response to one of the plurality of memory objects associated with the data being written to the second memory device, the controller is configured to access a portion of the plurality of memory objects containing the data in the second memory device.

11. The system of claim 8, wherein the host is configured to: Send a request to the controller for the data stored in the second memory device; and In response to the memory object associated with the data being written to the second memory device, the data is received from the second memory device via the controller.

12. The system of claim 8, wherein the physical address space for storing each of the plurality of memory objects spans continuously across the first memory device and the second memory device.

13. The system of claim 8, wherein the first memory device is not used as a cache in both the system and the second memory device.

14. The system of claim 8, wherein the host is configured such that the memory objects among the plurality of memory objects can be sent to the first memory device using the Double Data Rate (DDR) protocol (237) and to the second memory device using the Flash-based High Speed ​​NVME protocol (239).

15. A system comprising A first memory device (130, 230) includes a memory medium of a first type; The second memory device (140, 240) includes a memory medium of a second type; The first memory device and the second memory device are located outside the host computer; and A controller (115) coupled to the first memory device and the second memory device and configured to: Each of a plurality of memory objects is written to the first memory device, wherein each of the plurality of memory objects is associated with a first set of keys of a key-value database structure associated with the first memory device, and the first set of keys is stored in the first memory device. and In response to the fact that the size of a particular memory object among the plurality of memory objects reaches the page size of the second memory device, the particular memory object is written to the second memory device; or In response to the access frequency of a particular memory object among the plurality of memory objects being lower than a threshold access frequency, the particular memory object is written to the second memory device; in: Writing a specific memory object to the second memory device includes: Retrieve a key from the first set of keys associated with the specific memory object from the first memory device to locate the specific memory object in the first memory device; Update the key in the first set of keys associated with the specific memory object, and the updated key is associated with the second memory device; and Associating the specific memory object with the updated key and storing the updated key in the first memory device, wherein the updated key indicates the storage location of the specific memory object in the second memory device; The first type of memory medium is a non-volatile memory including phase-change memory or resistive random access memory (RAM); and The second type of memory media includes NAND flash or NOR flash.

16. The system of claim 15, wherein the controller is configured to: In response to a specific memory object among the plurality of memory objects having a size lower than the page size of the second memory device, the specific memory object is maintained in the first memory device; or In response to the access frequency of a particular memory object among the plurality of memory objects being higher than a threshold access frequency, the particular memory object is maintained in the first memory device.

17. The system of claim 15, wherein the page size is a NAND page size.

18. The system of claim 15, wherein the controller is configured to write the plurality of memory objects to the first memory device using the key-value database structure comprising the first set of keys and the updated keys.

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