Dynamically scalable set-associative cache method, apparatus, device and media
By dynamically expanding cache groups, shared cache blocks are associated with frequently used cache groups, which solves the problem of low cache group resource utilization and improves storage access performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PENG CHENG LAB
- Filing Date
- 2022-08-31
- Publication Date
- 2026-07-17
AI Technical Summary
In existing technologies, the utilization rate of cache group resources is low, which leads to frequent replacement operations in some cache groups while other cache groups are idle, resulting in resource waste.
By dynamically associating shared cache blocks with frequently used cache groups, their storage space is expanded, the number of cache blocks in the cache group is increased, and replacement operations are reduced.
It improves the resource utilization of the cache group, reduces replacement operations, and enhances storage access performance.
Smart Images
Figure CN115357196B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing, and in particular to a dynamically scalable set-associative cache method, apparatus, device, and storage medium. Background Technology
[0002] In related technologies, the cache organization structure is a set-associative structure, which divides the cache into many cache sets, each containing a number of cache blocks. The number of cache blocks in each set is the associativity of the cache. When writing data, the set in the cache where the data should be placed is determined based on the memory access address issued by the processor.
[0003] However, the addresses accessed by the processor during program execution may not be evenly distributed across different cache sets. Some cache sets may fill up early, while a large number of data blocks still need to be placed into those cache sets. This results in frequent replacement operations, where a cache block is flushed to the next level of storage according to the replacement policy, and new data blocks are written to that location. Meanwhile, other cache sets may remain inaccessible, with their cache blocks remaining idle. This is the technical problem of low cache set resource utilization in existing technologies.
[0004] Application content
[0005] The main objective of this application is to provide a dynamically scalable set-associative cache method, apparatus, device, and storage medium, aiming to solve the technical problem of low resource utilization of existing cache sets.
[0006] To achieve the above objectives, this application provides a dynamically scalable set-associative cache method, the method comprising:
[0007] Based on the write address of the data to be cached, a first cache group is determined from the data cache; wherein, the data cache further includes at least one shared cache block;
[0008] Determine whether there is any remaining storage space in all cache blocks corresponding to the first cache group;
[0009] If there is no remaining storage space, at least one temporary cache block is selected from at least one shared cache block; wherein, the temporary cache block is a shared cache block that does not store data.
[0010] Associate the temporary cache block with the first cache group and return the address information of the temporary cache block;
[0011] Based on the address information, the data to be cached is written into the temporary cache block.
[0012] In one embodiment, determining a temporary cache block from at least one shared cache block if there is no remaining storage space includes:
[0013] If there is no remaining storage space, then determine the data storage status of at least one shared cache block in turn;
[0014] The first shared cache block that does not store data is used as the temporary cache block.
[0015] In one embodiment, after writing the data to be cached into the temporary cache block according to the address information, the method further includes:
[0016] If the data written in the temporary cache block is retrieved, the association between the temporary cache block and the cache group is terminated.
[0017] In one embodiment, the method further includes:
[0018] Based on the access address of the received access request, determine the second cache group of the data to be accessed in the data cache;
[0019] Search for the data to be accessed corresponding to the access request in all cache blocks corresponding to the second cache group;
[0020] If the cache misses, the data to be accessed is searched for in the second temporary cache block corresponding to the second cache group.
[0021] If a hit occurs in the second temporary cache block, the stored data in the second temporary cache block is returned.
[0022] In one embodiment, the step of searching for the data to be accessed from the second temporary cache block corresponding to the second cache group if a cache miss occurs includes:
[0023] If a cache miss occurs, determine whether the second cache group is associated with the second temporary cache block.
[0024] If an association exists, the data to be accessed is searched from the second temporary cache block.
[0025] In one embodiment, the data cache has a pre-configured shared cache block indicator table;
[0026] The step of determining whether the second cache group is associated with the second temporary cache block includes:
[0027] Query the temporary cache status corresponding to the second cache group in the shared cache block indicator table;
[0028] If the temporary cache status is valid, then it is determined that the second cache group is associated with the second temporary cache block;
[0029] If the temporary cache status is invalid, then it is determined that the second cache group is not associated with the second temporary cache block;
[0030] The step of searching for the data to be accessed in the second temporary cache block includes:
[0031] The data to be accessed is searched from the second temporary cache block according to the second address information corresponding to the second cache group in the shared cache block indication table.
[0032] In one embodiment, after determining the second cache group of the data to be accessed in the data cache based on the access address of the received access request, the method further includes:
[0033] Search in parallel for the data to be accessed corresponding to the access request from all cache blocks and the second temporary cache block corresponding to the second cache group;
[0034] If a match is found, the stored data that was found is returned.
[0035] Secondly, this application also provides a dynamically scalable set-associative cache device, the device comprising:
[0036] A cache group determination module is used to determine a first cache group from a data cache based on the write address of the data to be cached; wherein the data cache further includes at least one shared cache block;
[0037] The space determination module is used to determine whether there is any remaining storage space in all cache blocks corresponding to the first cache group;
[0038] A temporary cache determination module is used to select a temporary cache block from at least one shared cache block if there is no remaining storage space; wherein the temporary cache block is a shared cache block that does not store data.
[0039] A cache association module is used to associate the temporary cache block with the first cache group and return the address information of the temporary cache block;
[0040] The data writing module is used to write the data to be cached into the temporary cache block according to the address information.
[0041] Thirdly, this application also provides a data caching device, including: a processor, a memory, and a data caching program stored in the memory, wherein the data caching program is executed by the processor to implement the steps of the dynamically scalable set-associative cache method described in any of the first aspects above.
[0042] Fourthly, this application also provides a computer-readable storage medium storing a data caching program, which, when executed by a processor, implements the dynamically scalable set-associative caching method described in any of the first aspects.
[0043] This application proposes a dynamically scalable set-associative cache method, comprising: determining a first cache group from a data cache based on the write address of the data to be cached; wherein the data cache further includes at least one shared cache block; determining whether there is remaining storage space in all cache blocks corresponding to the first cache group; if there is no remaining storage space, selecting a temporary cache block from the at least one shared cache block; wherein the temporary cache block is a shared cache block that does not store data; associating the temporary cache block with the first cache group and returning the address information of the temporary cache block; and writing the data to be cached into the temporary cache block according to the address information.
[0044] Therefore, in this application, a portion of the storage space in the data cache is used as a shared cache block. When some cache groups are used frequently, resulting in the storage space of the cache blocks they contain being used up, at least one shared cache block can be associated with the cache group, that is, at least one shared cache block is allocated to the aforementioned cache group for use, thereby increasing the number of cache blocks in the cache group, expanding its storage space, thereby reducing the occurrence of replacements, and thus improving resource utilization. Attached Figure Description
[0045] Figure 1 A schematic diagram of the data caching device required for the dynamically scalable set-associative caching method of this application;
[0046] Figure 2 This is a flowchart illustrating the first embodiment of the dynamically scalable set-associative caching method of this application.
[0047] Figure 3 This is a flowchart illustrating the second embodiment of the dynamically scalable set-associative caching method of this application.
[0048] Figure 4 This is a flowchart illustrating the third embodiment of the dynamically scalable set-associative caching method of this application.
[0049] Figure 5 This is a flowchart illustrating the fourth embodiment of the dynamically scalable set-associative caching method of this application.
[0050] Figure 6 This is a flowchart illustrating the fifth embodiment of the dynamically scalable set-associative caching method of this application.
[0051] Figure 7 This is a functional module diagram of an embodiment of the dynamically scalable set-associative cache device of this application.
[0052] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0053] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.
[0054] In related technologies, the processor's operating speed in a computer or chip is often greater than the read / write speed of main memory. To improve the processor's access speed to main memory, a cache is introduced. A cache is a small-capacity but high-speed memory located between the processor and main memory (DRAM, Dynamic Random Access Memory), typically composed of SRAM (Static Random Access Memory). A system may have multiple levels of cache. Because the cache capacity is small, it stores a subset of the data in main memory. It utilizes the principles of temporal and spatial locality of reference to improve memory access performance. If the data needed by the processor is found in the current level of cache, it is called a hit. With a hit, there is no need to access the slower next level of memory; the data can be retrieved directly from the cache. Because the cache operates much faster than main memory, performance is significantly improved. If the data needed by the processor is not found in the current level of cache, it is called a miss, and the next level of memory needs to be accessed to retrieve the required data.
[0055] In a cache, the smallest unit for exchanging data with the next-level storage is a cache block (or line). This means that data is transferred between the cache and the next-level storage in units of cache blocks. A common cache organization structure is set-associative, which divides the cache into many cache sets, each containing a number of cache blocks. The number of cache blocks in each cache set is the associativity of that cache. When writing data, the cache set in the cache is determined by the memory access address issued by the processor. However, which cache block within that set is not fixed; any cache block in that set can potentially hold the data. For example, in a 256-set 4-way cache structure, there are 256 sets, each containing 4 cache blocks. The cache set in which a data block is placed is fixed, but the 4 positions within that cache set are not fixed.
[0056] One type of failure in set-associative caches is called a conflict failure. Because a cache set contains a limited number of cache blocks, if many data blocks from different addresses are mapped to the same cache set, some data blocks may be discarded and then replaced when needed again, resulting in a conflict failure. Increasing the associativity can reduce conflict failures.
[0057] In current implementations, the number of cache sets and their associativity are generally fixed; that is, the number of sets, the associativity, and the cache capacity remain constant. However, during program execution, the addresses accessed by the processor may not be evenly distributed across the cache sets. Some cache sets may be filled early, yet a large number of data blocks still need to be placed into those cache sets, leading to frequent replacement operations: according to the replacement policy, a cache block is flushed to the next level of storage, and a new data block is written to that location. Meanwhile, other cache sets may remain inaccessible, with their cache blocks remaining idle. For example, a cache may contain 1024 sets, each with 4 cache blocks (a 4-way set-associative cache). If sets 0 and 1 are completely idle, set 2 contains all valid data, and set 3 contains 3 valid blocks... If the newly accessed data needs to be placed in the second group at this time, a cache conflict will occur and the cache will fail. The data block needs to be retrieved from the lower-level storage, and a cache block from the second group needs to be written to the next level of storage. Then, the new data is put into that cache block. At this time, although there are many free spaces in other groups, they cannot be used because the second group is full and needs to be replaced.
[0058] Therefore, in related technologies, the group to which a cache block belongs is fixed. Even if cache blocks in some groups are idle while frequent replacement operations occur in other groups, it cannot use cache blocks in idle groups.
[0059] To address this issue, this application provides a solution that increases the number of cache blocks in certain cache groups based on their utilization, thereby mitigating replacement frequency, reducing miss rates, increasing hit rates, and ultimately improving memory access performance. In this application, increasing the number of cache blocks in certain cache groups is achieved by allocating shared cache blocks. Specifically, when frequent use of certain cache groups leads to the exhaustion of their cache block storage space, at least one shared cache block can be associated with that cache group, thus allocating at least one shared cache block to that cache group. This increases the number of cache blocks within that cache group, expands its storage space, reduces replacement occurrences, and ultimately improves resource utilization.
[0060] The inventive concept of this application is further illustrated below with reference to some specific embodiments.
[0061] Reference Figure 1 , Figure 1The hardware operating environment involved in the embodiments of this application Data caching A schematic diagram of the equipment.
[0062] like Figure 1 As shown, the data caching device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as a disk drive. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.
[0063] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the data caching device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0064] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and a data caching program.
[0065] exist Figure 1 In the data caching device shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in the data caching device of this application can be set in the data caching device. The data caching device calls the data caching program stored in the memory 1005 through the processor 1001 and executes the dynamically scalable group-associative cache method provided in the embodiment of this application.
[0066] Based on, but not limited to, the above hardware structure, this application provides a first embodiment of a data cache. (Refer to...) Figure 2 , Figure 2 A flowchart illustrating the first embodiment of the dynamically scalable set-associative caching method of this application is shown.
[0067] It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.
[0068] In this embodiment, the method includes:
[0069] Step S101: Determine the first cache group from the data cache according to the write address of the data to be cached; wherein the data cache also includes at least one shared cache block.
[0070] Specifically, in this embodiment, when the processor processes data to be cached, it issues a cache instruction. This cache instruction includes a corresponding access address, i.e., a write address. This access address points to a specific cache group in the data cache. Based on the above description, it can be understood that the data cache is a high-speed cache, a small-capacity but high-speed memory located between the processor and the main memory DRAM (Dynamic Random Access Memory), typically composed of SRAM (Static Random Access Memory). The system may have multiple levels of cache; in this case, the data cache in this embodiment can be a level-one cache. Furthermore, based on the above description, since the processor's write addresses during program execution may not be evenly distributed across the various cache groups, the write address may point to some frequently used cache groups.
[0071] In this embodiment, the entire cache space in the data cache consists of two parts: a fixed storage space and a shared storage space. The architecture of the fixed storage space is the same as that in existing group-associative caches, meaning that each cache block belongs to a fixed cache group. The shared storage space consists of at least one shared cache block, which is not fixed to any particular cache group.
[0072] In one example, the data cache address width is 32 bits, and the cache block width is 4 bytes. Therefore: the Offset field has a width of 2 bits (4 bytes represented by 2 bits), the index has a width of 8 bits (for 256 groups), and the Tag field has a width of 22 bits. The fixed storage space includes 256 cache groups, each with 2-way cache blocks. The shared storage space includes 128 cache blocks. Understandably, to simplify control costs, two consecutive shared cache blocks can be allocated as a unit, and the entire shared storage space can be distributed among 64 cache groups. Alternatively, each shared cache block can also be allocated as a unit, and the entire shared storage space can be distributed among 128 cache groups. Specifically, the number of shared cache blocks used simultaneously as a unit can be configured by registers.
[0073] The cache block structure in both fixed storage space and shared storage space is the same, including a 1-bit valid bit V field, a 22-bit tag field, and a 32-bit data field.
[0074] In some specific embodiments, the data cache is configured with a shared storage space management module, which is responsible for recording the total size of the shared storage space, the grouping status, the utilization status of each group, and the allocation and reclamation of shared cache blocks.
[0075] In this step, the cache group that needs to write data is first determined based on the issued write address.
[0076] Step S102: Determine whether there is any remaining storage space in all cache blocks corresponding to the first cache group.
[0077] Step S103: If there is no remaining storage space, at least one temporary cache block is selected from at least one shared cache block; wherein, the temporary cache block is a shared cache block that does not store data.
[0078] Step S104: Associate the temporary cache block with the first cache group and return the address information of the temporary cache block.
[0079] Specifically, first determine if there are any free blocks among all cache blocks corresponding to the first cache group in the fixed storage space. If there are, write the data to be cached into the free block. At this point, the data caching process ends.
[0080] If there are no free blocks among all cache blocks corresponding to the first cache group in the fixed storage space, then the storage space corresponding to the first cache group in the fixed storage space has been used up and there is no remaining storage space.
[0081] At this point, the storage space corresponding to the first cache group can be expanded. That is, at least one temporary cache block is selected from at least one shared cache block. It can be understood that a temporary cache block is a blank shared cache block that is not used by other cache groups and therefore has no stored data.
[0082] After identifying blank temporary cache blocks, these blocks are associated with the first cache group, meaning the shared cache block in the shared storage space is temporarily allocated to the first cache group. In other words, with this association, the cache blocks in the first cache group consist of two parts: cache blocks permanently assigned to it in the fixed storage space and cache blocks temporarily allocated to it in the shared storage space. Therefore, in this embodiment, the storage space of the first cache group is expanded.
[0083] It is understandable that associating a temporary cache block with the first cache group means that, before the association is broken, the temporary cache block can be considered a fixed cache block of the first cache group.
[0084] The temporary cache block is associated with the first cache group, and the address information of the temporary cache block is returned so that the processor can accurately determine the physical location of the temporary cache block.
[0085] Understandably, since a temporary cache block can include two consecutive shared cache blocks, the returned address information can be the starting address of the temporary cache block to save internal resources.
[0086] Step S105: Write the data to be cached into a temporary cache block according to the address information.
[0087] In this step, the processor writes the data to be cached into the temporary cache block.
[0088] In one example, the second cache group in the fixed storage space needs to be written to, but both of its cache blocks already contain valid data. If the data to be written is placed into the second group, a conflict will occur. In this case, an expansion request can be sent to the shared storage space management module. Upon receiving the request, the shared storage space management module selects two consecutive empty shared cache blocks from at least one of its managed shared cache blocks and allocates them as a unit to the second group. The second group then comprises a total of four cache blocks: two existing cache blocks and two temporary cache blocks. The data to be written can then be placed into one of the two temporary cache blocks.
[0089] As can be seen, in this embodiment, a portion of the storage space in the data cache is used as a shared cache block. When some cache groups are used frequently, resulting in the storage space of the cache blocks they contain being used up, at least one shared cache block can be associated with the cache group, that is, at least one shared cache block is allocated to the aforementioned cache group for use, thereby increasing the number of cache blocks in the cache group, expanding its storage space, thereby reducing the occurrence of replacements, and thus improving resource utilization.
[0090] As one implementation method, step S103 specifically includes:
[0091] Step S1031: If there is no remaining storage space, determine the data storage status of at least one shared cache block in sequence.
[0092] Step S1032: Use the first shared cache block without stored data as a temporary cache block.
[0093] Specifically, in this embodiment, to avoid uneven usage among cache groups, the shared cache block will sequentially determine the data storage status of at least one shared cache block, and then use the first shared cache block not assigned to a cache group with fixed storage space as a temporary cache block. It is worth noting that the first shared cache block not assigned to a cache group with fixed storage space may have been historically assigned to other cache groups, but at the current moment, this shared cache block is not associated with any cache group.
[0094] In this embodiment, sequentially searching the shared cache space can also improve search efficiency.
[0095] Based on the above embodiments, a second embodiment of the dynamically scalable set-associative cache method of this application is proposed. (Refer to...) Figure 3 , Figure 3 A flowchart illustrating a second embodiment of a method for applying a dynamically scalable set-associative cache is shown.
[0096] In this embodiment, after step S105, the method further includes:
[0097] Step S106: If the data written in the temporary cache block is retrieved, then the association between the temporary cache block and the cache group is terminated.
[0098] In this embodiment, if the data written in the temporary cache block is retrieved, the temporary data block becomes a blank cache block again. At this time, the association between the temporary cache block and the cache group is severed, and the temporary cache block reverts to a shared cache block. Therefore, if other cache groups request to expand storage space at this time, the temporary cache block can be reallocated and used.
[0099] Based on the above embodiments, a third embodiment of data caching in this application is proposed. (Refer to...) Figure 4 , Figure 4 A flowchart illustrating a third embodiment of a method for applying a dynamically scalable set-associative cache is shown.
[0100] It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.
[0101] In this embodiment, the method includes:
[0102] Step S201: Determine the second cache group of the data to be accessed in the data cache based on the access address of the received access request;
[0103] Step S202: Search for the data to be accessed corresponding to the access request from all cache blocks corresponding to the second cache group;
[0104] Step S203: If a cache miss occurs, search for the data to be accessed in the second temporary cache block corresponding to the second cache group.
[0105] Step S204: If a hit is found in the second temporary cache block, the stored data in the second temporary cache block is returned.
[0106] It is understood that in this embodiment, steps S201 to S204 can be performed after steps S101 to S105, or before, or even in parallel; there are no restrictions here.
[0107] Specifically, when the processor needs to access data, it still issues a corresponding access address. At this time, the processor determines the corresponding second cache group in the data cache based on the access address, and then searches in all cache blocks corresponding to the second cache group to determine whether a cache hit has occurred.
[0108] Specifically, the cache hit determination method is as follows: In the second cache group, whether it's a cache block in the fixed storage space or a temporary cache block allocated in the shared storage space, the valid bit of any cache block is 1, and the tag field in the cache block equals the tag field in the access address. If a cache hit occurs, the data in the cache block is the required data.
[0109] In this embodiment, the cache block corresponding to the second cache group in the fixed storage space can be accessed first to determine whether a cache hit occurs, and then the temporary cache block corresponding to the second cache group in the shared storage space can be accessed to determine whether a cache hit occurs.
[0110] In one specific embodiment, step S203 includes:
[0111] Step S2031: If a cache miss occurs, determine whether the second cache group is associated with a second temporary cache block;
[0112] Step S2032: If there is an association, search for the data to be accessed in the second temporary cache block.
[0113] Specifically, when the shared storage space allocates temporary storage space, i.e., temporary cache blocks, for the second cache group, the data to be accessed is searched from the second temporary cache block.
[0114] If no temporary storage space is allocated for this second cache group in the shared storage space, the cache becomes invalid, and the processor reads the data from the next level of storage.
[0115] Furthermore, it is understandable that if there is no cache hit in the shared memory space, the cache becomes invalid, and the processor reads the data from the next level of memory.
[0116] Based on the above embodiments, a fourth embodiment of the dynamically scalable set-associative cache method of this application is proposed.
[0117] See Figure 5 In this embodiment, a shared cache block indicator table is pre-configured in the data cache. The method includes:
[0118] Step S301: Determine the second cache group of the data to be accessed in the data cache based on the access address of the received access request;
[0119] Step S302: Search for the data to be accessed corresponding to the access request from all cache blocks corresponding to the second cache group;
[0120] Step S303: If a cache miss occurs, query the temporary cache status corresponding to the second cache group in the shared cache block indicator table;
[0121] Step S304: If the temporary cache status is valid, then it is determined that the second cache group is associated with the second temporary cache block;
[0122] Step S305: If the temporary cache status is invalid, then it is determined that the second cache group is not associated with the second temporary cache block.
[0123] Step S306: If there is an association, search for the data to be accessed in the second temporary cache block according to the second address information corresponding to the second cache group in the shared cache block indication table.
[0124] Step S307: If a hit is found in the second temporary cache block, the stored data in the second temporary cache block is returned.
[0125] It is understood that in this embodiment, steps S301 to S307 can be performed after steps S101 to S105, or before, or even in parallel; there are no restrictions here.
[0126] Specifically, in this embodiment, the shared cache block indicator table is used to indicate whether each cache group has allocated cache blocks in the shared storage space. In one example, its number of entries is the same as the number of cache groups, i.e., 256 entries. Each entry corresponds to a cache group sequentially (entry 0 corresponds to group 0, entry 1 corresponds to group 1, and so on up to entry 255 corresponding to group 255). The shared cache block indicator table has a valid bit (V field), which indicates whether the cache group has temporary cache blocks in the shared storage space, that is, it is used to indicate its temporary cache status. A valid bit of 1 indicates that the cache group has allocated temporary cache blocks in the shared storage space, i.e., it is in a valid state. A valid bit of 0 indicates that no temporary cache blocks have been allocated, i.e., it is in an invalid state.
[0127] If the valid bit is 1, the Baddr field of the shared cache block indicator table (with a width of 7 bits due to a total of 128 shared blocks) indicates the starting address of the two cache blocks allocated to this cache group in the shared memory space. Thus, the data for this group can be found in the shared space based on the Baddr field.
[0128] Understandably, when writing data, if a cache group needs to expand its space, it sends a request to the shared storage space management module. The shared storage space management module searches sequentially, starting from group 0, for the first unallocated shared cache block. If the search is successful, it returns a success flag and the starting address of the allocated space. If all shared space is used up, it returns a failure message. The data cache updates the shared cache block indicator table based on the request result and the obtained address: if the allocation is successful, it sets the valid position of that group in the shared space indicator table to 1 and writes Baddr to the address obtained in the request; otherwise, it does not modify the shared space indicator table.
[0129] Understandably, if a cache block is released, the shared storage space management module needs to be notified. The shared storage space management module then determines whether all data blocks in the temporary cache block allocated to the cache group are invalid. If all are invalid, the valid position of the group in the shared space indicator table is set to 0, which means unbinding the temporary cache block from the cache group.
[0130] Alternatively, in the fifth embodiment of this application, see [reference]. Figure 6 The methods include:
[0131] Step S401: Determine the second cache group of the data to be accessed in the data cache based on the access address of the received access request;
[0132] Step S402: Search in parallel for the data to be accessed corresponding to the access request from all cache blocks and the second temporary cache block corresponding to the second cache group.
[0133] Step S403: If a hit occurs, return the stored data of the hit.
[0134] In other words, in this embodiment, in order to improve efficiency, the data to be accessed corresponding to the access request can be searched in parallel from all cache blocks corresponding to the second cache group and the second temporary cache block.
[0135] To enable those skilled in the art to better understand the scope of protection of the claims of this application, specific implementation examples in specific application scenarios are used to explain and illustrate the technical solutions described in the claims of this application. It should be understood that the following examples are only used to explain this application and are not intended to limit the scope of protection of the claims of this application.
[0136] In a specific example, the address width of the data cache is 32 bits, the cache block width is 4 bytes, then: the width of the Offset field is 2 bits (4 bytes width is represented by 2 bits), the width of the index is 8 bits (256 groups), and the width of the Tag field is 22 bits.
[0137] Its storage structure includes: 256 fixed storage spaces, each with 2-way cache blocks, and a certain amount of shared storage space, such as 128 shared cache blocks. Two consecutive shared cache blocks are allocated as a unit, and the entire shared storage space can be distributed among 64 cache spaces. In addition, each cache space can be configured with registers to expand by 2 temporary cache blocks once, that is, the number of cache blocks in the cache space increases from 2 to 4.
[0138] The cache block structure is the same in both the fixed storage space and the shared storage space, including a 1-bit valid bit V field, a 22-bit tag field, and a 32-bit data field.
[0139] When reading data, the cache group corresponding to the access address is first found based on the access address, that is, the value of the index field in the address.
[0140] The system searches all cache blocks in the fixed storage space for that cache group. If a cache block has a valid value of 1 and its label content matches the label of the address to be accessed, it is considered a hit; otherwise, it is considered a miss in the fixed storage space. If a hit occurs, the required data is returned based on the offset in the address.
[0141] In the event of a fixed storage space miss, check if the valid bit corresponding to the cache group (as indicated by the index field) in the shared cache block indicator table is valid. If it is 1, it is valid, indicating that space has been allocated for the cache group in the shared storage space; if it is 0, it means that no temporary cache block has been allocated for the cache group in the shared storage space.
[0142] If the group is valid in the shared cache block indicator table, the starting address of the temporary cache block for that group in the shared memory space is found according to the Baddr in the indicator table. All temporary cache blocks for that group in the shared memory space are then retrieved and a cache hit is checked. If a hit occurs, the required data is returned based on the offset in the address. Otherwise, the required data is not present in the cache, i.e., a cache miss, and data needs to be read from the next level of memory.
[0143] When a cache miss occurs and data needs to be read from the next level of storage and written to the cache, a valid bit is used to determine if there is a free cache block in the fixed storage space of the cache group. If there is a free cache block in the fixed storage space, the newly read data block is written to that free location in the fixed storage space, and the data is returned based on the offset.
[0144] If the cache group has no free cache blocks in the fixed storage space, then check whether the valid bit of the cache group in the shared cache block indicator table is set to 1.
[0145] If so, then the cache group in the shared storage space has a temporary cache block. Write the data to the free block of the cache group in the shared storage space and return the data based on the offset.
[0146] If the valid bit is 0, a request is sent to the shared storage space management module. The shared storage space management module searches sequentially, starting from group 0, for the first unallocated shared cache block. If the search is successful, it returns a success flag and the starting address of the allocated space. If all shared space is used up, it returns a failure message. The data cache updates the shared cache block indicator table based on the request result and the obtained address: if the allocation is successful, it sets the valid bit of that group in the shared space indicator table to 1 and writes Baddr to the address obtained in the request; otherwise, it does not modify the shared space indicator table.
[0147] It's worth noting that if there's free shared storage space, blocks can be allocated to that cache group. If there's no free shared storage space, new shared cache blocks cannot be allocated to that cache group, or if the shared space allocated to that cache group is also not free, a block is selected for replacement according to the replacement strategy (the old data block is written to the next level of storage, and the new block is written to that location), and the data is returned based on the offset.
[0148] As can be seen, this embodiment divides the traditional set-associative cache structure into fixed storage space and shared storage space. Thus, after the fixed storage space of a cache group is exhausted, some space can be expanded from the shared storage space, thereby increasing the number of cache blocks in the cache group and expanding its storage space, thereby reducing the occurrence of replacement and improving resource utilization.
[0149] Based on the same inventive concept, see [reference] Figure 7 This application also provides a dynamically scalable set-associative cache device, the device comprising:
[0150] The cache group determination module is used to determine the first cache group from the data cache based on the write address of the data to be cached; wherein the data cache also includes at least one shared cache block;
[0151] The space determination module is used to determine whether there is any remaining storage space in all cache blocks corresponding to the first cache group;
[0152] A temporary cache determination module is used to select at least one temporary cache block from at least one shared cache block if there is no remaining storage space; wherein, the temporary cache block is a shared cache block that does not store data;
[0153] The cache association module is used to associate temporary cache blocks with the first cache group and return the address information of the temporary cache blocks;
[0154] The data writing module is used to write the data to be cached into a temporary cache block according to the address information.
[0155] It should be noted that the various implementations of the dynamically scalable set-associative cache device in this embodiment and the technical effects they achieve can be referred to the various implementations of the dynamically scalable set-associative cache method in the foregoing embodiments, and will not be repeated here.
[0156] Furthermore, embodiments of this application also propose a computer storage medium storing a data caching program. When executed by a processor, the data caching program implements the steps of the dynamically scalable set-associative cache method described above. Therefore, it will not be repeated here. Additionally, the beneficial effects of using the same method will not be repeated here either. For technical details not disclosed in the computer-readable storage medium embodiments of this application, please refer to the description of the method embodiments of this application. As an example, program instructions can be deployed to execute on a single computing device, or on multiple computing devices located at one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.
[0157] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0158] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided in this application, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.
[0159] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.
[0160] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A dynamically scalable set-associative cache method, characterized in that, The dynamically scalable set-associative caching method is applied to a data cache, which includes: fixed storage space and shared storage space; The fixed storage space is organized into a group-associative structure, the fixed storage space includes multiple cache groups, each cache group includes a fixed number N cache blocks, and the number N of cache blocks is greater than 1; The shared storage space includes: at least one shared cache block that does not belong to any fixed cache group; The data cache has a pre-set shared cache block indicator table. The number of entries in the shared cache block indicator table is the same as the number of cache groups. Each entry corresponds to a cache group in sequence. Each entry includes a valid bit field and a starting address field in the shared storage space. The method includes: The first cache group is determined from the fixed storage space of the data cache based on the index field in the write address of the data to be cached; Determine whether there is remaining storage space in the N-way cache block corresponding to the first cache group; If there is no remaining storage space in the N-way cache block, then at least one shared cache block without stored data is selected from at least one shared cache block in the shared storage space as a temporary cache block; The temporary cache block is associated with the first cache group, and the valid bit field of the corresponding entry of the first cache group is updated to a valid state and the starting address field is updated to the address of the temporary cache block in the shared storage space in the shared cache block indicator table, so that the cache blocks included in the first cache group are composed of the original fixed N-way cache blocks and the temporary cache block, and the address information of the temporary cache block is returned. Based on the address information, the data to be cached is written into the temporary cache block; After the data to be cached is written, when subsequent access requests to the first cache group determine that the first cache group is associated with the temporary cache block by querying the valid bit field of the corresponding entry of the first cache group in the shared cache block indication table, the temporary cache block is included in the search range of the first cache group according to the starting address field, and the data to be accessed corresponding to the access request is searched in parallel from all cache blocks and the temporary cache block corresponding to the first cache group. If the data written in the temporary cache block is retrieved, the association between the temporary cache block and the first cache group is terminated.
2. The dynamically scalable set-associative cache method according to claim 1, characterized in that, The step of selecting at least one unstored shared cache block as a temporary cache block from at least one shared cache block in the shared storage space if there is no remaining storage space in the N-way cache blocks includes: If there is no remaining storage space, then determine the data storage status of at least one shared cache block in turn; The first shared cache block that does not store data is used as the temporary cache block.
3. The dynamically scalable set-associative cache method according to claim 1, characterized in that, After the step of searching in parallel from all cache blocks corresponding to the first cache group and the temporary cache block for the data to be accessed corresponding to the access request, the method further includes: If a match is found, the stored data that was found is returned.
4. A dynamically scalable set-associative cache device, characterized in that, The device includes: The cache group determination module is used to determine the first cache group from the fixed storage space of the data cache based on the index field in the write address of the data to be cached; The space determination module is used to determine whether there is remaining storage space in the N-way cache block corresponding to the first cache group; The temporary cache determination module is used to select at least one shared cache block without stored data as a temporary cache block if there is no remaining storage space in the N-way cache block; The cache association module is used to associate the temporary cache block with the first cache group, update the valid bit field of the corresponding entry of the first cache group to the valid state in the shared cache block indicator table, update the start address field to the address of the temporary cache block in the shared storage space, so that the cache blocks included in the first cache group are composed of the original fixed N-way cache blocks and the temporary cache block, and return the address information of the temporary cache block. The data writing module is used to write the data to be cached into the temporary cache block according to the address information; The data writing module is further configured to, after the data to be cached is written, when subsequent access requests to the first cache group determine that the first cache group is associated with the temporary cache block by querying the valid bit field of the corresponding entry of the first cache group in the shared cache block indication table, include the temporary cache block in the search range of the first cache group according to the starting address field, and search in parallel from all cache blocks corresponding to the first cache group and the temporary cache block for the data to be accessed corresponding to the access request. The data writing module is further configured to, if the data written in the temporary cache block is retrieved, then release the association between the temporary cache block and the first cache group.
5. A data caching device, characterized in that, include: A processor, a memory, and a data cache program stored in the memory, the data cache program being executed by the processor to implement the steps of the dynamically scalable set-associative cache method as described in any one of claims 1-3.
6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a data caching program, which, when executed by a processor, implements the dynamically scalable set-associative caching method as described in any one of claims 1 to 3.