Probing filters, processing units, computing devices, and related methods

Abstract

This application provides a snooping filter, processing unit, computing device, and related method. This solution is applicable to various chips, including those based on CISC, RISC (especially RISC-V), or VLIM instruction set architectures, such as IoT chips and audio / video chips. The snooping filter includes: a receiving unit, used to receive coordinate information sent by the private cache after a first cache line is filled into the private cache; and a snooping unit, used to, when determining from the coordinate information that the mapping entry corresponding to the target filling position stores the identification information of the second cache line, transfer the identification information of the second cache line from the mapping entry corresponding to the target filling position to a sacrifice entry, and store the identification information of the first cache line in the mapping entry corresponding to the target filling position. This solution can reduce the bandwidth occupied by the snooping filter for communication between the processor core and external systems.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a snooping filter, processing unit, computing device and related methods. Background Technology

[0002] In a processing unit with multiple processor cores, the cache includes private caches and shared caches. Private caches belong to a specific processor core, while shared caches belong to multiple processor cores. When a processor core queries data from its cache, it first checks its private cache. If the data is not found there, it queries the next lower-level cache. If the required data is stored in the private cache of another processor core, it needs to be queried from that private cache; this process is called snooping. Snooping on the private caches of other processor cores reduces the operating efficiency of those cores.

[0003] Currently, a snooping filter is set up to store information related to the data stored in the private cache. By querying the snooping filter, it is possible to identify private caches that do not contain the required data, thereby avoiding snooping on private caches that do not contain the required data.

[0004] However, in order to ensure that the snooping filter can accurately reflect the data stored in the private cache, whenever the private cache actively deletes a cache line, it needs to send a deletion request to the snooping filter to remove the relevant information of the deleted cache line from the snooping filter. Even if the deleted cache line is the same as the data in memory, a deletion request still needs to be sent to the snooping filter. This will occupy the communication bandwidth between the processor core and the external processor core, affecting the performance of the processing unit. Summary of the Invention

[0005] In view of this, embodiments of this application provide a snooping filter, a processing unit, a computing device, and a related method to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a snooping filter is provided, comprising: a receiving unit, configured to receive coordinate information sent by the private cache after a first cache line is filled into the private cache, wherein the coordinate information is used to indicate the target filling position of the first cache line in the private cache; and a snooping unit, configured to, when determining based on the coordinate information that the mapping entry corresponding to the target filling position stores the identification information of a second cache line, transfer the identification information of the second cache line from the mapping entry corresponding to the target filling position to a sacrifice entry, and store the identification information of the first cache line in the mapping entry corresponding to the target filling position, wherein different cache lines correspond to different identification information.

[0007] According to a second aspect of the embodiments of this application, a processing unit is provided, comprising: a snooping filter as described in the first aspect above; and at least two processor cores for querying the snooping filter to determine the private cache where the required data is located.

[0008] According to a third aspect of the embodiments of this application, a computing device is provided, comprising: a processing unit as described in the second aspect above; and a memory coupled to the processing unit for storing data required by the processing unit.

[0009] According to a fourth aspect of the embodiments of this application, a snooping filtering method is provided, comprising: receiving coordinate information sent by the private cache after a first cache line is filled into the private cache, wherein the coordinate information is used to indicate the target filling position of the first cache line in the private cache; when it is determined from the coordinate information that the mapping table entry corresponding to the target filling position stores the identification information of a second cache line, transferring the identification information of the second cache line from the mapping table entry corresponding to the target filling position to a sacrifice table entry, and storing the identification information of the first cache line in the mapping table entry corresponding to the target filling position, wherein different cache lines correspond to different identification information.

[0010] According to the snooping filtering scheme provided in this application embodiment, the filling positions in the private cache correspond one-to-one with the mapping entries in the snooping filter. After the first cache line is filled to the target filling position, if the mapping entry corresponding to the target filling position stores the identification information of the second cache line, the snooping unit transfers the identification information of the second cache line to the sacrifice entry and stores the identification information of the first cache line in the mapping entry corresponding to the target filling position. Since the filling positions correspond one-to-one with the mapping entries, when the second cache line does not need to be written back to data, the private cache only needs to send the coordinate information of the target filling position to the snooping filter. The snooping filter stores the identification information of the first cache line in the mapping entry corresponding to the target filling position and transfers the identification information of the second cache line to the sacrifice entry. Therefore, for cache lines that do not need to be written back to data, the private cache does not need to send a deletion request to the snooping filter to ensure that the snooping filter determines which private caches cannot store the required data, thereby reducing the number of snooping requests to the private caches of other processor cores. This reduces the bandwidth occupied by sending deletion requests on the communication between the processor core and the external processor core, thereby ensuring the performance of the processing unit. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0012] Figure 1 This is a schematic diagram of a computing device used in one embodiment of this application;

[0013] Figure 2 This is a schematic diagram of a processing unit according to an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of a snooping filter according to an embodiment of this application;

[0015] Figure 4 This is a schematic diagram of a private cache and eavesdropping filter according to an embodiment of this application;

[0016] Figure 5 This is a flowchart of a snooping filtering method according to an embodiment of this application. Detailed Implementation

[0017] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0018] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows.

[0019] Snooping: In a processing unit that includes multiple processor cores, if the data required by one processor core is stored in the private cache of other processor cores, then the processor core needs to query the private cache of other processor cores for the required data. This process is called snooping.

[0020] Snoop filter: Since snooping on the private caches of other processor cores can reduce the operating efficiency of those cores, a lookup table of the upper cache is stored near the next level cache to reduce the number of snoops. This lookup table stores relevant information about the data stored in the corresponding private cache. By using the lookup table, it can be determined whether the required data is stored in the corresponding private cache. This lookup table is called a snoop filter.

[0021] Cache line: When the processor core reads data from main memory into the buffer memory, it needs to read the required data and a portion of the nearby data. Each set of data read is called a cache line. Each level of cache can store many cache lines, and each level of cache stores data in units of cache lines.

[0022] computing devices

[0023] Figure 1 A schematic block diagram of a computing device 10 is shown. The computing device 10 can be built based on various types of processing units and driven by any operating system such as Windows, UNIX, or Linux. Furthermore, the computing device 10 can be implemented in hardware and / or software such as PCs, desktops, laptops, servers, and mobile communication devices.

[0024] like Figure 1 As shown, the computing device 10 may include one or more processing units 12 and a memory 14. The memory 14 in the computing device 10 may serve as main memory (or simply main memory or RAM) for storing instruction information and / or data information represented by data signals. For example, the memory 14 may store data provided by the processing unit 12 (e.g., budget results) and may also be used to realize data exchange between the processing unit 12 and the external storage device 16 (or auxiliary memory or external memory).

[0025] In some cases, the processing unit 12 needs to access the memory 14 via the bus 11 to retrieve or modify data in the memory 14. Since the access speed of the memory 14 is relatively slow, to alleviate the speed difference between the processing unit 12 and the memory 14, the computing device 10 also includes a cache memory 18 communicatively connected to the bus 11. The cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly accessed. The cache memory 18 can be implemented using a storage device such as Static Random Access Memory (SRAM). The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a Level 1 cache (L1Cache), a Level 2 cache (L2Cache), and a Level 3 cache (L3Cache). The cache memory 18 can also be a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (e.g., the Level 1 cache, or both the Level 1 cache and the Level 2 cache) can be integrated inside the processing unit 12 or integrated with the processing unit 12 on the same on-chip system.

[0026] Based on this, the processing unit 12 may include an instruction execution unit 121 and a memory management unit 122, among other components. When executing instructions that require memory modification, the instruction execution unit 121 initiates a write access request, specifying the data to be written into memory and its corresponding physical address. The memory management unit 122 translates the virtual addresses specified by these instructions into the physical addresses mapped to those virtual addresses. The physical address specified in the write access request may be consistent with the physical address specified in the corresponding instruction.

[0027] Information exchange between memory 14 and cache memory 18 can be organized according to data blocks. In some embodiments, cache memory 18 and memory 14 can be divided into data blocks with the same spatial size. A data block can serve as the smallest unit of data exchange between cache memory 18 and memory 14 (including one or more data of a preset length). For the sake of brevity and clarity, each data block in cache memory 18 will be referred to as a cache block (or cache line), and different cache blocks will have different cache block addresses. Each data block in memory 14 will be referred to as a memory block, and different memory blocks will have different memory block addresses. Cache block addresses and / or memory block addresses may include physical address tags used to locate data blocks.

[0028] Due to space and resource limitations, cache memory 18 cannot cache all the contents of memory 14; that is, the storage capacity of cache memory 18 is usually smaller than that of memory 14, and the addresses of individual cache blocks provided by cache memory 18 cannot correspond to all the memory block addresses provided by memory 14. When processing unit 12 needs to access memory, it first accesses cache memory 18 via bus 11 to determine whether the content to be accessed is already stored in cache memory 18. If the content to be accessed is already stored in cache memory 18, cache memory 18 is hit, and processing unit 12 directly retrieves the content to be accessed from cache memory 18. If the content to be accessed is not stored in cache memory 18, cache memory 18 and processing unit 12 need to access memory 14 via bus 11 to find the corresponding information in memory 14. Because the access speed of cache memory 18 is very fast, the efficiency of processing unit 12 can be significantly improved when cache memory 18 is hit, thereby improving the performance and efficiency of the entire computing device 10.

[0029] In addition, the computing device 10 may also include a storage device 16, a display device, an audio device, a mouse / keyboard, and other input / output devices. The storage device 16 may be a hard disk, optical disk, or flash memory, etc., coupled to the bus 11 via a corresponding interface, for storing and retrieving information. The display device may be coupled to the bus 11 via a corresponding graphics card, and is used to display information according to the display signals provided by the bus 11.

[0030] The computing device 10 may also include a communication device 17, enabling the computing device 10 to communicate with networks or other devices in various ways. The communication device 17 may include one or more communication modules, including wireless communication modules adapted to specific wireless communication protocols. For example, the communication device 17 may include a WLAN module for implementing WiFi communication conforming to the IEEE 802.11 standard. The communication device 17 may include a WWAN module for implementing wireless wide area communication conforming to cellular or other wireless wide area protocols. The communication device 17 may also include communication modules employing other protocols, such as a Bluetooth module, or other custom-type communication modules. The communication device 17 may also be a port for serial data transmission.

[0031] It should be noted that the structure of the computing device 10 may vary depending on the motherboard, operating system, and instruction set architecture. For example, many current computing devices are equipped with an input / output control center connected between the bus 11 and various input / output devices, and this input / output control center may be integrated into the processing unit 12 or independent of the processing unit 12.

[0032] Processing unit

[0033] Figure 2 This is a schematic block diagram of a processing unit 12 according to one embodiment of this application. Figure 2As shown, each processing unit 12 may include multiple processor cores 120 for processing instructions. The processing and execution of instructions can be controlled by the user (e.g., through an application program) and / or the system platform. Each processor core 120 can be used to process a specific instruction set, which can support Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW) based computation. Specifically, processor core 120 is suitable for processing the RISC-V instruction set. Different processor cores 120 can each process different or the same instruction sets. Processor core 120 may also include other processing modules, such as a Digital Signal Processor (DSP). As an example, Figure 2 The diagram shows processor cores 1 through m, where m is a positive integer.

[0034] Figure 1 The cache memory 18 shown can be wholly or partially integrated into the processing unit 12. Depending on the architecture, the cache memory 18 can be a single or multi-level internal cache memory located within and / or outside each processor core 120 (e.g., ...). Figure 2 The three-level cache memory L1 to L3 are shown. Figure 2 The cache, uniformly identified as 18, may also include instruction-oriented caches and instruction caches, as well as data caches. Each processor core 120 in processing unit 12 may share at least a portion of the cache memory; for example, processor cores 1 to m may share a third-level cache L3. Each processor core 120 in processing unit 12 has its own private cache; for example, each processor core 120 has a first-level cache L1 and a second-level cache L2. Processing unit 12 may also include an external cache (not shown), and other cache structures may also serve as external caches for processing unit 12.

[0035] like Figure 2 As shown, the processing unit 12 may include a register file 126, which may include multiple registers for storing different types of data and / or instructions. These registers may be of different types, such as integer registers, floating-point registers, status registers, instruction registers, and pointer registers. The registers in the register file 126 may be implemented using general-purpose registers, or a specific design may be adopted according to the actual needs of the processing unit 12.

[0036] Processing unit 12 may include a memory management unit (MMU) 122 for translating virtual addresses to physical addresses. The memory management unit 122 caches a portion of the entries in the page table and can also retrieve uncached entries from memory. Each processor core 120 may have one or more memory management units 122. The memory management units 122 in different processor cores 120 can be synchronized with those in other processing units or processor cores, allowing each processing unit or processor core to share a unified virtual memory system.

[0037] The processing unit 12 is used to execute the instruction sequence (i.e., the program). The process of the processing unit 12 executing each instruction includes: fetching the instruction from the memory where the instructions are stored, decoding the fetched instruction, executing the decoded instruction, and keeping the instruction execution result, etc., and so on, until all the instructions in the instruction sequence are executed or a halt instruction is encountered.

[0038] To implement the above process, the processing unit 12 may include an instruction fetch unit 124, an instruction decoding unit 125, an instruction dispatch unit (not shown), an instruction execution unit 121, and a retirement unit 123, etc.

[0039] The instruction fetch unit 124 serves as the startup engine for the processing unit 12, used to move instructions from memory 14 to the instruction register (which may be...). Figure 2 The instruction is stored in one of the registers in the register file 126 shown, and the next fetch address is received or calculated according to the fetch algorithm, which can be an incrementing or decrementing address based on the instruction length.

[0040] After the instruction is fetched, the processing unit 12 enters the instruction decoding stage. The instruction decoding unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 121. The operand acquisition information may include pointers to immediate values, registers, or other software / hardware that can provide source operands.

[0041] The instruction dispatch unit, typically located within the high-performance processing unit 12, lies between the instruction decoding unit 125 and the instruction execution unit 121. It is used for instruction scheduling and control, efficiently allocating instructions to different instruction execution units 121, thus enabling parallel operation of multiple instructions. After an instruction is fetched, decoded, and scheduled to the corresponding instruction execution unit 121, the unit begins executing the instruction, performing the operation specified by the instruction, and thus fulfilling the corresponding function.

[0042] The retirement unit 123 (or instruction retirement unit or instruction write-back unit) is mainly used to write the execution results generated by the instruction execution unit 121 back to the corresponding storage location (e.g., a register inside the processing unit 12) so that subsequent instructions can quickly obtain the corresponding execution results from that storage location.

[0043] For different types of instructions, different instruction execution units 121 can be set up in the processing unit 12 accordingly. The instruction execution unit 121 can be an arithmetic unit (e.g., including an arithmetic logic unit, an integer processing unit, a vector arithmetic unit, etc., used to perform operations based on operands and output the operation results), a memory execution unit (e.g., used to access memory according to instructions to read data in memory or write specified data to memory, etc.), and a coprocessor, etc. In the processing unit 12, each instruction execution unit 121 can run in parallel and output the corresponding execution results.

[0044] When executing a certain type of instruction (such as a memory access instruction), the instruction execution unit 121 needs to access memory 14 to obtain information stored in memory 14 or to provide data that needs to be written to memory 14. It should be noted that the instruction execution unit 121 used to execute memory access instructions can also be simply referred to as a memory execution unit, which can be a load store unit (LSU) and / or other units used for memory access.

[0045] After the memory access instruction is fetched by the instruction fetch unit 124, the instruction decoding unit 125 can decode the memory access instruction, allowing the source operand of the memory access instruction to be fetched. The decoded memory access instruction is then provided to the corresponding instruction execution unit 121, which can perform corresponding operations on the source operand of the memory access instruction (e.g., the arithmetic logic unit performs operations on the source operand stored in the register) to obtain the address information corresponding to the memory access instruction, and initiate corresponding requests based on the address information, such as address translation requests, write access requests, etc.

[0046] The source operand of a memory access instruction typically includes an address operand. The instruction execution unit 121 performs operations on this address operand to obtain the virtual or physical address corresponding to the memory access instruction. When the memory management unit 122 is disabled, the instruction execution unit 121 can directly obtain the physical address of the memory access instruction through logical operations. When the memory management unit 121 is enabled, the corresponding instruction execution unit 121 initiates an address translation request based on the virtual address corresponding to the memory access instruction. This address translation request includes the virtual address corresponding to the address operand of the memory access instruction. The memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address based on the entry matching the virtual address, so that the instruction execution unit 121 can access the cache memory 18 and / or memory 14 according to the translated physical address.

[0047] Depending on their function, memory access instructions can include load instructions and store instructions. The execution of a load instruction typically does not require modification of information in memory 14 or cache memory 18; the instruction execution unit 121 only needs to read data stored in memory 14, cache memory 18, or external storage devices based on the address operand of the load instruction. Unlike load instructions, the source operand of a store instruction includes not only address operands but also data information. The execution of a store instruction typically requires modification of information in memory 14 and / or cache memory 18. The data information in a store instruction can point to data to be written. The source of this written data can be the execution result of an arithmetic instruction, load instruction, or other instructions; data provided by registers or other storage units in the processing unit 12; or immediate values.

[0048] like Figure 2 As shown, the processing unit 12 includes a snooping filter 15, which is located near the shared cache L3. There can be one or more snooping filters 15; for example, different processor cores 120 can correspond to different snooping filters 15, or multiple processor cores 120 can correspond to the same snooping filter 15. The snooping filter 15 stores information related to the data stored in the private caches (L1 and L2) of the corresponding processor core 120. Other processor cores 120 can determine whether the required data is stored in the private cache of the processor core 120 corresponding to the snooping filter 15 by querying the snooping filter 15. For example, processor core 2 can determine whether the private cache corresponding to processor core 1 contains the data required by processor core 2 by querying the snooping filter 15 corresponding to processor core 1.

[0049] The snooping filter 15 stores information related to the data stored in the private cache of the corresponding processor core 120. When the data stored in the private cache changes, the snooping filter 15 needs to update the stored information so that the stored information corresponds to the data stored in the corresponding private cache, so that other processor cores 120 can determine whether the required data is stored in the corresponding private cache by querying the snooping filter 15.

[0050] This application focuses on the process of the eavesdropping filter 15 updating the stored relevant information. The process of the eavesdropping filter 15 updating the stored relevant information will be described in detail later.

[0051] eavesdropping filter

[0052] Multi-core processing units typically include multiple levels of cache. The top-level cache has a smaller capacity but faster access speed, while the bottom-level cache has a larger capacity but slower access speed. The top-level cache is private to a specific processor core, while the bottom-level caches are shared by multiple processor cores. For example, the L1 cache is private to a single processor core and is used only to cache data from that core, while the L2 cache is shared by multiple processor cores to cache data from multiple cores sharing the L2 cache. When a processor core needs to retrieve specific data, it first checks its private cache. If the data is not found there, it then checks the next lower-level cache. If the required data is stored in the private caches of other processor cores, then the system needs to search those private caches.

[0053] Currently, the snooping filter stores information related to the data stored in the private cache. To ensure that the information stored in the snooping filter accurately reflects the data stored in the private cache, a deletion request needs to be sent to the snooping filter whenever the private cache actively deletes a cache line. This removes the relevant information of the deleted cache line from the snooping filter. When the deleted cache line is identical to the data in memory, no data write-back is needed, but a deletion request still needs to be sent to the snooping filter to remove the relevant information of the deleted cache line from the snooping filter, ensuring a one-to-one correspondence between the relevant information stored in the snooping filter and the cache lines in the private cache. Because the processor core needs to frequently send deletion requests to the snooping filter, this will consume the communication bandwidth between the processor core and the external network, affecting the performance of the processing unit.

[0054] This application embodiment addresses the issue of excessive bandwidth consumption in communication between the kernel and external systems due to snooping filter entry deletion. It is primarily implemented through snooping filter 15. The internal structure of snooping filter 15 and its implementation process in this application embodiment are discussed in detail below.

[0055] Figure 3 This is a schematic diagram of the internal structure of a listening filter according to an embodiment of this application. Figure 3 As shown, the snooping filter 15 includes a receiving unit 151 and a snooping unit 152. After the first cache line is filled into the private cache, the private cache sends coordinate information to the receiving unit 151. This coordinate information indicates the target filling position of the first cache line in the private cache. After receiving the coordinate information, the receiving unit 151 can determine whether the mapping table entry corresponding to the target filling position stores the identification information of the second cache line. If the mapping table entry corresponding to the target filling position stores the identification information of the second cache line, the identification information of the second cache line is transferred from the mapping table entry corresponding to the target filling position to the sacrifice entry, and the identification information of the first cache line is stored in the mapping table entry corresponding to the target filling position. Different cache lines correspond to different identification information.

[0056] The snooping filter 15 is used to store the identification information of the buffer lines filled in the private cache. There can be one or more private caches. Different cache lines correspond to different identification information, which can be used to distinguish different cache lines. For example, the identification information can be the memory address of the cache line.

[0057] The private cache includes multiple padding locations for filling cache lines. The snooping filter 15 includes multiple mapping entries, each corresponding one-to-one with a padding location in the private cache. These mapping entries store the identifier information of the cache line being filled at the corresponding padding location. For example, if the private cache has N padding locations, where N is a positive integer greater than or equal to 2, then the snooping filter 15 includes N mapping entries, with different padding locations corresponding to different mapping entries. In addition to these mapping entries, the snooping filter 15 also includes sacrifice entries. These sacrifice entries also store the identifier information of cache lines, but they do not belong to any single padding location; instead, they are shared by multiple padding locations.

[0058] The target filling position in the private cache is previously filled with a second cache line. When the first cache line is filled to the target filling position, the private cache sends the coordinate information of the target filling position to the receiving unit 151. The listening unit 152, based on the coordinate information received by the receiving unit 151, transfers the identifier information of the second cache line stored in the mapping table entry corresponding to the target filling position to the sacrifice table entry, and stores the identifier information of the first cache line in the mapping table entry corresponding to the target filling position. If the second cache line does not need to be written back, after the first cache line is filled to the target filling position, the second cache line is squeezed out of the private cache, and the identifier information of the second cache line is stored in the sacrifice table entry. This also ensures that the identifier information of all cache lines stored in the private cache is stored in the listening filter 15.

[0059] In this embodiment, the filling positions in the private cache correspond one-to-one with the mapping entries in the snooping filter 15. After the first cache line is filled to the target filling position, if the mapping entry corresponding to the target filling position stores the identification information of the second cache line, the snooping unit 152 transfers the identification information of the second cache line to the sacrifice entry and stores the identification information of the first cache line in the mapping entry corresponding to the target filling position. Since the filling positions correspond one-to-one with the mapping entries, when the second cache line does not need to be written back to data, the private cache only needs to send the coordinate information of the target filling position to the snooping filter 15. The snooping filter 15 stores the identification information of the first cache line in the mapping entry corresponding to the target filling position and transfers the identification information of the second cache line to the sacrifice entry. Therefore, for cache lines that do not need to be written back to data, the private cache does not need to send a deletion request to the snooping filter 15 to ensure that the snooping filter determines which private caches cannot store the required data, thereby reducing the number of snooping requests to the private caches of other processor cores. This reduces the bandwidth occupied by sending deletion requests in the communication between the processor core and the external processor core, thereby ensuring the performance of the processing unit.

[0060] In one possible implementation, when the listening unit 152 determines that the mapping table entry corresponding to the target filling position is empty based on the coordinate information, it stores the identification information of the first cache line into the mapping table entry corresponding to the target filling position.

[0061] Since there is a one-to-one correspondence between the filling positions in the private cache and the mapping table entries in the eavesdropping filter 15, if the mapping table entry corresponding to the target filling position is empty, it means that no other cache lines were filled at the target filling position before the first cache line was filled, or that the cache line filled at the target filling position was excluded from the private cache before the first cache line was filled. When it is determined from the coordinate information that the mapping table corresponding to the target filling position is empty, the eavesdropping unit 152 stores the identification information of the first cache line into the mapping table entry corresponding to the target filling position, and uses the identification information of the first cache line to indicate that the first cache line is stored in the private cache.

[0062] In this embodiment, when the mapping entry corresponding to the target filling position is empty, the snooping unit 152 does not need to perform the step of transferring the identification information to the sacrifice entry. Instead, it directly stores the identification information of the first cache line to be filled into the target filling position into the mapping entry corresponding to the target filling position. Then, when other processor cores query the snooping filter 15, they can determine that the first cache line is stored in the private cache corresponding to the snooping filter 15 based on the identification information stored in the mapping entry corresponding to the target filling position, thus ensuring that the processor cores can quickly query the required data.

[0063] In one possible implementation, the snooping filter 15 includes at least one snooping entry set. Each snooping entry set includes a sacrifice entry and at least one mapping entry. Each snooping entry set corresponds to a set of fill positions in a private cache. Each fill position set includes at least one fill position. The number of mapping entries in each snooping entry set is equal to the number of fill positions in the corresponding fill position set. Different mapping entries in the corresponding snooping entry set and fill position set correspond to different fill positions. After determining that the mapping entry corresponding to the target fill position stores the identifier information of the second cache line based on the coordinate information, the snooping unit 152 determines the snooping entry set to which the mapping entry corresponding to the target fill position belongs, and then transfers the identifier information of the second cache line from the mapping entry corresponding to the target fill position to the sacrifice entry included in that snooping entry set.

[0064] For example, the private cache includes y sets of padding locations, each set containing x padding locations, where x and y are positive integers greater than or equal to 1. The snooping filter 15 includes y sets of snooping entries, each set containing x mapping entries and 1 sacrifice entry. The padding location sets correspond one-to-one with the snooping entry sets; for example, padding location set 0 corresponds to snooping entry set 0, padding location set 1 corresponds to snooping entry set 1, and padding location set y-1 corresponds to snooping entry set y-1. Within the corresponding padding location sets and snooping entry sets, padding locations correspond one-to-one with mapping entries; for example, padding location 0 corresponds to mapping entry 0, padding location 1 corresponds to mapping entry 1, and padding location x-1 corresponds to mapping entry x-1.

[0065] After filling the first cache line into the filling position x-1 in the filling position set 0, the listening unit 152 will transfer the identification information of the second cache line stored in the mapping entry x-1 in the listening entry set 0 to the sacrifice entry in the listening entry set 0, and store the identification information of the first cache line into the mapping entry x-1 in the listening entry set 0.

[0066] For the same cache line, each time the cache line is stored in the private cache, it needs to be filled into the same set of fill positions. However, the cache line can be filled into different fill positions within the set of fill positions. For example, each time cache line L is stored in the private cache, it is filled into fill position set 1. If the cache line L was filled into fill position 1 in fill position set 1 last time, it can be filled into fill position 0 in fill position set 1 next time.

[0067] In this embodiment, the private cache includes multiple fill position sets, and the snooping filter 15 includes multiple snooping entry sets, so that the fill position sets and snooping entry sets correspond one-to-one, and the fill positions and mapping entries in the corresponding fill position sets and snooping entry sets correspond one-to-one. This facilitates determining the mapping entry corresponding to the fill position based on coordinate information, improving the efficiency of the snooping filter 15 in updating the identification information. In addition, each snooping entry set also includes a sacrifice entry. The mapping entries in the same snooping entry set share a sacrifice entry to store the transferred identification information. Moreover, the same cache line is always filled into the same fill position set. Therefore, when other processor cores query the snooping filter 15, they only need to query the snooping entry set corresponding to the fill position set used to store the required data to determine whether the private cache contains the data required by other processor cores. It is not necessary to traverse all the identification information stored in the snooping filter 15, thereby improving the efficiency of the processor core in obtaining the required data from the private cache of other processor cores.

[0068] In one possible implementation, the number of pending cache line fill requests corresponding to each set of fill positions is less than or equal to 1, wherein the cache line fill request is used to request the filling of cache lines to the fill positions included in the corresponding set of fill positions.

[0069] Each set of fill positions can include multiple fill positions. For each set of fill positions, a cache line fill request is used to request the filling of cache lines into the fill positions included in that set. Upon receiving a cache line fill request, the set of fill positions responds by filling the corresponding fill position with a cache line. After a cache line is filled into a fill position, the cache lines previously stored at that fill position will be evicted from the private cache. If the evicted cache line needs to be written back, during the write-back process, the cache line's identification information will be stored in the sacrifice entry in the corresponding snooping entry set.

[0070] For example, based on the correspondence between the fill position set and the listener entry set, and the correspondence between the fill position and the mapping entry in the aforementioned embodiments, the second cache line is stored in fill position 1 of fill position set 1. When the private cache receives a cache line fill request and fills the first cache line into fill position 1 of fill position set 1, the second cache line will be squeezed out of the private cache, and the identification information of the second cache line will be transferred from mapping entry 1 of listener entry set 1 to the sacrifice entry of listener entry set 1. If the second cache line is different from the data in memory, the second cache line needs to be written back. During the write-back process of the second cache line, the identification information of the second cache line is stored in the sacrifice entry of listener entry set 1 to ensure the correspondence between the identification information stored in the listener filter 15 and the cache line in the private cache.

[0071] In this embodiment, since the set of fill positions corresponds one-to-one with the set of listener entries, and each set of listener entries includes a sacrifice entry, if a cache line needs to be written back, the identification information of the cache line needs to be stored in the corresponding sacrifice entry during the write-back process. This ensures that the cache lines stored in the private cache have corresponding identification information in the listener filter 15. To prevent the identification information of other cache lines from being transferred to the sacrifice entry and overwriting the identification information of the cache line before the write-back of a cache line is completed, thus causing the cache lines stored in the private cache to not have corresponding identification information in the listener filter 15, only one or more cache line fill requests are allowed for each set of fill positions. This ensures that each cache line stored in the private cache has corresponding identification information stored in the listener filter 15, thereby ensuring the correctness of the processor core in finding the required data by querying the listener filter 15.

[0072] In one possible implementation, when the eavesdropping unit 152 transfers the identification information of the second cache line to the sacrifice entry, if the sacrifice entry stores the identification information of the third cache line, then the identification information of the second cache line is used to overwrite the identification information of the third cache line in the sacrifice entry.

[0073] For example, when transferring the identification information of the second cache line from the mapping entry 1 in the listener entry set 1 to the sacrifice entry in the listener entry set 1, if the sacrifice entry in the listener entry set 1 is empty, the identification information of the second cache line is directly stored in the sacrifice entry in the listener entry set 1. If the sacrifice entry in the listener entry set 1 stores the identification information of the third cache line, the identification information of the second cache line is used to overwrite the identification information of the third cache line in the sacrifice entry in the listener entry set 1, so as to store the identification information of the second cache line in the sacrifice entry in the listener entry set 1.

[0074] In this embodiment, since each listener entry set includes a sacrifice entry, when the cache line to be replaced is different from the data in memory, a data filling request can be initiated first, followed by a data write-back request. This eliminates the need to first initiate an entry deletion operation to the listener filter 15, and then an entry addition operation, thereby improving the speed of data filling into the cache. Because each listener entry set includes a sacrifice entry, when transferring the identifier information of a cache line from a mapping entry to a sacrifice entry in the same listener entry set, even if the sacrifice entry previously stored identifier information for other cache lines, the cache line corresponding to that identifier information no longer exists in the private cache and can therefore be overwritten.

[0075] In one possible implementation, each processor core corresponds to one snoop filter 15. A processor core may include multiple private caches, each private cache including at least one set of fill locations. The snoop filter 15 includes multiple snoop entry sets, and at least two fill location sets corresponding to each snoop entry set are located in at least two private caches. Different snoop entry sets correspond to different fill location sets, and each private cache is located within the same processor core.

[0076] Each private cache includes at least one set of padding locations. Different private caches may have the same or different number of padding location sets. The total number of padding location sets in each private cache is equal to the number of listener entry sets in listener filter 15. Each listener entry set corresponds to one padding location set, and different listener entry sets correspond to different padding location sets.

[0077] For example, the processor core includes a Level 1 cache and a Level 2 cache, each containing y fill locations. The snoop filter contains 2y snoop entries, where y snoop entries correspond to y fill locations in the Level 1 cache, and the other y snoop entries correspond to y fill locations in the Level 2 cache. Different snoop entry sets correspond to different fill location sets.

[0078] In the embodiments of this application, the snooping filter 15 includes a set of snooping entries that can correspond to multiple sets of fill positions in the same private cache or multiple sets of fill positions in different private caches. Thus, the snooping filter 15 is applicable to processor cores that include one private buffer or processor cores that include multiple private buffers, ensuring that the snooping filter 15 has strong applicability.

[0079] In one possible implementation, each padding location in the same set corresponds to the same index information, which can identify the address range of the cache line that can be filled by the padding location in the private cache.

[0080] Within the private cache, different padding location sets are assigned index information starting from 0 and incrementing by 1, meaning the index information for each padding location set is 0, 1, 2, ... The cacheable address range is divided into at least one address segment, ensuring that the number of address segments equals the number of padding location sets. Similarly, different address segments are assigned index information starting from 0 and incrementing by 1, ensuring that each address segment corresponds to a padding location set with the same index information. Any address segment containing a cache line can only be cached at the padding location corresponding to its index information.

[0081] Corresponding to the fill positions in the private cache, index information and path information can be assigned to the mapping entries in the snooping filter 15, so that the corresponding fill positions and mapping entries have the same index information and path information. This allows multiple mapping entries with the same index information to be grouped into the same snooping entry set. Additionally, index information is assigned to the sacrifice entries, so that different sacrifice entries correspond to different index information. This ensures that each snooping entry set includes one sacrifice entry, and that mapping entries and sacrifice entries within the same snooping entry set have the same index information.

[0082] Figure 4 This is a schematic diagram of a private cache and eavesdropping filter provided in one embodiment of this application. Figure 4 As shown, the private cache includes y sets of padding locations, and each set of padding locations includes x padding locations. Different sets of padding locations correspond to different index information, namely index0, index1, ..., index(y-1). The padding locations within the same set of padding locations have the same index information, and the padding locations within the same set of padding locations correspond to different path information, namely way0, way1, ..., way(x-1).

[0083] Corresponding to the padding positions included in the private cache, the snooping filter 15 includes y snooping entry sets, each snooping entry set including x mapping entries and 1 sacrifice entry. Different snooping entry sets correspond to different index information, with the index information corresponding to each snooping entry set being index0, index1, ..., index(y-1), respectively. The mapping entries included in the same snooping entry set correspond to the same index information, while the mapping entries included in the same snooping entry set correspond to different path information, with the path information corresponding to each mapping entry being way0, way1, ..., way(x-1), respectively.

[0084] The padding positions in the private cache correspond one-to-one with the mapping table entries in the snooping filter 15. The padding positions in the private cache are filled with cache lines and their identifiers, while the mapping table entries in the snooping filter 15 store the identifiers of the cache lines that are filled at the corresponding padding positions.

[0085] In this embodiment, the address range of the filling position in the private cache is used as index information. The filling position in the private cache is divided into multiple filling position sets according to the index information, so that each filling position in the same filling position set has the same index information, and each filling position in the same filling position set corresponds to different road information. This provides different index information and road information for each mapping table entry included in the eavesdropping filter 15, so that the filling positions with the same index information and road information correspond to the mapping table entries, thereby realizing a one-to-one correspondence between the filling positions and the mapping table entries.

[0086] In one possible implementation, the identification information could be the address information of the cache line in memory.

[0087] In this embodiment, since different cache lines have different addresses in memory, the address information of the cache line in memory can be used as the identification information of the cache line. This allows different cache lines to be distinguished based on the identification information, making it convenient for the processor core to find the required data from the private cache of other processor cores based on the identification information of the cache line, thus ensuring the efficiency of the processor core in finding the required data and thereby ensuring the performance of the processing unit.

[0088] Eavesdropping Filtering Methods

[0089] Figure 5 This is a flowchart of a snooping filtering method according to an embodiment of this application. This snooping filtering method can be executed by the snooping filter 15 in the above embodiment. Figure 5 As shown, this eavesdropping filtering method includes the following steps:

[0090] Step 501: Receive coordinate information sent by the private cache after the first cache line is filled into the private cache, wherein the coordinate information is used to indicate the target filling position of the first cache line in the private cache;

[0091] Step 502: When the mapping table entry corresponding to the target filling position is determined to contain the identification information of the second cache line based on the coordinate information, the identification information of the second cache line is transferred from the mapping table entry corresponding to the target filling position to the sacrifice table entry, and the identification information of the first cache line is stored in the mapping table entry corresponding to the target filling position. Different cache lines correspond to different identification information.

[0092] In this embodiment, the fill positions in the private cache correspond one-to-one with the mapping table entries. After the first cache line is filled to the target fill position, if the mapping table entry corresponding to the target fill position stores the identification information of the second cache line, then the identification information of the second cache line is transferred to the sacrifice table entry, and the identification information of the first cache line is stored in the mapping table entry corresponding to the target fill position. Since the fill positions correspond one-to-one with the mapping table entries, when the second cache line does not need to be written back to data, the identification information of the first cache line is stored in the mapping table entry corresponding to the target fill position, while the identification information of the second cache line is transferred to the sacrifice table entry. Therefore, for cache lines that do not need to be written back to data, the private cache does not need to send a deletion request to the snooping filter to ensure that the snooping filter determines which private caches cannot store the required data, thereby reducing the number of snooping requests on the private caches of other processor cores. This reduces the bandwidth occupied by sending deletion requests on the communication between the processor core and the external processor core, thereby ensuring the performance of the processing unit.

[0093] In one possible implementation, when the mapping table entry corresponding to the target filling position is determined to be empty based on the coordinate information, the identifier information of the first cache line is stored in the mapping table entry corresponding to the target filling position.

[0094] In one possible implementation, transferring the identification information of the second cache line from the mapping entry corresponding to the target padding position to the sacrifice entry includes: determining the snooping entry set to which the mapping entry corresponding to the target padding position belongs, and transferring the identification information of the second cache line from the mapping entry corresponding to the target padding position to the sacrifice entry included in the snooping entry set. The snooping filter includes at least one snooping entry set, each snooping entry set includes a sacrifice entry and at least one mapping entry, each snooping entry set corresponds to a padding position set in the private cache, each padding position set includes at least one padding position, the number of mapping entries in each snooping entry set is equal to the number of padding positions in the corresponding padding position set, and different mapping entries in the corresponding snooping entry set and padding position set correspond to different padding positions.

[0095] In one possible implementation, transferring the identification information of the second cache line from the mapping entry corresponding to the target fill position to the sacrifice entry includes: if the sacrifice entry stores the identification information of the third cache line, the identification information of the second cache line is used to overwrite the identification information of the third cache line in the sacrifice entry, wherein the number of cache line fill requests to be completed corresponding to each fill position set is less than or equal to 1, and the cache line fill request is used to request to fill the cache line to the fill position included in the corresponding fill position set.

[0096] It should be noted that the details of the eavesdropping filtering method have been described in detail in the eavesdropping filter section of the above embodiments with reference to the structural diagram. The specific process can be found in the description of the eavesdropping filter embodiments above, and will not be repeated here.

[0097] Computer storage media

[0098] This application also provides a computer-readable storage medium storing instructions for causing a machine to perform the snooping filtering method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0099] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of this application.

[0100] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0101] Computer program products

[0102] This application also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0103] The commercial value of the embodiments in this application

[0104] In addressing the issue of excessive communication bandwidth occupied by snooping filters between the processor core and external systems, this application's embodiments employ a sacrifice entry. When the private cache fills a cache line, it notifies the snooping filter of the corresponding coordinate information. The snooping filter stores the identifier information of the filled cache line in the corresponding mapping entry. If the mapping entry contains other identifier information, but the corresponding cache line does not require write-back, only the coordinate information needs to be provided to the snooping filter. The snooping filter will then store the original cache line's identifier information in the sacrifice entry. This eliminates the need for the private cache to send deletion requests to the snooping filter, reducing the bandwidth occupied between the processor core and external systems and thus ensuring the performance of the processing unit. Because of the added sacrifice entry and the restriction that only one fill request is allowed at the same fill location set, when the replaced cache line differs from the data in memory, a data fill request can be initiated first, followed by a data write-back request, ensuring the speed of data fill in the cache.

[0105] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0106] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0107] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0108] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A listening filter, comprising: A receiving unit is configured to receive coordinate information sent by the private cache after the first cache line is filled into the private cache, wherein the coordinate information is used to indicate the target filling position of the first cache line in the private cache; The eavesdropping unit is configured to, when determining that the mapping entry corresponding to the target filling position stores the identification information of the second cache line based on the coordinate information, determine the eavesdropping entry set to which the mapping entry corresponding to the target filling position belongs, transfer the identification information of the second cache line from the mapping entry corresponding to the target filling position to the sacrifice entry contained in the eavesdropping entry set, and store the identification information of the first cache line in the mapping entry corresponding to the target filling position, wherein different cache lines correspond to different identification information; The snooping filter includes at least one snooping entry set, each snooping entry set including a sacrifice entry and at least one mapping entry, each snooping entry set corresponding to a padding location set in the private cache, each padding location set including at least one padding location, the number of mapping entries in each snooping entry set being equal to the number of padding locations in the corresponding padding location set, and different mapping entries in the corresponding snooping entry set and padding location set corresponding to different padding locations.

2. The eavesdropping filter according to claim 1, wherein, The listening unit is configured to store the identifier information of the first cache line into the mapping table entry corresponding to the target filling position when it is determined from the coordinate information that the mapping table entry corresponding to the target filling position is empty.

3. The snoop filter of claim 2, wherein, The number of pending cache line fill requests corresponding to each fill position set is less than or equal to 1. A cache line fill request is used to request the filling of cache lines into the fill positions included in the corresponding fill position set.

4. The eavesdropping filter according to claim 3, wherein, The listening unit is configured to, when transferring the identification information of the second cache line to the sacrifice entry, if the sacrifice entry stores the identification information of the third cache line, overwrite the identification information of the third cache line in the sacrifice entry with the identification information of the second cache line.

5. The snoop filter of claim 1, wherein, The snooping filter includes at least two snooping entry sets, and at least two padding location sets corresponding to the at least two snooping entry sets are located in at least two private caches. Different snooping entry sets correspond to different padding location sets, and the at least two private caches are located within the same processor core.

6. The snoop filter of claim 1, wherein, Each padding location in the same set corresponds to the same index information, which is used to identify the address range of the cache line that can be filled by the padding location in the private cache.

7. The snoop filter of any one of claims 1-6, wherein, The identification information includes the memory address of the corresponding cache line.

8. A processing unit, comprising: The eavesdropping filter according to any one of claims 1-7; At least two processor cores are used to query the snooping filter to determine the private cache where the required data is located.

9. A computing device, comprising: The processing unit according to claim 8; A memory, coupled to the processing unit, stores the data required by the processing unit.

10. A snooping filtering method, applied to a snooping filter, comprising: After the first cache line is filled into the private cache, the private cache sends coordinate information, wherein the coordinate information is used to indicate the target filling position of the first cache line in the private cache; When it is determined that the mapping entry corresponding to the target filling position stores the identification information of the second cache line based on the coordinate information, the eavesdropping entry set to which the mapping entry corresponding to the target filling position belongs is determined, the identification information of the second cache line is transferred from the mapping entry corresponding to the target filling position to the sacrifice entry contained in the eavesdropping entry set, and the identification information of the first cache line is stored in the mapping entry corresponding to the target filling position, wherein different cache lines correspond to different identification information; The snooping filter includes at least one snooping entry set, each snooping entry set includes a sacrifice entry and at least one mapping entry, each snooping entry set corresponds to a padding location set in the private cache, each padding location set includes at least one padding location, the number of mapping entries in each snooping entry set is equal to the number of padding locations in the corresponding padding location set, and different mapping entries in the corresponding snooping entry set and padding location set correspond to different padding locations.

11. The snoop filtering method of claim 10, wherein, The method further includes: When it is determined from the coordinate information that the mapping table entry corresponding to the target filling position is empty, the identifier information of the first cache line is stored in the mapping table entry corresponding to the target filling position.

12. The eavesdropping filtering method according to claim 10, wherein, The step of transferring the identification information of the second cache line from the mapping entry corresponding to the target filling position to the sacrifice entry contained in the eavesdropping entry set includes: If the sacrifice entry stores the identification information of the third cache line, the identification information of the third cache line in the sacrifice entry is overwritten by the identification information of the second cache line. The number of cache line filling requests to be completed corresponding to each filling position set is less than or equal to 1. The cache line filling request is used to request the filling of cache lines to the filling positions included in the corresponding filling position set.

Images