A semiconductor structure and a method of manufacturing the same

Abstract

The embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a first insulating layer on the substrate; etching the first insulating layer and the substrate to form a first groove; forming a dielectric layer, the dielectric layer filling the first groove; performing an etching process on the dielectric layer located in the first groove, so that the upper surface of the dielectric layer and the bottom surface of the first insulating layer have a preset height difference; and removing the first insulating layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] In the manufacturing process of semiconductor structures, such as complementary metal-oxide-semiconductor image sensors (CMOS Image Sensor, CIS), it is usually necessary to form an insulating layer on a substrate, then etch the insulating layer and the substrate to form trenches and fill the trenches with a dielectric layer, and finally remove the insulating layer. The dielectric layer located in the substrate serves to isolate the device.

[0003] However, since the top of the dielectric layer protrudes from the upper surface of the substrate, it is often impossible to completely remove the insulating layer located on the sidewall of the dielectric layer. The residual insulating layer will have an adverse effect on subsequent processes. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor structure, including:

[0005] Provide substrate;

[0006] A first insulating layer is formed on the substrate;

[0007] The first insulating layer and the substrate are etched to form a first trench;

[0008] A dielectric layer is formed, which fills the first trench;

[0009] An etching process is performed on the dielectric layer located in the first trench to create a predetermined height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer.

[0010] Remove the first insulating layer.

[0011] In some embodiments, the preset height difference ranges from 0 to 10 nm.

[0012] In some embodiments, an etching process is performed on the dielectric layer located within the first trench to create a predetermined height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer, including:

[0013] Etch the dielectric layer located within the first trench;

[0014] Measure the height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer;

[0015] If the height difference is within the range of the preset height difference, the etching process ends;

[0016] If the upper surface of the dielectric layer is higher than the bottom surface of the first insulating layer, and the height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer exceeds the preset height difference range, then the etching and height difference measurement steps are performed again until the height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer is within the preset height difference range, at which point the etching process ends.

[0017] In some embodiments, the dielectric layer is etched using an etching solution comprising hydrofluoric acid or an etching solution comprising dilute sulfuric acid and hydrogen peroxide.

[0018] In some embodiments, before forming a first insulating layer on the substrate, the method further includes: forming a second insulating layer on the substrate, the second insulating layer being located below the first insulating layer;

[0019] In the same step of etching the first insulating layer and the substrate, the method further includes etching the second insulating layer, wherein the first trench is located within the first insulating layer, the second insulating layer and the substrate.

[0020] In some embodiments, the first trench includes a first sub-trench and a second sub-trench; prior to forming the dielectric layer, the method further includes:

[0021] The substrate is etched downwards from the bottom surface of the second sub-trench to form the second trench.

[0022] In some embodiments, forming a dielectric layer includes:

[0023] A first dielectric sublayer is formed, which fills the first sub-trench and covers the inner wall of the second trench, the sidewall of the second sub-trench, and the upper surface of the first insulating layer.

[0024] In some embodiments, after forming the first dielectric sublayer, the method further includes:

[0025] An isolation layer is formed within the second trench, the isolation layer covering the first dielectric sublayer located within the second trench and filling the second trench.

[0026] In some embodiments, after forming an isolation layer within the second trench, the method further includes:

[0027] A second dielectric sublayer is formed, which covers the first dielectric sublayer and fills the second sub-trench.

[0028] In some embodiments, after forming the second dielectric sublayer, the method further includes:

[0029] The first dielectric sublayer and the second dielectric sublayer located above the first insulating layer and the first trench are removed using a chemical mechanical polishing process to form the dielectric layer.

[0030] This disclosure also provides a semiconductor structure, including:

[0031] Substrate;

[0032] A first insulating layer is located on the substrate;

[0033] The first trench is located within the first insulating layer and the substrate;

[0034] A dielectric layer that fills a portion of the first trench, and the upper surface of the dielectric layer has a predetermined height difference with the bottom surface of the first insulating layer.

[0035] In some embodiments, the preset height difference ranges from 0 to 10 nm.

[0036] In some embodiments, the first trench includes a first sub-trench and a second sub-trench; the semiconductor structure further includes: a second trench located below the second sub-trench; and an isolation layer located within the second trench.

[0037] In some embodiments, the dielectric layer includes a first dielectric sublayer and a second dielectric sublayer, wherein the first dielectric sublayer fills a portion of the first sub-trench and covers the inner wall of the second trench and a portion of the sidewall of the second sub-trench, and the isolation layer and the substrate are spaced apart by the first dielectric sublayer; the second dielectric sublayer fills a portion of the second sub-trench, and the upper surface of the first dielectric sublayer and the upper surface of the second dielectric sublayer are flush.

[0038] In some embodiments, the semiconductor structure further includes a second insulating layer located on the upper surface of the substrate, the second insulating layer being located below the first insulating layer; the first trench is located within the first insulating layer, the second insulating layer, and the substrate.

[0039] The semiconductor structure and manufacturing method thereof provided in this disclosure include: providing a substrate; forming a first insulating layer on the substrate; etching the first insulating layer and the substrate to form a first trench; forming a dielectric layer that fills the first trench; performing an etching process on the dielectric layer located in the first trench to create a predetermined height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer; and removing the first insulating layer. Before removing the first insulating layer, this disclosure etches the dielectric layer located in the first trench, creating a predetermined height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer. Specifically, the upper surface of the dielectric layer is flush with, slightly lower than, or slightly higher than the bottom surface of the first insulating layer. This avoids or improves the situation where the first insulating layer remains on the sidewalls of the dielectric layer during removal, eliminating or mitigating the adverse effects of the first insulating layer on subsequent processes.

[0040] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the accompanying drawings and claims. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A flowchart illustrating the semiconductor structure provided in the embodiments of this disclosure;

[0043] Figures 2 to 12 A process flow diagram of a method for manufacturing a semiconductor structure provided in this disclosure embodiment;

[0044] Figure 13a This is a schematic diagram of a semiconductor structure provided in related technologies. Figure 13b for Figure 13a A magnified schematic diagram of a local region Q in the middle. Detailed Implementation

[0045] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] In the manufacturing process of semiconductor structures, such as complementary metal-oxide-semiconductor image sensors (CMOS Image Sensor, CIS), it is usually necessary to form an insulating layer on a substrate, then etch the insulating layer and the substrate to form trenches and fill the trenches with a dielectric layer, and finally remove the insulating layer. The dielectric layer located in the substrate serves to isolate the device.

[0052] Figure 13a This is a schematic diagram of a semiconductor structure provided in related technologies. Figure 13b for Figure 13a A magnified schematic diagram of a local region Q in the middle, where, Figure 13a The semiconductor structure formed after removing the insulating layer 12 is shown in the figure. The semiconductor structure includes a substrate 10 and a dielectric layer 11 partially located within the substrate 10. However, since the top of the dielectric layer 11 protrudes from the upper surface of the substrate 10, and due to etching characteristics, the trenches and the dielectric layer 11 located within the trenches are often inverted trapezoidal, that is, the sidewalls of the dielectric layer 11 and the surface of the substrate 10 have an acute angle. Thus, when removing the insulating layer 12, it is often impossible to completely remove the insulating layer 12 located on the sidewalls of the dielectric layer 11, and the residual insulating layer 12 will have an adverse effect on subsequent processes.

[0053] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0054] This disclosure provides a method for manufacturing a semiconductor structure; please refer to the following for details. Figure 1 As shown in the figure, the method includes the following steps:

[0055] Step 101: Provide a substrate;

[0056] Step 102: Form a first insulating layer on the substrate;

[0057] Step 103: Etch the first insulating layer and the substrate to form the first trench;

[0058] Step 104: Form a dielectric layer, which fills the first trench;

[0059] Step 105: Perform an etching process on the dielectric layer located in the first trench to create a preset height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer;

[0060] Step 106: Remove the first insulating layer.

[0061] In this embodiment of the present disclosure, before removing the first insulating layer, a dielectric layer located in the first trench is etched, and a predetermined height difference is made between the upper surface of the dielectric layer and the bottom surface of the first insulating layer. That is, the upper surface of the dielectric layer is flush with the bottom surface of the first insulating layer, or slightly lower than the bottom surface of the first insulating layer, or slightly higher than the bottom surface of the first insulating layer. In this way, during the removal of the first insulating layer, the residue of the first insulating layer on the sidewall of the dielectric layer is avoided or improved, and the adverse effects of the first insulating layer on subsequent processes are eliminated or mitigated.

[0062] The manufacturing method provided in this disclosure can be used to manufacture image sensors, such as complementary metal-oxide-semiconductor image sensors (CMOS image sensors, CIS). However, it is not limited to this; the manufacturing method can also be used to manufacture any semiconductor structure including isolation trenches.

[0063] Figures 2 to 12 A process flow diagram of a method for manufacturing a semiconductor structure provided in this disclosure. The following is in conjunction with... Figures 2 to 12 The method for manufacturing the semiconductor structure provided in the embodiments of this disclosure will be described in further detail.

[0064] First, perform step 101, as follows: Figure 2 As shown, a substrate 20 is provided.

[0065] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0066] Next, proceed to step 102, as follows: Figure 3 As shown, a first insulating layer 22 is formed on the substrate 20.

[0067] The first insulating layer 22 can be formed on the substrate 20 using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the first insulating layer 22 includes, but is not limited to, nitrides, such as silicon nitride.

[0068] See you again Figure 3In one embodiment, before forming the first insulating layer 22 on the substrate 20, the method further includes forming a second insulating layer 21 on the substrate 20, the second insulating layer 21 being located below the first insulating layer 22. The second insulating layer 21 is used to protect the substrate 20 from damage or contamination in subsequent processes. The second insulating layer 21 can be formed on the substrate 20 using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the second insulating layer 21 includes, but is not limited to, oxides, such as silicon oxide.

[0069] Next, proceed to step 103, as follows: Figure 4 As shown, the first insulating layer 22 and the substrate 20 are etched to form the first trench T1.

[0070] In one embodiment, the same step of etching the first insulating layer 22 and the substrate 20 further includes etching the second insulating layer 21, wherein the first trench T1 is located within the first insulating layer 22, the second insulating layer 21, and the substrate 20. In some embodiments, due to the characteristics of etching, the first trench T1 is inverted trapezoidal, and the sidewall of the first trench T1 forms an acute angle with the upper surface of the second insulating layer 21.

[0071] In one embodiment, the first trench T1 includes a first sub-trench T11 and a second sub-trench T12, and a second trench T2 can subsequently be formed below the second sub-trench T12 (see [link]). Figure 5 ).

[0072] Next, proceed to step 104, as follows: Figure 6 , Figure 9 , Figure 10 As shown, a dielectric layer 26 is formed, and the dielectric layer 26 fills the first trench T1.

[0073] like Figure 5 As shown, in one embodiment, the method further includes etching the substrate 20 downward from the bottom surface of the second sub-trench T12 to form a second trench T2. In some embodiments, the depth of the second trench T2 is greater than the depth of a portion of the first trench T1 located within the substrate 20.

[0074] See you again Figure 6 The formation of dielectric layer 26 includes: firstly, forming a first dielectric sublayer 23, wherein the first dielectric sublayer 23 fills the first sub-trench T11 and covers the inner wall of the second trench T2, the side wall of the second sub-trench T12 and the upper surface of the first insulating layer 22.

[0075] The first dielectric sublayer 23 may have a single-layer structure and may be formed by a one-step deposition process. However, it is not limited to this; the first dielectric sublayer 23 may also have a multi-layer structure and be formed by multiple deposition processes. For example, the first dielectric sublayer 23 may be formed by: firstly, forming a portion of the first dielectric sublayer 23 that fills the first sub-trench T11; then, forming another portion of the first dielectric sublayer 23 that covers the inner wall of the second trench T2, the sidewall of the second sub-trench T12, and the upper surface of the first insulating layer 22. In other embodiments, the first dielectric sublayer 23 may also be formed by: firstly, forming a dielectric material layer that fills the first sub-trench T11, the second sub-trench T12, and the second trench T2 and covers the first insulating layer 22; then, removing a portion of the dielectric material layer to form the first dielectric sublayer 23. However, it is not limited to this; the first dielectric sublayer 23 may be formed in any other possible manner, and this disclosure does not impose excessive limitations on this.

[0076] Figure 5 , Figure 6 The first dielectric sublayer 23 shown is deposited on the substrate 20 after the formation of the second trench T2, but it is not limited thereto. In other embodiments, the first sub-trench T11 and the first dielectric sublayer 23 located in the first sub-trench T11 may be formed first, followed by the formation of the second sub-trench T12, the second trench T2 and the first dielectric sublayer 23 located in the second sub-trench T12 and the second trench T2. This disclosure does not impose too many restrictions on this.

[0077] The first dielectric sublayer 23 can be formed on the substrate 20 using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Optionally, after forming the first dielectric sublayer 23, an annealing process is performed on the first dielectric sublayer 23 to reduce or eliminate defects within the first dielectric sublayer 23 and improve the density of the first dielectric sublayer 23, thereby improving the isolation effect of the first dielectric sublayer 23. The material of the first dielectric sublayer 23 includes, but is not limited to, oxides, such as silicon oxide.

[0078] Next, as Figures 7 to 8 As shown, after forming the first dielectric sublayer 23, the method further includes: forming an isolation layer 24 in the second trench T2, the isolation layer 24 covering the first dielectric sublayer 23 located in the second trench T2 and filling the second trench T2.

[0079] Specifically, forming the isolation layer 24 includes: forming an isolation material layer 24′, the isolation material layer 24′ filling the second trench T2 and the second sub-trench T12 and covering the first dielectric sub-layer 23; removing part of the isolation material layer 24′ using a chemical mechanical polishing process, so that the upper surface of the isolation material layer 24′ is flush with the upper surface of the first dielectric sub-layer 23; and etching back the isolation material layer 24′ to form the isolation layer 24, the isolation layer 24 filling the second trench T2. The isolation material layer 24′ can be formed by processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0080] In practice, the semiconductor structure can be an image sensor, such as a complementary metal-oxide-semiconductor image sensor (CMOS Image Sensor, CIS). A photodiode can then be formed within the substrate 20. The dielectric layer 26 and the isolation layer 24 are used to isolate two adjacent photodiodes. In one embodiment, the isolation layer 24 is made of polysilicon. Using polysilicon as the material for the isolation layer 24 in this embodiment provides better isolation. In some embodiments, the isolation layer 24 is p-type doped, and the dopant ions within the isolation layer 24 include, but are not limited to, boron, thereby further improving the isolation effect of the isolation layer 24. The isolation layer 24 and the substrate 20 are separated by a first dielectric sublayer 23, which provides electrical isolation. Furthermore, when the isolation material layer 24′ is doped, the first dielectric sublayer 23 can prevent dopant ions from entering the substrate 20.

[0081] Next, see you again. Figure 9 After forming the isolation layer 24 within the second trench T2, the method further includes forming a second dielectric sublayer 25, which covers the first dielectric sublayer 23 and fills the second sub-trench T12. The material of the second dielectric sublayer 25 includes high-density plasma (HDP) oxide, such as HDP silicon oxide, thereby improving the isolation effect of the second dielectric sublayer 25.

[0082] Specifically, the formation process of the second dielectric sublayer 25 can be as follows: First, a seed layer is formed, which covers the inner wall of the second sub-trench T12 and the upper surface of the first dielectric sublayer 23; then, the second dielectric sublayer 25 is deposited on the seed layer. The deposition method of the second dielectric sublayer 25 can be chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. Optionally, after the formation of the second dielectric sublayer 25, a water washing process can be performed on the second dielectric sublayer 25 to remove contaminants or deposition byproducts on the second dielectric sublayer 25.

[0083] Next, see you again. Figure 10 After forming the second dielectric sublayer 25, the method further includes: removing the first dielectric sublayer 23 and the second dielectric sublayer 25 located above the first insulating layer 22 and the first trench T1 using a chemical mechanical polishing process to form a dielectric layer 26, the upper surface of which is flush with the upper surface of the first insulating layer 22. In some embodiments, the dielectric layer 26 located in the first trench T1 is inverted trapezoidal in shape.

[0084] Next, proceed to step 105, as follows: Figure 11 As shown, an etching process is performed on the dielectric layer 26 located in the first trench T1 to create a preset height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22.

[0085] Figure 11 The upper surface of the dielectric layer 26 shown is flush with the bottom surface of the first insulating layer 22, but it is not limited to this. The upper surface of the dielectric layer 26 may also be higher or lower than the bottom surface of the first insulating layer 22. In one embodiment, the preset height difference ranges from 0 to 10 nm, for example, from 0 to 6 nm. That is, the upper surface of the dielectric layer 26 may be flush with, slightly lower than, or slightly higher than the bottom surface of the first insulating layer 22. The first insulating layer 22 will be removed in subsequent processes. In this way, the removal of the first insulating layer 22 avoids or improves the situation where the first insulating layer 22 remains on the sidewall of the dielectric layer 26, eliminating or mitigating the adverse effects of the first insulating layer 22 on subsequent processes.

[0086] Here, the dielectric layer 26 can be etched using one or more etching processes. Specifically, the dielectric layer 26 located in the first trench T1 is etched to create a predetermined height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22, including:

[0087] Etch the dielectric layer 26 located in the first trench T1;

[0088] The height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is measured.

[0089] If the height difference is within the preset height difference range, the etching process ends;

[0090] If the upper surface of the dielectric layer 26 is higher than the bottom surface of the first insulating layer 22, and the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 exceeds a preset height difference range, then the etching and height difference measurement steps are performed again until the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is within the preset height difference range, at which point the etching process ends. In this embodiment, the dielectric layer 26 located in the first trench T1 is etched in one or more etching processes. By measuring the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22, it is ensured that the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is within the preset height difference range. This allows for more precise removal of a portion of the dielectric layer 26, avoiding over-etching or under-etching that could reduce product yield. In some embodiments, Physical Fault Analysis (PFA) is used to measure the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22.

[0091] In one embodiment, the dielectric layer 26 is etched using an etching solution comprising hydrofluoric acid or an etching solution comprising dilute sulfuric acid and hydrogen peroxide. Optionally, after etching the dielectric layer 26, a water washing process is performed on the dielectric layer 26 to remove contaminants or etching byproducts.

[0092] Next, proceed to step 106, as follows: Figure 12 As shown, the first insulation 22 is removed.

[0093] This embodiment of the disclosure avoids leaving the first insulating layer 22 on the substrate 20 by removing the dielectric layer 26 located within the first trench T1 before removing the first insulating layer 22. In one embodiment, removing the first insulating layer 22 includes etching the first insulating layer 22 using an etching solution comprising phosphoric acid.

[0094] It should be noted that those skilled in the art can make possible changes to the order of the above steps without departing from the scope of protection of this disclosure.

[0095] This disclosure also provides a semiconductor structure, such as... Figure 11 As shown, it includes: a substrate 20; a first insulating layer 22 located on the substrate 20; a first trench T1 located within the first insulating layer 22 and the substrate 20; and a dielectric layer 26 that fills a portion of the first trench T1, with a predetermined height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22.

[0096] The substrate may be a semiconductor substrate, and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0097] In one embodiment, the semiconductor structure further includes a second insulating layer 21 located on the upper surface of the substrate 20, the second insulating layer 21 being situated below the first insulating layer 22; a first trench T1 is located within the first insulating layer 22, the second insulating layer 21, and the substrate 20. In practice, the first insulating layer 22 and the second insulating layer 21 can be formed on the substrate 20 using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The material of the first insulating layer 22 includes, but is not limited to, nitrides, such as silicon nitride. The material of the second insulating layer 21 includes, but is not limited to, oxides, such as silicon oxide.

[0098] In the step of forming the first trench T1, due to the etching characteristics, the first trench T1 is inverted trapezoidal, and the sidewall of the first trench T1 has an acute angle with the upper surface of the second insulating layer 21.

[0099] In one embodiment, the first trench T1 includes a first sub-trench T11 and a second sub-trench T12; the semiconductor structure further includes: a second trench T2 located below the second sub-trench T12; and an isolation layer 24 located within the second trench T2. The second trench T2 is formed by etching the substrate 20 downwards from the bottom surface of the second sub-trench T12. In some embodiments, the depth of the second trench T2 is greater than the depth of the portion of the first trench T1 located within the substrate 20. The isolation layer 24 can be formed within the second trench T2 using processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0100] In practice, the semiconductor structure can be an image sensor, such as a complementary metal-oxide-semiconductor image sensor (CMOS Image Sensor, CIS). Photodiodes can then be formed within the substrate 20, with the dielectric layer 26 and the isolation layer 24 used to isolate adjacent photodiodes. In one embodiment, the isolation layer 24 is made of polycrystalline silicon. Using polycrystalline silicon as the material for the isolation layer 24 in this embodiment provides better isolation. In some embodiments, the isolation layer 24 is p-type doped, and the dopant ions within the isolation layer 24 include, but are not limited to, boron, thereby further improving the isolation effect of the isolation layer 24.

[0101] In one embodiment, the dielectric layer 26 includes a first dielectric sublayer 23 and a second dielectric sublayer 25. The first dielectric sublayer 23 fills a portion of the first sub-trench T11 and covers the inner wall of the second trench T2 and a portion of the sidewall of the second sub-trench T12. The isolation layer 24 and the substrate 20 are separated by the first dielectric sublayer 23. The second dielectric sublayer 25 fills a portion of the second sub-trench T12, and the upper surface of the first dielectric sublayer 23 and the upper surface of the second dielectric sublayer 25 are flush. Here, the first dielectric sublayer 23 located between the isolation layer 24 and the substrate 20 provides electrical isolation. Furthermore, when the isolation material layer 24′ is doped, the first dielectric sublayer 23 can prevent dopant ions from entering the substrate 20. The material of the first dielectric sublayer 23 includes, but is not limited to, oxides, such as silicon oxide. The material of the second dielectric sublayer 25 includes high-density plasma (HDP) oxides, such as HDP silicon oxide, thereby improving the isolation effect of the second dielectric sublayer 25.

[0102] In actual operation, the dielectric layer 26 can be formed as follows: First, before forming the isolation layer 24 in the second trench T2, a first dielectric sublayer 23 is formed. The first dielectric sublayer 23 fills the first sub-trench T11 and covers the inner wall of the second trench T2, the side wall of the second sub-trench T12, and the upper surface of the first insulating layer 22. Next, after forming the isolation layer 24 in the second trench T2, a second dielectric sublayer 25 is formed. The second dielectric sublayer 25 covers the first dielectric sublayer 23 and fills the second sub-trench T12. Then, a chemical mechanical polishing process is used to remove the first dielectric sublayer 23 and the second dielectric sublayer 25 located above the first insulating layer 22 and the first trench T1, forming the dielectric layer 26. Then, the dielectric layer 26 located in the first trench T1 is etched so that the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 have a predetermined height difference. In practice, an etching solution containing hydrofluoric acid or an etching solution containing dilute sulfuric acid and hydrogen peroxide can be used to etch the dielectric layer 26 located in the first trench T1.

[0103] Figure 11 The upper surface of the dielectric layer 26 shown is flush with the bottom surface of the first insulating layer 22, but it is not limited to this. The upper surface of the dielectric layer 26 may also be higher or lower than the bottom surface of the first insulating layer 22. In one embodiment, the preset height difference ranges from 0 to 10 nm, for example, from 0 to 6 nm. That is, the upper surface of the dielectric layer 26 may be flush with, slightly lower than, or slightly higher than the bottom surface of the first insulating layer 22. The first insulating layer 22 will be removed in subsequent processes. In this way, the removal of the first insulating layer 22 avoids or improves the situation where the first insulating layer 22 remains on the sidewall of the dielectric layer 26, eliminating or mitigating the adverse effects of the first insulating layer 22 on subsequent processes.

[0104] In practice, the dielectric layer 26 located in the first trench T1 can be etched using one or more etching processes. Specifically, firstly, the dielectric layer 26 located in the first trench T1 is etched; then, the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is measured; if the height difference is within the preset height difference range, the etching process ends; if the upper surface of the dielectric layer 26 is higher than the bottom surface of the first insulating layer 22, and the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 exceeds the preset height difference range, then the etching and height difference measurement steps are repeated until the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is within the preset height difference range, at which point the etching process ends.

[0105] Here, the dielectric layer 26 located in the first trench T1 is etched using one or more etching processes, and the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is measured to ensure that the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22 is within a preset range. This allows for more precise removal of part of the dielectric layer 26, avoiding over-etching or under-etching that could reduce product yield. In some embodiments, Physical Fault Analysis (PFA) is used to measure the height difference between the upper surface of the dielectric layer 26 and the bottom surface of the first insulating layer 22.

[0106] In subsequent processes, the first insulating layer 22 can be removed to form a structure like... Figure 12 The semiconductor structure shown. In actual operation, the first insulating layer 22 can be etched using an etching solution containing phosphoric acid.

[0107] It should be noted that the above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, include: Provide substrate; A first insulating layer is formed on the substrate; The first insulating layer and the substrate are etched to form a first trench, the first trench including a first sub-trench and a second sub-trench; The substrate is etched downwards from the bottom surface of the second sub-trench to form the second trench; A dielectric layer is formed, the dielectric layer filling the first trench, the dielectric layer including a first dielectric sub-layer, the first dielectric sub-layer filling the first sub-trench and covering the inner wall of the second trench, the side wall of the second sub-trench, the first insulating layer, and the upper surface of the first insulating layer; An etching process is performed on the dielectric layer located in the first trench to create a predetermined height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer. Remove the first insulating layer.

2. The manufacturing method according to claim 1, characterized by, The preset height difference ranges from 0 to 10 nm.

3. The production method according to claim 1, characterized by An etching process is performed on the dielectric layer located within the first trench to create a predetermined height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer, including: Etch the dielectric layer located within the first trench; Measure the height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer; If the height difference is within the range of the preset height difference, the etching process ends; If the upper surface of the dielectric layer is higher than the bottom surface of the first insulating layer, and the height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer exceeds the preset height difference range, then the etching and height difference measurement steps are performed again until the height difference between the upper surface of the dielectric layer and the bottom surface of the first insulating layer is within the preset height difference range, at which point the etching process ends.

4. The production method according to claim 1, characterized by The dielectric layer is etched using an etching solution containing hydrofluoric acid or an etching solution containing dilute sulfuric acid and hydrogen peroxide.

5. The production method according to claim 1, wherein Before forming a first insulating layer on the substrate, the method further includes: forming a second insulating layer on the substrate, the second insulating layer being located below the first insulating layer; In the same step of etching the first insulating layer and the substrate, the method further includes etching the second insulating layer, wherein the first trench is located within the first insulating layer, the second insulating layer and the substrate.

6. The production method according to claim 1, characterized by After forming the first dielectric sublayer, the method further includes: An isolation layer is formed within the second trench, the isolation layer covering the first dielectric sublayer located within the second trench and filling the second trench.

7. The production method according to claim 6, wherein After forming an isolation layer within the second trench, the method further includes: A second dielectric sublayer is formed, which covers the first dielectric sublayer and fills the second sub-trench.

8. The production method according to claim 7, wherein After forming the second dielectric sublayer, the method further includes: The first dielectric sublayer and the second dielectric sublayer located above the first insulating layer and the first trench are removed using a chemical mechanical polishing process to form the dielectric layer.

9. A semiconductor structure, characterized by include: Substrate; A first insulating layer is located on the substrate; A first trench is located within the first insulating layer and the substrate, and the first trench includes a first sub-trench and a second sub-trench. The second trench is located below the second sub-trench; A dielectric layer, the dielectric layer filling a portion of the first trench, the dielectric layer including a first dielectric sub-layer, the first dielectric sub-layer filling the first sub-trench and covering the inner wall of the second trench, the side wall of the second sub-trench, the first insulating layer, and the upper surface of the first insulating layer, and the upper surface of the dielectric layer having a preset height difference with the bottom surface of the first insulating layer.

10. The semiconductor structure of claim 9, wherein, The preset height difference ranges from 0 to 10 nm.

11. The semiconductor structure according to claim 9, characterized in that, Also includes: An isolation layer is located within the second trench.

12. The semiconductor structure according to claim 11, characterized in that, The dielectric layer further includes a second dielectric sublayer, and the isolation layer and the substrate are spaced apart by the first dielectric sublayer; The second dielectric sublayer fills the second sub-groove, and the upper surface of the first dielectric sublayer and the upper surface of the second dielectric sublayer are flush.

13. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure further includes a second insulating layer located on the upper surface of the substrate, the second insulating layer being located below the first insulating layer; the first trench is located within the first insulating layer, the second insulating layer, and the substrate.

Images