Semiconductor structure and three-dimensional NAND memory device

Abstract

A semiconductor structure is disclosed, comprising: a memory level assembly located over a semiconductor substrate and including at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack; a plurality of laterally elongated contact via structures extending vertically through the memory level assembly, extending laterally along a first horizontal direction, and laterally dividing the at least one alternating stack into a plurality of laterally spaced apart blocks, including a group of three adjacent blocks including a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction, and wherein a first subset of the memory stack structures extends through the first block, a second subset of the memory stack structures extends through the second block, and a third subset of the memory stack structures extends through the third block; and a through-memory level via region. A three-dimensional NAND memory device is also disclosed.

Description

[0001] This application is a divisional application of Chinese national phase patent application 201680055260.6 of PCT international patent application PCT / US2016 / 054018, filed on September 27, 2016, and claims priority to U.S. provisional patent application 62 / 271,210, filed on December 22, 2015, and U.S. non-provisional patent applications 15 / 269,041, 15 / 269,112, 15 / 269,294, 15 / 268,946, and 15 / 269,017, filed on September 19, 2016.

[0002] Cross-references to related applications

[0003] This application claims priority to the following applications: U.S. Provisional Application Serial No. 62 / 271210, filed December 22, 2015; U.S. Non-Provisional Application Serial No. 15 / 269041, filed September 19, 2016; U.S. Non-Provisional Application Serial No. 15 / 269112, filed September 19, 2016; U.S. Non-Provisional Application Serial No. 15 / 269294, filed September 19, 2016; U.S. Non-Provisional Application Serial No. 15 / 269946, filed September 19, 2016; and U.S. Non-Provisional Application Serial No. 15 / 269017, filed September 19, 2016, the entire contents of which are incorporated herein by reference. Technical Field

[0004] This disclosure relates generally to the field of semiconductor devices, and more specifically to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods for manufacturing the same. Background Technology

[0005] Recently, ultra-high-density memory devices using three-dimensional (3D) stacked memory stacking structures, sometimes referred to as Bit Cost Scalable (BiCS) architectures, have been proposed. For example, a 3D NAND stacked memory device can be formed from an array of alternating stacks of insulating and spacer material layers, which are formed as conductive layers or replaced with conductive layers. Memory openings are formed by alternating stacks and filled with memory stacking structures, each including vertically stacked memory elements and vertical semiconductor channels. Memory hierarchy components, including alternating stacks and memory stacking structures, are formed on a substrate. Conductive layers can be used as word lines in the 3D NAND stacked memory device, and bit lines covering the memory stacking structure array can be connected to the drain terminals of the vertical semiconductor channels. As 3D memory devices shrink to smaller device sizes, the device area of ​​peripheral devices occupies a large portion of the total chip area. Therefore, methods to provide various peripheral devices (e.g., word line driver circuitry) without significantly increasing the overall chip size are desired. Furthermore, efficient power distribution networks in the memory stacking structure array can improve the performance of 3D memory devices. A method to enhance power distribution without excessively increasing the footprint of the semiconductor chip is also desired. Summary of the Invention

[0006] According to one aspect of this disclosure, a three-dimensional NAND memory device is provided, comprising: a word line driver device located on or above a substrate; an alternating stack of word lines and insulating layers located above the word line driver device; a plurality of memory stack structures extending through the alternating stacks, each memory stack structure including a memory film and a vertical semiconductor channel; and a through-memory via structure electrically coupling word lines in a first memory block to the word line driver device. The through-memory via structure extends through a through-memory via region located between a stepped region of the first memory block and a stepped region of another memory block.

[0007] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a memory hierarchy assembly situated on a semiconductor substrate and including at least one alternately stacked memory stack structure extending vertically through the at least one alternately stacked memory stack, wherein the at least one alternately stacked memory stack includes alternating layers of respective insulating and conductive layers; a plurality of laterally elongated contact via structures extending vertically through the memory hierarchy assembly, extending laterally along a first horizontal direction, and laterally dividing the at least one alternately stacked memory stack into a plurality of laterally spaced blocks, wherein the plurality of blocks includes a set of three adjacent blocks, which sequentially include a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction; and a through-memory via region located adjacent to a longitudinal end of the second block and between a stepped region of the first block and a stepped region of the third block. Each stepped region of the first and third blocks includes a step in which each lower conductive layer extends further along the first horizontal direction than any upper conductive layer within the memory hierarchy assembly. The through-memory via region includes a through-memory via structure that extends vertically from at least a first horizontal plane including the topmost surface of the memory layer component to a second horizontal plane including the bottommost surface of the memory layer component.

[0008] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided. A memory-level assembly is formed on a semiconductor substrate. The memory-level assembly includes at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack. The at least one alternating stack includes alternating layers of corresponding insulating layers and corresponding conductive layers, and the at least one alternating stack includes a stepped region comprising a step in which each lower conductive layer extends further along a first horizontal direction than any upper conductive layer within the memory-level assembly. A plurality of laterally elongated contact via structures are formed through the memory-level assembly. The plurality of laterally elongated contact via structures extend laterally along the first horizontal direction and laterally divide the at least one alternating stack into a plurality of laterally spaced blocks. The plurality of blocks includes a set of at least three adjacent blocks, which sequentially include a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction; and each includes a first stepped region, a second stepped region, and a third stepped region. The second stepped region is removed. The second stepped region is removed. A through-memory-level via structure is formed in the region of the removed second stepped region, while the first and third stepped regions remain intact. Each through-hole structure extends vertically from at least a first horizontal plane containing the topmost surface of the memory hierarchy components to a second horizontal plane containing the bottommost surface of the memory hierarchy components.

[0009] According to another aspect of this disclosure, a three-dimensional NAND memory device is provided, comprising: word line driver devices located on or above a substrate; alternately stacked word lines and an insulating layer located above the word line driver devices; a plurality of memory stack structures extending through the alternately stacked memory stack structures, each memory stack structure including a memory film and a vertical semiconductor channel; and a through-memory via structure electrically coupling word lines in a first memory block to the word line driver devices. The through-memory via structure extends through a portion of dielectric filling material located between a stepped region of the first memory block and a stepped region of another memory block.

[0010] According to another aspect of this disclosure, a semiconductor structure is provided, comprising: a word line switching device including field-effect transistors and located on a semiconductor substrate; and a memory level assembly covering the semiconductor substrate and including at least one alternately stacked and vertically extending memory stack structure through the at least one alternately stacked. Each of the at least one alternately stacked includes an alternating layer comprising a corresponding insulating layer and an alternating layer including a corresponding conductive layer for word lines of the memory stack structure. A plurality of laterally elongated contact via structures extend vertically through the memory level assembly, laterally extending along a first horizontal direction, and laterally dividing the memory level assembly into a plurality of laterally spaced blocks. The plurality of blocks includes a set of three adjacent blocks, which sequentially include a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction. The through-memory via region is located directly on the area of ​​the word line switching device at the longitudinal end of the second block and between the stepped regions of the first block and the third block. Each stepped region of the first and third blocks includes a step in which each lower conductive layer extends further along a first horizontal direction than any upper conductive layer within the memory hierarchy assembly. The through-memory via region includes through-memory via structures, each of which provides a conductive path between the corresponding word line switching device and the corresponding word line.

[0011] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided. A word line switching device including a field-effect transistor is formed on a semiconductor substrate. A memory hierarchy assembly is formed above the semiconductor substrate, the memory hierarchy assembly including at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack. Each of the at least one alternating stack includes alternating layers of a corresponding insulating layer and a corresponding conductive layer, and the at least one alternating stack includes a stepped region comprising a step in which each lower conductive layer extends further along a first horizontal direction than any upper conductive layer within the memory hierarchy assembly. A plurality of laterally elongated contact via structures are formed through the memory hierarchy assembly. The plurality of laterally elongated contact via structures extend laterally along the first horizontal direction and laterally divide the at least one alternating stack into a plurality of laterally spaced blocks. The plurality of blocks includes a set of three adjacent blocks, which sequentially include a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction; and respectively include a first stepped region, a second stepped region, and a third stepped region. The nodes of the word line switching device are electrically connected to portions of the conductive layers in the first and third step regions by using a through-hole structure formed in the region of the second step region.

[0012] According to another aspect of this disclosure, a semiconductor structure is provided, comprising: a memory hierarchy assembly located on a semiconductor substrate and comprising at least one first alternating stack of a first portion of a conductive layer and an insulating layer, and further comprising memory stack structures extending vertically through the at least one first alternating stack, wherein each memory stack structure includes a memory film and a vertical semiconductor channel, wherein the conductive layer includes word lines for the memory stack structure; an insulating deep trench structure extending vertically through the memory hierarchy assembly and defining a region of a through-memory-level via region laterally spaced from the at least one first alternating stack; at least one second alternating stack located in the through-memory-level via region, wherein the at least one second alternating stack comprises alternating layers of dielectric spacer layers and second portions of the insulating layer, and each of the dielectric spacer layers is located at the same level as a corresponding conductive layer; and a through-memory-level via structure located in the through-memory-level via region and extending vertically from a first horizontal plane including the top surface and the bottom surface of the memory hierarchy assembly and comprising a conductive material.

[0013] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided. At least one alternating stacked insulating layer and dielectric spacer layer are formed on a semiconductor substrate. A memory stack structure is formed through the at least one alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. A deep trench is formed through the at least one alternating stack, defining a region through a memory-level via region. A portion of the at least one alternating stack exists within the through-memory-level via region. A portion of the dielectric spacer layer outside the through-memory-level via region is replaced with a conductive layer, while at least one alternating stack portion in the deep trench remains intact. The conductive layer constitutes a word line for the memory stack structure. A through-memory-level via structure is formed within the through-memory-level via region. The through-memory-level via structure extends vertically from a first horizontal plane including the topmost surface of the remaining portion of the at least one alternating stack and the bottommost surface of the at least one alternating stack.

[0014] According to another aspect of this disclosure, a semiconductor structure is provided, comprising: a memory hierarchy assembly located on a semiconductor substrate and including at least one alternating stack of a first portion comprising a conductive layer and an insulating layer, and further comprising memory stack structures extending vertically through the at least one alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. The conductive layer forms word lines for the memory stack structure. A plurality of laterally elongated contact via structures extend vertically through the memory hierarchy assembly, laterally extending along a first horizontal direction, and laterally dividing the at least one alternating stack into a plurality of laterally spaced blocks within the memory hierarchy assembly. At least one through-memory-level via structure is located in a through-memory-level via region within a block; wherein the through-memory-level via region is located between a pair of laterally elongated contact via structures and between two sets of memory stack structures located within the block; wherein each of the at least one through-memory-level via structure extends vertically through the memory hierarchy assembly.

[0015] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided. A memory level assembly is formed on a semiconductor substrate. The memory level assembly includes at least one alternating stack of first portions of conductive and insulating layers, and further includes memory stack structures extending vertically through the at least one alternating stack. Each memory stack structure includes a memory film and a vertical semiconductor channel. A plurality of laterally elongated contact via structures are formed through the memory level assembly. The plurality of laterally elongated contact via structures extend laterally along a first horizontal direction and laterally divide the at least one alternating stack into a plurality of laterally spaced blocks within the memory level assembly. At least one through-memory-level via structure is formed in a through-memory-level via region within a block. The through-memory-level via region is located between a pair of laterally elongated contact via structures and between two sets of memory stack structures located within the block and including the through-memory-level via structure. Each of the at least one through-memory-level via structure extends vertically through the memory level assembly. Attached Figure Description

[0016] Figure 1A This is a vertical cross-sectional view of a first exemplary structure after forming a semiconductor device, at least one lower-level dielectric layer, and a lower-level metal interconnect structure on a semiconductor substrate according to a first embodiment of the present disclosure.

[0017] Figure 1B It is along Figure 1A The horizontal plane B-B' in Figure 1A The first exemplary structure is shown in a horizontal cross-sectional view. The serrated vertical plane A-A' corresponds to... Figure 1A The plane of the vertical cross-section.

[0018] Figure 2 This is a vertical cross-sectional view of a first exemplary structure after alternating stacking of a planar semiconductor material layer and a first insulating layer and a first spacer material layer, according to a first embodiment of the present disclosure.

[0019] Figure 3 This is a vertical cross-sectional view of a first exemplary structure following the patterning of a first layer of stepped regions on an alternating stack of first layers and the formation of a first layer of backward stepped dielectric material portions, according to a first embodiment of the present disclosure.

[0020] Figure 4A This is a vertical cross-sectional view of a first exemplary structure after the formation of a first layer of support column structure and an interlayer dielectric layer, according to a first embodiment of the present disclosure.

[0021] Figure 4B It is along Figure 4AA horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 4A The plane of the vertical cross-section.

[0022] Figure 5A This is a vertical cross-sectional view of a first exemplary structure after the formation of a first layer memory opening, according to a first embodiment of the present disclosure.

[0023] Figure 5B It is along Figure 5A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 5A The plane of the vertical cross-section.

[0024] Figure 6 This is a vertical cross-sectional view of a first exemplary structure after the formation of the sacrificial memory opening filling portion, according to a first embodiment of the present disclosure.

[0025] Figure 7 This is a first exemplary structural vertical cross-sectional view according to a first embodiment of the present disclosure, after the second layer of alternating stacking of the second insulating layer and the second spacer material layer, the second layer of stepped dielectric material portion, and the second insulating capping layer.

[0026] Figure 8A This is a vertical cross-sectional view of a first exemplary structure after the formation of a second layer dielectric support pillar and a drain selection layer shallow trench isolation structure according to a first embodiment of the present disclosure.

[0027] Figure 8B It is along Figure 8A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 8A The plane of the vertical cross-section.

[0028] Figure 9A This is a vertical cross-sectional view of a first exemplary structure after the formation of a memory opening, according to a first embodiment of the present disclosure.

[0029] Figure 9B It is along Figure 9A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 9A The plane of the vertical cross-section.

[0030] Figure 10A This is a vertical cross-sectional view of a first exemplary structure after the formation of a memory stack structure and a contact layer dielectric layer, according to a first embodiment of the present disclosure.

[0031] Figure 10B It is along Figure 10A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 10A The plane of the vertical cross-section.

[0032] Figure 11A This is a vertical cross-sectional view of a first exemplary structure after forming an opening through the memory hierarchy, according to a first embodiment of the present disclosure.

[0033] Figure 11B It is along Figure 11A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 11A The plane of the vertical cross-section.

[0034] Figure 12A This is a vertical cross-sectional view of a first exemplary structure after the formation of a dielectric filling material, according to a first embodiment of the present disclosure.

[0035] Figure 12B It is along Figure 12A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 12A The plane of the vertical cross-section.

[0036] Figure 13A This is a vertical cross-sectional view of a first exemplary structure after the formation of the rear contact groove, according to a first embodiment of the present disclosure.

[0037] Figure 13B It is along Figure 13A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 13A The plane of the vertical cross-section.

[0038] Figure 14A This is a vertical cross-sectional view of a first exemplary structure after the rear recess is formed by removing the spacer material layer, according to a first embodiment of the present disclosure.

[0039] Figure 14B It is along Figure 14A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 14A The plane of the vertical cross-section.

[0040] Figure 14C According to the first embodiment of this disclosure, along Figure 14B A vertical cross-sectional view of the first exemplary structure in the sawtooth vertical plane C-C'.

[0041] Figure 15AThis is a vertical cross-sectional view of a first exemplary structure after the formation of a conductive layer, an insulating spacer, and a rear contact via structure, according to a first embodiment of the present disclosure.

[0042] Figure 15B It is along Figure 15A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 15A The plane of the vertical cross-section.

[0043] Figure 15C According to the first embodiment of this disclosure, along Figure 15B A vertical cross-sectional view of the first exemplary structure in the sawtooth vertical plane C-C'.

[0044] Figure 16A This is a vertical cross-sectional view of a first exemplary structure after forming a through-memory layer via structure, a word line contact via structure, and an upper-level via structure according to a first embodiment of the present disclosure.

[0045] Figure 16B It is along Figure 16A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 16A The plane of the vertical cross-section.

[0046] Figure 16C According to the first embodiment of this disclosure, along Figure 16B A vertical cross-sectional view of the first exemplary structure in the sawtooth vertical plane C-C'.

[0047] Figure 17A This is a vertical cross-sectional view of a first exemplary structure after the formation of the upper-level line structure according to the first embodiment of this disclosure.

[0048] Figure 17B It is along Figure 17A A horizontal cross-sectional view of the first exemplary structure with horizontal plane B-B' in the diagram. The serrated vertical plane A-A' corresponds to... Figure 17A The vertical cross-sectional view of the plane. The patterns of the upper-level linear structure are superimposed in the shape of dashed lines.

[0049] Figure 17C According to the first embodiment of this disclosure, along Figure 17B A vertical cross-sectional view of the first exemplary structure in the sawtooth vertical plane C-C'.

[0050] Figure 17D This is a top view of a first exemplary structure according to a first embodiment of the present disclosure.

[0051] Figure 17E and 17FThis is a top view of an alternative exemplary structure according to a first embodiment of the present disclosure.

[0052] Figure 18 This is a vertical cross-sectional view of a second exemplary structure after forming a semiconductor device, a lower-level metal interconnect structure, and at least one lower-level dielectric layer, according to a second embodiment of the present disclosure.

[0053] Figure 19A This is a vertical cross-sectional view of a second exemplary structure formed after the formation of a through-hole structure and an upper-level metal interconnect structure according to a second embodiment of the present disclosure.

[0054] Figure 19B This is a cross-sectional plan view of a metal interconnect structure according to a second embodiment of the present disclosure.

[0055] Figure 20 This is a vertical cross-sectional view of a variant of a second exemplary structure following the formation of a semiconductor device, a lower-level metal interconnect structure, and at least one lower-level dielectric layer, according to a second embodiment of the present disclosure.

[0056] Figure 21 This is a vertical cross-sectional view of a variant of a second exemplary structure following the formation of a first layer structure including a sacrificial memory opening filling portion and a first layer support column structure, according to a second embodiment of the present disclosure.

[0057] Figure 22 This is a vertical cross-sectional view of a variation of the second exemplary structure after forming the second layer structure, memory stack structure, second layer support pillar structure, contact layer dielectric layer and rear contact trench according to the second embodiment of this disclosure.

[0058] Figure 23 This is a vertical cross-sectional view of a variant of a second exemplary structure after forming a through-hole structure in accordance with the second embodiment of the present disclosure.

[0059] Figure 24A This is a vertical cross-sectional view of a third exemplary structure according to a third embodiment of the present disclosure, after the formation of a first layer of alternating stacking, a first layer of support pillar structure, a sacrificial memory opening filling portion, and a sacrificial rear contact trench filling portion.

[0060] Figure 24B It is along Figure 24A A horizontal cross-sectional view of the third exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 24A The plane of the vertical cross-section.

[0061] Figure 25AThis is a vertical cross-sectional view of a third exemplary structure according to a third embodiment of the present disclosure, after the formation of a second layer of alternating stacking, a second layer of support pillar structure, a drain selection layer shallow trench structure, a memory opening, and a deep trench.

[0062] Figure 25B It is along Figure 25A A horizontal cross-sectional view of the third exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 25A The plane of the vertical cross-section.

[0063] Figure 26A This is a vertical cross-sectional view of a third exemplary structure after forming a memory stack structure and an insulating deep trench structure according to a third embodiment of the present disclosure.

[0064] Figure 26B It is along Figure 26A A horizontal cross-sectional view of the third exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 26A The plane of the vertical cross-section.

[0065] Figure 27A This is a vertical cross-sectional view of a third exemplary structure after the formation of the rear contact groove, according to a third embodiment of the present disclosure.

[0066] Figure 27B It is along Figure 27A A horizontal cross-sectional view of the third exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 27A The plane of the vertical cross-section.

[0067] Figure 28A This is a vertical cross-sectional view of a third exemplary structure after forming a laterally elongated contact through-hole structure according to a third embodiment of the present disclosure.

[0068] Figure 28B It is along Figure 28A A horizontal cross-sectional view of the third exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 28A The plane of the vertical cross-section.

[0069] Figure 29A This is a vertical cross-sectional view of a third exemplary structure after forming a through-hole structure in accordance with a third embodiment of the present disclosure.

[0070] Figure 29B It is along Figure 29A A horizontal cross-sectional view of the third exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 29A The plane of the vertical cross-section.

[0071] Figure 29C According to the third embodiment of this disclosure, along Figure 29B A vertical cross-sectional view of the third exemplary structure in the sawtooth vertical plane C-C'.

[0072] Figure 30 This is a vertical cross-sectional view of a third exemplary structure after the formation of an upper-level metal interconnect structure, according to a third embodiment of the present disclosure.

[0073] Figure 31A This is a vertical cross-sectional view of a variation of a third exemplary structure after the formation of an insulating deep trench structure according to a third embodiment of the present disclosure.

[0074] Figure 31B It is along Figure 31A A horizontal cross-sectional view of a variant of the third exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 31A The plane of the vertical cross-section.

[0075] Figure 32A This is a vertical cross-sectional view of a variation of a third exemplary structure following the formation of a memory stack structure, a laterally elongated contact via structure, and a through-memory layer via structure, according to a third embodiment of the present disclosure.

[0076] Figure 32B It is along Figure 32A A horizontal cross-sectional view of a variant of the third exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 32A The plane of the vertical cross-section.

[0077] Figure 33A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a first layer alternating stack, a second layer alternating stack, and a memory stack structure according to a fourth embodiment of the present disclosure.

[0078] Figure 33B It is along Figure 33A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 33A The plane of the vertical cross-section.

[0079] Figure 34A This is a horizontal cross-sectional view of a fourth exemplary structure after forming a through-memory level opening and a rear contact trench, according to a fourth embodiment of the present disclosure.

[0080] Figure 34B It is along Figure 34A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 34A The plane of the vertical cross-section.

[0081] Figure 35A This is a vertical cross-sectional view of a fourth exemplary structure after the deposition and patterning of the insulating liner layer according to a fourth embodiment of the present disclosure.

[0082] Figure 35B It is along Figure 35A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 35A The plane of the vertical cross-section.

[0083] Figure 36A This is a vertical cross-sectional view of a fourth exemplary structure after the rear recess has been formed, according to a fourth embodiment of the present disclosure.

[0084] Figure 36B It is along Figure 36A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 36A The plane of the vertical cross-section.

[0085] Figure 37A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a conductive layer, according to a fourth embodiment of the present disclosure.

[0086] Figure 37B It is along Figure 37A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 37A The plane of the vertical cross-section.

[0087] Figure 38A This is a vertical cross-sectional view of a fourth exemplary structure after forming an insulating deep trench structure and a laterally elongated contact via structure according to a fourth embodiment of the present disclosure.

[0088] Figure 38B It is along Figure 38A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 38A The plane of the vertical cross-section.

[0089] Figure 39A This is a vertical cross-sectional view of a fourth exemplary structure after forming a through-hole structure in accordance with a fourth embodiment of the present disclosure.

[0090] Figure 39B It is along Figure 39A A horizontal cross-sectional view of the fourth exemplary structure in the horizontal plane B-B'. The sawtooth vertical plane A-A' corresponds to... Figure 39A The plane of the vertical cross-section.

[0091] Figure 40 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of an upper-level metal interconnect structure, according to a fourth embodiment of the present disclosure.

[0092] Figure 41 This is a vertical cross-sectional view of a first variant of a fourth exemplary structure after the formation of a patterned insulating liner layer, according to a fourth embodiment of the present disclosure.

[0093] Figure 42 This is a vertical cross-sectional view of a first variant of a fourth exemplary structure following the formation of an insulating deep trench structure, a laterally elongated contact via structure, and a through-memory layer via structure, according to a fourth embodiment of the present disclosure.

[0094] Figure 43 This is a vertical cross-sectional view of a first variant of a fourth exemplary structure after the formation of an upper-level metal interconnect structure according to a fourth embodiment of the present disclosure.

[0095] Figure 44A This is a vertical cross-sectional view of a second variant of a fourth exemplary structure following the formation of a first layer alternating stack, a second layer alternating stack, a memory stack structure, and a drain selection layer shallow trench isolation structure, according to the fourth embodiment of this disclosure.

[0096] Figure 44B It is along Figure 44A A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 44A The plane of the vertical cross-section.

[0097] Figure 45A This is a vertical cross-sectional view of a second variant of the fourth exemplary structure after forming a through-memory level opening and a rear contact trench, according to the fourth embodiment of this disclosure.

[0098] Figure 45B It is along Figure 45A A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 45A The plane of the vertical cross-section.

[0099] Figure 46A This is a vertical cross-sectional view of a second variant of a fourth exemplary structure after replacing the sacrificial material layer with a conductive layer, according to a fourth embodiment of the present disclosure.

[0100] Figure 46B It is along Figure 46AA horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 46A The plane of the vertical cross-section.

[0101] Figure 47A This is a vertical cross-sectional view of a second variant of a fourth exemplary structure following the deposition of a conformal insulating layer and anisotropic etching, according to a fourth embodiment of the present disclosure, wherein the anisotropic etching removes a horizontal portion of the conformal insulating layer and deepens an opening through the memory hierarchy.

[0102] Figure 47B It is along Figure 47A A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 47A The plane of the vertical cross-section.

[0103] Figure 48A This is a vertical cross-sectional view of a second variant of a fourth exemplary structure after forming a laterally elongated contact via structure and a through-memory layer via structure, according to a fourth embodiment of the present disclosure.

[0104] Figure 48B It is along Figure 48A A horizontal cross-sectional view of the second variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 48A The plane of the vertical cross-section.

[0105] Figure 49 This is a vertical cross-sectional view of a second variant of a fourth exemplary structure after the formation of an upper-level metal interconnect structure, according to a fourth embodiment of the present disclosure.

[0106] Figure 50A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure following the formation of a first layer alternating stack, a second layer alternating stack, a memory stack structure, and a drain selection layer shallow trench isolation structure, according to the fourth embodiment of this disclosure.

[0107] Figure 50B It is along Figure 50A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 50A The plane of the vertical cross-section.

[0108] Figure 51A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure after forming an opening through the memory hierarchy, according to a fourth embodiment of the present disclosure.

[0109] Figure 51B It is along Figure 51AA horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 51A The plane of the vertical cross-section.

[0110] Figure 52A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure after replacing the sacrificial material layer with a conductive layer, according to a fourth embodiment of the present disclosure.

[0111] Figure 52B It is along Figure 52A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 52A The plane of the vertical cross-section.

[0112] Figure 53A This is a vertical cross-sectional view of a third variation of a fourth exemplary structure after the formation of an insulating liner, according to a fourth embodiment of the present disclosure.

[0113] Figure 53B It is along Figure 53A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 53A The plane of the vertical cross-section.

[0114] Figure 54A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure after forming a through-hole structure in accordance with the fourth embodiment of this disclosure.

[0115] Figure 54B It is along Figure 54A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 54A The plane of the vertical cross-section.

[0116] Figure 55A This is a vertical cross-sectional view of a third variant of a fourth exemplary structure following the formation of a laterally elongated contact via structure and an upper-level metal interconnect structure, according to a fourth embodiment of the present disclosure.

[0117] Figure 55B It is along Figure 55A A horizontal cross-sectional view of the third variant of the fourth exemplary structure, with horizontal plane B-B' in the middle. The serrated vertical plane A-A' corresponds to... Figure 55A The plane of the vertical cross-section.

[0118] Figure 56AThis is a vertical cross-sectional view of a fourth variant of a fourth exemplary structure after forming a memory stack structure and a laterally elongated contact via structure according to a fourth embodiment of the present disclosure.

[0119] Figure 56B It is along Figure 56A A horizontal cross-sectional view of the fourth variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 56A The plane of the vertical cross-section.

[0120] Figure 57A This is a vertical cross-sectional view of a fourth variant of a fourth exemplary structure after forming an opening through the memory hierarchy, according to a fourth embodiment of the present disclosure.

[0121] Figure 57B It is along Figure 57A A horizontal cross-sectional view of the fourth variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 57A The plane of the vertical cross-section.

[0122] Figure 58A This is a vertical cross-sectional view of a fourth variant of a fourth exemplary structure after the formation of an insulating liner, according to a fourth embodiment of the present disclosure.

[0123] Figure 58B It is along Figure 58A A horizontal cross-sectional view of the fourth variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 58A The plane of the vertical cross-section.

[0124] Figure 59A This is a vertical cross-sectional view of a fourth variant of a fourth exemplary structure after forming a through-hole structure and an upper-level metal interconnect structure according to a fourth embodiment of the present disclosure.

[0125] Figure 59B It is along Figure 59A A horizontal cross-sectional view of the fourth variant of the fourth exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 59A The plane of the vertical cross-section.

[0126] Figure 60 This is a horizontal cross-sectional view of a fifth variation of the fourth exemplary structure according to the fourth embodiment of this disclosure.

[0127] Figure 61A This is a vertical cross-sectional view of a second variant of a third exemplary structure after the formation of a memory stack structure according to a third embodiment of the present disclosure.

[0128] Figure 61B yes Figure 61A A horizontal cross-sectional view of the second variant of the third exemplary structure. The serrated vertical plane A-A' corresponds to... Figure 61A The plane of the vertical cross-section.

[0129] Figure 62A This is a vertical cross-sectional view of a second variant of a third exemplary structure after simultaneously forming a rear contact groove and a deep trench, according to a third embodiment of the present disclosure.

[0130] Figure 62B yes Figure 62A A horizontal cross-sectional view of the second variant of the third exemplary structure. The serrated vertical plane A-A' corresponds to... Figure 62A The plane of the vertical cross-section.

[0131] Figure 63A This is a vertical cross-sectional view of a second variant of a third exemplary structure after the formation of an upper-level line structure, according to a third embodiment of the present disclosure.

[0132] Figure 63B It is along Figure 63A A horizontal cross-sectional view of the second variant of the third exemplary structure in the horizontal plane B-B'. The serrated vertical plane A-A' corresponds to... Figure 63A The plane of the vertical cross-section.

[0133] Figure 63C According to the third embodiment of this disclosure, along Figure 63B A vertical cross-sectional view of a second variant of the third exemplary structure of the sawtooth vertical plane C-C' in the figure.

[0134] Figure 64 This is a vertical cross-sectional view of a third variant of a third exemplary structure after the formation of an upper-level line structure, according to a third embodiment of the present disclosure.

[0135] Figure 65A This is a vertical cross-sectional view of a sixth variant of a fourth exemplary structure after the formation of the sacrificial memory opening fill portion and the sacrificial deep trench fill portion, according to the fourth embodiment of this disclosure.

[0136] Figure 65B It is along Figure 65A A horizontal cross-sectional view of the sixth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 65A The plane of the vertical cross-section.

[0137] Figure 66A This is a vertical cross-sectional view of a sixth variant of a fourth exemplary structure after the formation of a memory stack structure and a pseudo memory stack structure according to the fourth embodiment of this disclosure.

[0138] Figure 66B It is along Figure 66A A horizontal cross-sectional view of the sixth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 66A The plane of the vertical cross-section.

[0139] Figure 67A This is a vertical cross-sectional view of a sixth variant of the fourth exemplary structure after the formation of the rear recess according to the fourth embodiment of this disclosure.

[0140] Figure 67B It is along Figure 67A A horizontal cross-sectional view of the sixth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 67A The plane of the vertical cross-section.

[0141] Figure 68A This is a vertical cross-sectional view of a sixth variant of a fourth exemplary structure following the formation of a conductive layer and a laterally elongated contact via structure according to a fourth embodiment of the present disclosure.

[0142] Figure 68B It is along Figure 68A A horizontal cross-sectional view of the sixth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 68A The plane of the vertical cross-section.

[0143] Figure 69A This is a vertical cross-sectional view of a sixth variant of a fourth exemplary structure following the formation of a through-hole structure and an upper-level metal interconnect structure according to a fourth embodiment of the present disclosure.

[0144] Figure 69B It is along Figure 69A A horizontal cross-sectional view of the sixth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 69A The plane of the vertical cross-section.

[0145] Figure 70A This is a vertical cross-sectional view of a seventh variant of a fourth exemplary structure after the formation of a memory stack structure and a contact layer dielectric layer, according to a fourth embodiment of the present disclosure.

[0146] Figure 70B It is along Figure 70A A horizontal cross-sectional view of the seventh variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 70A The plane of the vertical cross-section.

[0147] Figure 71A This is a vertical cross-sectional view of a seventh variant of the fourth exemplary structure according to the fourth embodiment of the present disclosure, after simultaneously forming a rear contact trench and a through-hole cavity through the memory layer.

[0148] Figure 71B It is along Figure 71A A horizontal cross-sectional view of the seventh variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 71A The plane of the vertical cross-section.

[0149] Figure 72A This is a vertical cross-sectional view of a seventh variant of the fourth exemplary structure according to the fourth embodiment of this disclosure, after the sacrificial material layer is replaced with a conductive layer.

[0150] Figure 72B It is along Figure 72A A horizontal cross-sectional view of the seventh variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 72A The plane of the vertical cross-section.

[0151] Figure 73A This is a vertical cross-sectional view of a seventh variant of a fourth exemplary structure following the formation of a laterally extending contact via structure and a through-memory stack via structure, according to a fourth embodiment of the present disclosure.

[0152] Figure 73B It is along Figure 73A A horizontal cross-sectional view of the seventh variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to... Figure 73A The plane of the vertical cross-section.

[0153] Figure 73C According to the fourth embodiment of this disclosure, along Figure 73B A vertical cross-sectional view of the seventh variant of the fourth exemplary structure of the sawtooth vertical plane C-C' in the figure.

[0154] Figure 74 This is a vertical cross-sectional view of a seventh variant of a fourth exemplary structure after the formation of an overmetal interconnect structure according to a fourth embodiment of the present disclosure.

[0155] Figure 75A This is a vertical cross-sectional view of an eighth variant of the fourth exemplary structure after forming a through-hole structure for a memory stack, according to the fourth embodiment of this disclosure.

[0156] Figure 75B It is along Figure 75A A horizontal cross-sectional view of the eighth variant of the fourth exemplary structure with horizontal plane B-B' in the figure. The serrated vertical plane A-A' corresponds to...Figure 75A The plane of the vertical cross-section.

[0157] Figure 76 This is a vertical cross-sectional view of an eighth variant of a fourth exemplary structure after the formation of an overmetal interconnect structure according to a fourth embodiment of the present disclosure. Detailed Implementation

[0158] As described above, this disclosure relates to three-dimensional non-volatile memory devices, such as vertical NAND strings and other three-dimensional devices, and methods for manufacturing the same, various aspects of which are described below. Embodiments of this disclosure can be used to form various semiconductor devices, such as three-dimensional monolithic memory array devices comprising multiple NAND memory strings. Drawings are not to scale. Multiple instances of an element may be replicated while illustrating a single instance of the element unless explicitly described or clearly indicated that a copy of the element does not exist.

[0159] Ordinal numbers such as "first," "second," and "third" are used only to identify similar elements and may be used differently in the specification and claims of this disclosure. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the surfaces of the second element, the first element is "directly located" "on" the second element. As used herein, a "processing" structure or a "temporary" structure refers to a structure that is subsequently modified.

[0160] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of horizontal planes of a continuous structure, either between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers above and / or below it.

[0161] As used herein, a “memory level” or “memory array level” refers to a level corresponding to the general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the topmost surface of the memory element array and a second horizontal plane that includes the bottommost surface of the memory element array. As used herein, a “through-memory level” element refers to an element that extends vertically through the memory level.

[0162] As used in this article, "semiconductor material" refers to a material with a density of 1.0 × 10⁻⁶. -6 S / cm up to 1.0×10 5Materials with electrical conductivity in the range of S / cm can be fabricated with conductivity from 1.0 S / cm to 1.0 × 10⁻⁶ when appropriately doped with electrical dopant. 5 Doped materials with electrical conductivity in the range of S / cm. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / cm. 5 Materials with a conductivity of S / cm. As used herein, "insulating material" or "dielectric material" refers to a conductivity less than 1.0 × 10⁻⁶. -6 Materials with S / cm. All conductivity measurements were performed under standard conditions.

[0163] A monolithic three-dimensional memory array is an array in which multiple memory levels are formed on a single substrate, such as a semiconductor wafer, without intermediate substrates. The term "monolithic" means that the layers of each level of the array are deposited directly on top of the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167 entitled "Three-Dimensional Structure Memory," a non-monolithic stacked memory has been constructed by forming memory levels on separate substrates and stacking the memory levels vertically. The substrate may be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed on separate substrates, this memory is not a true monolithic three-dimensional memory array. The substrate may include integrated circuits, such as driver circuitry for the memory device, fabricated thereon.

[0164] The various three-dimensional memory devices disclosed herein include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein. The monolithic three-dimensional NAND string is located in a monolithic three-dimensional array of NAND strings disposed above a substrate. At least one memory cell in a first device stage of the three-dimensional array of NAND strings is located on another memory cell in a second device stage of the three-dimensional array of NAND strings.

[0165] Reference Figure 1A and 1BThis illustration shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a semiconductor substrate 9 and a semiconductor device 710 formed thereon. A shallow trench isolation structure 720 may be formed on the semiconductor substrate 9 to provide electrical isolation between the semiconductor devices. For example, the semiconductor device 710 may include a field-effect transistor, which includes a corresponding source region 742, a drain region 744, a channel region 746, and a gate structure 750. The field-effect transistor may be arranged in a CMOS configuration. Each gate structure 750 may, for example, include a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor device may include any semiconductor circuitry to support the operation of a subsequently formed memory structure, commonly referred to as driver circuitry, also referred to as peripheral circuitry. As used herein, peripheral circuitry refers to any or all of word line decoder circuitry, word line switch circuitry, bit line decoder circuitry, bit line sensing and / or switching circuitry, power / distribution circuitry, data buffers, and latches, or any other semiconductor circuitry that may be implemented outside the memory array structure for the memory device. For example, a semiconductor device may include a word line switching device for electrically biasing word lines of a subsequently formed three-dimensional memory structure.

[0166] At least one dielectric layer is formed over the semiconductor device, referred herein as at least one lower-level dielectric layer 760. The at least one lower-level dielectric layer 760 may include, for example: an optional dielectric pad 762, such as a silicon nitride pad that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure; a planarizing dielectric layer 764, which is used to provide a planar surface coplanar with the top surface of the dielectric pad 762 or the top surface of the gate structure 750; an optional planar pad 766; and at least one lower-level interconnect dielectric layer 768, which collectively serve as a matrix of a lower-level metal interconnect structure 780, which provides electrical wiring between the various nodes of the semiconductor device and subsequently forms bonding pads for through-hole structures in the memory hierarchy. The lower-level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain or gate electrode contacts contacting corresponding source and drain nodes of the device), lower-level metal lines 784, lower-level via structures 786, and a lower-level top metal structure 788 configured as a bonding pad for a subsequently formed through-memory-level via structure. The region of the semiconductor device and the combination of at least one lower-level dielectric layer 760 and the lower-level metal interconnect structure 780 are referred to herein as a lower-level peripheral device region 700, which is located below the subsequently formed memory-level assembly and includes peripheral devices for the memory-level assembly. The lower-level metal interconnect structure 780 is embedded in at least one lower-level dielectric layer 760. In one embodiment, the top surface of the lower-level top metal structure 788 may be located at or below a horizontal plane including the top surface of at least one lower-level dielectric layer 760.

[0167] The lower-level metal interconnect structure 780 can be electrically shorted to a node (e.g., source 742, drain 744, or gate electrode 750) of the semiconductor device 710 (e.g., a CMOS device), and is located at the level of at least one lower-level dielectric layer 760. Through-hole structure (through memory layer) Figure 1A and 1B (Not shown) can then be formed directly on the lower-level metal interconnect structure 780. In one embodiment, the pattern of the lower-level metal interconnect structure 780 can be selected such that the topmost lower-level metal structure 788 (which is a subset of the topmost lower-level metal interconnect structures 780) can provide a bonding pad structure within the through-memory-level via region 400. The through-memory-level via region 400 is the region in which the through-memory-level via structure extending vertically through the memory-level via assembly is subsequently formed.

[0168] like Figure 1BAs shown, the through-memory level via region 400 may be located adjacent to the memory array region 100 in which the memory device array is subsequently formed. The word line contact via region 200 may be located adjacent to the through-memory level via region 400 and the memory array region 100. In one embodiment, the through-memory level via region 400 and the word line contact via region 200 may be located at the peripheral edge of the memory array region 100, which is perpendicular to a first horizontal direction h1 (e.g., the word line direction) and parallel to a second horizontal direction hd2 (e.g., the bit line direction). In one embodiment, the region of the first exemplary structure may be divided into multiple blocks (B1, B2, B3...) that are laterally separated along the second horizontal direction hd2 and can be mapped one-to-one with positive integers, i.e., indexed by positive integers. The same word line in a given device level may be used as the control gate electrode for each memory cell in the same device level within each corresponding memory block.

[0169] Multiple instances of the through-hole region 400 and the word line contact region 200 can alternate along the second horizontal direction hd2. In an illustrative example, each instance of the through-hole region 400 can be located within the region of a corresponding even-numbered block (e.g., B2, B4, etc.), and each instance of the word line contact via region 200 can be located within the region of a corresponding odd-numbered block (e.g., B1, B3, etc.). Adjacent pairs of odd and even blocks (e.g., B1 and B2) can be repeated periodically along the second horizontal direction.

[0170] Although a specific pattern for the lower-level top metal structure 788 is shown here, it should be understood that the pattern of the lower-level top metal structure 788 can be changed to optimize the wiring in the lower-level peripheral device region 700, provided that the lower-level top metal structure 788 provides a suitable bonding pad area for the subsequently formed through-memory layer via structure.

[0171] Reference Figure 2 Optional planar conductive material layer 6 and planar semiconductor material layer 10 can be formed on the underlying peripheral device region 700. Optional planar conductive material layer 6 includes a conductive material, such as a metal or heavily doped semiconductor material. For example, optional planar conductive material layer 6 may include a tungsten layer having a thickness in the range of 3 nm to 100 nm, but smaller and larger thicknesses are also possible. A metal nitride layer (not shown) may be provided on top of planar conductive material layer 6 as a diffusion barrier layer. Layer 6 can be used as a special source line in the finished device. Alternatively, layer 6 may include an etch stop layer and may include any suitable conductive, semiconductor, or insulating layer.

[0172] A planar semiconductor material layer 10 may be formed on at least one underlying dielectric layer 760. The planar semiconductor material layer 10 includes a semiconductor material, which may include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, and / or other semiconductor materials known in the art. In one embodiment, the planar semiconductor material layer 10 may include a polycrystalline semiconductor material (e.g., polycrystalline silicon) or an amorphous semiconductor material (e.g., amorphous silicon) that is converted to a polycrystalline semiconductor material in a subsequent processing step (e.g., an annealing step). The planar semiconductor material layer 10 may be formed directly over a subset of semiconductor devices on a semiconductor substrate 9 (e.g., a silicon wafer). As used herein, the first element is considered "directly above" the second element if the first element is located above a horizontal plane including the topmost surface of the second element and the regions of the first and second elements have overlapping areas in a planar view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 9). In one embodiment, the planar semiconductor material layer 10 or a portion thereof may be doped with an electrical dopant, which may be a p-type dopant or an n-type dopant. The conductivity type of the dopants in the planar semiconductor material layer 10 is referred to herein as the first conductivity type. A dielectric pad layer 52 may be formed on the top surface of the planar semiconductor material layer 10.

[0173] Subsequently, alternating stacks of first and second material layers are formed. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least one other alternating stack of material layers is subsequently formed over the alternating stack of first and second material layers, the alternating stack is referred to herein as a first-layer alternating stack. The hierarchy of the first-layer alternating stack is referred to herein as a first-layer hierarchy, and the hierarchy of the alternating stack subsequently formed directly over the first-layer hierarchy is referred to herein as a second-layer hierarchy, and so on.

[0174] The first alternating stack of layers may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although this disclosure has described with reference to embodiments in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thus avoiding the need to perform a replacement process) are explicitly covered herein.

[0175] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. A plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the planar semiconductor material layer 10. As used herein, "sacrificial material" refers to material that is removed during subsequent processing steps.

[0176] As used herein, alternating stacking of first and second elements refers to a structure in which instances of first and second elements alternate. Each instance of a first element in a plurality of non-alternating end elements is adjacent to two instances of a second element on both sides, and each instance of a second element in a plurality of non-alternating end elements is adjacent to two instances of a first element on both sides. The first elements may have the same thickness or may have different thicknesses. The second elements may have the same thickness or may have different thicknesses. Alternating layers of first and second material may begin with an instance of a first material layer or an instance of a second material layer, and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, instances of first and second elements may be formed in alternating layers of periodically repeating units.

[0177] The first alternating stack (132, 142) may include a first insulating layer 132 made of a first material and a first sacrificial material layer 142 made of a second material different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high k) dielectric oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, dielectric metal oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0178] The second material of the first sacrificial material layer 142 is a sacrificial material that can be selectively removed from the first material of the first insulating layer 132. As used herein, the removal of the first material is “selective” for the second material if the removal process removes the first material at a rate at least twice that of removing the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the removal process of the first material relative to the second material.

[0179] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. A second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may, for example, be used as a control gate electrode for a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride.

[0180] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. For example, the first material of the first insulating layer 132 may be deposited by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0181] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 can range from 20 nm to 50 nm, but smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the paired first insulating layer 132 and first sacrificial material layer 142 can range from 2 to 1024, and is typically from 8 to 256, but more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the alternating stack of first layers (132, 142) can have a uniform thickness that remains substantially constant within each respective first sacrificial material layer 142.

[0182] A first insulating capping layer 170 is then formed over the stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the insulating capping layer 170 can range from 20 nm to 300 nm, although smaller and larger thicknesses are also possible.

[0183] Reference Figure 3The first insulating capping layer 170 and the alternating stacked first layers (132, 142) can be patterned to form a first stepped surface in each through-memory level via region 400 and each word line contact via region 200. Each through-memory level via region 400 and word line contact via region 200 may include a corresponding first stepped region SA1 in which the first stepped surface is formed and a second stepped region SA2 in which additional stepped surfaces will subsequently be formed in a second layer structure (which is subsequently formed over the first layer structure) and / or an additional layer structure. For example, the first stepped surface can be formed by forming a mask layer with openings therein, etching cavities within the layer of the first insulating capping layer 170, and repeatedly extending the etched area and vertically recessing the cavities by etching each pair of first insulating layers 132 and first sacrificial material layers 142, with the first sacrificial material layers 142 located directly below the bottom surface of the etched cavities within the etched area. A dielectric material can be deposited to fill the first stepped cavity to form a first backward-stepped dielectric material portion 165. As used herein, a "backward-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with the vertical distance from the top surface of the substrate on which the element is situated. The alternating stack of the first layers (132, 142) and the first backward-stepped dielectric material portion 165 together constitute the first layer structure, which is the structure in a subsequently modified process.

[0184] Reference Figure 4A and 4B The first-layer support pillar structure 171 can be formed in the portion of the first alternating stack (132, 142) where the memory stack structure is not formed at a sufficiently high density in subsequent processing steps. For example, the first-layer support pillar structure 171 can be formed in the through-hole region 400 and the word line contact through-hole region 200 of the memory layer. For example, the first-layer support pillar structure 171 can be formed by forming through-hole cavities through the first alternating stack (132, 142) and filling the through-hole cavities with a dielectric material such as silicon oxide and / or a dielectric metal oxide (such as aluminum oxide). The position of the step S in the first alternating stack (132, 142) is... Figure 4B The line shown in the middle is a dashed line.

[0185] Optionally, the interlayer dielectric layer 180 can be deposited on top of the first layer structure (132, 142, 165, 170). The interlayer dielectric layer 180 comprises a dielectric material such as silicon oxide. The thickness of the interlayer dielectric layer 180 can range from 30 nm to 300 nm, although smaller and larger thicknesses are also possible.

[0186] Reference Figure 5A and 5BA first-layer memory opening 149 is formed by a first alternating stack (132, 142) extending at least to the top surface of the planar semiconductor material layer 10. The first-layer memory opening 149 can be formed in the memory array region 100 at a location where a memory stack structure comprising a vertical stack of memory elements will subsequently be formed. For example, a photolithographic material stack (not shown) including at least one photoresist layer can be formed over a first insulating cap layer 170 (and optionally layer 180), and photolithographic patterning can be performed to form an opening within the photolithographic material stack. The pattern in the photolithographic material stack can be transferred through the first insulating cap layer 170 (and optionally layer 180) and across the entire first alternating stack (132, 142) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. A portion of the first insulating cap layer 170 (and optionally layer 180) and the first alternating stack (132, 142) below the opening in the patterned photolithographic material stack is etched to form the first-layer memory opening 149. In other words, the pattern in the patterned photolithography material stack forms the first memory opening 149 by the transfer of the first insulating capping layer 170 and the first layer of alternating stacks (132, 142).

[0187] In one embodiment, the chemistry of the anisotropic etching process used to etch the materials through the alternating stacks of the first layers (132, 142) can be alternated to optimize the etching of the first and second materials in the alternating stacks of the first layers (132, 142). For example, the anisotropic etching can be a series of reactive ion etchings or a single etching (e.g., CF4 / O2 / Ar etching). The sidewalls of the first layer memory opening 149 can be substantially vertical or can be tapered. Subsequently, for example, the patterned photolithographic material stack can be removed by ashing.

[0188] Optionally, a portion of the first layer memory opening 149 at the level of the interlayer dielectric layer 180 can be laterally extended by isotropic etching. For example, if the interlayer dielectric layer 180 comprises a dielectric material (such as borosilicate glass) having a greater etch rate than the first insulating layer 132 (which may comprise undoped silicate glass), isotropic etching (such as wet etching using HF) can be used to enlarge the lateral dimension of the first layer memory opening at the level of the interlayer dielectric layer 180. The portion of the first layer memory opening 149 at the level of the interlayer dielectric layer 180 can optionally be widened to provide a larger bonding pad for subsequently forming a second layer memory opening through alternating stacking of second layers (which is then formed prior to the formation of the second layer memory opening).

[0189] A sacrificial memory opening fill portion 131 may be formed in the first memory opening 149. For example, a sacrificial fill material layer is deposited in the first memory opening 149. The sacrificial fill material layer includes a sacrificial material that can subsequently be selectively removed from the materials of the first insulating layer 132 and the first sacrificial material layer 142. In one embodiment, the sacrificial fill material layer may include a semiconductor material, such as silicon (e.g., a-Si or polycrystalline silicon), a silicon-germanium alloy, germanium, III-V compound semiconductor materials, or combinations thereof. Optionally, a thin etch stop layer (e.g., a silicon oxide layer with a thickness in the range of 1 nm to 3 nm) may be employed prior to the deposition of the sacrificial fill material layer. The sacrificial fill material layer may be formed by non-conformal deposition or conformal deposition methods. In another embodiment, the sacrificial fill material layer may include amorphous silicon or carbon-containing materials (e.g., amorphous carbon or diamond-like carbon) that can subsequently be removed by ashing.

[0190] A portion of the deposited sacrificial material can be removed from the first insulating capping layer 170 (and optionally layer 180, if present). For example, the sacrificial filler layer can be planarized and recessed into the top surface of the first insulating capping layer 170 (and optionally layer 180, if present). The planarization process can include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the first insulating layer 170 (and optionally layer 180, if present) can be used as an etch stop layer or a planarization stop layer. Each remaining portion of the sacrificial material in the first memory opening 149 constitutes a sacrificial memory opening fill portion 131. The top surface of the sacrificial memory opening fill portion 131 can be coplanar with the top surface of the interlayer dielectric layer 180. The sacrificial memory opening fill portion 131 may or may not include cavities therein.

[0191] Reference Figure 7 A second layer structure can be formed on the first layer structure (132, 142, 170, 131). The second layer structure may include additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may then be formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes alternating third and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0192] In one embodiment, the third material layer may be the second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third and fourth material layers may be the second insulating layer 232 and the second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that can be selectively removed from the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode that can, for example, be used as a control gate electrode for a vertical NAND device.

[0193] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include alternating plurality of second insulating layers 232 and second sacrificial material layers 242. For example, a third material for the second insulating layer 232 may be deposited by chemical vapor deposition (CVD). For example, a fourth material for the second sacrificial material layer 242 may be formed by CVD or atomic layer deposition (ALD).

[0194] The third material of the second insulating layer 232 can be at least one insulating material. The insulating material that can be used in the second insulating layer 232 can be any material that can be used in the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be selectively removed from the third material of the second sacrificial material layer 242. The sacrificial material that can be used in the second sacrificial material layer 242 can be any material that can be used in the first sacrificial material layer 142. In one embodiment, the second insulating material can be the same as the first insulating material, and the second sacrificial material can be the same as the first sacrificial material.

[0195] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can range from 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the paired second insulating layer 232 and second sacrificial material layer 242 can range from 2 to 1024, and is typically from 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) can have a uniform thickness that remains substantially constant within each respective second sacrificial material layer 242.

[0196] Using the same set of processing steps as those used to form the first stepped surface in the first stepped region SA1, and with appropriate adjustment of the pattern of at least one mask layer, a second stepped surface in the second stepped region SA2 can be formed in the through-memory via region 400 and the word line contact via region 200. A second layer of backward stepped dielectric material portion 265 can be formed above the second stepped surface in the through-memory via region 400 and the word line contact via region 200.

[0197] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242). The second insulating capping layer 270 comprises a dielectric material different from that of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may comprise silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) may comprise silicon nitride.

[0198] Generally, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed on the planar semiconductor material layer 10, and at least one backward-stepped dielectric material portion (165, 265) can be formed above the stepped region on at least one alternating stack (132, 142, 232, 242).

[0199] Reference Figure 8A and 8B The second support pillar structure 271 can be formed in the portion of the second alternating stack (132, 142) covering the first support pillar structure 171. For example, the second support pillar structure 271 can be formed directly on the top surface of the first support pillar structure 171 in the through-hole region 400 and the word line contact through-hole region 200. For example, the second support pillar structure 271 can be formed by forming through-hole cavities through the second alternating stack (232, 242) and filling the through-hole cavities with a dielectric material such as silicon oxide and / or a dielectric metal oxide (such as aluminum oxide).

[0200] Optionally, the drain-selection layer shallow trench isolation structure 72 can be formed by a subset of layers in the upper part of the second alternating stack (232, 242). The second sacrificial material layer 242 cut by the selected drain-selection layer shallow trench isolation structure 72 corresponds to the layer in which the drain-selection layer conductive layer is subsequently formed. The drain-selection layer shallow trench isolation structure 72 divides the block (B1, B2, B3...) into multiple sub-blocks along the first horizontal direction hd1. The drain-selection layer shallow trench isolation structure 72 includes a dielectric material such as silicon oxide. The position of the step S in the first alternating stack (132, 142) and the second alternating stack (232, 242) is... Figure 8BThe steps are shown as dashed lines. The stepped regions in the first, second, and third memory blocks rise in the same diagonal direction (e.g., from left to right).

[0201] Reference Figure 9A and 9B A second-layer memory opening extending through the second-layer structure (232, 242, 270) is formed in the region covering the sacrificial memory opening filling portion 131. A photoresist layer can be applied to the second-layer structure (232, 242, 270) and can be photolithographically patterned to form the same pattern as the pattern of the sacrificial memory opening filling portion 131 (i.e., the pattern of the first-layer memory opening). A photolithographic mask used for patterning the first-layer memory opening 149 can be used to pattern the second-layer memory opening. Anisotropic etching can be performed to transfer the pattern of the photolithographically patterned photoresist layer through the second-layer structure (232, 242, 270). In one embodiment, the chemistry of the anisotropic etching process for etching the material through the alternating stack of the second layers (232, 242) can be alternated to optimize the etching of the alternating material layers in the alternating stack of the second layers (232, 242). For example, the anisotropic etching can be a series of reactive ion etchings. For example, the patterned photolithographic material stack can be removed by ashing after the anisotropic etching process.

[0202] The top surface of the lower sacrificial memory opening fill portion 131 can be physically exposed at the bottom of each second-layer memory opening. After the top surface of the sacrificial memory opening fill portion 131 is physically exposed, an etching process can be performed that selectively removes the sacrificial material (e.g., C4F8 / O2 / Ar etching) of the sacrificial memory opening fill portion 131 from the material of the alternating stacked second layers (232, 242) and the alternating stacked first layers (132, 142).

[0203] When the sacrificial memory opening fill portion 131 is removed, each vertically adjacent pair of second-layer memory openings and first-layer memory openings 149 forms a continuous cavity extending through the alternating stacks of first and second layers (132, 142). This continuous cavity is referred to herein as memory opening 49. The top surface of the planar semiconductor material layer 10 may be physically exposed at the bottom of each memory opening 49.

[0204] Reference Figure 10A and 10BThe base channel portion 11 can optionally be formed at the bottom of each memory opening 49 by a selective semiconductor deposition process. Selective semiconductor deposition grows semiconductor material only from the semiconductor surface (i.e., the physically exposed surface of the planar semiconductor material layer 10) and suppresses semiconductor material growth from the insulator surface. During the selective semiconductor deposition process, reactants (such as silanes, dichlorosilanes, trichlorosilanes, dichlorosilanes, etc.) can flow into the deposition chamber simultaneously or alternately with an etchant (such as hydrogen chloride). Since the semiconductor material is deposited at a higher deposition rate on the semiconductor surface than on the insulator surface, selective growth can be achieved by setting an etch rate between the deposition rate of the semiconductor material on the semiconductor surface and the deposition rate of the semiconductor material on the insulator surface. In one embodiment, the top surface of the base channel portion 11 can extend through a source selection level in which a source selection level conductive layer can subsequently be formed.

[0205] Memory stack structures 55 may be formed in memory openings 49. In an illustrative example, each memory stack structure 55 may include a memory film 50, a vertical semiconductor channel 60, and an optional dielectric core 62. In one embodiment, each memory film 50 may include an optional barrier dielectric layer 51, a memory material layer 54, and a tunneling dielectric layer 56, as shown in the illustration. In one embodiment, each vertical semiconductor channel 60 may include a first semiconductor channel 601 and a second semiconductor channel 602. Although the memory opening 49 and support opening for the first layer support pillar structure 171 are shown as... Figure 5A and 4A In one embodiment, the memory opening 49 and the support opening for the first layer pillar structure 171 are formed in separate steps, but in another embodiment, the memory opening 49 and the support opening are formed in the same step. In this embodiment, while the memory stack structure 55 is formed in the memory opening 49, the first layer support pillar structure 171, including a pseudo memory stack structure without electrical connections to bit lines, can be formed in the support opening.

[0206] The barrier dielectric layer 51 includes a barrier dielectric layer material, such as silicon oxide, a dielectric metal oxide (e.g., aluminum oxide), or a combination thereof. Alternatively, the barrier dielectric layer 51 may be omitted during this processing step, and alternatively may be formed by a back recess, as will be described in more detail below. In one embodiment, the memory material layer 54 may be a charge-trapping material including a dielectric charge-trapping material, which may be, for example, silicon nitride.

[0207] The memory material layer 54 may be formed as a single memory material layer of uniform composition, or may comprise a stack of multiple memory material layers. If used, the multiple memory material layers may comprise multiple spaced-apart floating gate material layers comprising conductive materials (e.g., metals such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof) and / or semiconductor materials (e.g., polycrystalline or amorphous semiconductor materials comprising at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or additionally, the memory material layer 54 may comprise an insulating charge-trapping material, such as one or more silicon nitride portions. Alternatively, the memory material layer 54 may comprise conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 can range from 2nm to 20nm, although smaller and larger thicknesses are also possible.

[0208] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Depending on the operational pattern of the monolithic three-dimensional NAND string memory device to be formed, charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly referred to as an ONO stack. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, although smaller and larger thicknesses are also possible.

[0209] A first semiconductor channel layer can be deposited on the memory film 50 using a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer can range from 2 nm to 10 nm, although smaller and larger thicknesses are also possible. The first semiconductor channel layer and the memory film 50 can be anisotropically etched to remove their horizontal portions. The horizontal bottom of each memory film 50 can be removed from the bottom of each memory opening. Each remaining portion of the first semiconductor channel layer constitutes a first semiconductor channel 601. The first semiconductor channel can include a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel 601 can include amorphous silicon or polycrystalline silicon.

[0210] The second semiconductor channel layer may be deposited on the first semiconductor channel 601 (i.e., the remaining vertical portion of the first semiconductor channel layer) and on the top surface of the epitaxial channel portion 11 (or, in the absence of the epitaxial channel portion 11, the substrate semiconductor layer 10). The second semiconductor channel layer comprises a semiconductor material, which may be any semiconductor material that can be used in the first semiconductor channel layer. Both the first and second semiconductor channel layers may be doped with a first conductivity type (i.e., the same conductivity type as the substrate semiconductor layer 10) or may be substantially intrinsic, i.e., having a conductivity not exceeding 1.0 × 10⁻⁶. 17 / cm 3 The dopant concentration. In one embodiment, the second semiconductor channel layer may comprise amorphous silicon or polycrystalline silicon. The thickness of the second semiconductor channel layer may range from 2 nm to 10 nm, although smaller and larger thicknesses are also possible.

[0211] Dielectric material can be deposited in the cavity surrounded by the second semiconductor channel layer and subsequently recessed below the top surface of the second insulating capping layer 270. Each remaining portion of the dielectric material in the memory opening constitutes a dielectric core 62. A doped semiconductor material having a second conductivity type (opposite to the first conductivity type) can be deposited on the dielectric core 62 and within the cavity in the memory opening to form a drain region 63. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from above the top surface of the second insulating capping layer 270, for example by chemical mechanical planarization (CMP) or recess etching, to form the drain region 63. Each remaining portion of the second semiconductor channel layer constitutes a second semiconductor channel 602. The combination of the first semiconductor channel 601 and the second semiconductor channel 602 within the memory opening constitutes a vertical semiconductor channel 60.

[0212] Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60 of a corresponding horizontal channel within an adjacent planar semiconductor material layer 10. Each memory film 50 may include a barrier dielectric layer 51 contacting a sidewall of a memory opening, a plurality of charge storage regions located on the inner sidewall of the barrier dielectric layer 51 (embodied as portions of the memory material layer 54 at each level of the sacrificial material layers (142, 242)), and a tunneling dielectric layer 56 located within the plurality of charge storage regions.

[0213] The first layer structure (132, 142, 170, 165, 171), the second layer structure (232, 242, 270, 265, 271), the interlayer dielectric layer 180, and the memory stack structure 55 together constitute a memory layer assembly. The memory layer assembly is formed above the planar semiconductor material layer 10, such that the planar semiconductor material layer 10 includes horizontal semiconductor channels electrically connected to the vertical semiconductor channels 60 within the memory stack structure 55.

[0214] A first contact level dielectric layer 280 can be formed on the memory level assembly. The first contact level dielectric layer 280 is formed on the contact level, and various contact via structures are subsequently formed through this contact level to the drain region 63 and various conductive layers that replace the sacrificial material layers (142, 242) in subsequent processing steps.

[0215] Reference Figure 11A and 11B A through-memory level opening 769 can be formed in each through-memory level via region 400 by means of a memory level component. For example, the through-memory level opening 769 extending through the memory level component can be formed in a region of the second step region. The through-memory level opening 769 can be formed, for example, by applying a photoresist layer 767 on a first contact level dielectric layer 280; photolithographically patterning the photoresist layer 767 to form an opening in each through-memory level via region 400; and anisotropically etching portions of the first contact level dielectric layer 280 and the memory level component located below the opening in the photoresist layer. In one embodiment, the area of ​​each opening may include a major portion (i.e., more than 50%) of the total area of ​​the corresponding through-memory level via region 400.

[0216] The through-memory level opening 769 is formed only in the through-memory level via region 400, and not in the word line contact via region 200 or the memory array region 100. The regions in the word line contact via region 200 or the memory array region 100 are covered by a mask layer (such as a patterned photoresist layer 767).

[0217] The through-memory level opening 769 may extend through the entire memory level assembly, the planar semiconductor material layer 10, the optional planar conductive material layer 6, and into at least one lower-level dielectric material layer 760. In one embodiment, the bottom surface of each through-memory level opening 769 may be located above the top surface of the lower-level metal interconnect structure 780. Alternatively, the top surface of the lower-level metal interconnect structure 780 may be physically exposed in the through-memory level opening 769. In one embodiment, the through-memory level opening 769 may include a substantially vertical sidewall extending through the memory level assembly and the planar semiconductor material layer 10. As used herein, a sidewall is “substantially vertical” if it is vertical or deviates from a vertical plane by an angle of less than 5 degrees.

[0218] Reference Figure 12A and 12B For example, dielectric filler portions 430 are formed within each through-memory level opening 769 by depositing dielectric filler material and removing excess dielectric filler material from a horizontal plane including the top surface of the first contact level dielectric layer 280. The dielectric filler portions 430 include dielectric materials such as undoped silicate glass (e.g., silicon oxide), doped silicate glass, or spin-coated glass (SOG). The dielectric filler material can be deposited by conformal deposition, a combination of non-conformal deposition and reflow material, or spin-coating. Excess dielectric filler material can be removed by recess etching, chemical mechanical planarization (CMP), or a combination thereof.

[0219] Reference Figure 13A and 13B Subsequently, a rear contact trench 79 is formed through the first contact-level dielectric layer 280 and the memory-level assembly. For example, a photoresist layer can be photolithographically patterned on the first contact-level dielectric layer 280 to form an elongated opening extending along a first horizontal direction hd1. A subset of the openings in the patterned photoresist layer falls on the boundaries between blocks (B0, B1, B2, B3...). Anisotropic etching is performed to transfer the pattern in the patterned photoresist layer through the first contact-level dielectric layer 280 and the memory-level assembly to the top surface of the planar semiconductor material layer 10. The photoresist layer can then be removed, for example, by ashing.

[0220] The rear contact trench 79 extends along the first horizontal direction hd1 and thus elongates along the first horizontal direction hd1. The rear contact trench 79 includes a first subset of the rear contact trenches 79 that extends through the memory array region 100, adjacent to the word line contact via region 200, and adjacent to the through memory hierarchy via region 400. The first subset 79 of the rear contact trenches is formed by a memory hierarchy assembly that extends laterally along the first horizontal direction hd1 and laterally divides the memory hierarchy assembly (which typically includes at least one alternating stack (132, 142, 232, 242)) into a plurality of laterally spaced blocks (B0, B1, B2, B3...).

[0221] Each block (B0, B1, B2, B3...) includes a corresponding portion of the memory array region between adjacent pairs of rear contact trenches 79 in a first subset of the rear contact trenches 79. Each block (B0, B1, B2, B3...) may include a corresponding portion of the memory array region 100, a stepped region located at one longitudinal end of the corresponding portion of the memory array region 100 and including a word line contact via region 200, and another stepped region located at the other longitudinal end of the corresponding portion of the memory array region 100 and including a through-memory hierarchical via region 400. In one embodiment, the placement of the word line contact via regions 200 along consecutive blocks (B0, B1, B2, B3...) may alternate between two opposite sides. In an illustrative example, each odd-numbered block (B1, B3, etc.) has a corresponding word line contact via region 200 on one side (e.g., the left side), and each even-numbered block (B2, B4, etc.) has a corresponding word line contact via region 200 on the opposite side (e.g., the right side). Similarly, the through-memory level via region 400 can be placed alternately on two opposite sides along a continuous block (B0, B1, B2, B3...) such that the through-memory level via region 400 does not overlap with the word line contact via region 200. In the illustrative example, each even-numbered block (B0, B2, B4, etc.) has a corresponding through-memory level via region 400 on one side (e.g., the left side), and each odd-numbered block (B1, B3, etc.) has a corresponding word line contact via region 200 on the opposite side (e.g., the right side).

[0222] In the illustrative example, multiple blocks may include a set of three adjacent blocks (e.g., B1, B2, B3), which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The first block B1, the second block B2, and the third block B3 may each include a first stepped region (e.g., Figure 10B The area where the word line contacts the via area 200 on the left side of block B1 shown), and the second step area (e.g.) Figure 10BThe region shown is the through-memory level via region 400 on the left side of block B2, and the third step region is the word line contact via region 200 on the left side of block B3. As described above, adjacent pairs of odd and even blocks (such as B1 and B2) can be periodically repeated along the second horizontal direction.

[0223] Optionally, a second subset of the back contact trench 79 may be provided within each block (B0, B1, B2, B3...). If adopted, the second subset of the back contact trench 79 may extend along a first horizontal direction hd1 and may be positioned to appropriately divide each block into multiple sub-blocks. The back contact trench 79 may include sub-block boundaries within each memory block. The back contact trench 79 may be discontinuous to allow the same word line to extend in a connection region 778 between two adjacent sub-blocks in the same block. If a drain contact hierarchy shallow trench isolation structure 72 is employed, the drain contact hierarchy shallow trench isolation structure 72 may extend along the first horizontal direction hd1 to separate a subset of layers in the upper portion of the second layer alternating stack (232, 242) within each sub-block or within each block. Various design optimizations may be employed to divide the block into sub-blocks or dependent cells.

[0224] Reference Figures 14A-14C An etchant can be introduced into the rear contact trench 79 to selectively etch the materials of the first and second sacrificial material layers (142, 242) relative to the materials of the first and second insulating layers (132, 232), the first and second insulating cap layers (142, 242), and the outermost layer of the memory film 50, for example, using an isotropic etching process. A first rear recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. A second rear recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed. In one embodiment, the first and second sacrificial material layers (142, 242) may comprise silicon nitride, and the materials of the first and second insulating layers (132, 232) may be silicon oxide. In another embodiment, the first and second sacrificial material layers (142, 242) may comprise semiconductor materials, such as germanium or a silicon-germanium alloy, and the materials of the first and second insulating layers (132, 232) may be selected from silicon oxide and silicon nitride.

[0225] The isotropic etching process can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process, wherein the etchant is introduced into the back contact trench 79 in a vapor phase. For example, if the first and second sacrificial material layers (142, 242) comprise silicon nitride, the etching process can be a wet etching process, wherein the exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which is selective for silicon oxide, silicon, and various other materials used in the art. In cases where the sacrificial material layers (142, 242) comprise semiconductor materials, a wet etching process (which may employ a wet etchant such as a KOH solution) or a dry etching process (which may include vapor-phase HCl) can be used.

[0226] Each of the first and second rear recesses (143, 243) may be a laterally extending cavity having a lateral dimension greater than the vertical dimension of the cavity. In other words, the lateral dimension of each of the first and second rear recesses (143, 243) may be greater than the height of the corresponding rear recess (143, 243). A plurality of first rear recesses 143 may be formed in the volume from which material is removed from the first sacrificial material layer 142. A plurality of second rear recesses 243 may be formed in the volume from which material is removed from the second sacrificial material layer 242. Each of the first and second rear recesses (143, 243) may extend substantially parallel to the top surface of the substrate 9. The rear recesses (143, 243) may be vertically limited by the top surface of the lower insulating layer (132 or 232) and the bottom surface of the upper insulating layer (132 or 232). In one embodiment, each of the first and second rear recesses (143, 243) may have a uniform height.

[0227] In one embodiment, after the first and second sacrificial material layers (142, 242) are removed, the sidewall surface of each base channel portion 11 can be physically exposed in each bottommost first rear recess 143. Furthermore, the top surface of the planar semiconductor material layer 10 can be physically exposed at the bottom of each rear contact trench 79. An annular dielectric spacer 116 can be formed around each base channel portion 11 by oxidizing the physically exposed peripheral portions of the base channel portions 11. Additionally, a semiconductor oxide portion 616 can be formed from each physically exposed surface portion of the planar semiconductor material layer 10 simultaneously with the formation of the annular dielectric spacer 116.

[0228] Reference Figures 15A to 15CA backside barrier dielectric layer (not shown) may optionally be deposited in the backside recesses (143, 243) and the backside contact trench 79, as well as on the first contact-level dielectric layer 280. The backside barrier dielectric layer may be deposited on a physically exposed portion of the outer surface of the memory stack structure 55. The backside barrier dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. If used, the backside barrier dielectric layer may be formed by conformal deposition processes such as atomic layer deposition or chemical vapor deposition. The thickness of the backside barrier dielectric layer may range from 1 nm to 60 nm, but smaller and larger thicknesses are also possible.

[0229] At least one conductive material may be deposited in a plurality of rear recesses (143, 243), on the sidewalls of the rear contact trench 79, and above the first contact level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element.

[0230] Multiple first conductive layers 146 can be formed in multiple first rear recesses 143, multiple second conductive layers 246 can be formed in multiple second rear recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each rear contact trench 79 and above the first contact layer dielectric layer 280. Therefore, the first and second sacrificial material layers (142, 242) can be replaced by the first and second conductive material layers (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced by an optional portion of the first conductive layer 146 and the rear barrier dielectric layer, and each second sacrificial material layer 242 can be replaced by an optional portion of the second conductive layer 246 and the rear barrier dielectric layer. A rear cavity exists in the portion of each rear contact trench 79 that is not filled by the continuous metal material layer 46L.

[0231] Metallic materials can be deposited using conformal deposition methods, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. The metallic material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof. Non-limiting exemplary metallic materials that can be deposited in the back recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metallic material may include, for example, tungsten and / or a metal nitride. In one embodiment, the metallic material used to fill the back recesses (143, 243) may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the metallic material can be deposited using chemical vapor deposition or atomic layer deposition.

[0232] Residual conductive material can be removed from within the rear contact trench 79. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each rear contact trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first rear recess 143 constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second rear recess 243 constitutes a second conductive layer 246. Each conductive layer (146, 246) can be a conductive line structure.

[0233] A subset of the second conductive layer 246 located at the level of the shallow trench isolation structure 72 in the drain select layer constitutes the drain select gate electrode. A subset of the first conductive layer 146 located at each level of the annular dielectric spacer 116 constitutes the source select gate electrode. A subset of the conductive layers (146, 246) located between the drain select gate electrode and the source select gate electrode can be used as a combination of control gate and word line located at the same level. The control gate electrode within each conductive layer (146, 246) is the control gate electrode for a vertical memory device including the memory stack structure 55.

[0234] Each memory stack structure 55 includes a vertically stacked memory elements at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. Semiconductor devices in the lower peripheral device region 700 may include word line switching devices configured to control bias voltages on the respective word lines. The memory level assembly is situated on the semiconductor substrate 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 extending vertically through at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). At least one alternating stack (132, 146, 232, 246) includes a stepped region, which includes a step in which each lower conductive layer (146, 246) extends further along a first horizontal direction hd1 than any upper conductive layer (146, 146) in the memory hierarchy assembly.

[0235] A dopant of a second conductivity type, opposite to the first conductivity type of the planar semiconductor material layer 10, can be implanted into the surface portion of the substrate semiconductor layer 10 to form a source region 61 beneath the bottom surface of each rear contact trench 79. Insulating spacers 74 comprising dielectric material can be formed around each rear contact trench 79, for example, by depositing a conformal insulating material (e.g., silicon oxide) and subsequent anisotropic etching. The first contact-level dielectric layer 280 can be thinned due to parallel etching during anisotropic etching of the vertical portions of the horizontal portions of the deposited conformal insulating material.

[0236] A conformal insulating layer may be deposited in the rear contact trench 79 and may be anisotropically etched to form an insulating spacer 74. The insulating spacer 74 comprises an insulating material, such as silicon oxide, silicon nitride, and / or a dielectric metal oxide. A cavity extending laterally along the first horizontal direction hd1 exists within each insulating spacer 74.

[0237] A rear contact via structure can be formed in the remaining volume of each rear contact trench 79, for example by depositing at least one conductive material and removing excess portions of the deposited at least one conductive material above a horizontal plane including the top surface of the first contact level dielectric layer 280 through a planarization process such as chemical mechanical planarization or recess etching. The rear contact via structure is electrically insulated in all lateral directions and is laterally elongated along the first horizontal direction hd1. Therefore, the rear contact via structure is referred to herein as a laterally elongated contact via structure 76. As used herein, a structure is "laterally elongated" if its maximum lateral dimension along the first horizontal direction is at least five times greater than its maximum lateral dimension along a second horizontal direction perpendicular to the first horizontal direction.

[0238] Optionally, each laterally elongated contact via structure 76 may include multiple rear contact via portions, such as a lower rear contact via portion and an upper rear contact via portion. In an illustrative example, the lower rear contact via portion may include a doped semiconductor material (e.g., doped polysilicon) and may be formed by depositing a layer of doped semiconductor material to fill the rear contact trench 79 and removing the deposited doped semiconductor material from the top of the rear contact trench 79. The upper rear contact via portion may include at least one metal material (e.g., a combination of TiN pad and W filler material) and may be formed by depositing at least one metal material over the lower rear contact via portion and removing excess portions of at least one metal material from a horizontal plane including the top surface of the first contact level dielectric layer 280. The first contact level dielectric layer 280 may be thinned and removed during a later portion of a planarization process that may employ chemical mechanical planarization (CMP), recessed etching, or a combination thereof. Each laterally elongated contact via structure 76 may be formed through the memory level assembly and located on a corresponding source region 61. The top surface of each laterally elongated contact via structure 76 may be located above the horizontal plane including the top surface of the memory stack structure 55.

[0239] Multiple laterally elongated contact via structures 76 extend laterally along a first horizontal direction hd1 and laterally divide at least one alternately stacked (132, 146, 232, 246) into a plurality of laterally spaced blocks (B0, B1, B2, B3...). Each of the blocks comprises a set of three adjacent blocks, which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and each includes a first stepped region (e.g., Figure 13B The word line contact via area 200 shown), the second step area (e.g.) Figure 13B The through-memory layer via region 400 shown, and the third step region (which may be located in...) Figure 13B (Below the through-memory level via region 400 in the third block B3 outside the region).

[0240] Reference Figures 16A-16C Optionally, a second contact-level dielectric layer 282 may be formed on the first contact-level dielectric layer 280. The second contact-level dielectric layer 282 comprises a dielectric material, such as silicon oxide or silicon nitride. The thickness of the second contact-level dielectric layer 282 may range from 30 nm to 300 nm, although smaller and larger thicknesses are also possible.

[0241] Various contact via structures can be formed through the contact-level dielectric layers (280, 282), dielectric fill material portions 430, and lower dielectric materials on each node of the memory device in the memory hierarchy assembly and on the lower-level metal interconnect structure 780. Specifically, the through-memory via structure 488 can be formed through the dielectric fill material portion 430 and optionally through the contact-level dielectric layers (280, 282) to electrically contact (i.e., electrically couple to) the lower-level metal interconnect structure 780. The word line contact via structure 86 can be formed through the contact-level dielectric layers (280, 282) and the second backward-stepped dielectric material portion 265 in region 200.

[0242] A subset of the word line contact via structures 86 that contact the second conductive layer 246 extends through the second backward-stepped dielectric material portion 265 in region 200, but does not extend through the first backward-stepped dielectric material portion 165. Another subset of the word line contact via structures 86 that contact the first conductive layer 146 extends through the second backward-stepped dielectric material portion 265 and through the first backward-stepped dielectric material portion 165 in region 200.

[0243] A drain contact via structure 88, in contact with drain region 63, may extend through the contact-level dielectric layers (280, 282) and the second insulating capping layer 270 in device region 100. A source connection via structure 91 may extend through the contact-level dielectric layers (280, 282) to provide electrical connection to laterally extended contact via structures 76 in regions 100, 200, and / or 400.

[0244] Each via structure (488, 86, 88, 91) can be formed using a corresponding set of patterning and filling processes. Alternatively, a common set of patterning and filling processes can be used to form two or more types of via structures (488, 86, 88, 91), provided that the anisotropic etching processes therein can control the verticality of the cavities at each target height level for each type of cavity formed simultaneously.

[0245] In one embodiment, the word line contact via structure 86 can be formed to pass through the first step region (e.g., Figure 16B The word line contact via area 200 and the third step area shown in the figure) Figure 16B In another example of the word line contact via region 200 below the shown area, at least one backward-stepped dielectric material portion (165, 265) is located on the corresponding portion of the conductive layer (146, 246) in the first and third blocks (B1, B3) (e.g., in odd-numbered blocks), and not on the second stepped region (e.g., in the second stepped region). Figure 16BThe through-memory layer via region 400 shown (e.g., in even-numbered blocks) forms any contact via structure.

[0246] Each through-memory level via 488 can be formed through a dielectric filler portion 430 (e.g., in an even-numbered block). The through-memory level via 488 can be formed separately from other via structures (86, 88, 91) by patterning the dielectric filler portion 430 and depositing a conductive material (e.g., TiN, W, Al, Ti, Cu, etc.) into openings in the portion 430. Alternatively, the through-memory level via 488 can be formed during the same patterning and deposition steps as one or more other via structures (86, 88, 91) and / or the back-contact via structure 76.

[0247] While odd and even blocks have been described above, it should be noted that regions 400 and 200 do not necessarily alternate sequentially on one side of region 100. For example, a set of two adjacent regions 200 may be separated by a single region 400 or by a set of two adjacent regions 400 on a given side (e.g., left or right) of region 100. On one side (e.g., left) of device region 100, a subset of through-memory-level via structures 488 may be formed in regions 400 of even-numbered step regions after removing these even-numbered step regions, such as the second step region, while odd-numbered step regions, such as the first and third step regions, remain intact. As used herein, a region or structure is “intact” if there is no substantial structural change to it. Each through-memory-level via structure 488 extends vertically from at least a first horizontal plane including the topmost surface of the memory-level component to a second horizontal plane including the bottommost surface of the memory-level component.

[0248] On the contrary, such as Figure 17E As shown, on the opposite side (e.g., the right side) of region 100, after removing these odd-numbered step regions, such as the first step region, a subset of through-hole structures that penetrate the memory hierarchy can be formed in region 400 of the region of odd-numbered step regions, while even-numbered step regions, such as the second step region, remain intact.

[0249] Therefore, as Figures 2 to 7 As shown, multiple alternating sacrificial layers (142, 242) and insulating layers (132, 232) are deposited to form at least one alternating stack. Then, multiple rear-side trenches 79 are formed, extending laterally along the first horizontal direction hd1 through the at least one alternating stack, as shown. Figures 13A-13BAs shown. The sacrificial layer (142, 242) is selectively removed from at least one alternating stack of multiple rear-side trenches 79 to form multiple rear-side recesses (143, 243) between the insulating layers (132, 232), as... Figures 14A-14C As shown.

[0250] Multiple conductive layers (146, 246) are formed in the rear recesses through multiple rear trenches, insulating spacers 74 are formed in multiple rear trenches 79, and multiple laterally elongated contact via structures 76 are formed in the multiple rear trenches 79 above the insulating spacers 74, such as Figures 15A-15C As shown.

[0251] The step of forming multiple conductive layers in the rear recesses through multiple rear trenches occurs after the step of removing the second step region and forming the dielectric filling material portion 430, as follows: Figure 11A-12B As shown. The step of removing the second step region includes removing the insulating layer and sacrificial layer in the second step region to form a through-memory level opening 769. The conductive layer 46 is not formed in the dielectric filling material portion 430 located in the through-memory level opening 769.

[0252] Reference Figure 17A-17F A line-level dielectric layer 110 can be formed on the contact-level dielectric layers (280, 282). Various metal interconnect structures (108, 103, 101) can be formed in the line-level dielectric layer 110. The metal interconnect structures (108, 103, 101) may include an upper-level metal interconnect structure 108 electrically coupled (e.g., formed thereon or in physical contact with it) to corresponding pairs of word line contact via structures 86 and through memory-level via structures 488, bit lines 103 extending along the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures 101 contacting source connection via structures 91 to provide a conductive path for biasing the source region 61 through laterally extended contact via structures 76. A drain-side select gate electrode contact via structure 87 is located in region 200 adjacent to device region 100. In each sub-block between adjacent rear contact trenches 79 in region 200, two or more steps may exist, exposing two or more word lines perpendicularly separated from adjacent device levels. In this case, two or more word line contact via structures 86 (e.g., ...) are positioned parallel to each other in the same sub-block. Figure 17E and 17F The two structures shown (86) are in contact with the corresponding vertically separated word lines.

[0253] exist Figure 17B and 17D An exemplary layout for the upper-level metal interconnect structure 108 is shown in the figure. Figure 17D It is a top view. Figure 17B This is a horizontal cross-sectional view, in which the shapes of the upper-level metal interconnect structure 108 and bit line 103 are shown in dashed lines. The upper-level metal interconnect structure 108 may extend across adjacent blocks, i.e., across the corresponding laterally elongated contact via structure 76. For example, some upper-level metal interconnect structures 108 may extend through a second block as well as one of the first and third blocks. Figure 17E and 17F Another exemplary layout of the upper-level metal interconnect structure is shown. In this embodiment, some upper-level metal interconnect structures 108 are electrically coupled to the lower-level metal interconnect structure 780 via through-memory-level vias 488 located in region 400, and electrically coupled to word lines 46 via word line contact vias 86 located in region 200. Other upper-level metal interconnect structures 208 are electrically coupled to word lines 46 via word line contact vias 86 located in region 200, but not electrically coupled to the lower-level metal interconnect structure 780 via through-memory-level vias 488 located in region 400. These upper-level metal interconnect structures 208 may be electrically coupled to driver circuitry devices at locations other than region 400. Bit lines 103 are formed on the memory-level components and are electrically coupled to nodes (e.g., drain region 63) of the memory stack structure 55 via drain contact vias 88. As used herein, if there is any of an electrical short circuit (i.e., ohmic contact), electronic tunneling communication, or resistive (i.e., Schottky) contact between the first element and the second element, the first element is electrically coupled to the second element. In this case, the upper-level metal interconnect structure 108 can be electrically shorted to the corresponding word line through the word line contact via structure 86, such as implemented as conductive layer 46.

[0254] A first exemplary structure includes a memory hierarchy assembly situated on a semiconductor substrate 9 and comprising at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 extending vertically through the at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) comprises alternating layers of a corresponding insulating layer (132 or 232) and a corresponding conductive layer (146 or 246). A plurality of laterally elongated contact via structures 76 extend vertically through the memory hierarchy assembly, extend laterally along a first horizontal direction hd1, and laterally divide the at least one alternating stack (132, 146, 232, 246) into a plurality of laterally spaced blocks (B0, B1, B2, B3...). Multiple blocks (B0, B1, B2, B3...) comprise a group of at least three adjacent blocks, which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to a first horizontal direction hd1. A through-memory via region 400 is located on the longitudinal end of the second block B2 and between the stepped regions of the first block B1 and the stepped regions of the third block B3.

[0255] Each stepped region of the first and third blocks (B1, B3) includes a step in which each lower conductive layer (146 or 246) extends further along a first horizontal direction hd1 than any upper conductive layer (146 or 246) in the memory hierarchy assembly. The through-memory via region 400 includes a through-memory via structure 488 that extends vertically from at least a first horizontal plane including the topmost surface of the memory hierarchy assembly to a second horizontal plane including the bottommost surface of the memory hierarchy assembly.

[0256] At least one lower-level dielectric layer 760 covers the semiconductor substrate 9. A planar semiconductor material layer 10 covers at least one lower-level dielectric layer 760 and includes a horizontal semiconductor channel 58 electrically connected to a vertical semiconductor channel 60 within the memory stack structure 55. A semiconductor device 710 (e.g., a CMOS transistor for word line driver circuitry) may be located on the semiconductor substrate 9. A lower-level metal interconnect structure 780 may be electrically shorted to nodes (e.g., source, drain, and drain / or gate electrodes) of the semiconductor device 710 and embedded in at least one lower-level dielectric layer 760 covering the planar semiconductor material layer 10. A through-hole structure 488 contacts the lower-level metal interconnect structure 780.

[0257] An upper-level metal interconnect structure 108 covers the memory-level components and is embedded in at least one upper-level dielectric layer 110. At least a portion of the upper-level metal interconnect structure 108 is electrically coupled to a corresponding lower-level metal interconnect structure 780 via a corresponding through-memory-level via structure 488 located in region 400, and electrically coupled to a corresponding word line 46 via a corresponding word line contact via structure 86 located in region 200. Bit lines 103 also cover the memory-level components and are electrically coupled to nodes of the memory stack structure 55 (via drain region 63), and are embedded in at least one upper-level dielectric layer 110. Each memory stack structure 55 includes a vertical stack of memory elements located in each conductive layer (146, 246). The conductive layers (146, 246) include word lines for the memory elements. In one embodiment, the semiconductor device may include word line switching devices configured to control bias voltages on the corresponding word lines.

[0258] In one embodiment, each through-memory via 488 can contact a corresponding lower-level metal interconnect 780. In one embodiment, a subset of semiconductor devices 710 on the semiconductor substrate 9 can be located below a region of the planar semiconductor material layer 10, i.e., have area overlap with the upper planar semiconductor material layer 10.

[0259] In one embodiment, the dielectric filling material portion 430 may be located within the through-memory via region 400. The dielectric filling material portion 430 may laterally surround the through-memory via structure 488 and may extend vertically from at least a first horizontal plane including the topmost surface of the memory layer assembly to a second horizontal plane located below the bottommost surface of the memory layer assembly.

[0260] The planar semiconductor material layer 10 is located below the memory hierarchy assembly and may include a horizontal semiconductor channel 58 electrically connected to a vertical semiconductor channel 60 within the memory stack structure 55. A second horizontal plane is located below the bottom surface of the planar semiconductor material layer. In one embodiment, the dielectric filler portion 430 may include a generally vertical sidewall extending through the memory hierarchy assembly and the planar semiconductor material layer 10.

[0261] In one embodiment, a plurality of laterally elongated contact via structures 76 may extend vertically through the memory hierarchy assembly, laterally along a first horizontal direction hd1, and laterally divide the memory hierarchy assembly into a plurality of laterally spaced blocks (B0, B1, B2, B3...). The plurality of blocks may, for example, comprise a set of three adjacent blocks, which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. A dielectric filler portion 430 may be located on the longitudinal end of the second block B2 and between the stepped regions of the first block B1 and the third block B3. Each stepped region of the first and third blocks (B1, B3) includes a step in which each lower conductive layer (146 or 246) extends further along the first horizontal direction hd1 than any upper conductive layer (146 or 246) within the memory hierarchy assembly.

[0262] Each memory stack structure 55 may include a memory film 50 and a vertical semiconductor channel 60 adjacent to a corresponding horizontal channel 58 within a planar semiconductor material layer 10 beneath the memory hierarchy assembly. Word line contact via structures 86 may extend through backward-stepped dielectric material portions (265, 165) of the stepped regions of the first and third blocks (B1, B3) in coverage area 200 and may contact corresponding portions of the conductive layers (146, 246) in the first and third blocks (B1, B3). Upper-level metal interconnect structures 108 may electrically short-circuit the corresponding pairs of word line contact via structures 86 and through-memory hierarchy via structures 488, may cover the memory hierarchy assembly, and may span one of the second block B2 in region 400 and the first and third blocks (B1, B3) in region 200.

[0263] Reference Figure 18 This illustrates a second exemplary structure according to a second embodiment of the present disclosure. Specifically, in this second embodiment, the word line switching device 710 of the semiconductor device for the second exemplary structure is located in region 400 instead of under region 100 as in the first embodiment. Otherwise, the steps and structure described above with respect to the first embodiment could be used in the second embodiment. By changing the pattern of the semiconductor device and the underlying metal interconnect structure 780, it is possible to... Figure 1A and 1B The first exemplary structure derives the second exemplary structure.

[0264] In the illustrative example, word line switching device 710 may be a field-effect transistor in a CMOS configuration, formed in a through-memory via region 400. Alternatively, a subset of word line switching devices may be formed outside the region through-memory via region 400, such as below a region of memory array region 100 or below a region of word line contact via region 200. The active region 730 of the word line switching device (…) Figure 1A The source region 742 and drain region 744 shown can be laterally surrounded by the shallow trench isolation structure 720.

[0265] The lower-level metal interconnect structure 780 may be embedded in at least one lower-level dielectric layer 760 and may be electrically shorted to the node of a word line switching device located above or on the semiconductor substrate 9. The lower-level metal interconnect structure 780 may be configured such that the lower-level topmost metal structure 788 provides suitable bonding pads for subsequent through-memory-level via structures formed in each region of the through-memory-level via region 400.

[0266] Reference Figures 19A-19B ,implement Figures 2 to 17A The -17D processing steps form a planar semiconductor material layer 10, memory-level components, various contact via structures (88, 86, 91, 488), a line-level dielectric layer 110, and metal interconnect structures (108, 101), as well as bit lines 103 embedded in the line-level dielectric layer 110.

[0267] In one embodiment, the field-effect transistor of the word line switching device can be as follows: Figure 19B The CMOS-configured pairings shown share a common power node, which can be the source or drain region 730 connected to the power metal interconnect structure 7802. The gate structure 750 can span the channel region of the field-effect transistor. A switch output node metal interconnect structure can be connected to the output node of each field-effect transistor, which can be the drain or source region of the corresponding field-effect transistor. The power metal interconnect structure 7802 and the switch output node metal interconnect structure are subsets of the lower-level metal interconnect structure 780. The word line switching devices can be arranged as a periodic array that repeats periodically along the second horizontal direction hd2 at the width of two adjacent blocks (e.g., the width of a combination of the first block B1 and the second block B2).

[0268] Specifically, such as Figure 19AAs shown, a planar semiconductor material layer 10 may be formed over at least one lower-level dielectric layer 760. Memory layer assemblies may be formed over the planar semiconductor material layer 10, and the planar semiconductor material layer 10 may include a horizontal semiconductor channel 58 electrically connected to a vertical semiconductor channel 60 within a memory stack structure 55. The memory layer assemblies may be formed over a semiconductor substrate 9 and the planar semiconductor layer 10. The memory layer assemblies include at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 extending vertically through the at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a corresponding insulating layer (132 or 232) and a corresponding conductive layer (146 or 246). Each memory stack structure 55 includes a vertical stack of memory elements located at each level of the conductive layers (146, 246). The conductive layers (146, 246) include word lines for memory elements.

[0269] At least one alternating stack (132, 146, 232, 246) includes a stepped region comprising a step in which each lower conductive layer (146, 246) extends further along a first horizontal direction than any upper conductive layer (146, 146) in the memory hierarchy assembly. At least one backward stepped dielectric material portion (165, 265) may be formed on the stepped region on at least one alternating stack (132, 146, 232, 246).

[0270] Multiple laterally elongated contact via structures 76 are formed through the memory hierarchy assembly. The multiple laterally elongated contact via structures 76 extend laterally along a first horizontal direction hd1 and laterally divide at least one alternating stack (132, 146, 232, 246) into a plurality of laterally spaced blocks (B1, B2, B3, B4...). Multiple blocks (B1, B2, B3, B4...) comprise a set of three adjacent blocks, which sequentially include a first block B1, a second block B2, a third block B3, and a fourth block B4 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and each includes a first stepped region (e.g., word line contact via region 200 containing the remaining steps of the third and fourth blocks B3 and B4), a second stepped region (from which the steps are removed, e.g., through-memory-level via region 400 of the first and second blocks B1 and B2), and a third stepped region (e.g., word line contact via region 200 containing the remaining third steps of an additional block such as B0 (not shown for clarity).

[0271] A through-memory level opening 769 extending through the memory level assembly can be formed in the region of a removed stepped region, such as a second stepped region. The through-memory level opening 769 can extend into at least one lower-level dielectric material layer 760. The through-memory level opening 769 may include substantially vertical sidewalls extending through the memory level assembly and the planar semiconductor material layer 10. A dielectric filler portion 430 can be formed in the through-memory level opening 769. Following these steps is the formation of a back trench 79, replacing the sacrificial material layers (142, 242) with conductive layers (146, 246), and the formation of insulating spacers 74 and contact via structures (e.g., source electrodes or local interconnects) 76 in the back trench 79, as described above.

[0272] The word line contact via structure 86 can be formed on or above portions of the conductive layers (146, 246) in the remaining stepped regions, such as the first and third stepped regions, without simultaneously forming any contact via structure above the removed stepped regions, such as the second stepped region. The word line contact via structure 86 can also be formed above the remaining stepped regions, such as the first and third stepped regions, through at least one backward stepped dielectric material portion (165, 265) and directly on the corresponding portions of the conductive layers (146, 246) in the first and third blocks (B1, B3), without simultaneously forming any contact via structure above the removed stepped regions, such as the second stepped region B2.

[0273] As described in the previous embodiments, each through-memory via 488 may form a portion 430 filled with dielectric material. Each through-memory via 488 extends vertically from at least a first horizontal plane including the topmost surface of the memory layer assembly to a second horizontal plane including the bottommost surface of the memory layer assembly.

[0274] The nodes of the word line switching device can be electrically connected to portions of the conductive layers (146, 246) in the remaining stepped regions, such as the first and third stepped regions, of the through-memory hierarchical via structure 488 formed in the removed stepped region, such as the second stepped region. For example, upper-level metal interconnect structures 108 can be formed on the through-memory hierarchical via structure 488 and above the memory hierarchical assembly and on the word line contact via structure 86. For example, upper-level metal interconnect structures 108 can be formed on corresponding pairs of word line contact via structures 86 and through-memory hierarchical via structures 488 formed above the memory hierarchical assembly. At least one upper-level metal interconnect structure 108 can extend across the second block B2 and the third block B3. In one embodiment, each upper-level metal interconnect structure 108 can span a corresponding laterally extended contact via structure 76 located between the first block B1 and the third block B3.

[0275] Reference Figure 20 A variation of the second exemplary structure is shown, which can be achieved by forming a subset of optional dielectric pad layers 52 and alternating stacks of first layers (132, 142) at the same level as the word line switching device, at least one lower-level dielectric layer 760, and lower-level metal interconnect structure 780. Figure 18 The second exemplary structure is derived. For example, word line switching devices and lower-level metal interconnect structures 780 may be formed in the through-hole region 400 of the memory hierarchy and outside the region of the memory array region 100.

[0276] In one embodiment, a subset of dielectric pad layer 52 and alternating stacked first layers (132, 142) may be formed on substrate 9. Subsequently, portions of the subset of alternating stacked first layers (132, 142) may be removed from the outside of memory array region 100, and stepped regions having the steps of the subset of alternating stacked first layers (132, 142) may be formed in the peripheral portion of the memory array region 100 adjacent to the through-memory stack via region 400 or word line contact via region 200. Lower-level backward dielectric material portions 765 may be formed above each stepped region and removed in region 700. Then, semiconductor device 710, at least one lower-level dielectric layer 760, and lower-level metal interconnect structure 780 are formed on substrate 9 in region 700. The lower-level backward dielectric material portions 765 may have a top surface substantially at the same level as the top surface of the deposited subset of alternating stacked first layers and the top surface of at least one lower-level dielectric layer 760.

[0277] Reference Figure 21 A complementary subset of the first layer of alternating stacks (132, 142) can be formed on top of the deposition subset of the first layer of alternating stacks (132, 142). This can be performed... Figure 3 , Figure 4A and 4B , Figure 5A and 5B as well as Figure 6 The processing steps are used to form the first layer structure. (Refer to...) Figure 22 It can be executed Figure 7 The processing steps to Figure 10A and 10B The processing steps are used to form the second layer structure. In this embodiment, the horizontal channel is located within the substrate 9 below the memory layer assembly because layer 10 can be omitted in this embodiment. Alternatively, layer 10 is formed directly on the substrate 9 outside region 10.

[0278] Reference Figure 23 It can be executed Figure 11A and 11B The processing steps to Figures 17A-17DThe processing steps are to electrically connect the nodes of the word line switching device to portions of the conductive layer (146, 246) in the remaining stepped regions, such as the first and third stepped regions, of the through-memory layer via structure 488 formed in the removed stepped region, such as the second stepped region.

[0279] Reference Figure 24A and 24B A third exemplary structure according to a third embodiment of this disclosure includes a deep trench separating a first portion of alternating stacks of insulating layers and sacrificial insulating material layers from a second portion of alternating stacks of insulating layers in which the sacrificial insulating material layers are replaced by conductive word line layers. The third exemplary structure can be derived from the first exemplary structure, the second exemplary structure, or variations thereof by performing processing steps up to forming the first alternating stack. As in the first and second embodiments, the lower-level metal interconnect structure 780 can be electrically shorted to the nodes of the semiconductor device and can be embedded in at least one lower-level dielectric layer 760 formed on the semiconductor substrate 9. The layout of the pattern of the first-level support pillar structure 171 can be optionally modified to optionally remove the first-level support pillar structure 171 from the central portion of each through-memory stack via region 400. Figure 5A , 5B The processing step 6 is modified to form a pattern for forming the first memory opening 149. Optional planar conductive material layer 6 and planar semiconductor material layer 10 may be patterned to form an opening 151 extending through these layers to the underlying insulating layer 760. The opening 151 is located below region 400 and may be filled with another insulating material layer (e.g., silicon oxide or doped silicate glass) 760.

[0280] Specifically, concurrently with the formation of the first memory opening 149, a first deep trench can be formed in each through-memory stack via region 400. For example, a photoresist layer can be applied after the formation of the first insulating capping layer 170 or the interlayer dielectric layer 180, and can be photolithographically patterned to form a patterned photoresist layer including a pattern of the memory opening and a pattern for forming the first deep trench through the alternating stack of the first layers (132, 142). Anisotropic etching is performed through the alternating stack of the first layers (132, 142) to form the first memory opening 149 and the first deep trench.

[0281] Sacrificial memory opening fill portion 131 may be formed in the first layer memory opening 149, and sacrificial deep trench fill portion 141 may be formed in the first layer deep trench. For example, a sacrificial filler material layer is deposited in the first layer memory opening 149 and the first layer deep trench, and excess portions of the sacrificial filler material layer may be removed from above the top surface of the interlayer stacked dielectric layer 180. The sacrificial filler material may include the same material as in the first and second embodiments.

[0282] Each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial memory opening fill portion 131. Each remaining portion of the sacrificial material in the first layer deep trench constitutes a sacrificial deep trench fill portion 141. The top surfaces of the sacrificial memory opening fill portion 131 and the sacrificial deep trench fill portion 141 may be coplanar with the top surface of the first insulating capping layer 170. The sacrificial memory opening fill portion 131 may or may not include cavities therein.

[0283] Reference Figure 25A and 25B It can be executed Figure 7 , 8A The processing steps 8B, 9A, and 9B modify the pattern used to form the second layer opening. Specifically, the pattern of the first layer deep trench can be added to the pattern of the second layer memory opening. After transferring the pattern in the photoresist layer through anisotropic etching of the second layer alternating stack (232, 242), the second layer deep trench is formed above the first layer deep trench. The pattern of the second layer deep trench can be the same as the pattern of the first layer deep trench. The sacrificial memory opening filling portion 131 and the sacrificial deep trench filling portion 141 are then removed by selective etching or ashing (if portions 131 and 141 contain carbon-based material). Each stack of the first layer deep trench and the second layer deep trench constitutes a deep trench 449. Memory openings 49 extending through at least one alternating stack (132, 142, 232, 242) can be formed simultaneously with the formation of the deep trench 449.

[0284] In one embodiment, each deep trench 449 may have a U-shaped horizontal cross-sectional shape, such that the two open ends of the U-shape include vertical sidewalls formed by the surface of at least one backward-stepped dielectric material portion (165, 265). In this case, the two sides of each deep trench 449 may extend along a first horizontal direction hd1 parallel to the longitudinal direction of the rear contact trench 79 and may be abutted against each other through the connecting portion of the deep trench 449. The two sides extend along a second longitudinal direction hd2 on the proximal side of the deep trench 449 and may extend along the first horizontal direction beyond the region of the bottom layer of the first alternating stack (132, 142) on the distal side of the deep trench 449. As used herein, the "proximal" side of the deep trench 449 refers to the side closer to the memory array region 100, and the "distal" side of the deep trench 449 refers to the side farther from the memory array region 100.

[0285] In another embodiment, each deep trench 449 may have a closed shape (e.g., polygonal, circular, elliptical, irregular shape, etc.) such that regions of memory hierarchy components are located inside each deep trench 449, and complementary regions of memory hierarchy components are located outside each deep trench 449. In this case, the deep trench 449 separates the interior of the deep trench 449 from the exterior of the deep trench 449, wherein the closed shape corresponds to a region of the deep trench 449. As used herein, a closed shape is a shape having a closed outer periphery and an opening within the closed outer periphery defined by a closed inner periphery. The opening in the deep trench 449 is located above the opening 151 in layer 10 and may have the same or similar shape and / or size as the opening 151.

[0286] The deep trench 449 defines a corresponding region of the through-memory level via region 400 and extends through at least one alternating stack (132, 142, 232, 242). A portion of at least one alternating stack (132, 142, 232, 242) is present within the through-memory level via region 400. Specifically, a portion of at least one alternating stack (132, 142, 232, 242) including an insulating sacrificial material layer (142, 242) may laterally surround a set of inner sidewalls of the deep trench 449 when the deep trench 449 has a closed shape, or in the case that the deep trench 449 is U-shaped, within a combination of the set of inner sidewalls of the deep trench 449 and a vertical surface comprising a plane connecting a pair of vertical edges of the deep trench 449 located at the distal end of the deep trench 449.

[0287] Reference Figure 26A and 26B It can be executed Figure 10A and 10BA subset of the processing steps are used to form an optional base channel portion 11 and memory stack structure 55. Drain regions 63 may be formed on top of each vertical semiconductor channel 60.

[0288] In one embodiment, all surfaces of the deep trench 449 may be dielectric surfaces. The pedestal channel portions 11 are formed using selective semiconductor deposition, such that the pedestal channel portions 11 are grown only at the bottom of each memory opening 49 from the physically exposed semiconductor surface of the planar semiconductor material layer 10, without any semiconductor material being deposited in the deep trench 449.

[0289] While forming the memory stack structure 55, a pseudo-memory stack structure 155 is formed within each deep trench 449. For example, by depositing and anisotropically etching a stack of layers including at least one dielectric material layer (51, 54, 56), an insulating pad 50 can be formed in each deep trench 449 while a memory film 50 is formed within each memory opening 49. Subsequently, a conformal semiconductor material layer can be deposited on the memory film 50 and the insulating pad 50, and by employing a planarization process, portions of the conformal semiconductor material layer can be removed from above at least one alternating stack (132, 142, 232, 242). Each remaining portion of the conformal semiconductor material layer constitutes a vertical semiconductor channel 60, which can be an active channel of a vertical field-effect transistor (if present within the memory stack structure 55) or a semiconductor filler portion 60 (if present within the pseudo-memory stack structure 155 within the deep trench 449).

[0290] Each pseudo-memory stack 155 may have the same set of elements as the memory stack 55. A set of insulating films formed in the deep trench 449 and having the same material stack as the memory film 50 is referred to herein as insulating pad 50. A pseudo-drain region 463 may be formed on top of each pseudo-memory stack 155. The pseudo-memory stack 155 may be electrically isolated from all lower-level elements and laterally surrounding elements. For example, each pseudo-memory stack 155 may contact the top surface of at least one lower-level dielectric layer 760 (e.g., at least one lower-level interconnect dielectric layer 768 filling the opening 151) and the sidewalls of at least one alternating stack (132, 142, 232, 242), interlayer dielectric layer 180, first insulating cap layer 170, and second insulating cap layer 270.

[0291] Each combination of the pseudo memory stack structure 155 and the pseudo drain region 463 constitutes an insulating deep trench structure (155, 463) that fills the corresponding deep trench 449. The region of each through-memory level via region 400 includes a region defined by the closed inner periphery of the corresponding insulating deep trench structure (155, 463).

[0292] Reference Figure 27A and 27B It can be executed Figure 13A and 13B A complementary subset of the processing steps to form the first contact level dielectric layer 280 and the rear contact trench 79.

[0293] Reference Figure 28A and 28B It can be executed Figure 14B , 14C The processing steps 15B and 15C involve replacing the sacrificial material layers (142, 242) with conductive layers (246, 246). In one embodiment, the sacrificial material layers (142, 242) may include dielectric spacer layers, i.e., dielectric material layers perpendicularly spaced from the insulating layers (132, 232). The insulating deep trench structures (155, 463), either alone or in combination with the backward stepped dielectric material portions (165, 265), prevent etchant from propagating laterally into the region laterally surrounded by the insulating deep trench structures (155, 463), such that no rear recesses (143, 243) are formed within the region 400 surrounded by the deep trench structures (155, 463). A portion of the dielectric spacer layer (i.e., sacrificial material layers (142, 242)) located outside the deep trench structure (i.e., outside the through-hole region 400 of the memory layer) is replaced by a conductive layer (146, 246), while at least one alternating stacked portion (132, 142, 232, 242) in each deep trench 449 remains intact. The conductive layer (146, 246) constitutes the word lines for the memory stack structure 55, which are formed outside the deep trench structure (i.e., outside region 400) but not inside the deep trench structure (i.e., inside region 400).

[0294] Subsequently, a conformal insulating material layer is deposited and anisotropically etched within each rear contact trench 79 to form an insulating spacer 74. Laterally extending contact via structures 76 are present within each rear contact trench 79. A plurality of laterally elongated contact via structures 76 extending along a first horizontal direction hd1 laterally divide the memory hierarchy assembly into a plurality of laterally spaced blocks (B1, B2, B3...). The plurality of blocks (B1, B2, B3...) may include a set of three adjacent blocks, which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0295] When the deep trench 449 is U-shaped, the remaining portion of the backward stepped dielectric material portion (265 or 165) can be in the conductive layer (146, 246) portion of the first stepped region (e.g.) Figure 28BThe remaining portion of the dielectric spacer layer (i.e., sacrificial material layers (142, 242)) in the first block B1 shown in the word line contact via region 200 and the second step region (e.g., Figure 28B It extends continuously on the through-memory layer via region 400 in the second block B2.

[0296] Reference Figures 29A-29C Through-memory via (TMV) structures 488 can be formed in each TMV region 400. For example, a via cavity can be formed extending through the remainder of the second alternating stack of the first contact interlayer dielectric layer 280, the second insulating layer 232, and the second sacrificial layer 242, the remainder of the first alternating stack of the first insulating layer 132 and the first sacrificial layer 142, and the upper portion of at least one lower-level dielectric layer 760. Generally, the TMV structure 488 can extend vertically from a first horizontal plane including the topmost surface of the remainder of at least one alternating stack (132, 142, 232, 242) and the bottommost surface of at least one alternating stack (132, 142, 232, 242). Figures 16A-16C The same processing steps can form various additional via structures (86, 87, 88). Because the alternating stacked materials in region 400 are electrically insulating, the through-memory level via structures 488 extending through the alternating stacked insulating layers in region 400 are not short-circuited with each other or with any word lines 400 in the stack outside region 400.

[0297] Reference Figure 30 A line-level dielectric layer 110 can be formed on the contact-level dielectric layers (280, 282). Using... Figures 17A-17D The processing steps may involve forming various metal interconnect structures (108, 101) and bit lines 103 in the line-level dielectric layer 110. As in the first and second embodiments, the bit lines 103 may cover memory-level components, may be electrically coupled to nodes of the memory stack structure 55 (e.g., drain region 63), and may be embedded in at least one upper-level dielectric layer, such as the line-level dielectric layer 110. Through-memory via structures 488 may contact corresponding pairs of upper-level metal interconnect structures 108 and lower-level metal interconnect structures 780. The upper-level metal interconnect structures 108 interconnect corresponding pairs of via structures (86, 488) and (87, 488).

[0298] Reference Figure 31A and 31BA variation of the third exemplary structure can be derived from the third exemplary structure by forming the deep trench 149 and the insulating deep trench structure 466 in a step separate from forming the corresponding memory opening 49 and the memory stack structure 55. A variation of the third exemplary structure can be derived from the third exemplary structure by forming the deep trenches 149 and the insulating deep trench structure 466 in a step separate from forming the corresponding memory opening 49 and the memory stack structure 55. Figure 8A and 8B The method steps shown derive a method for fabricating a third exemplary structure. For example, a photoresist layer can be applied to... Figure 8A and 8B On the first exemplary structure, and can be photolithographically patterned to form a corresponding Figure 25A and 25B The opening of the deep trench pattern is shown. Anisotropic etching is performed by alternating stacking of a second layer (232, 242) and an alternating stacking of a first layer (132, 142) to form the deep trench.

[0299] The deep trenches can then be filled with a dielectric material, such as silicon oxide, to form a deep trench isolation structure, which is a deep trench fill structure 466. In one embodiment, the deep trench fill structure 466 may be substantially composed of a dielectric material. In one embodiment, the region penetrating the memory level via region 400 may include the enclosed inner periphery of the insulating deep trench structure 466.

[0300] Reference Figure 32A and 32B They can be executed sequentially. Figures 9A to 15C The steps involve replacing the sacrificial material layers (142, 242) with conductive layers (246, 246) and forming insulating spacers 74 and laterally extending contact via structures 76. Subsequently, the following steps can be employed: Figures 29A-29C The processing steps involve forming a through-memory level via structure 488 in each through-memory level via region 400. This is achieved using... Figures 16A-16C The same processing steps can be used to form various additional via structures (86, 87, 88). Subsequently, a line-level dielectric layer 110 can be formed on the contact-level dielectric layers (280, 282), and can be employed... Figures 17A-17D The processing steps form various interconnect structures (108, 101) and bit lines 103 in the online hierarchical dielectric layer 110.

[0301] Figure 30 The third exemplary structure shown in the figure and Figure 32A and 32BVariations include a semiconductor structure comprising a memory hierarchy assembly situated on a semiconductor substrate 9 and comprising at least one first alternating stack of a first portion of conductive layers (146, 246) and insulating layers (132, 232), and further comprising a memory stack structure 55 extending vertically through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The conductive layers (146, 246) form word lines for the memory stack structure 55. The semiconductor structure also includes an insulating deep trench structure {466 or (155, 463)} extending vertically through the memory hierarchy assembly and defining a region of a through-memory via region 400 laterally spaced from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure also includes at least one second alternating stack located within the through-memory via region 400. At least one second alternating stack comprises alternating layers of second portions of dielectric spacer layers (142, 242) and insulating layers (132, 232), and each dielectric spacer layer (142, 242) is located at the same level as a corresponding conductive layer (146, 246). The semiconductor structure further includes a through-memory via structure 488 located within the through-memory via region 400 and extending vertically from a first horizontal plane including the top and bottom surfaces of the memory layer assembly, and comprising a conductive material.

[0302] In one embodiment, the region through the memory level via region 400 includes the closed inner periphery of an insulating deep trench structure {466 or (155, 463)}. In this case, the entire set of outer sidewalls of at least one second alternating stack (132, 142, 232, 242) is accessible to the inner sidewall of the insulating deep trench structure {466 or (155, 463)}.

[0303] In one embodiment, a plurality of laterally elongated contact via structures 76 may extend along a first horizontal direction hd1 and may laterally divide the memory hierarchy assembly into a plurality of laterally spaced blocks (B1, B2, B3...). In one embodiment, the plurality of blocks (B1, B2, B3...) may include a set of three adjacent blocks, which sequentially include a first block B1, a second block B2, and a third block B3 arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Insulating deep trench structures {466 or (155, 463)} may be located on the longitudinal end of the second block B2 and between the stepped regions of the first block B1 and the stepped regions of the third block B3. Each stepped region of the first and third blocks (B1, B3) may include a step in which each lower conductive layer (146, 246) extends further along the first horizontal direction hd1 than any upper conductive layer (146, 146) within the memory hierarchy assembly.

[0304] In one embodiment, the bottom surface of the rear stepped dielectric material portion (265 or 165) may contact the top surface of the steps of the first and third stepped regions in the corresponding first and third blocks (B1, B3). In one embodiment, an additional rear stepped dielectric material portion (265 or 165) may be present within the inner wall of the insulating deep trench structure {466 or (155, 463)}. In this case, the bottom surface of the additional rear stepped dielectric material portion may include the same material as the rear stepped dielectric material portion (165, 265) and may be laterally spaced from the rear stepped dielectric material portion by the insulating deep trench structure {466 or (155, 463)}, and may contact the top surface of the steps of at least one second alternating stack (132, 142, 232, 242).

[0305] In one embodiment, the insulating deep trench structure {466 or (155, 463)} may be U-shaped. In this case, the additional step bottom surface of the backward stepped dielectric material portion (165 or 265) may contact the step top surface of at least one second alternating stack (132, 142, 232, 242).

[0306] In one embodiment, each of the plurality of laterally elongated contact via structures 76 may be laterally surrounded by an insulating spacer 74. The insulating deep trench structures (155, 463) may include an insulating pad 50 comprising the same material as the memory film 50 in the memory stack structure 55.

[0307] In one embodiment, a plurality of laterally elongated contact via structures 76 may include source lines that contact the corresponding lower source region 61, which in turn contact the corresponding horizontal channel 58.

[0308] In one embodiment, the insulating trench structure (155, 463) may include a layer stack comprising the same set of layers as those included in each memory stack structure 55, namely the memory film 50 and the vertical semiconductor channel 60.

[0309] In one embodiment, the insulating trench structure 466 may consist substantially of a dielectric filling material portion.

[0310] The semiconductor structure may further include a semiconductor device located on a semiconductor substrate 9, a lower-level metal interconnect structure 780 electrically shorted to the nodes of the semiconductor device and embedded in at least one lower-level dielectric layer 760 covering the semiconductor substrate 9, and a planar semiconductor material layer 10 covering at least one lower-level dielectric layer 760 and including a horizontal semiconductor channel 58 connected to a vertical semiconductor channel 60 within a memory stack structure 55.

[0311] In one embodiment, the semiconductor structure may further include an upper-level metal interconnect structure 108 covering the memory-level components, electrically coupled to a node of the memory stack structure 55 and embedded in at least one upper-level dielectric layer 110. Through-memory via structures 488 may extend vertically through the memory-level components and may contact corresponding pairs of upper-level metal interconnect structures 108 and lower-level metal interconnect structures 780.

[0312] Reference Figure 33A and 33B This illustrates a fourth exemplary structure according to a fourth embodiment of the present disclosure, which can be formed simultaneously with any of the first, second, and third exemplary structures or variations thereof, or can be formed as a separate structure. It can be employed with methods for forming... Figure 10A and 10B The same processing steps as the first exemplary structure are used to form Figure 33A and 33B The fourth exemplary structure shown does not form a rear contact trench 79. Through-memory-level via regions 500 can be formed within the memory array region 100. Each through-memory-level via region 500 can be formed entirely within a block (B1, B2, etc.). Through-memory-level via regions 500 can be formed without forming the additional through-memory-level via regions 400 of the first, second, and third embodiments, or through the same memory-level components in addition to the through-memory-level via regions 400 of the first, second, and third embodiments.

[0313] Each of at least one alternating stack of insulating layers (132, 232) and sacrificial material layers (142, 242) is an alternating stack in process, which is modified in subsequent processing steps. Although an embodiment in which through-memory-level via regions 500 are formed within memory array region 100 is described herein, embodiments in which additional or alternative through-memory-level via regions 500 are formed in stepped regions are also contemplated herein. Various pseudo-memory stack structures 55D may be formed around the through-memory-level via regions 500, which do not serve as electrical connections for device components but are used for structural support during the formation of rear recesses in subsequent processing steps.

[0314] Reference Figure 34A and 34BThe rear contact trench 79 and the deep trench 579 can be simultaneously formed through the memory level assembly. For example, a photoresist layer can be applied to the first contact level dielectric layer 280 and can be photolithographically patterned to form openings, including patterns for the rear contact trench 79 as in the previous embodiment and patterns for the deep trenches, which can be identical to the deep trench patterns of the third embodiment or its variations. Anisotropic etching is performed to transfer the patterns in the patterned photoresist layer through the memory level assembly, thereby forming the rear contact trench 79 and the deep trench 579. The photoresist layer can then be removed, for example, by ashing. Each deep trench 579 may include a region within its outer periphery that extends through the memory level via region 400.

[0315] Reference Figure 35A and 35B An insulating liner layer 572L can be deposited in the deep trench 579 and the rear contact trench 79. The insulating liner layer 572L comprises a dielectric material such as silicon oxide, silicon nitride, and / or a dielectric metal oxide such as aluminum oxide. The insulating liner layer 572L can be deposited as a conformal material layer using conformal deposition methods such as chemical vapor deposition or atomic layer deposition. The thickness of the insulating liner layer 572L can range from 3 nm to 60 nm, although smaller and larger thicknesses are also possible.

[0316] A photoresist layer 577 may be applied onto an insulating pad layer 572L and may be photolithographically patterned to cover the insulating pad layer 572L within the through-hole region 500 of the memory level via, where the insulating pad layer 572L is not covered by the photoresist layer outside the through-hole region 500. An etching process (which may be isotropic or anisotropic) may be used to remove the physically exposed portion of the insulating pad layer 572L from the outside of the through-hole region 500. The patterned insulating pad layer 572L is formed on the sidewalls of the deep trench 579 and over a portion of the first contact level dielectric layer 280 within the through-hole region 500. The sidewalls of the rear contact trench 76 are physically exposed to the environment. As used herein, “environment” means any gaseous environment that the semiconductor substrate may be physically exposed to during the manufacturing process, and includes air, vacuum, inert environments, and depressurized environments. The photoresist layer 577 is subsequently removed, for example, by ashing.

[0317] Reference Figure 36A and 37A It can be executed Figure 11A and 11BThe processing steps involve removing the selectively sacrificial material layers (142, 242) that selectively affect the insulating layers (132, 232). Specifically, etchant can be introduced through the rear contact trench 79 to form the rear recesses (143, 243). A patterned insulating liner layer 572L covers all sidewalls of each deep trench 579 and prevents the etchant from etching portions surrounding at least one alternating stack (132, 142, 232, 242). Thus, during the formation of the rear recesses (143, 243), each portion of at least one alternating stack (132, 142, 232, 242) laterally surrounded by the vertical portions of the corresponding patterned insulating liner layer 572L remains intact.

[0318] Reference Figure 37A and 37B It can be executed Figure 12A and 12B The processing steps involve forming conductive layers (146, 246) in the rear recesses (143, 243). The conductive layers (146, 246) can be formed by introducing reactants through the rear contact trench 79, thereby forming at least one alternating stack of insulating layers (132, 232) and conductive layers (146, 246). Trench cavities 579' exist within each patterned insulating liner layer 572L. The remainder of the alternating stacks (132, 142, 232, 242) in at least one processing step remains within each region surrounded by the deep trench 579.

[0319] Reference Figure 38A and 38B It can be executed Figure 13A and 13B The processing steps are to form the insulating spacer 74 and the laterally elongated contact via structure 76. Specifically, the insulating material layer may be conformally deposited and anisotropically etched to form the insulating spacer 74 in each rear contact trench 79 and the inner insulating pad 574 in each trench cavity 579'. The inner insulating pad 574 may be formed within each patterned insulating pad layer 572L concurrently with the formation of the insulating spacer 74. The insulating spacer 74 and the insulating pad (i.e., the inner insulating pad 574) may be formed simultaneously in the rear contact trench 79 and the deep trench 579, respectively. The inner insulating pad 574 and the insulating spacer 74 may comprise the same dielectric material and may have the same thickness.

[0320] Conductive material is deposited to fill the remaining volume of the rear contact trench 79 and trench cavity 579'. Excess conductive material can be removed from a horizontal plane, including the top surface of the first contact level dielectric layer 280, through a planarization process such as chemical mechanical planarization. Each remaining portion of the conductive material within the insulating spacer 74 constitutes a laterally elongated contact via structure 76. Each remaining portion of the conductive material within the inner insulating pad 574 constitutes a conductive fill portion 576. Multiple laterally elongated contact via structures 76 and conductive fill portions 576 can be formed simultaneously on the insulating spacer 74 and the insulating pad, respectively. Horizontal portions of the patterned insulating pad layer 572L can be removed from above the top surface of the first contact level dielectric layer 280. Each remaining portion of the patterned insulating pad layer 572L constitutes an outer insulating pad 572.

[0321] Multiple laterally elongated contact via structures 76 are formed through the memory hierarchy assembly. The multiple laterally elongated contact via structures 76 extend laterally along a first horizontal direction hd1 and divide at least one alternately stacked laterally into multiple laterally spaced blocks (B1, B2, B3...) within the memory hierarchy assembly.

[0322] Reference Figure 39A and 39B At least one through-memory level opening is formed within the region of each through-memory level via area 500 of the memory level assembly. This can be achieved during the initial etching process. Figure 2 and 7 During the anisotropic etching of at least one alternating stack of materials (132, 142, 232, 242) and at least one lower-level dielectric layer 760 formed in the processing steps, a photolithographically patterned mask including openings in a region through the memory level via region 500 is employed. The top surface of the lower-level metal interconnect structure 780 can be physically exposed at the bottom of each through-memory level opening. Conductive material is deposited in the through-memory level cavity, and excess portions of the conductive material can be removed from a horizontal plane including the top surface of the first contact level dielectric layer 280. Each remaining portion of the conductive material in the through-memory level opening constitutes a through-memory level via structure 588, which can contact the corresponding lower-level metal interconnect structure 780.

[0323] In one embodiment, at least one through-memory-level via (TML) structure 588 may be formed in a TML region 500 within the block. The TML region 500 may be disposed between a pair of laterally elongated contact via structures 76 and between two sets of memory stack structures 55 located within the block. The TML region 500 may include the TML structure 588. Each of the at least one TML structure 588 extends vertically through the memory hierarchy assembly.

[0324] Reference Figure 40 The drain contact via structure 88 and word line contact via structure can be formed as in the first to third embodiments. A line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first to third embodiments. The metal interconnect structure can include an upper-level metal interconnect structure 108, which can be formed on corresponding pairs of word line contact via structures 86 and through-memory-level via structures 588, bit lines 103 extending along the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures (not shown). Alternatively, the upper-level metal interconnect structure 108 can include source shunts or power bands contacting the through-memory-level via structures 588. The source shunt can be a shunt parallel to and extending between the bit lines 103. The power band can be any conductive line connecting the driver circuitry to an external power supply.

[0325] Figure 40The fourth exemplary structure shown includes a semiconductor structure comprising a memory hierarchy assembly situated on a semiconductor substrate 9 and including at least one first alternating stack of a first portion of conductive layers (146, 246) and insulating layers (132, 232), and further including a memory stack structure 55 extending vertically through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The conductive layers (146, 246) form word lines for the memory stack structure 55. The semiconductor structure also includes insulating deep trench structures (572, 574, 576) extending vertically through the memory hierarchy assembly and defining a region of through-memory via region 500 laterally offset from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure also includes at least one second alternating stack located within the through-memory via region 500. At least one second alternating stack comprises alternating layers of second portions of dielectric spacer layers (142, 242) and insulating layers (132, 232), and each dielectric spacer layer (142, 242) is located at the same level as a corresponding conductive layer (146, 246). The semiconductor structure also includes a through-memory via structure 588 located within the through-memory via region 500 and extending vertically from a first horizontal plane including the top and bottom surfaces of the memory layer assembly, and comprising a conductive material.

[0326] In one embodiment, a plurality of laterally elongated contact via structures 76 extending along a first horizontal direction hd1 can laterally divide the memory hierarchy assembly into a plurality of laterally spaced blocks, and each of the plurality of laterally elongated contact via structures 76 can be laterally surrounded by an insulating spacer 74. Insulating deep trench structures (572, 574, 576) can include conductive fill portions 576 comprising the same conductive material as the plurality of laterally elongated contact via structures 76.

[0327] Reference Figure 41 The diagram illustrates a first variation of the fourth exemplary structure, which can be achieved by increasing the thickness of the insulating liner layer 572L. Figure 37A and 37B The fourth exemplary structure shown is derived. Specifically, the thickness of the insulating liner layer 572L is increased such that the maximum width of the trench cavity 579' after the insulating liner layer 572L is less than twice the width of the insulating material layer to be deposited, in order to form an insulating spacer in the rear contact trench 79.

[0328] Reference Figure 42The thickness of the deposited insulating material layer is such that it completely fills the rear contact trench 79 and the deep trench 579. Anisotropic etching is performed to remove the horizontal portions of the insulating material layer. Each remaining vertical portion of the insulating material layer in the rear contact trench 79 constitutes an insulating spacer. Each remaining portion of the insulating material layer filling the volume within the insulating pad layer 572 constitutes an insulating material filling portion 575. Subsequently, a conductive material is deposited and planarized to form a laterally extending contact via structure 76. The remaining portion of each insulating pad layer 572L constitutes an outer insulating pad 572.

[0329] In one embodiment, insulating material filling portions 575 may be formed in the deep trench 579 while insulating spacers 74 are formed in the rear contact trench 79. A plurality of laterally elongated contact via structures 76 may be formed on the insulating spacers 74. The remainder of at least one alternating stack (132, 142, 232, 242) in a process remains within the area surrounded by each deep trench 579.

[0330] Then, it can be executed. Figure 39A and 39B The processing steps are to form at least one through-memory level via structure 588 within each through-memory level via region 500.

[0331] Reference Figure 43 The drain contact via structure 88 and word line contact via structure can be formed as in the first to third embodiments. The line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first to third embodiments. The metal interconnect structure can include an upper-level metal interconnect structure 108, which may be formed on corresponding pairs of word line contact via structures 86 and through-memory-level via structures 588, or it may include a shunt line or power band connected to structure 588, a bit line 103 extending along the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and a source connection line structure (not shown).

[0332] Figure 43A first variant of the fourth exemplary structure shown includes a semiconductor structure comprising a memory hierarchy assembly situated on a semiconductor substrate 9 and comprising at least one first alternating stack of a first portion of conductive layers (146, 246) and insulating layers (132, 232), and further comprising a memory stack structure 55 extending vertically through the at least one first alternating stack. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The conductive layers (146, 246) form word lines for the memory stack structure 55. The semiconductor structure also includes insulating deep trench structures (572, 575) extending vertically through the memory hierarchy assembly and defining a region of through-memory via region 500 laterally offset from the at least one first alternating stack (132, 146, 232, 246). The semiconductor structure also includes at least one second alternating stack located within the through-memory via region 500. At least one second alternating stack comprises alternating layers of second portions of dielectric spacer layers (142, 242) and insulating layers (132, 232), and each dielectric spacer layer (142, 242) is located at the same level as a corresponding conductive layer (146, 246). The semiconductor structure also includes a through-memory via structure 588 located within the through-memory via region 500 and extending vertically from a first horizontal plane including the top and bottom surfaces of the memory layer assembly, and comprising a conductive material.

[0333] In one embodiment, a plurality of laterally elongated contact via structures 76 extending along a first horizontal direction hd1 can laterally divide the memory hierarchy assembly into a plurality of laterally spaced blocks, and each of the plurality of laterally elongated contact via structures 76 may be laterally surrounded by an insulating spacer 74. The insulating deep trench structures (572, 575) may be substantially composed of a dielectric material.

[0334] Reference Figure 44A and 44B The second variation of the fourth exemplary structure can be with Figure 33A and 33B The fourth exemplary structure shown is identical. A second variation of the fourth exemplary structure may be formed simultaneously with the formation of any one of the first, second, and third exemplary structures or variations thereof, or may be formed as a separate structure. As in the embodiments described above, alternating stacking may be performed in at least one process of forming insulating layers (132, 232) and dielectric spacer layers (which may be sacrificial material layers (142, 242)) on the semiconductor substrate 9.

[0335] Through-memory-level via regions 600, excluding memory stack structures 55, can be formed within the memory array region 100 in their respective central regions. Each through-memory-level via region 600 can be formed entirely within a block (B1, B2, etc.). A pseudo-memory stack structure 55D can be disposed around the through-memory-level via region 600. The pseudo-memory stack structure 55 is not an active component of the semiconductor structure, but rather serves to provide structural support during the formation of the back recesses (143, 243). The through-memory-level via regions 600 can be formed without forming the additional through-memory-level via regions 400 of the first, second, and third embodiments, or they can be formed through the same memory-level components in addition to the through-memory-level via regions 400 of the first, second, and third embodiments.

[0336] Reference Figure 45A and 45B The photoresist layer 677 may be applied onto the first contact level dielectric layer 280 and may be photolithographically patterned to form openings therein. The pattern of the openings includes the pattern of the rear contact trench 79 described above and the pattern of the through-memory level via structure subsequently formed in the through-memory level region 600.

[0337] The pattern in the photoresist layer 677 can be transferred through alternating stacking of the first contact layer dielectric layer 280 and insulating layers (132, 232) and dielectric spacer material layers (142, 242) to form back-side contact trenches 79 in the memory array region 100 and through-memory level openings 679 in the through-memory level via region 600. The top surface of the planar semiconductor layer 10 can be physically exposed at the bottom of each back-side contact trench 79. The back-side contact trenches 79 can be formed simultaneously with the formation of the through-memory level openings 679.

[0338] At least one lower-level dielectric layer 760 may have its top surface physically exposed at the bottom of each through-memory level opening 679. The top surface of the lower-level metal interconnect structure 780 may or may not be physically exposed at the bottom of the through-memory level opening 679. In one embodiment, the width of the through-memory level opening 679 may be greater than the width of the rear contact trench 79. In this case, more reactants may be supplied to the through-memory level opening 679 during anisotropic etching, and the bottom surface of the through-memory level opening 679 may be located below the bottom surface of the rear contact trench 79.

[0339] Reference Figure 46A and 46B For example, photoresist layer 677 can be removed by ashing. This can be performed... Figure 11A and 11BThe processing steps involve removing the sacrificial material layers (142, 242) that selectively etch the insulating layers (132, 232). In this case, the rear contact trench 79 and the through-memory level opening 679 can be used to introduce an etchant that selectively etches the sacrificial material layers (142, 242) onto the insulating layers (132, 232). Subsequently, the following steps can be performed: Figure 12A and 12B The processing steps are to form conductive layers (146, 246). Reactants can be introduced through the rear contact trench 79 and the through-memory level opening 679 to deposit the conductive layers (146, 246). An etch-back process can be used to remove excess deposited conductive material from inside the rear contact trench 79 and the through-memory level opening 679, and from above the first contact level dielectric layer 280. This forms an alternating stack (132, 146, 232, 246) of insulating layers (232, 232) and conductive layers (146, 246).

[0340] Reference Figure 47A and 47B A conformal insulating layer is deposited in the back contact trench 79 and the through-memory level opening 689 using conformal deposition processes such as chemical vapor deposition or atomic layer deposition. The conformal insulating layer includes a dielectric material, such as silicon oxide, silicon nitride, dielectric metal oxide, or a combination thereof.

[0341] Anisotropic etching is performed to remove the horizontal portion of the conformal insulating material layer. Where the top surface of the lower-level metal interconnect structure 780 is not physically exposed to the bottom of the through-memory level opening 679 prior to anisotropic etching, the anisotropic etching can remove at least one additional material of the lower-level dielectric layer 760 to physically expose the top surface of the lower-level metal interconnect structure 780. In this case, the through-memory level opening 679 can extend downwards while the conformal insulating material layer is anisotropically etched. During anisotropic etching, the lower-level metal interconnect structure 780 can be physically exposed to the bottom of one or more through-memory level openings 679.

[0342] Each remaining portion of the conformal insulating material layer in the rear contact trench 79 constitutes an insulating spacer 74. Each remaining portion of the conformal insulating material layer in the memory level opening 679 constitutes an insulating pad 674. After the conductive layers (146, 246) are formed, the insulating spacer 74 and the insulating pad 674 are formed simultaneously in the rear contact trench 79 and the memory level opening 679, respectively. A rear cavity 79' exists within each insulating spacer 74. A memory level cavity 679' exists within each insulating pad 674.

[0343] Reference Figure 48A and 48BAt least one conductive material can be deposited in the rear contact trench 79' and the through-memory layer trench 679'. Excess portions of the at least one conductive material can be removed from a horizontal plane including the top surface of the first contact layer dielectric layer 280 through a planarization process such as chemical mechanical planarization. Each remaining portion of the at least one conductive material in the rear contact trench 79 constitutes a laterally elongated contact via structure 76. Each remaining portion of the at least one conductive material in the through-memory layer opening 679 constitutes a through-memory layer via structure 676. Each through-memory layer via structure 676 is a portion of conductive filler material. The laterally elongated contact via structure 76 and the through-memory layer via structure 676 can be formed simultaneously in the rear contact trench 79 and the through-memory layer opening 679, respectively.

[0344] Reference Figure 49 The drain contact via structure 88 and word line contact via structure can be formed as in the first to third embodiments. The line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first to third embodiments. The metal interconnect structure may include an upper-level metal interconnect structure 108, which may be formed on corresponding pairs of word line contact via structures 86 and through-memory-level via structures 588, or may include a shunt line or power band connected to structure 588, a bit line 103 extending along a second horizontal direction and perpendicular to the first horizontal direction hd1, and a source connection line structure (not shown).

[0345] Reference Figure 50A and 50B The third variant of the fourth exemplary structure can be combined with Figure 44A and 44B The second variant of the fourth exemplary structure shown is the same, with optional modifications to the pattern for the drain-selection layer shallow trench isolation structure 72. As described above, a first layer alternating stack (132, 242), a second layer alternating stack (232, 242), a memory stack structure, and a drain-selection layer shallow trench isolation structure 72 can be formed.

[0346] Reference Figure 51A and 51B The photoresist layer 677 can utilize only the pattern of the through-memory level opening 679 and does not have Figure 45A and 45B The pattern of the rear contact groove 79 shown is applied and patterned. It can be applied and patterned as follows: Figure 45A and 45BAnisotropic etching is performed in the same manner as the processing steps to transfer the pattern in the photoresist layer 677 through alternating stacking (132, 142, 232, 242) and onto the upper portion of at least one dielectric layer 760. A through-memory level opening 679 is formed in the through-memory level region 600, without forming a back-side contact trench in the semiconductor structure.

[0347] Reference Figure 52A and 52B The photoresist layer 677 can be removed, for example, by ashing. This can be performed... Figure 11A and 11B The processing steps involve removing the sacrificial material layers (142, 242) that selectively affect the insulating layers (132, 232). In this case, an etchant can be introduced through the memory layer opening 679, which etches the sacrificial material layers (142, 242) that selectively affect the insulating layers (132, 232). Subsequently, the following steps can be performed: Figure 12A and 12B The processing steps are to form conductive layers (146, 246). Reactants can be introduced through the memory level opening 679 to deposit the conductive layers (146, 246). An etch-back process can be used to remove excess deposited conductive material from inside the memory level opening 679 and above the first contact level dielectric layer 280. This forms an alternating stack (132, 146, 232, 246) of insulating layers (232, 232) and conductive layers (146, 246).

[0348] Reference Figure 53A and 54B A conformal insulating layer is deposited in the through-memory level opening 689 using conformal deposition processes such as chemical vapor deposition or atomic layer deposition. The conformal insulating layer includes a dielectric material, such as silicon oxide, silicon nitride, dielectric metal oxide, or a combination thereof.

[0349] Anisotropic etching is performed to remove the horizontal portion of the conformal insulating material layer. Where the top surface of the lower-level metal interconnect structure 780 is not physically exposed to the bottom of the through-memory level opening 679 prior to anisotropic etching, the anisotropic etching can remove additional material from at least one lower-level dielectric layer 760 to physically expose the top surface of the lower-level metal interconnect structure 780. In this case, the through-memory level opening 679 can extend downwards while the conformal insulating material layer is anisotropically etched. During anisotropic etching, the lower-level metal interconnect structure 780 can be physically exposed to the bottom of one or more through-memory level openings 679. Each remaining portion of the conformal insulating material layer in the through-memory level opening 679 constitutes an insulating pad 674. A through-memory level cavity 679' exists within each insulating pad 674.

[0350] Reference Figure 54A and 54B At least one conductive material may be deposited in the through-memory layer cavity 679'. Excess portions of the at least one conductive material can be removed from a horizontal plane including the top surface of the first contact layer dielectric layer 280 through a planarization process such as chemical mechanical planarization. Each remaining portion of the at least one conductive material in the through-memory layer opening 679 constitutes a through-memory layer via structure 676. Each through-memory layer via structure 676 is a portion of conductive filler material.

[0351] Reference Figure 55A and 55B This allows for the formation of multiple insulating spacers 74 and multiple laterally extending contact via structures 76 located within corresponding insulating spacers 74. The rear contact groove can be formed by employing... Figure 11B The pattern shown is an alternating stack of insulating layers (132, 232) and conductive layers (146, 246). Insulating spacers 74 can be formed by deposition of a dielectric material and anisotropic etching. Source regions 61 can be formed beneath each rear contact trench. Laterally extending contact via structures 76 can be formed by depositing at least one conductive material and using a planarization process to remove excess portions of at least one conductive material.

[0352] Subsequently, drain contact via structure 88 and word line contact via structure can be formed as in the first to third embodiments. Line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first to third embodiments. The metal interconnect structure may include upper-level metal interconnect structure 108, which may be formed on corresponding pairs of word line contact via structures 86 and through-memory-level via structures 588, or may include shunt lines or power bands connected to structure 588, bit lines 103 extending along a second horizontal direction and perpendicular to the first horizontal direction, and source connection line structures (not shown).

[0353] Reference Figure 56A and 56B It can be seen from Figure 13A and 13B The first exemplary structure shown in the figure or corresponding to Figure 13A and 13B The processing steps described above, any of the second, third, and fourth exemplary structures or variations thereof, derive a fourth variation of the fourth exemplary structure.

[0354] Through-memory-level via regions 600, excluding memory stack structures 55, can be formed within the memory array region 100 in their respective central regions. Each through-memory-level via region 600 can be formed entirely within a block (B1, B2, etc.). A pseudo-memory stack structure 55D can be disposed around the through-memory-level via region 600. The pseudo-memory stack structure 55 is not an active component of the semiconductor structure, but rather serves to provide structural support during the formation of the back recesses (143, 243). The through-memory-level via regions 600 can be formed without forming the additional through-memory-level via regions 400 of the first, second, and third embodiments, or they can be formed through the same memory-level components in addition to the through-memory-level via regions 400 of the first, second, and third embodiments.

[0355] Reference Figure 57A and 57B The photoresist layer 677 can be utilized Figure 51A and 51B The pattern shown in the diagram, which extends through the memory layer opening 679, is applied and patterned. Anisotropic etching can be performed to transfer the pattern in the photoresist layer 677 through alternating stacks (132, 142, 232, 242) and onto the upper portion of at least one dielectric layer 760. The through-memory layer opening 679 is formed in the through-memory layer region 600, while a plurality of laterally extending contact via structures 76 and insulating spacers 74 are present in the semiconductor structure. The top surface of the lower-level metal interconnect structure 780 can be physically exposed at the bottom of the through-memory layer opening 679.

[0356] Reference Figure 58A and 58B It can be executed Figure 53A and 53B The processing steps are to form an insulating pad 674 that laterally surrounds the corresponding through-memory level cavity 679'.

[0357] Reference Figure 59A and 59B The drain contact via structure 88 and word line contact via structure can be formed as in the first to third embodiments. The line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first to third embodiments. The metal interconnect structure may include an upper-level metal interconnect structure 108, which may be formed on corresponding pairs of word line contact via structures 86 and through-memory-level via structures 588, or may include a shunt line or power band connected to structure 588, a bit line 103 extending along a second horizontal direction and perpendicular to the first horizontal direction, and a source connection line structure (not shown).

[0358] Reference Figure 60 This illustrates a fifth variation of the fourth exemplary structure according to a fourth embodiment of the present disclosure, which can be derived from any of the second, third, and fourth variations of the fourth exemplary structure by patterning the through-memory level opening 679 in a manner that does not separate the shallow trench isolation structure 72 of the drain contact level. In this case, the through-memory level via structure 676 can be formed as a two-dimensional array.

[0359] Reference Figure 61A and 61B It can be seen from Figure 10A and 10B Structure or from Figure 22 The structure derives a second variation of the third exemplary structure. The memory stack structure 55 and the first contact level dielectric layer 280 can be formed using any of the methods described above.

[0360] Reference Figure 62A and 62B It can be executed Figure 34A and 34B The processing steps involve simultaneously forming a rear contact trench 79 and a deep trench 579 through the memory hierarchy assembly. In this embodiment, the location of the deep trench 579 is selected to be outside the memory array region 100 and within each through-memory hierarchy via region 400, and it may have the same location as the through-memory hierarchy via regions 400 in the first, second, and third embodiments.

[0361] For example, a photoresist layer can be applied to the first contact-level dielectric layer 280, and it can be photolithographically patterned to form openings, including patterns of the back contact trench 79 as in the previous embodiment and patterns of the deep trench 579. Anisotropic etching is performed to transfer the patterns in the patterned photoresist layer through the memory-level assembly, thereby forming the back contact trench 79 and the deep trench 579. The photoresist layer can then be removed, for example, by ashing. Each deep trench 579 may include a region within its outer periphery that extends through the memory-level via region 400.

[0362] Reference Figures 63A-63C Can be executed sequentially Figure 35A and 35BThe processing steps 36A and 36B, 37A and 37B, 38A and 38B, 39A and 39B, and 40 are used to form a plurality of laterally elongated contact via structures 76 through the memory hierarchy assembly and to fill each deep trench 579 having insulating deep trench structures (572, 574, 576) extending vertically through the memory hierarchy assembly. Through-memory via structures 488 can form each dielectric material assembly laterally surrounded by corresponding insulating deep trench structures (572, 573, 576). Each dielectric material assembly may include at least one alternating stack of insulating layers (132, 232) and spacer dielectric layers (142, 242), a second backward-stepped dielectric material portion 265, and an optional first backward-stepped dielectric material portion 165.

[0363] Various contact via structures (88, 86), line-level dielectric layers 110, and various metal interconnect structures and bit lines 103 extending through the line-level dielectric layers 110 can be formed. The metal interconnect structures may include upper-level metal interconnect structures 108. In one embodiment, a subset of the upper-level metal interconnect structures 108 may be electrically coupled to (e.g., formed thereon or in physical contact with) corresponding pairs of word line contact via structures 86 and through-memory-level via structures 488. Bit lines 103 extend along a second horizontal direction hd2 and are perpendicular to a first horizontal direction hd1. Word line interconnect structures 106 may include portions of the upper-level metal interconnect structures 108 electrically shorted from the through-memory-level via structures 488, and / or may include metal lines connected to peripheral circuitry for driving word lines in memory stack structures 55 within the memory array region 100. Alternatively or additionally, at least one subset of the through-memory-level via structures 488 may be used for various purposes, such as providing power supply voltage, electrical grounding, etc.

[0364] Reference Figure 64 It can be executed Figure 41 and 42 The processing steps derive a third variant of the third exemplary structure from a second variant of the third exemplary structure to form an insulating deep trench structure (572, 575), each of which includes a pair of insulating pads 572 and an insulating material filling portion 575.

[0365] Reference Figure 65A and 65B It can be done in Figure 44B The first deep trench is formed within the through-hole region 600 of the memory layer shown in the figure. Figure 24A and 24B The third exemplary structure leads to a sixth variation of the fourth exemplary structure. This can be achieved using... Figure 24A and 24BThe processing steps involve forming a sacrificial deep trench filling portion 141 in the first layer of deep trenches.

[0366] Reference Figure 66A and 66B By executing Figure 25A , 25B The processing steps of 26A and 26B form a second layer of alternating stacks (232, 242) and memory stack structure 55 and pseudo memory stack structure 155. Pseudo memory stack structure 155 is an insulating deep trench structure that provides electrical isolation between the interior and exterior of pseudo memory stack structure 155.

[0367] Reference Figure 67A and 67B It can be executed Figure 27A and 27B The processing steps and Figure 28A and Figure 28B A subset of the processing steps to form the rear recess (143, 243).

[0368] Reference Figure 68A and 68B It can be executed Figure 28A and 28B A complementary subset of the processing steps is used to form conductive layers (146, 246) outside the through-hole region 600 of the memory hierarchy. Insulating spacers 74 and laterally extending contact via structures 76 may be formed in the rear contact trench 79.

[0369] Reference Figure 69A and 69B At least one through-memory level opening forms a memory level assembly within the region passing through each through-memory level via region 600. This can be achieved during the initial etching process. Figure 2 and 7 During the anisotropic etching of at least one alternating stack of materials (132, 142, 232, 242) and at least one lower-level dielectric layer 760 formed in the processing steps, a photolithographically patterned mask including openings in a region through the memory level via region 600 is employed. The top surface of the lower-level metal interconnect structure 780 can be physically exposed at the bottom of each through-memory level opening. Conductive material is deposited in the through-memory level cavity, and excess portions of the conductive material can be removed from a horizontal plane including the top surface of the first contact level dielectric layer 280. Each remaining portion of the conductive material in the through-memory level opening constitutes a through-memory level via structure 588, which can contact the corresponding lower-level metal interconnect structure 780.

[0370] In one embodiment, at least one through-memory-level via (TML) structure 588 may be formed in a TML region 600 within the block. The TML region 600 may be disposed between a pair of laterally elongated contact via structures 76 and between two sets of memory stack structures 55 located within the block. The TML region 600 may include the TML structure 588. Each of the at least one TML structure 588 extends vertically through the memory hierarchy assembly.

[0371] Drain contact via structure 88 and word line contact via structure can be formed as in the first to third embodiments. Line-level dielectric layer 110 can be formed on the first contact-level dielectric layer 280. Various metal interconnect structures can be formed in the line-level dielectric layer 110 as in the first to third embodiments. The metal interconnect structure may include upper-level metal interconnect structure 108, which may be formed on corresponding pairs of word line contact via structures 86 and through-memory-level via structures 588, or may include shunt lines or power bands connected to structure 588, bit lines 103 extending along the second horizontal direction hd2 and perpendicular to the first horizontal direction hd1, and source connection line structures (not shown).

[0372] Reference Figure 70A and 70B It can be seen from Figure 10A and 10B The first exemplary structure shown derives a seventh variation of the fourth exemplary structure. The memory stack structure 55 and the first contact level dielectric layer 280 can be formed using the method described above. The pattern of the support pillar structures (171, 271) can be modified to avoid the subsequent formation of regions through the memory level via structures.

[0373] Reference Figure 71A and 71B A photoresist layer is applied and photolithographically patterned thereto form an opening for the pattern including the aforementioned back contact trench 79 and the pattern of the through-memory via structure to be formed in each through-memory via region 400. The pattern in the photoresist layer is transferred through the memory layer assembly to simultaneously form the back contact trench 79 and the through-memory via cavity 479. In one embodiment, anisotropic etching may be selective for the semiconductor material of the planar semiconductor layer 10 to achieve etching of at least one physically exposed portion of the lower dielectric layer 760. In one embodiment, the top surface of the lower metal interconnect structure 780 may be physically exposed on the bottom of the through-memory via cavity 479.

[0374] Reference Figure 72A and 72B It can be executed Figure 52A and52B The processing steps involve replacing the sacrificial material layers (142, 242) with conductive layers (146, 246). Each of the through-hole cavity 479 and the rear contact trench 79 can be used to provide etchant to remove material from the sacrificial material layers (142, 242) to form the rear recesses (143, 243), and to provide reactants to deposit the conductive material of the conductive layers (146, 246).

[0375] Reference Figures 73A-73C A conformal insulating layer, including a dielectric material (such as silicon oxide), can be deposited and anisotropically etched to simultaneously form an insulating pad 474 in both the through-memory-level via cavity 479 and the insulating spacer 74 within the rear contact trench 79. The source region 61 can be formed by implanting an electrically dopant into the physically exposed portion of the planar semiconductor material layer 10. Through-memory-level via structures 476 can be formed in each of the remaining volumes of the through-memory-level via cavity 479, and laterally extending contact via structures 76 can be formed in each of the remaining volumes of the rear contact trench 79 by depositing and planarizing at least one conductive material (such as TiN and W). Various contact via structures (86, 88) can be formed using the methods described above.

[0376] Reference Figure 74 A line-level dielectric layer 110 and various metal interconnect structures and bit lines 103 extending through the line-level dielectric layer 110 can be formed. The metal interconnect structures may include upper-level metal interconnect structures 108. In one embodiment, a subset of the upper-level metal interconnect structures 108 may be electrically coupled to (e.g., formed thereon or in physical contact with) corresponding pairs of word line contact via structures 86 and through-memory-level via structures 476. Bit lines 103 extend along a second horizontal direction hd2 and perpendicular to a first horizontal direction hd1. Word line interconnect structures 106 may include portions of the upper-level metal interconnect structures 108 electrically shorted to through-memory-level via structures 476, and / or may include metal lines connected to peripheral circuitry for driving word lines in memory stack structures 55 within the memory array region 100. Alternatively or additionally, at least one subset of through-memory-level via structures 488 may be used for various purposes, such as providing power supply voltage, electrical grounding, etc.

[0377] Reference Figure 75A and 75B This can be achieved by delaying the formation of the rear contact trench 79 until after the formation of the insulating pad 474 and the through-hole structure 476 in the memory hierarchy. Figure 70A and 70B The seventh variation of the fourth exemplary structure derives the eighth variation of the fourth exemplary structure.

[0378] Reference Figure 76 As described above, a rear contact trench 79, an insulating spacer 74, a source region 61, a laterally extending contact via structure 76, an additional contact via structure 88, a line-level dielectric layer 110, and various metal interconnect structures 108 and bit lines 103 extending through them can be formed.

[0379] Various through-memory-level via structures (588, 676) of the fourth exemplary structure or variations thereof can be used to provide vertical conductive paths in selected areas of the memory array region 100. The through-memory-level via structures (588, 676) can be used as part of a power distribution network, or can be used to provide various control signals to a three-dimensional memory device in a manner that shortens signal paths and thus minimizes signal loss and capacitive coupling.

[0380] A fourth exemplary structure or any variation thereof may include a semiconductor structure comprising a memory hierarchy assembly situated on a semiconductor substrate 9 and including a first portion of at least one alternately stacked conductive layer (146, 246) and insulating layer (132, 232), and further including a memory stack structure 55 extending vertically through at least one alternately stacked memory stack structure 55. Each memory stack structure 55 includes a memory film 50 and a vertical semiconductor channel 60. The conductive layers (146, 246) form word lines for the memory stack structure 55. A plurality of laterally elongated contact via structures 76 extend vertically through the memory hierarchy assembly, laterally extending along a first horizontal direction hd1, and laterally dividing the at least one alternate stack into a plurality of laterally spaced blocks (B1, B2, B3...) within the memory hierarchy assembly. At least one through-memory-level via structure (588, 676) is located in a through-memory-level via region 400 within the block. The through-memory-level via region 400 is located between a pair of laterally elongated contact via structures 76 and between two sets of memory stack structures 55 located within the block. Each of at least one through-hole structure (588, 676) extends vertically through the memory hierarchy component.

[0381] Semiconductor devices may be located on semiconductor substrate 9. A lower-level metal interconnect structure 680 may be electrically shorted to nodes of the semiconductor device and may embed at least one lower-level dielectric layer 760 covering semiconductor substrate 9. The lower-level metal interconnect structure 680 may contact at least one through-memory via structure (588, 676). A planar semiconductor material layer 10 may cover at least one lower-level dielectric layer 760 and may include a horizontal semiconductor channel 58 connected to a vertical semiconductor channel 60 within the memory stack structure 55.

[0382] In one embodiment, each of at least one through-memory via structure 676 may be laterally electrically isolated from the conductive layers (146, 246) via a corresponding insulating pad 674. In one embodiment, the bottom of each sidewall of at least one through-memory via structure (588, 676) is in physical contact with at least one lower-level dielectric layer 760. In some embodiments, each insulating pad 674 may have a larger than that of the conductive layers (146, 246). Figure 49 The corresponding through-memory layer via structure 676, surrounded by the insulating pad 674 shown, has a smaller vertical range.

[0383] In one embodiment, each of the plurality of laterally elongated contact via structures 76 is laterally electrically isolated from at least one alternating stack (132, 246, 232, 246) via an insulating spacer 74. In another embodiment, each of at least one through-memory level via structure 676 is laterally electrically isolated from at least one alternating stack (132, 246, 232, 246) via an insulating pad 674 having the same material composition and the same thickness as the insulating spacer 74.

[0384] The planar semiconductor material layer 10 may cover the semiconductor substrate 9 and may include horizontal semiconductor channels 58 connected to vertical semiconductor channels 60 within the memory stack structure 55. At least one through-memory level via structure (588, 686) may extend through an opening in the planar semiconductor material layer 10. In one embodiment, a plurality of laterally extended contact via structures 76 may terminate on the top surface of the planar semiconductor material layer 10. The plurality of laterally extended contact via structures 76 may include source lines contacting respective underlying source regions 61 of the corresponding horizontal channels 58 within the planar semiconductor material layer 10.

[0385] In some embodiments, at least one second alternating stack (132, 142, 232, 242) may be located in the through-memory level via region 400. The at least one second alternating stack (132, 142, 232, 242) comprises alternating layers of a second portion of a dielectric spacer layer (142, 242) and an insulating layer (132, 232), and each dielectric spacer layer (142, 242) is located at the same level as a corresponding conductive layer (146, 246). The through-memory level via region 400 may include insulating deep trench structures {(572, 574, 576), (572, 575)} that laterally surround at least one second alternating stack (132, 142, 232, 242).

[0386] The inner sidewalls of the insulating deep trench structure {(572, 574, 576), (572, 575)} and the sidewalls of at least one through-memory level via structure 588 are in physical contact with at least one second alternating stack (132, 142, 232, 242).

[0387] In one embodiment, the insulating trench structures (572, 574, 576) may include an outer insulating pad 572 and an inner insulating pad 574. Each of the plurality of laterally elongated contact via structures 76 may be laterally surrounded by an insulating spacer 74 comprising a dielectric material having the same composition and thickness as the inner insulating pad 574.

[0388] In one embodiment, the insulating deep trench structure (572, 574, 576) may include a conductive fill portion 576 having the same material composition as the plurality of laterally extended contact via structures 76.

[0389] In one embodiment, the insulating deep trench structure (572, 575) may consist of an outer insulating pad 572 and an inner insulating fill portion 565, and each of the plurality of laterally elongated contact through-hole structures 76 may be laterally surrounded by an insulating spacer 74 comprising the same dielectric material as the inner insulating fill portion 574.

[0390] Each exemplary structure and its variations may include a three-dimensional memory structure. The memory stack structure 55 may include memory elements of a vertical NAND device. Conductive layers (146, 246) may include or may be electrically connected to corresponding word lines of the vertical NAND device. The semiconductor substrate 9 may include a silicon substrate. The vertical NAND device may include an array of monolithic three-dimensional NAND strings on the silicon substrate. At least one memory cell in a first device layer of the monolithic three-dimensional NAND string array is located above another memory cell in a second device layer of the monolithic three-dimensional NAND string array. The silicon substrate may contain an integrated circuit including word line driver circuitry and bit line driver circuitry for the memory device. The array of monolithic three-dimensional NAND strings may include a plurality of semiconductor channels, wherein at least one end of each of the plurality of semiconductor channels (58, 11, 60) (e.g., vertical semiconductor channel 60) extends substantially perpendicular to the top surface of semiconductor substrate 9; a plurality of charge storage elements (e.g., embodied as portions of memory material layers 54 located at each word line level), each charge storage element being located in a corresponding one of the plurality of semiconductor channels (58, 11, 60); and a plurality of control gate electrodes (e.g., embodied as subsets of conductive layers (146, 246) having a strip shape extending substantially parallel to the top surface of semiconductor substrate 9 (e.g., along a first horizontal direction hd1), the plurality of control gate electrodes including at least a first control gate electrode located at a first device level and a second control gate electrode located at a second device level.

[0391] The via contact structures located in regions 400, 500 and / or 600 provide electrical contact with driver circuitry located below the memory array, thereby reducing the overall device size / coverage on the substrate and utilizing device areas that are not fully utilized in prior art devices, which reduces device cost.

[0392] While specific embodiments have been mentioned above, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of this disclosure. In cases where embodiments employing specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible to those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: A memory-level assembly, situated on a semiconductor substrate, includes at least one alternating stack and a memory stack structure extending vertically through the at least one alternating stack, wherein the at least one alternating stack includes alternating layers of respective insulating and conductive layers. Multiple laterally elongated contact via structures extend vertically through the memory hierarchy assembly, extending laterally along a first horizontal direction, and laterally dividing the at least one alternating stack into a plurality of laterally spaced blocks, wherein the plurality of blocks include a set of three adjacent blocks, the set of three adjacent blocks sequentially comprising a first block, a second block, and a third block arranged along a second horizontal direction perpendicular to the first horizontal direction, and wherein the memory stack structure of the first subgroup extends through the first block, the memory stack structure of the second subgroup extends through the second block, and the memory stack structure of the third subgroup extends through the third block; as well as A through-memory level via region is located adjacent to the longitudinal end of the second block and between the stepped region of the first block and the stepped region of the third block, wherein the through-memory level via region includes a vertically extending through-memory level via structure embedded in a dielectric filling material portion.

2. The semiconductor structure according to claim 1, further comprising: At least one lower-level dielectric layer covers the semiconductor substrate; as well as A planar semiconductor material layer covers the at least one lower-level dielectric layer and includes a horizontal semiconductor channel electrically connected to a vertical semiconductor channel within the memory stack structure.

3. The semiconductor structure according to claim 2, further comprising: Semiconductor devices are located on the semiconductor substrate; as well as A lower-level metal interconnect structure is electrically shorted to a node of the semiconductor device and embedded in at least one lower-level dielectric layer, the at least one lower-level dielectric layer being below the planar semiconductor material layer, wherein the through-memory via structure contacts the lower-level metal interconnect structure.

4. The semiconductor structure according to claim 3, wherein: Each of the memory stack structures comprises a vertical stack of memory elements located at each level of the conductive layer; The conductive layer includes word lines for the memory element; and The semiconductor device includes a word line switch device configured to control the bias voltage on a corresponding word line.

5. The semiconductor structure according to claim 4, further comprising: The word line contacts a through-hole structure, which extends through a backward stepped dielectric material portion and contacts the word line, the backward stepped dielectric material portion covering the stepped areas of the first and third blocks; by The upper-level metal interconnect structure electrically shorts the corresponding pair of word line contact via structures and through-memory level via structures, wherein the upper-level metal interconnect structure covers the memory level components and spans the second block and one of the first block and the third block.

6. The semiconductor structure of claim 5, wherein each of the through-hole structures in the memory hierarchy contacts a corresponding overlaid upper-level metal interconnect structure.

7. The semiconductor structure of claim 5, wherein the subgroup of semiconductor devices on the semiconductor substrate is located below a region of the planar semiconductor material layer.

8. The semiconductor structure of claim 1, wherein the dielectric filling material portion extends vertically from at least a first horizontal plane containing the topmost surface of the memory hierarchy assembly to a second horizontal plane located below the bottommost surface of the memory hierarchy assembly.

9. The semiconductor structure of claim 8, further comprising a planar semiconductor material layer below the memory cascade assembly and including a horizontal semiconductor channel electrically connected to a vertical semiconductor channel within the memory stack structure, wherein the second horizontal plane is located below the bottom surface of the planar semiconductor material layer.

10. The semiconductor structure according to claim 9, wherein: The dielectric filling material portion includes substantially vertical sidewalls that extend through the memory cascade assembly and the planar semiconductor material layer; Each stepped region of the first and third blocks includes a step, in which the conductive layer beneath each step extends further along the first horizontal direction than any overlying conductive layer within the memory hierarchy assembly; and Each of the memory stack structures includes a memory film and a vertical semiconductor channel adjacent to a corresponding horizontal channel within a planar semiconductor material layer below the memory tier assembly.

11. The semiconductor structure of claim 10 further includes a plurality of bit lines electrically coupled to the drain region of the memory stack body structure.

12. The semiconductor structure of claim 8, wherein the dielectric filling material portion has a rectangular horizontal cross-sectional shape and substantially vertical sidewalls extending vertically from the first horizontal plane to the second horizontal plane.

13. The semiconductor structure of claim 12, wherein each of the through-memory layer vias extends vertically from the first horizontal plane to the second horizontal plane.

14. The semiconductor structure according to claim 1, wherein: The memory stack structure includes memory elements of a vertical NAND device; The conductive layer includes or is electrically connected to a corresponding word line of the vertical NAND device; The semiconductor substrate includes a silicon substrate; The vertical NAND device comprises an array of monolithic three-dimensional NAND strings on the silicon substrate; At least one memory cell in the first device layer of the monolithic 3D NAND string array is located above another memory cell in the second device layer of the monolithic 3D NAND string array. The silicon substrate contains an integrated circuit, which includes word line driver circuitry and bit line driver circuitry for a memory device; and The array of the monolithic three-dimensional NAND strings includes: A plurality of semiconductor channels, wherein at least one end of each of the plurality of semiconductor channels extends substantially perpendicular to the top surface of the semiconductor substrate; Multiple charge storage elements, each charge storage element being located in a corresponding one adjacent to the plurality of semiconductor channels; and A plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes including at least a first control gate electrode located in the first device layer and a second control gate electrode located in the second device layer.

15. The semiconductor structure of claim 1, further comprising an interface in which a substantially vertical sidewall of the dielectric filling material portion of the memory layer assembly physically contacts a substantially vertical sidewall of the second block at the interface and extends laterally along the second horizontal direction.

16. The semiconductor structure of claim 15, wherein the lateral separation distance between the bottom vertical surface of the stepped surface of the stepped region of the first block and the plane containing the interface along the first horizontal direction is greater than the lateral separation distance between the through-memory via structure and the interface along the first horizontal direction.

17. The semiconductor structure of claim 15, further comprising a planar semiconductor material layer below and perpendicularly spaced from the semiconductor substrate, wherein a substantially vertical sidewall of the dielectric filling material portion contacts a sidewall of the planar semiconductor material layer.

18. The semiconductor structure of claim 1, wherein the at least one alternating stack comprises: A first alternating stack of a first insulating layer and a first conductive layer; as well as The second alternating stack of the second insulating layer and the second conductive layer The interlayer dielectric layer is located between the first alternating stack and the second alternating stack.

19. The semiconductor structure according to claim 18, further comprising: The first backward stepped dielectric material portion includes a first stepped bottom surface, the first stepped bottom surface contacting the lower part of the stepped region of the first block and the lower part of the stepped region of the third block; as well as The second backward-stepped dielectric material portion includes a second step bottom surface, which contacts the upper part of the stepped region of the first block and the upper part of the stepped region of the third block. The interlayer dielectric layer extends laterally between the first backward stepped dielectric material portion and the second backward stepped dielectric material portion.

20. The semiconductor structure of claim 19, wherein the dielectric filling material portion contacts a substantially vertical sidewall of the first backward stepped dielectric material portion, a substantially vertical sidewall of the second backward stepped dielectric material portion, and a substantially vertical sidewall of the interlayer dielectric layer.

21. The semiconductor structure of claim 1, wherein the lateral separation distance along the first horizontal direction between one of the through-memory layer via structures and the memory stack structure of the second subgroup is less than the lateral separation distance along the first horizontal direction between the bottom vertical surface of the stepped surface in the stepped region of the first block and the memory stack structure of the first subgroup.

22. The semiconductor structure of claim 21, wherein the lateral separation distance between one of the through-memory via structures and the memory stack structure of the second subgroup along the first horizontal direction is greater than the lateral separation distance between the top vertical surface of the stepped surface in the stepped region of the first block and the memory stack structure of the first subgroup along the first horizontal direction.

23. A three-dimensional NAND memory device, comprising: Word line driver devices, located on or above a substrate; An alternating stack of word lines and insulating layers is located above the word line driver device; Multiple memory stack structures extend through the alternating stacks, each memory stack structure including a memory film and a vertical semiconductor channel; Multiple laterally elongated contact via structures extend vertically through the alternating stack, extending laterally along a first horizontal direction, and laterally dividing at least one alternating stack into multiple laterally spaced memory blocks, wherein the multiple laterally spaced memory blocks include a set of three adjacent blocks, the set of three adjacent blocks sequentially comprising a first memory block, a second memory block, and a third memory block arranged along a second horizontal direction perpendicular to the first horizontal direction, and wherein the memory stack structure of the first subgroup extends through the first memory block, the memory stack structure of the second subgroup extends through the second memory block, and the memory stack structure of the third subgroup extends through the third memory block; as well as A through-hole structure is used to electrically couple word lines in the first memory block to the word line driver device. The through-memory via structure extends through a dielectric filling material portion located near the longitudinal end of the second memory block and between the stepped regions of the first memory block and the third memory block, and laterally spaced from each of the stepped regions of the first memory block and the third memory block.

24. The device according to claim 23, further comprising: The word line contacts a via structure that extends through a dielectric material portion and contacts the word line in the first memory block, the dielectric material portion covering the stepped area of ​​the first memory block; as well as The upper-level metal interconnect structure electrically shorts the corresponding pair of word line contact via structures and through-memory level via structures, wherein the upper-level metal interconnect structure covers the alternating stack and spans the first memory block and the dielectric filling material portion; The stepped regions of the first memory block and the third memory block rise in the same diagonal direction.

25. The device of claim 23, further comprising an interface, wherein a substantially vertical sidewall of the dielectric-filled portion of the memory hierarchy assembly physically contacts a substantially vertical sidewall of the second memory block at the interface and extends laterally along the second horizontal direction, wherein the lateral separation distance between the bottom vertical surface of the stepped surface of the stepped region of the first memory block and the plane containing the interface along the first horizontal direction is greater than the lateral separation distance between the through-memory via structure and the interface along the first horizontal direction.

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