Semiconductor device and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and a storage system, and relates to the technical field of semiconductor chips, and is used for improving the storage density of the semiconductor device. The semiconductor device comprises a substrate, a first stack structure arranged on one side of the substrate, a plurality of storage columns penetrating through the first stack structure, a plurality of storage points corresponding to one storage column, the plurality of storage points being arranged along a first direction perpendicular to the substrate, the storage column comprising a storage functional layer and an inner electrode arranged in sequence, the storage functional layer being located between a plurality of plate line layers and the inner electrode, the storage functional layer and the inner electrode each having a portion opposite to the plate line layer, and the storage functional layer and the inner electrode forming a storage point with the plate line layer, the plurality of storage points corresponding to one storage column sharing the inner electrode level, and a plurality of transistors arranged on a side of the first stack structure away from the substrate, the transistors being electrically connected with the inner electrode. The semiconductor device is applied to a three-dimensional memory to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method and storage system. Background Technology

[0002] Ferroelectric random access memory (FeRAM), as a new type of memory, is increasingly being used due to its advantages over traditional dynamic random access memory (DRAM), such as non-volatility, high speed, and low power consumption.

[0003] Currently, ferroelectric memories still maintain a two-dimensional structure and have low storage density. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor device and a method for fabricating the same, as well as a storage system, for improving the storage density of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a semiconductor device is provided. The semiconductor device includes: a substrate; a first stacked structure disposed on one side of the substrate, the first stacked structure including a plurality of alternating plate line layers and a plurality of first dielectric layers; a plurality of memory pillars penetrating the first stacked structure, each memory pillar including a memory functional layer and an internal electrode sequentially disposed from the outside to the inside, the memory functional layer being located between the plurality of plate line layers and the internal electrode, the portions of the memory functional layer and the internal electrode opposite to the plate line layers forming a memory point with the plate line layers; and a plurality of transistors disposed on the side of the first stacked structure away from the substrate, the transistors being electrically connected to the internal electrodes.

[0007] The semiconductor device provided in the above embodiments of this disclosure, by setting multiple stacked board lines, with each board line layer surrounding a storage functional layer and the storage functional layer and the portion of the internal electrode opposite to the board line layer forming storage points, can obtain a storage cell containing multiple storage points and one transistor. One storage point can be used to store 1 bit of data, and multiple storage points can be used to store multiple bits of data. Thus, compared with the storage cell of the 1T1C structure in the prior art, the storage capacity of the semiconductor device is improved. On the other hand, in the embodiments of this disclosure, the transistor is set on the side of the first stacked structure away from the substrate. Compared with the prior art, where the transistor is formed on the substrate and is epitaxially generated on the substrate, the substrate must be a semiconductor substrate, which leads to limited material selection for the substrate. In the embodiments of this disclosure, the requirements for the substrate are reduced, and the substrate only needs to serve a supporting function.

[0008] In some embodiments, the semiconductor device further includes: at least one first isolation structure extending through the first stacked structure to the substrate, the first isolation structure extending along a second direction parallel to the substrate; the at least one first isolation structure dividing the first stacked structure into a plurality of memory blocks arranged along the third direction, the memory blocks including a plurality of memory strings, the memory strings being formed by a plurality of memory points corresponding to the same memory pillar; wherein the third direction is parallel to the substrate and intersects the second direction.

[0009] In some embodiments, there are multiple first isolation structures, and the multiple first isolation structures divide the first stack structure into 8n storage blocks; where n is a positive integer and n≥1.

[0010] In some embodiments, the storage block has a core region and a step region arranged sequentially along the second direction; a plurality of storage strings are located in the core region; and the portions of the plurality of board lines located in the step region are step-shaped.

[0011] In some embodiments, the semiconductor device further includes: a plurality of contacts located in the stepped region; the contacts extending along a first direction and in contact with the plate line layer; the first direction being perpendicular to the substrate.

[0012] In some embodiments, the semiconductor device includes: a second stacked structure disposed on the side of the first stacked structure away from the substrate, and a plurality of channel structures extending through the second stacked structure to the first stacked structure; the second stacked structure includes: a word line layer; and second dielectric layers located on opposite sides of the word line layer; the channel structure includes a gate dielectric layer and a channel layer disposed sequentially, the gate dielectric layer being located between the word line layer and the channel layer, and the gate dielectric layer, the channel layer, and the portion of the word line layer surrounding the gate dielectric layer forming the transistor.

[0013] In some embodiments, the material of the trench layer includes polycrystalline silicon.

[0014] In some embodiments, the semiconductor device further includes: a plurality of second isolation structures extending through the second stacked structure to the first stacked structure, the plurality of second isolation structures being arranged sequentially along a second direction and all extending along a third direction; the third direction and the second direction are both parallel to the substrate and intersect each other; wherein the plurality of second isolation structures divide the word line layer into a plurality of word lines.

[0015] In some embodiments, the semiconductor device further includes: a bit line layer located on the side of the second stacked structure away from the substrate, the bit line layer including a plurality of bit lines extending along the second direction and arranged sequentially along the third direction; the bit lines being electrically connected to a plurality of transistors.

[0016] In some embodiments, the plurality of transistors are arranged in multiple rows along the third direction; among the plurality of transistors in the same row, the channel layers of the odd number of transistors are electrically connected to the same bit line, and the channel layers of the even number of transistors are electrically connected to the same bit line.

[0017] In some embodiments, the semiconductor device further includes a bridging layer located between the second stacked structure and the bit line layer, the bridging layer including a plurality of bridging portions, one end of the bridging portion being in contact with the channel layer of the transistor and the other end being in contact with the bit line.

[0018] In some embodiments, the material of the storage functional layer is a ferroelectric material, an antiferroelectric material, a phase change material, or a magnetic material.

[0019] In some embodiments, the storage column further includes a support column, with the inner electrode surrounding the support column.

[0020] On the other hand, a method for fabricating a semiconductor device is provided, the method comprising: providing a substrate; forming a first stacked structure on one side of the substrate, the first stacked structure comprising a plurality of alternating plate line layers and a plurality of first dielectric layers; forming a plurality of receiving holes penetrating the first stacked structure to the substrate; sequentially forming a storage functional layer and an internal electrode within the receiving holes to form a storage pillar, wherein the portions of the storage functional layer and the internal electrode opposite to the plate line layers form storage points with the plate line layers; and forming a plurality of transistors on the side of the first stacked structure away from the substrate, the transistors being electrically connected to the internal electrode.

[0021] In some embodiments, before forming a plurality of transistors on the side of the first stacked structure away from the substrate, the fabrication method further includes: forming at least one first isolation trench through the first stacked structure to the substrate; the isolation trenches are arranged sequentially along a third direction and all extend along a second direction; the third direction and the second direction are both parallel to the substrate and intersect each other; the at least one first isolation structure divides the first stacked structure into a plurality of memory blocks arranged along the third direction, the memory blocks including a plurality of memory strings, the memory strings being formed by a plurality of memory points corresponding to the same memory pillar; wherein the third direction is parallel to the substrate and intersects with the second direction.

[0022] In some embodiments, forming a plurality of transistors on the side of the first stacked structure away from the substrate includes: forming a second stacked structure on the side of the first stacked structure away from the substrate; the second stacked structure includes: a word line layer, second dielectric layers located on opposite sides of the word line layer; forming a plurality of channel vias penetrating the second stacked structure to the first stacked structure; the channel vias exposing internal electrodes located within the receiving vias; sequentially forming a gate dielectric layer and a channel layer within the plurality of channel vias to form a channel structure; the gate dielectric layer being located between the word line layer and the channel layer, and the gate dielectric layer, the channel layer, and a portion of the word line layer surrounding the gate dielectric layer forming the transistors.

[0023] In some embodiments, the fabrication method further includes: forming a plurality of second isolation trenches penetrating from the second stacked structure to the first stacked structure, the plurality of second isolation trenches being arranged sequentially along a second direction and all extending along a third direction; the third direction and the second direction being parallel to the substrate and intersecting therein; forming a second isolation structure within the second isolation trenches; the plurality of second isolation structures dividing the word line layer into a plurality of word lines.

[0024] In some embodiments, the fabrication method further includes: forming a bit line layer on the side of the second stacked structure away from the substrate; the bit line layer includes a plurality of bit lines extending along the second direction and arranged sequentially along the third direction; the bit lines are electrically connected to a plurality of transistors.

[0025] In some embodiments, before forming the bit line layer on the side of the second stacked structure away from the substrate, the fabrication method further includes: forming a bridging layer on the side of the second stacked structure away from the substrate; the bridging layer includes a plurality of bridging portions, one end of which is in contact with the channel layer of the transistor and the other end of which is in contact with the bit line.

[0026] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor device as described in some of the embodiments above, and peripheral devices located on the side of the transistor in the semiconductor device away from the substrate and electrically connected to the transistor.

[0027] In another aspect, a storage system is provided, comprising: a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0028] In another aspect, an electronic device is provided, characterized in that it includes the storage system described above.

[0029] It is understood that the beneficial effects of the semiconductor device fabrication method, three-dimensional memory, storage system and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a block diagram of a storage system according to some embodiments;

[0032] Figure 2 A block diagram of a storage system according to some other embodiments;

[0033] Figure 3 A cross-sectional view of a three-dimensional memory according to some embodiments;

[0034] Figure 4 This is an equivalent circuit diagram of a memory cell in related technologies;

[0035] Figure 5 This is a process structure diagram of a memory cell in related technologies;

[0036] Figure 6A A top view of a semiconductor device according to some embodiments;

[0037] Figure 6B for Figure 6A A sectional view along A-A';

[0038] Figure 6C for Figure 6B A magnified view of region B in the middle;

[0039] Figure 6D This is an equivalent circuit diagram of a memory cell according to some embodiments;

[0040] Figure 6E This is a structural diagram of a semiconductor device according to some embodiments;

[0041] Figure 6F for Figure 6A A sectional view along B-B';

[0042] Figure 7 A cross-sectional view of yet another semiconductor device according to some embodiments;

[0043] Figure 8 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0044] Figures 9A to 9J This is a structural diagram corresponding to each step in a method for fabricating another semiconductor device according to some embodiments. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0056] Some embodiments of this disclosure provide an electronic device that may include a storage system configured to implement data storage as described below, and may also include at least one of a central processing unit (CPU) and a cache.

[0057] For example, the electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (such as smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0058] Some embodiments of this disclosure provide a storage system 1000. See also... Figure 1 and Figure 2 The storage system 1000 includes a controller 400 and a three-dimensional memory 300. The controller 400 is coupled to the three-dimensional memory 300 and is configured to control the three-dimensional memory 300 to store data.

[0059] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into the aforementioned electronic devices.

[0060] In some examples, please refer to Figure 1 The storage system 1000 includes a controller 400 and a three-dimensional memory 300; in other examples, please refer to Figure 2 The storage system 1000 includes a controller 400 and multiple three-dimensional memory units 300. For example, the storage system 1000 includes a controller 400 and four three-dimensional memory units 300. The storage system 1000 can be integrated into a memory card, or it can be integrated into a solid-state drive (SSD).

[0061] Among them, memory cards include one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0062] In some examples, in storage system 1000, controller 400 is configured to operate in low duty cycle environments, such as SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0063] In other examples, in storage system 1000, controller 400 is configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0064] In some examples, controller 400 can be configured to manage data stored in 3D memory 300 and communicate with external devices (such as a host).

[0065] In some examples, the controller 400 can also be configured to control the operation of the three-dimensional memory 300, such as read, erase, and program operations.

[0066] In some examples, controller 400 may also be configured to manage various functions related to data stored or to be stored in 3D memory 300, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0067] In some examples, controller 400 is also configured to process error correction codes for data read from or written to 3D memory 300.

[0068] It is readily understood that the controller 400 can also perform any other suitable function, such as formatting the three-dimensional memory 300. For example, the controller 400 can communicate with external devices (e.g., a host) via at least one of various interface protocols.

[0069] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0070] The aforementioned controller may be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0071] Some embodiments of this disclosure provide a three-dimensional memory 300. This three-dimensional memory 300 can be applied to the aforementioned storage system 1000; of course, it can also be applied to other storage systems, and this disclosure does not impose any limitations thereon.

[0072] In some examples, please refer to Figure 3 The three-dimensional memory 300 includes a semiconductor device 10 and peripheral devices 20.

[0073] For example, peripheral device 20 is located on one side of semiconductor device 10 and is electrically connected to semiconductor device 10.

[0074] Semiconductor device 10 and peripheral device 20 can be combined together by hybrid bonding or other means.

[0075] For example, the hybrid bonding may include both metal-metal bonding and dielectric-dielectric bonding.

[0076] For example, please continue reading Figure 3 The peripheral device 20 includes a substrate 201 and a peripheral circuit layer 202. The peripheral circuit layer 202 is located on the side of the substrate 201 close to the semiconductor device 10 and is electrically connected to the semiconductor device 10. The peripheral device 20 is configured to control and sense the semiconductor device 10.

[0077] It should be noted that the aforementioned peripheral device 20 includes one or more sub-circuits. Specifically, the aforementioned peripheral device 20 may include, for example, at least one of page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), and any active (or passive) components of the circuit (e.g., transistors, diodes, resistors, and capacitors).

[0078] The peripheral device 20 may also include any other circuitry compatible with advanced logic processes. For example, the peripheral device 20 includes logic circuitry (e.g., processors and programmable logic devices), and / or memory circuitry (e.g., static random access memory).

[0079] The aforementioned peripheral device 20 may include, for example, a plurality of transistors. Exemplarily, at least a portion of the transistors are formed in the substrate 201 (e.g., below the top surface of the substrate 201), and / or are formed directly on the substrate 201.

[0080] Furthermore, the substrate 201 described above may be made of a semiconductor material, such as silicon, germanium, and silicon-on-insulator thin film.

[0081] In one implementation, please refer to Figure 4 and Figure 5 The memory cell of the semiconductor device 10 has a 1T1C structure, that is, a memory cell includes a transistor T and a storage capacitor C.

[0082] For example, such as Figure 5As shown, the first electrode 01 of transistor T is connected to the bit line (BL), the gate 03 of transistor T is connected to the word line (WL), and the second electrode 02 of transistor T is connected to one of the lower plates 04 of storage capacitor C.

[0083] In addition, the storage capacitor C also includes an upper plate 05 and a storage function layer 06 located between the lower plate 04 and the upper plate 05.

[0084] In the semiconductor device 10 mentioned above, each memory cell can only store one bit of data. The storage capacity is small, which may cause the read and write speed of the memory to be unable to keep up with the processing speed of the processor, ultimately limiting the performance improvement of electronic products such as computers and mobile phones.

[0085] Based on this, some embodiments of this disclosure provide a semiconductor device 10, please refer to... Figure 6A and Figure 6B , Figure 6B for Figure 6A A cross-sectional view along A-A'. The semiconductor device 10 includes a substrate 1 and a first stacked structure 2 disposed on one side of the substrate 1.

[0086] In some examples, substrate 1 is a semiconductor substrate. For example, substrate 1 is a single-crystal silicon substrate, a single-crystal germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc. For another example, substrate 1 is a P-type doped polycrystalline silicon substrate or an N-type doped polycrystalline silicon substrate. For yet another example, substrate 1 is a gallium arsenide substrate, an indium phosphide substrate, or a silicon carbide substrate, etc.

[0087] In other examples, substrate 1 is made of a non-conductive material, which may include, for example, glass, plastic, or sapphire wafers.

[0088] In some examples, please refer to Figure 6B The first stacked structure 2 includes multiple alternating board line layers 21 and multiple first dielectric layers 22.

[0089] For example, the board line layer 21 may be made of a conductive material, which may include one or more of the following conductive materials: poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver); the first dielectric layer 22 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0090] It should be noted that in the first stacking structure 2, the thicknesses of the multiple first dielectric layers 22 can be approximately the same or different; the thicknesses of the multiple board line layers 21 can also be approximately the same or different; the choice can be made according to actual needs. Furthermore, the number of stacked board line layers 21 in the first stacking structure 2 determines the number of storage points 30 corresponding to the same storage column 3 as described below; the number of stacked layers in the first stacking structure 2 can be, for example, 32, 64, 96, 128, etc. The more stacked layers in the first stacking structure 2, the higher the integration, that is, the more storage points 30. Specifically, the number of stacked board line layers 21 and the stacking height in the first stacking structure 2 can be designed according to actual storage requirements; this disclosure does not impose specific limitations in this regard.

[0091] In some examples, please refer to [link / reference]. Figure 6B and Figure 6C , Figure 6C for Figure 6B A partial enlarged view of region B shows that the semiconductor device 10 also includes: a plurality of storage pillars 3 extending through the first stacked structure 2 to the substrate 1, and a plurality of transistors 4 disposed on the side of the first stacked structure 2 away from the substrate 1.

[0092] For example, the same storage column 3 corresponds to multiple storage points 30.

[0093] For example, the plurality of storage points 30 are arranged along a first direction Z perpendicular to the substrate 1.

[0094] For example, the storage column 3 includes a storage functional layer 31 and an inner electrode 32 arranged sequentially from the outside to the inside. For example, the storage functional layer 31 is located between the plurality of board line layers 21 and the inner electrode 32.

[0095] For example, both the storage function layer 31 and the internal electrode 32 extend along the first direction Z.

[0096] For example, the storage function layer 31 is tubular and surrounds the periphery of the inner electrode 32.

[0097] In this configuration, transistor 4 is electrically connected to the internal electrode 32. For example, the source of transistor 4 is electrically connected to the internal electrode 32. Similarly, the drain of transistor 4 is electrically connected to the internal electrode 32.

[0098] It should be noted that the drain or source of transistor 4 can be determined according to the direction of current flow.

[0099] Optionally, the internal electrode 32 may be made of a conductive material, such as one or more of the following: TiN (titanium nitride), TaN (tantalum nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), Pt (platinum).

[0100] For example, the storage function layer 31 is used to enable the semiconductor device 10 to perform storage functions.

[0101] For example, the portions of the storage function layer 31 and the internal electrode 32 that are opposite to the board line layer 21 form a storage point 30 with the board line layer 21.

[0102] In this process, the portion of each board line layer 21 surrounding the storage function layer 31 constitutes the external electrode of the storage point 30.

[0103] For example, the number of board line layers 21 is multiple, and each board line layer 21 forms a storage point 30 by surrounding a portion of the storage function layer 31 and by the portion of the storage function layer 31 and the inner electrode 32 opposite to the board line layer 21.

[0104] For example, the storage points 30 corresponding to the same storage column 3 share an inner electrode 32, which extends along a first direction Z perpendicular to the substrate 1, thereby enabling multiple storage points 30 to be arranged along the first direction Z perpendicular to the substrate 1.

[0105] For example, the material of the storage function layer 31 can include a variety of materials, as long as the storage function layer 31 can achieve the storage effect. The embodiments of this disclosure do not limit this.

[0106] For example, the storage layer 31 can be a ferroelectric layer, which may include a high-k (i.e., high dielectric constant) dielectric material, such as hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), tungsten oxide (WO3), molybdenum oxide (MO3), vanadium oxide (V2O3), lanthanum oxide (La2O3), and / or any combination thereof, of transition metal oxides. Furthermore, the high-k dielectric material may be doped. For example, the storage layer 31 may be HfO2 doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof.

[0107] For example, the portion of the board line layer 21 surrounding the storage function layer 31, and the portion of the storage function layer 31 and the internal electrode 32 opposite to the board line layer 21, form a ferroelectric capacitor, i.e., the aforementioned storage point 30. In this case, the three-dimensional memory 300 including the semiconductor device 10 is a ferroelectric memory.

[0108] Ferroelectric polarization is non-volatile because once polarization occurs, an external electric field cannot change the polarization direction until the magnitude of the electric field reaches a threshold (i.e., the coercive field Ec or the reverse coercive field -Ec). Ferroelectric RAMs use polarization reversal or switching effects and store digital bits "0" and "1" according to the direction of spontaneous polarization.

[0109] For example, a programming voltage Vp can be applied to the inner electrode 32 of the ferroelectric capacitor, and the outer electrode of the ferroelectric capacitor can be connected to the board line layer 21. When the programming voltage Vp changes from positive to negative (or vice versa), the polarization direction of the ferroelectric capacitor material can be switched. And the ferroelectric capacitor can be set or reset to a logic state "1" or "0".

[0110] Ferroelectric memories, as a novel type of memory, are increasingly widely used due to their advantages over traditional dynamic random access memory (DRAM), including non-volatility, high speed, and low power consumption. Existing ferroelectric memories mainly include ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) memories.

[0111] For example, multiple storage points 30 and transistors 4 corresponding to the same storage column 3 constitute the aforementioned storage cell.

[0112] For example, please refer to Figure 6D , Figure 6D The diagram shown is an equivalent circuit diagram of a plurality of storage points 30 and transistor 4 in a storage cell in the above embodiments of the present disclosure. Figure 6D Three storage points 30 are given as an example, but it is also possible to include two storage points 30 or more storage points 30.

[0113] For example, transistor 4 is electrically connected to one end of a plurality of storage points 30 (e.g., the inner electrode 32 of storage point 30); the other end of each storage point 30 (e.g., the outer electrode of storage point 30) is electrically connected to board line layer 21.

[0114] In the embodiments of this disclosure, by setting multiple stacked board line layers 21, each board line layer 21 surrounds a portion of the storage function layer 31, and the portions of the storage function layer 31 and the internal electrode 32 opposite to the board line layer 21 form storage points 30, thus obtaining a storage cell containing multiple storage points 30 and a transistor 4. One storage point 30 can be used to store 1 bit of data, and multiple storage points 30 can be used to store multiple bits of data. Therefore, compared with the storage cell of the 1T1C structure in the prior art, the storage capacity of the semiconductor device 10 is improved. On the other hand, in the embodiments of this disclosure, the transistor 4 is disposed on the side of the first stacked structure 2 away from the substrate 1. Compared with the prior art, where the transistor is formed on the substrate and is generated by epitaxy on the substrate, the substrate must be a semiconductor substrate, which leads to limited material selection for the substrate. In the embodiments of this disclosure, the requirements for the substrate 1 are reduced, and the substrate 1 only serves a supporting function.

[0115] In some embodiments, please continue reading Figure 6B and Figure 6C The semiconductor device 10 also includes a support pillar 33.

[0116] For example, the support column 33 extends along the first direction Z.

[0117] For example, the support post 33 may be cylindrical, with the inner electrode 32 surrounding the support post 33.

[0118] For example, the support column 33 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0119] By setting the support pillar 33, the transistor 4 can be supported, which facilitates the subsequent formation of multiple transistors 4 on the side of the first stacked structure 2 away from the substrate 1.

[0120] In some embodiments, please continue reading Figure 6B The semiconductor device 10 further includes at least one first isolation structure 5 extending through the first stacked structure 2 to the substrate 1.

[0121] For example, the first isolation structure 5 extends along the second direction Y.

[0122] In this case, the second direction Y is parallel to the substrate 1.

[0123] In some examples, at least one first isolation structure 5 divides the first stack structure 2 into multiple storage blocks 23.

[0124] For example, when there is one first isolation structure 5, the first isolation structure 5 can divide the first stacked structure 2 into two storage blocks 23; when there are N first isolation structures 5, N first isolation structures 5 can divide the first stacked structure 2 into N+1 storage blocks 23.

[0125] For example, each storage block 23 includes multiple storage strings 310, which are formed by multiple storage points 30 corresponding to the same storage column 3.

[0126] For example, such as Figure 6B As shown, storage points 30-1, 30-2, and 30-3 corresponding to the same storage column 3 form a storage string 310.

[0127] For example, the number of storage strings 310 included in each storage block 23 may be the same or different, and the embodiments of this disclosure do not limit this.

[0128] Furthermore, those skilled in the art can design the arrangement and number of storage strings 310 according to storage capacity requirements. In one embodiment, multiple storage strings 310 can be sequentially arranged in a third direction X, and multiple storage strings 310 can also be sequentially arranged in a second direction Y, thereby forming a three-dimensional storage array.

[0129] For example, please continue reading Figure 6D The gate of transistor 4 is electrically connected to word line WL, the second electrode of transistor 4 is electrically connected to bit line BL, the first end of a plurality of storage points 30 (e.g., the inner electrode 32 of storage point 30) is electrically connected to the first electrode of transistor 4, and the second end of each storage point 30 (e.g., the outer electrode of storage point 30) is electrically connected to board line layer 21.

[0130] For example, the reading phase of each storage string 310 includes a first reading phase, a second reading phase, and a third reading phase.

[0131] During the first read phase, the word line WL is used to receive the word line control signal to turn on the transistor 4, and the bit line BL is used to receive the bit line control signal to precharge the voltage of the internal electrode 32 of the storage point 30.

[0132] In the second read phase, the word line WL is used to receive another word line control signal, causing transistor 4 to turn off. The board line layer 21, which is electrically connected to the selected memory point 30, is used to receive the board line control signal. The voltage difference between the board line control signal on the portion of the board line layer 21 surrounding the memory function layer 31 and the bit line control signal on the internal electrode 32 may cause the memory function layer 31 of the selected memory point 30 to remain unchanged (e.g., when the memory function layer 31 is a ferroelectric layer, the polarization direction of the ferroelectric layer remains unchanged), or it may cause the memory function layer 31 of the selected memory point 30 to change (e.g., when the memory function layer 31 is a ferroelectric layer, the polarization direction of the ferroelectric layer is reversed to release polarization charge, causing the voltage on the bit line to change).

[0133] In the third reading stage, the word line WL is used to receive the word line control signal, which turns on the transistor 4, detects the voltage or current on the bit line BL, determines whether the selected storage point 30 has changed in the storage function layer 31, and then reads the information stored therein.

[0134] When the system needs to read data, it first selects a row of storage strings 310 in storage block 23, and then further selects a storage point 30. When the semiconductor device 10 includes multiple storage blocks 23, it can simultaneously select one storage point 30 in each storage block 23 and simultaneously read the multi-bit data stored in the multiple storage points 30, which further meets the system requirements and improves the usability of the three-dimensional memory 300 of the semiconductor device 10 provided in the above embodiment.

[0135] In some examples, please refer to [link / reference]. Figure 6B Multiple first isolation structures 5 divide the first stack structure 2 into 8n storage blocks 23, where n is a positive integer and n≥1. For example, multiple first isolation structures 5 divide the first stack structure 2 into 8 storage blocks 23, 16 storage blocks 23, 24 storage blocks 23, etc. Figure 6B For example, multiple first isolation structures 5 are given to divide the first stacking structure 2 into 8 storage blocks 23.

[0136] For example, the three-dimensional memory 300 of the semiconductor device 10 provided in the above embodiments can store 4096 bits of data. When the first stacked structure 2 is divided into eight storage blocks 23 by multiple first isolation structures 5, each storage block 23 can store 512 bits of data. Figure 6E Show.

[0137] For example, such as Figure 6EAs shown, when the semiconductor device 10 includes eight storage blocks 23, the system can simultaneously read the data stored in one storage point 30 of each storage block 23, that is, the system can simultaneously read 8 bits of data stored in 8 storage points 30.

[0138] In this embodiment, by dividing the first stacking structure 2 into 8n storage blocks 23, the data transmission between the three-dimensional memory 300 including the semiconductor device 10 provided in the above embodiment and the system can be satisfied, so that the three-dimensional memory 300 and the system can transmit multi-bit data simultaneously, such as 8 bits, 16 bits, 24 bits, etc., which further meets the system requirements and improves the usability of the three-dimensional memory 300 including the semiconductor device 10 provided in the above embodiment.

[0139] In some embodiments, the material of the first isolation structure 5 may be an insulating material, which may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0140] Silicon oxide, silicon nitride, and silicon oxynitride are all inorganic insulating materials that effectively divide the first stacked structure 2 into multiple storage blocks 23, ensuring that adjacent storage blocks 23 are mutually insulated. Multiple storage points 30 within the multiple storage blocks 23 can be selected simultaneously, allowing for the simultaneous reading of multiple bits of data stored in those storage points 30. In some embodiments, please refer to... Figure 3 and Figure 6A The aforementioned storage block 23 has a core area C and a step area SS arranged sequentially along the second direction Y.

[0141] For example, multiple storage strings 310 are located in core area C, which can be used to implement storage functions.

[0142] For example, please continue reading Figure 3 The portion of the multiple board line layers 21 located in the step region SS is stepped. This stepped structure can be formed by performing multiple trim-etch cycles on multiple board line layers.

[0143] For example, the step region SS can be the electrical connection region of the board wire layer 21.

[0144] For example, when the first stack structure 2 includes a plurality of storage blocks 23, each storage block 23 has a core area C and a step area SS arranged sequentially along the second direction Y.

[0145] With the above configuration, each storage block 23 can have a complete set of steps. The step area SS serves as the electrical connection area of ​​the board line layer 21, which makes it easier for the board line layer 21 to transmit board line control signals to the selected storage point 30.

[0146] In some embodiments, please continue reading Figure 3 The semiconductor device 10 also includes: multiple contacts 6.

[0147] For example, multiple contacts 6 can be located in the stepped area SS.

[0148] In some examples, please refer to [link / reference]. Figure 3 Contact 6 extends along the first direction Z and contacts the plate line layer 21. The first direction Z is perpendicular to the substrate 1.

[0149] For example, contact 6 may include a conductive material, which may include at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, doped monocrystalline silicon, and silicide.

[0150] With the above configuration, contact 6 is electrically connected to board wire layer 21, enabling board wire control information to be transmitted to board wire layer 21 through contact 6, thereby realizing the reading and writing of stored information in core area C.

[0151] In some embodiments, please continue reading Figure 6B The semiconductor device 10 includes: a second stacked structure 7 disposed on the side of the first stacked structure 2 away from the substrate 1, and a plurality of channel structures 8 extending through the second stacked structure 7 to the first stacked structure 2.

[0152] In some examples, the second stack structure 7 includes a word line layer 71 and second dielectric layers 72 located on opposite sides of the word line layer 71.

[0153] For example, both word line layer 71 and the second dielectric layer 72 are planar structures, and the plane where word line layer 71 is located and the plane where the second dielectric layer 72 is located are both parallel to the plane where substrate 1 is located.

[0154] For example, the word line layer 71 is made of a conductive material, such as a metallic material. In alternative embodiments, it can be one or more of the following conductive materials: poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver).

[0155] For example, the second dielectric layer 72 may be made of an insulating material, which may include at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0156] In some examples, multiple channel structures 8 are configured in a one-to-one correspondence with multiple storage columns 3.

[0157] In some examples, please refer to [link / reference]. Figure 6B and Figure 6CThe aforementioned channel structure 8 includes a gate dielectric layer 81 and a channel layer 82 arranged sequentially.

[0158] The gate dielectric layer 81 is located between the word line layer 71 and the channel layer 82.

[0159] For example, the channel layer 82 has a cylindrical structure and extends along a first direction Z perpendicular to the substrate 1.

[0160] For example, the gate dielectric layer 81 is tubular and surrounds the periphery of the channel layer 82.

[0161] For example, a portion of the gate dielectric layer 81, the channel layer 82, and the word line layer 71 surrounding the gate dielectric layer 81 forms a transistor 4.

[0162] For example, the word line layer 71 surrounds a portion of the gate dielectric layer 81 to form the gate of transistor 4. The channel layer 82 is in contact with the internal electrode 32, and the portion of the channel layer 82 in contact with the internal electrode 32 forms the source or drain of transistor 4. Exemplarily, the material of the channel layer 82 can be one or more of semiconductor materials such as Si (silicon), poly-Si (p-Si), amorphous-Si (a-Si), In-Ga-Zn-O (IGZO), ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), and WS2 (tungsten disulfide).

[0163] For example, the gate dielectric layer 81 can be made of one or more insulating materials such as SiO2 (silicon dioxide), Al2O3 (alumina), HfO2 (hafnium dioxide), ZrO2 (zirconia), TiO2 (titanium dioxide), Y2O3 (yttrium oxide), and Si3N4 (silicon nitride). Thus, by bringing the channel layer 82 into contact with the inner electrode 32, electrical connections are achieved between the transistor 4 and the inner electrodes 32 of multiple storage points 30 belonging to the same memory cell. When the transistor 4 is turned on under the control of the word line control signal received by the word line layer 71, the bit line control signal can pass through the transistor 4 and pre-charge the voltage of the inner electrode 32 of the storage point 30.

[0164] In some embodiments, the material of the channel layer 82 includes polycrystalline silicon.

[0165] For example, the gate dielectric layer 81 and the channel layer 82 can be sequentially formed by thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0166] In related technologies, transistors are formed on a substrate. Generally, the channel layer of a transistor is made of monocrystalline silicon. In this case, the transistor is epitaxially generated on the substrate, and the manufacturing process is relatively complex. However, in the embodiments of this disclosure, the transistor 4 is disposed on the side of the first stacked structure 2 away from the substrate 1, and the channel layer 82 is made of polycrystalline silicon. The channel layer 82 is formed by thin film deposition processes such as CVD, PVD or ALD. Compared with the silicon epitaxial growth method used in related technologies to prepare the channel layer, the process difficulty is reduced.

[0167] In some embodiments, please refer to Figure 6A The semiconductor device 10 also includes: a plurality of second isolation structures 9.

[0168] For example, multiple second isolation structures 9 extend through the second stacked structure 7 to the first stacked structure 2.

[0169] In some examples, please refer to [link / reference]. Figure 6F , Figure 6F for Figure 6A A cross-sectional view along B-B'. Multiple second isolation grooves 9 are arranged sequentially along the second direction Y, and all extend along the third direction X.

[0170] Among them, the third direction X and the second direction Y are both parallel to the substrate 1 and intersect each other.

[0171] In some examples, please refer to [link / reference]. Figure 6A Multiple second isolation structures 9 divide the word line layer 71 into multiple word lines 711.

[0172] For example, there are three second isolation structures 91, which divide the word line layer 71 into four word lines 711. The number of second isolation structures 91 can also be two or more, and the embodiments of this disclosure do not limit this.

[0173] For example, transistors 4 electrically connected to the same word line 711 can be turned on or off simultaneously under the word line control signal transmitted on the word line 711. By dividing the word line layer 71 into multiple word lines 711, individual control of each part of the transistors 4 can be achieved.

[0174] In some embodiments, the semiconductor device 10 further includes a bit line layer 11 located on the side of the second stacked structure 7 away from the substrate 1, such as... Figure 7 As shown.

[0175] In some examples, such as Figure 7 As shown, the bit line layer 11 includes multiple bit lines 110 extending along the second direction Y and arranged sequentially along the third direction X.

[0176] For example, there can be multiple transistors 4 connected to a bit line 110. When transistor 4 is turned on under the control of the word line control signal transmitted by word line 711, the bit line control signal received by bit line 110 can pass through transistor 4 to precharge the voltage of the internal electrode 32 of storage point 30.

[0177] For example, multiple transistors 4 are arranged in multiple rows along the third direction X and in multiple columns along the second direction Y.

[0178] For example, among a plurality of transistors 4 located in the same row, the channel layer 82 of the odd number of transistors 4 is electrically connected to the same bit line 110, and the channel layer 82 of the even number of transistors 4 is electrically connected to the same bit line 110.

[0179] For example, when transistor 4 is turned on under the control of word line control signal transmitted by word line 711, bit line 110 is used to receive bit line control signal to precharge the voltage of internal electrode 32 of storage point 30.

[0180] In some embodiments, such as Figure 7 As shown, the semiconductor device 10 also includes a bridging layer 12 located between the second stacked structure 7 and the bit line layer 11.

[0181] In some examples, such as Figure 7 As shown, the bridging layer 12 includes a plurality of bridging sections 120.

[0182] For example, the bridging portion 120 corresponds one-to-one with the transistor 4. One end of the bridging portion 120 is in contact with the channel layer 82 of the transistor 4, and the other end is in contact with the bit line 110.

[0183] For example, the bridging portion 120 is made of a conductive material, such as a metal. The metal material can be one or more of the following conductive materials: TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver).

[0184] For example, the materials of the bridging portion 120 and the bit line 110 can be the same or different, and the embodiments of this disclosure do not limit this. When the materials of the bridging portion 120 and the bit line 110 are the same, the bridging portion 120 and the bit line 110 can be formed by the same process, which helps to simplify the process flow of the semiconductor device 10 and reduce the cost of the semiconductor device 10.

[0185] Thus, the connection between bit line 110 and transistor 4 is realized through bridging part 120. The channel layer 82 of transistor 4 is in contact with the inner electrode 32. Therefore, when transistor 4 is turned on, the bit line control signal transmitted by bit line 110 can pass through transistor 4 to precharge the voltage of the inner electrode 32 of storage point 30.

[0186] In some embodiments, the material of the storage functional layer 31 is a ferroelectric material, an antiferroelectric material, a phase change material, or a magnetic material.

[0187] For example, when the material of the storage functional layer 31 is a ferroelectric material, the portion of the plate wire layer 21 surrounding the storage functional layer 31 and the portion of the storage functional layer 31 and the inner electrode 32 opposite to the plate wire layer 21 form a ferroelectric capacitor, namely the aforementioned storage point 30.

[0188] For example, ferroelectric materials have nonlinear characteristics. The dielectric constant of ferroelectric materials can not only be adjusted, but the difference between the polarization states of the ferroelectric layer containing the ferroelectric material and the polarization state is very large. This makes ferroelectric capacitors smaller in size compared to other capacitors, for example, much smaller than the capacitors used to store charge in DRAM, which is beneficial for achieving high-density storage.

[0189] For example, the ferroelectric material can be one or more of the following: ZrO2, HfO2, Al-doped HfO2, Si-doped HfO2, Zr-doped HfO2, La-doped HfO2, Y-doped HfO2, etc., or materials based on such materials but doped with other elements.

[0190] For example, antiferroelectric materials have better stability and can effectively avoid wake-up effects, imprinting effects and polarization fatigue. Applying antiferroelectric materials to memory will result in better data retention characteristics.

[0191] For example, antiferroelectric materials can be PbZrO3, NH4H2PO4 (ADP), (NH4)2SO4, (NH4)2H3O6, perovskite, and RbNO3, etc.

[0192] For example, when the material of the storage functional layer 31 is a phase change material, the three-dimensional memory 300 including the semiconductor device 10 can be called a phase change memory.

[0193] The basic principle of phase-change memory (PCM) is to store "1" and "0" values ​​during the read phase by utilizing the reversible change of phase change material between high and low resistance. By controlling the continuous change in resistance of the phase change material using plate-line control signals, multi-level storage can be achieved, thus significantly increasing the memory's information storage capacity. In PCM, the reversible change of phase change material between amorphous and polycrystalline states is used to achieve this resistance change.

[0194] For example, the phase change material can be Ge-Sb-Te, Si-Sb-Te, Ag-In-Sb-Te, etc.

[0195] For example, the material of the storage functional layer 31 is a magnetic material. At this time, the substrate 1 can be a flexible substrate. Stress can be generated by deforming the flexible substrate. The magnetic material is very sensitive to stress. Under the action of stress, a magnetic transformation effect is generated, changing from antiferromagnetism to ferromagnetism. After the writing process is completed, the deformation of the flexible substrate disappears, the stress disappears, and the magnetic material changes from ferromagnetic state to antiferromagnetic state. Thus, the magnetic switching of the magnetic material is used to realize the writing of stored data.

[0196] For example, the magnetic material includes one or more of FeRh, Mn3GaC, and NiCoMnIn.

[0197] Some embodiments of this disclosure also provide a method for fabricating a semiconductor device, which can be applied, for example, to the semiconductor device 10 in any of the above embodiments.

[0198] Please see Figure 8 The above preparation method includes the following steps S1 to S7.

[0199] S1: As Figure 9A As shown, substrate 1 is provided.

[0200] The material and other related descriptions of the substrate 1 can be found in the descriptions of some of the above embodiments, and will not be repeated here.

[0201] S2: As Figure 9B As shown, a first stacked structure 2 is formed on one side of the substrate 1. The first stacked structure 2 includes a plurality of alternating line layers 21 and a plurality of first dielectric layers 22.

[0202] In some examples, a first stacked structure 2 can be formed on a substrate 1 using a thin film deposition process. For example, the thin film deposition process may include one or a combination of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0203] In some examples, step S2 includes steps S21 and S22.

[0204] S21: A plurality of alternating plate line layers 21 and a plurality of first dielectric layers 22 are formed on the substrate 1.

[0205] Multiple plate line layers 21 and multiple first dielectric layers 22 can be formed using thin film deposition processes.

[0206] S22: Pattern the portion of the plate line layer 21 located in the step area SS to form a step structure.

[0207] For example, the stepped structure can be formed by performing multiple trim-etch cycles on multiple board line layers 21.

[0208] After the above process, the region corresponding to the step structure formed by multiple plate line layers 21 on the substrate 1 can be called the step region SS of the semiconductor device 10.

[0209] S3: As Figure 9C As shown, a plurality of receiving holes 03 are formed through the first stacked structure 2 to the substrate 1.

[0210] Figure 9C (a) is a cross-sectional view of the substrate 1 and the first stacked structure 2. Figure 9C (b) in the middle is Figure 9C The top view of (a) in the image.

[0211] For example, the plurality of receiving holes 03 can be formed using a dry etching process or a wet etching process. The receiving holes 03 can extend along the first direction Z toward the substrate 1.

[0212] S4: As Figure 9D As shown, a storage functional layer 31 and an internal electrode 32 are sequentially formed within multiple receiving holes 03 to form multiple storage pillars 3.

[0213] For example, the same storage column 3 corresponds to multiple storage points 30.

[0214] For example, the plurality of storage points 30 are arranged along a first direction Z perpendicular to the substrate 1.

[0215] For example, storage points 30 corresponding to the same storage column 3 share the same internal electrode 32.

[0216] The storage function layer 31 is located between multiple board line layers 21 and the internal electrode 32.

[0217] For example, both the storage function layer 31 and the internal electrode 32 extend along the first direction Z.

[0218] For example, the storage function layer 31 is tubular and surrounds the periphery of the inner electrode 32.

[0219] For example, the portions of the storage function layer 31 and the internal electrode 32 that are opposite to the board line layer 21 form a storage point 30 with the board line layer 21.

[0220] For example, both the storage functional layer 31 and the internal electrode 32 can be formed by chemical vapor deposition (CVD) (e.g., metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), etc.). The storage functional layer 31 and the internal electrode 32 can also be formed by atomic layer deposition (ALD), sputtering, evaporation, or any combination thereof.

[0221] In some examples, step S4 further includes forming a support post 33 within a plurality of receiving holes 03.

[0222] For example, the support pillar 33 can be cylindrical, and the inner electrode 32 surrounds the support pillar 33. By forming the support pillar 33, the transistor 4 can be supported, which facilitates the subsequent formation of multiple transistors 4 on the side of the first stacked structure 2 away from the substrate 1.

[0223] S5: As Figure 9E As shown, at least one first isolation trench 05 is formed through the first stacked structure 2 to the substrate 1.

[0224] Figure 9E (a) is a cross-sectional view of the substrate 1 and the first stacked structure 2. Figure 9E (b) in the middle is Figure 9E The top view of (a) in the image.

[0225] In this configuration, at least one first isolation trench 05 is arranged sequentially along the third direction X and extends along the second direction Y; the third direction X and the second direction Y are parallel to the substrate 1 and intersect each other.

[0226] For example, the plurality of first isolation trenches 05 can be formed using a dry etching process or a wet etching process. The first isolation trenches 05 can extend along the first direction Z toward the substrate 1.

[0227] S6: As Figure 9F As shown, a first isolation structure 5 is formed within the first isolation groove 05.

[0228] The description of the materials and other related aspects of the first isolation structure 5 can be found in the descriptions of some of the above embodiments, and will not be repeated here.

[0229] In some examples, multiple first isolation structures 5 divide the first stack structure 2 into multiple storage blocks 23.

[0230] For example, such as Figure 9F As shown, multiple first isolation structures 5 divide the first stack structure 2 into 8n storage blocks 23, where n is a positive integer and n≥1. For example, multiple first isolation structures 5 divide the first stack structure 2 into 8 storage blocks 23.

[0231] For example, multiple storage points 30 included in the same storage column 3 form a storage string 310. Each storage block 23 includes multiple storage strings 310.

[0232] For example, the number of storage strings 310 included in each storage block 23 can be the same or different. By dividing the first stacking structure 2 into 8n storage blocks 23, the data transmission between the three-dimensional memory 300 including the semiconductor device 10 provided in the above embodiments and the system can be satisfied, so that the three-dimensional memory 300 and the system can transmit multi-bit data simultaneously, such as 8 bits, 16 bits, 24 bits, etc., further meeting the system requirements and improving the usability of the three-dimensional memory 300 including the semiconductor device 10 provided in the above embodiments.

[0233] S7: As Figures 9G to 9I As shown, a plurality of transistors 4 are formed on the side of the first stacked structure 2 away from the substrate 1, and the first electrode of the transistor 4 is electrically connected to the inner electrode 32.

[0234] In some examples, step S7 includes steps S71 to S73.

[0235] S71: As Figure 9G As shown, a second stacked structure 7 is formed on the side of the first stacked structure 2 away from the substrate 1. The second stacked structure 7 includes a word line layer 71 and second dielectric layers 72 located on opposite sides of the word line layer 71.

[0236] In some examples, a thin-film deposition process can be used to form a second stacked structure 7 on the side of the first stacked structure 2 away from the substrate 1. For example, the thin-film deposition process may include one or more combinations of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0237] For example, the orthographic projection of the second stacked structure 7 on the substrate 1 is located within the orthographic projection of the first stacked structure 2 on the substrate 1.

[0238] S72: As Figure 9H As shown, a plurality of channel holes 08 are formed through the second stacked structure 7 to the first stacked structure 2. Among them, the channel holes 08 expose the internal electrode 32 located in the receiving hole 03.

[0239] Figure 9H(a) is a cross-sectional view of the substrate 1, the first stacked structure 2, and the second stacked structure 7. Figure 9H (b) in the middle is Figure 9H The top view of (a) in the image.

[0240] For example, the channel holes 08 are arranged in multiple rows along the third direction X and in multiple columns along the second direction Y. Consequently, the transistors 4, which correspond one-to-one with the channel holes 08, are also arranged in multiple rows along the third direction X and in multiple columns along the second direction Y.

[0241] For example, the plurality of channel holes 08 can be formed using a dry etching process or a wet etching process. The channel holes 08 can extend along the first direction Z toward the substrate 1.

[0242] For example, the formed multiple channel holes 08 are configured to correspond one-to-one with multiple receiving holes 03.

[0243] S73: As Figure 9I As shown, a gate dielectric layer 81 and a channel layer 82 are sequentially formed within a plurality of channel holes 08 to form a plurality of channel structures 8. Figure 9I (a) in the figure is a cross-sectional view of the semiconductor device 10 in this embodiment. Figure 9I (b) in the middle is Figure 9I The top view of (a) in the image.

[0244] For example, a thin film deposition process such as chemical vapor deposition (CVD), PVD, ALD, or any combination thereof can be used to sequentially deposit the gate dielectric layer 81 and the channel layer 82 within the aforementioned receiving holes.

[0245] For example, the amount of filler gate dielectric layer 81 and channel layer 82 can be controlled by controlling the etching time or the type of plasma in the etching gas.

[0246] The gate dielectric layer 81 is located between the word line layer 71 and the channel layer 82.

[0247] For example, the channel layer 82 has a cylindrical structure and extends along a first direction Z perpendicular to the substrate 1.

[0248] For example, the gate dielectric layer 81 is tubular and surrounds the periphery of the channel layer 82.

[0249] For example, a portion of the gate dielectric layer 81, the channel layer 82, and the word line layer 71 surrounding the gate dielectric layer 81 forms a transistor 4.

[0250] For example, the word line layer 71 surrounds a portion of the gate dielectric layer 81 to form the gate of the transistor 4. The channel layer 82 is in contact with the inner electrode 32, and the portion of the channel layer 82 in contact with the inner electrode 32 forms the source or drain of the transistor 4. Exemplarily, the channel layer 82 has a cylindrical structure and extends along a first direction Z perpendicular to the substrate 1.

[0251] Thus, by bringing the channel layer 82 of the plurality of transistors 4 formed on the side of the first stacked structure 2 away from the substrate 1 into contact with the inner electrode 32, the transistors 4 are electrically connected to the inner electrodes 32 of the plurality of storage points 30 belonging to the same storage cell.

[0252] The preparation methods in the above embodiments of this disclosure have the same structure and beneficial effects as the semiconductor device 10 provided in some of the above embodiments, and will not be repeated here.

[0253] In some embodiments, after forming a plurality of transistors 4 on the side of the first stacked structure 2 away from the substrate 1, the above-described fabrication method further includes: S8 to S9.

[0254] S8: Form a second isolation trench 09 that extends through the second stacked structure 7 to the first stacked structure 2.

[0255] For example, a plurality of second isolation trenches 09 are arranged sequentially along the second direction Y, and all extend along the third direction X. The third direction X and the second direction Y are both parallel to the substrate 1 and intersect each other.

[0256] In some examples, please refer to Figure 9I The projection of the second isolation trench 09 onto the substrate 1 has a wavy shape. This allows the second isolation trench 09 to avoid interfering with the performance of the transistor 4.

[0257] S9: A second isolation structure 9 is formed within the second isolation groove 09.

[0258] For example, the materials and other related descriptions of the second isolation structure 9 can be referred to the descriptions in some of the above embodiments, and will not be repeated here.

[0259] For example, multiple second isolation structures 9 divide the word line layer 71 into multiple word lines 711.

[0260] For example, transistors 4 electrically connected to the same word line 711 can be turned on or off simultaneously under the word line control signal transmitted by the word line 711. By dividing the word line layer 71 into multiple word lines 711, individual control of each part of the transistors 4 can be achieved.

[0261] In some embodiments, after forming a plurality of transistors 4 on the side of the first stacked structure 2 away from the substrate 1, the above-described fabrication method further includes: Figure 9J As shown, a bit line layer 11 is formed on the side of the second stacked structure 7 away from the substrate 1.

[0262] Figure 9J (a) in the figure is a cross-sectional view of the semiconductor device 10 in this embodiment. Figure 9J (b) in the middle is Figure 9J The top view of (a) in the image.

[0263] For example, a bit line layer 11 can be formed on the side of the first stacked structure 2 away from the substrate 1 using a thin film deposition process. For example, the thin film deposition process can include one or more combinations of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0264] For example, such as Figure 9J As shown, the bit line layer 11 includes multiple bit lines 110 extending along a second direction and arranged sequentially along a third direction.

[0265] For example, multiple transistors 4 are arranged in multiple rows along the third direction X and in multiple columns along the second direction Y.

[0266] For example, among a plurality of transistors 4 located in the same column, the channel layer 82 of the odd number of transistors 4 is electrically connected to the same bit line 110, and the channel layer 82 of the even number of transistors 4 is electrically connected to the same bit line 110.

[0267] For example, the number of transistors 4 connected to a bit line 110 can be multiple.

[0268] In some examples, multiple transistors 4 are arranged in multiple rows along a third direction X and in multiple columns along a second direction Y. Among the multiple transistors 4 located in the same column, the channel layer 82 of the odd number of transistors 4 is electrically connected to the same bit line 110, and the channel layer 82 of the even number of transistors 4 is electrically connected to the same bit line 110.

[0269] For example, when transistor 4 is turned on under the control of the word line control signal transmitted by word line 711, the bit line control signal received by bit line 110 can pass through transistor 4 to precharge the voltage of the internal electrode 32 of storage point 30.

[0270] In some embodiments, before forming the bit line layer 11 on the side of the second stacked structure 7 away from the substrate 1, the above-described fabrication method further includes forming a bridging layer 12 between the second stacked structure 7 and the bit line layer 11.

[0271] For example, such as Figure 9J As shown, the bridging layer 12 includes a plurality of bridging sections 120.

[0272] For example, the bridging portion 120 and the bit line 110 can be made of the same material. The method for forming the bridging layer 12 can include: forming a dielectric layer on the side of the second stacked structure 7 away from the substrate 1; forming a plurality of grooves on the side of the dielectric layer away from the second stacked structure 7; forming vias within the grooves, the vias exposing the channel layer 82 of each transistor 4; depositing metal material within each via and groove; the metal material in each via forming the bridging portion 120; and the metal material in each groove forming the bit line 110. This allows for the simultaneous formation of the bridging portion 120 and the bit line 110, which further simplifies the fabrication process of the semiconductor device 10 and reduces the cost of fabricating the semiconductor device 10.

[0273] It should be noted that the grooves can be strip-shaped, and multiple grooves can extend along the second direction Y and be arranged sequentially along the third direction X.

[0274] One end of the bridging portion 120 is in contact with the channel layer 82 of the transistor 4, and the other end is in contact with the bit line 110. Thus, the connection between the bit line 110 and the transistor 4 is realized through the bridging portion 120. The channel layer 82 of the transistor 4 is in contact with the inner electrode 32. Therefore, when the transistor 4 is turned on, the signal transmitted by the bit line 110 can pass through the transistor 4 to precharge the voltage of the inner electrode 32 of the selected storage point 30.

[0275] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: Substrate; A first stacked structure is disposed on one side of the substrate, the first stacked structure comprising a plurality of alternating plate line layers and a plurality of first dielectric layers; Multiple memory pillars penetrate the first stacked structure, with each memory pillar corresponding to multiple memory points, and the multiple memory points are arranged along a first direction perpendicular to the substrate; The storage column includes a storage functional layer, an inner electrode, and a support column arranged sequentially from the outside to the inside. The storage functional layer is located between the plurality of plate wire layers and the inner electrode, and the inner electrode surrounds the support column. The support column is made of an insulating material. The portions of the storage functional layer and the internal electrode that are opposite to the board line layer form a storage point with the board line layer; multiple storage points corresponding to the same storage column share the internal electrode; and... A plurality of transistors are disposed on the side of the first stacked structure away from the substrate, and the transistors are electrically connected to the inner electrode.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: at least one first isolation structure extending through the first stacked structure to the substrate, the first isolation structure extending along a second direction parallel to the substrate; The at least one first isolation structure divides the first stacked structure into a plurality of memory blocks arranged along a third direction; wherein the third direction is parallel to the substrate and intersects the second direction.

3. The semiconductor device according to claim 2, characterized in that, There are multiple first isolation structures, and the multiple first isolation structures divide the first stack structure into 8n storage blocks; Where n is a positive integer and n≥1.

4. The semiconductor device according to claim 2, characterized in that, The material of the first isolation structure includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

5. The semiconductor device according to claim 2, characterized in that, The storage block has a core area and a stepped area arranged sequentially along the second direction; the storage block includes multiple storage strings; the storage string is formed by multiple storage points corresponding to the same storage column; Multiple of the aforementioned storage strings are located in the core area; The portion of the multiple plate-line layers located in the stepped area is stepped.

6. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: multiple contacts; The contact point extends along the first direction and is in contact with the plate line layer.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes: a second stacked structure disposed on the side of the first stacked structure away from the substrate, and a plurality of channel structures extending through the second stacked structure to the first stacked structure; The second stacked structure includes: a word line layer; and, The second dielectric layer is located on both sides of the word line layer; The channel structure includes a gate dielectric layer and a channel layer arranged sequentially, the gate dielectric layer being located between the word line layer and the channel layer, and the portion of the gate dielectric layer, the channel layer, and the word line layer surrounding the gate dielectric layer forming the transistor.

8. The semiconductor device according to claim 7, characterized in that, The channel layer is made of polycrystalline silicon.

9. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes: A plurality of second isolation structures extend through the second stacked structure to the first stacked structure. The plurality of second isolation structures are arranged sequentially along a second direction and all extend along a third direction. The third direction and the second direction are both parallel to the substrate and intersect each other. The second isolation structure divides the word line layer into multiple word lines.

10. The semiconductor device according to claim 7, characterized in that, The semiconductor device further includes: a bit line layer located on the side of the second stacked structure away from the substrate, the bit line layer including a plurality of bit lines extending along a second direction and arranged sequentially along a third direction; the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects the second direction; The bit line is electrically connected to a plurality of transistors.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: A bridging layer located between the second stacked structure and the bit line layer, the bridging layer including a plurality of bridging portions, one end of the bridging portion being in contact with the channel layer of the transistor and the other end being in contact with the bit line.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that, The material of the storage functional layer is a ferroelectric material, an antiferroelectric material, a phase change material, or a magnetic material.

13. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: Provide substrate; A first stacked structure is formed on one side of the substrate, the first stacked structure comprising a plurality of alternating plate line layers and a plurality of first dielectric layers; A plurality of receiving holes are formed extending through the first stacked structure to the substrate; A storage functional layer, an internal electrode, and a support pillar are sequentially formed within the receiving hole to form a storage pillar. Each storage pillar corresponds to multiple storage points, and the multiple storage points are arranged along a first direction perpendicular to the substrate. The support pillar is made of an insulating material. The storage function layer is located between the plurality of board line layers and the inner electrode. The portion of the storage function layer and the inner electrode that is opposite to the board line layer forms a storage point with the board line layer. Multiple storage points corresponding to the same storage column share the inner electrode. A plurality of transistors are formed on the side of the first stacked structure away from the substrate, and the transistors are electrically connected to the internal electrode.

14. The preparation method according to claim 13, characterized in that, Before forming a plurality of transistors on the side of the first stacked structure away from the substrate, the fabrication method further includes: At least one first isolation trench is formed, extending through the first stacked structure to the substrate; the isolation trenches are arranged sequentially along a third direction and all extend along a second direction; the third direction and the second direction are both parallel to the substrate and intersect each other; A first isolation structure is formed within the first isolation slot; at least one of the first isolation structures divides the first stacked structure into a plurality of storage blocks arranged along the third direction.

15. The preparation method according to claim 13, characterized in that, The formation of a plurality of transistors on the side of the first stacked structure away from the substrate includes: A second stacked structure is formed on the side of the first stacked structure away from the substrate; the second stacked structure includes: a word line layer and second dielectric layers located on opposite sides of the word line layer; A plurality of channel holes are formed extending from the second stack structure to the first stack structure; the channel holes expose internal electrodes located within the receiving holes; A gate dielectric layer and a channel layer are sequentially formed within a plurality of channel vias to form a channel structure; the gate dielectric layer is located between the word line layer and the channel layer, and the portion of the gate dielectric layer, the channel layer, and the word line layer surrounding the gate dielectric layer forms the transistor.

16. The preparation method according to claim 15, characterized in that, The preparation method further includes: A plurality of second isolation trenches are formed, extending through the second stacked structure to the first stacked structure. The plurality of second isolation trenches are arranged sequentially along a second direction and all extend along a third direction. The third direction and the second direction are both parallel to the substrate and intersect each other. A second isolation structure is formed within the second isolation groove; multiple second isolation structures divide the word line layer into multiple word lines.

17. The preparation method according to claim 16, characterized in that, The preparation method further includes: A bit line layer is formed on the side of the second stacked structure away from the substrate; the bit line layer includes a plurality of bit lines extending along the second direction and arranged sequentially along the third direction; the bit lines are electrically connected to a plurality of transistors.

18. The preparation method according to claim 17, characterized in that, Before forming the bit line layer on the side of the second stacked structure away from the substrate, the fabrication method further includes: A bridging layer is formed on the side of the second stacked structure away from the substrate; the bridging layer includes a plurality of bridging portions, one end of which is in contact with the channel layer of the transistor and the other end of which is in contact with the bit line.

19. A three-dimensional memory, characterized in that, include: A semiconductor device, wherein the semiconductor device is the semiconductor device as described in any one of claims 1 to 12; Peripheral devices, which are located on the side of the transistor in the semiconductor device away from the substrate and are electrically connected to the transistor.

20. A storage system, characterized in that, include: A three-dimensional memory, wherein the three-dimensional memory is the three-dimensional memory as described in claim 19; A controller is coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

21. An electronic device, characterized in that, Including the storage system as described in claim 20.

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