Amplitude limiter chip based on interdigitated structure

Abstract

The application relates to the technical field of microwave power limiter circuit, and provides a finger structure-based limiter chip, which comprises a substrate, an input end (100), an output end (200), a finger structure limiter (300) and a matching circuit (400) arranged on the substrate; the input end (100), the output end (200) and the finger structure limiter (300) are connected through the matching circuit (400), and the input end (100) and the output end (200) are respectively connected at two ends of the matching circuit (400). The chip can optimize small signal performance and improve the effectiveness of power resistance.

Description

Technical Field

[0001] This invention belongs to the field of microwave power limiter circuit technology, and particularly relates to a limiter chip based on an interpolation structure. Background Technology

[0002] In microwave front-end systems, circuits such as low-noise amplifiers or mixers are highly vulnerable to leakage power from the transmitter and high external power. Limiters serve as a crucial barrier to protect them. Based on their operating principle, limiters can be categorized into absorptive and reflective types. Absorptive limiters rely on diodes to absorb injected power, ensuring a low output power. In reflective limiters, the diode's conduction impedance becomes very low under large signal injection. This impedance change causes circuit adaptation, reflecting most of the power back to the signal source, thus achieving the limiting capability. The diode only absorbs a small portion of the power. Therefore, it can be seen that, regardless of whether it's an absorptive or reflective limiter, the power absorbed by the diode itself is the primary cause of die failure.

[0003] In existing technologies, circuit designers often increase the power handling capacity of limiters by increasing the diode size. However, this method creates a trade-off between power handling capacity and small-signal performance; improving power handling capacity deteriorates the small-signal performance of the limiter. Furthermore, due to the skin effect, the dynamic current of commonly used diodes flows only to one side of the electrode, significantly limiting current flow and exacerbating heat accumulation, thus reducing power handling capacity. Therefore, improving the power handling capacity of limiters without deteriorating their small-signal performance is a pressing need. Summary of the Invention

[0004] Therefore, it is necessary to provide a limiter chip based on an interpolation structure that can optimize small-signal performance while improving power tolerance, in order to address the aforementioned technical problems.

[0005] The present invention proposes a limiter chip based on interpolation structure, comprising: a substrate, and an input terminal (100), an output terminal (200), an interpolation structure limiter (300), and a matching circuit (400) disposed on the substrate;

[0006] The input terminal (100), the output terminal (200), and the interpolation structure limiter (300) are connected through the matching circuit (400), and the input terminal (100) and the output terminal (200) are respectively connected to the two ends of the matching circuit (400).

[0007] In one embodiment, the interpolation structure limiter (300) includes at least two levels of interpolation structure limiting branches, each level of which includes an interpolation structure diode.

[0008] In one embodiment, the interdigitated structure limiter (300) includes a first-level interdigitated structure limiting branch (301), a second-level interdigitated structure limiting branch (302), and a third-level interdigitated structure limiting branch (303);

[0009] The first-stage interpolation structure limiting stub (301) includes six interpolation structure diodes (10), and the second-stage interpolation structure limiting stub (302) and the third-stage interpolation structure limiting stub (303) each include two interpolation structure diodes (10).

[0010] In one embodiment, the interpolation structure diode includes two anodes and one cathode, with both sides of the anodes being surrounded by the cathode.

[0011] In one embodiment, the chip further includes a ground via (500) connected to a matching circuit (400).

[0012] In one embodiment, the substrate includes any one or more of gallium arsenide, silicon carbide, silicon, sapphire, and diamond.

[0013] In one embodiment, the interdigitated structure limiter (300) includes a reflective limiter or an absorptive limiter.

[0014] In one embodiment, the input terminal (100) and the output terminal (200) are GSG structures.

[0015] The aforementioned limiter chip based on an interpolation structure, by designing an interpolation-based limiter chip, offers several advantages over conventional structures. Firstly, it lengthens the dynamic current conduction path under large signals, reducing heat accumulation and resulting in a lower temperature when injecting the same power, thus improving power handling capability. Secondly, it reduces parasitic resistance without increasing the die cross-sectional area, thereby optimizing small-signal performance to some extent. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a limiter chip based on an interpolation structure in one embodiment.

[0017] Figure 2 This is a schematic diagram of a limiter chip based on an interpolation structure in another embodiment.

[0018] Figure 3 This is a schematic diagram of a limiter chip based on an interpolation structure in another embodiment.

[0019] Figure 4 This is a schematic diagram of the interpolation structure diode in one embodiment.

[0020] Figure 5 This is a schematic diagram of a conventional diode structure in one embodiment.

[0021] Figure 6 This is a schematic diagram of the insertion loss curves of a limiter with a commonly used structure and an interpolation structure in one embodiment.

[0022] Figure 7 This is a schematic diagram of the input standing wave curve of a limiter with a commonly used structure and interpolation structure in one embodiment.

[0023] Figure 8 This is a schematic diagram of the output standing wave curve of a limiter with a commonly used structure and interpolation structure in one embodiment.

[0024] Figure 9 This is a schematic diagram of the leakage level curves of a limiter with a commonly used structure and an interpolation structure in one embodiment. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] In one embodiment, such as Figure 1 As shown, a schematic diagram of a limiter chip based on an interpolation structure is provided, including: a substrate (not shown), and an input terminal (100), an output terminal (200), an interpolation structure limiter (300), and a matching circuit (400) disposed on the substrate.

[0027] For details, please refer to Figure 1 The input terminal (100), output terminal (200), and interpolation structure limiter (300) are connected through a matching circuit (400), with the input terminal (100) and output terminal (200) respectively connected to the two ends of the matching circuit (400). In this embodiment, the interpolation structure limiter (300) refers to a limiter composed of interpolation structure diodes, which may include multi-stage interpolation structure limiting branches. Each stage of the interpolation structure limiting branch is composed of interpolation structure diodes, and the number of interpolation structure limiting branches and interpolation structure diodes can be adjusted according to the input power and operating bandwidth. The matching circuit (400) is composed of a certain number of microstrip lines connected in series, and the corresponding impedance value and matching structure can be adjusted according to the operating frequency and bandwidth.

[0028] In this embodiment, by designing a limiter chip with an interpolation structure, compared to commonly used structures, this structure has two advantages: firstly, it increases the dynamic current conduction path under large signals, reduces heat accumulation, and results in a lower temperature when injecting the same power, thereby improving power handling capability; secondly, it reduces parasitic resistance without increasing the die cross-sectional area, thus optimizing small-signal performance to a certain extent.

[0029] In one embodiment, the interpolation structure limiter (300) includes at least two stages of interpolation structure limiting branches. Figure 1 The diagram shows a three-stage interpolation structure limiting stub. Specifically, each stage of the interpolation structure limiting stub is composed of interpolation structure diodes, the specific number of which is adjusted according to the actual input power and operating bandwidth. In this embodiment, when multiple stages of interpolation structure limiting stubs exist, the number of interpolation structure diodes in the first-stage interpolation structure limiting stub is preferably 6, and the number of interpolation structure diodes in other stages of the interpolation structure limiting stub is preferably 2. The anode and cathode indices of the interpolation diodes can be set according to actual needs, for example, 2, 3, 4, 5…N (N being infinity).

[0030] In one embodiment, such as Figure 2 The diagram shows a schematic of another limiter chip based on an interpolation structure. (Reference) Figure 2 In this embodiment, the interpolation structure limiter (300) includes a first-stage interpolation structure limiting stub (301), a second-stage interpolation structure limiting stub (302), and a third-stage interpolation structure limiting stub (303). The first-stage interpolation structure limiting stub (301) includes six interpolation structure diodes (10), while the second-stage interpolation structure limiting stub (302) and the third-stage interpolation structure limiting stub (303) each include two interpolation structure diodes (10). Furthermore, Figure 2 The matching circuit (400) shown consists of microstrip line (401), microstrip line (402), microstrip line (403) and microstrip line (404).

[0031] In one embodiment, such as Figure 3 As shown, another structural schematic diagram of a limiter chip based on an interpolation structure is provided. In this embodiment, the limiter chip based on the interpolation structure also includes a ground hole (500). The ground hole (500) is connected to the matching circuit (400) through a microstrip line (405). It can be understood that the matching circuit in this embodiment is composed of microstrip lines (401), (402), (403), (404), and (405) connected in series. The input terminal (100), the output terminal (200), the first-stage interpolation structure limiting stub (301), the second-stage interpolation structure limiting stub (302), the third-stage interpolation structure limiting stub (303), and the ground hole (500) are connected through these microstrip lines.

[0032] In one embodiment, such as Figure 4 The diagram shows a schematic of an interpolated diode structure. For details, please refer to... Figure 4 In this embodiment, the interpolated diode (10) includes two anodes (13) and (14) and one cathode (15), which can also be referred to as having two anodes (13) and (14). The anodes (13) and (14) are enclosed by the cathode (15). W1 and W2 are the widths of the two anodes (13) and (14), and L1 and L2 are the lengths of the two anodes (13) and (14). The length, width, and shape of the diode can be adjusted according to actual design requirements and are not limited here.

[0033] In this embodiment, the interpolated diode is compared to the conventional diode (conventional diode reference). Figure 5 As shown in the figure, it alleviates the contradiction between power tolerance and small-signal performance, improving power tolerance while also improving small-signal performance.

[0034] In one embodiment, the substrate includes any one or more of gallium arsenide, silicon carbide, silicon, sapphire, and diamond; that is, the substrate may be composed of any one or more of gallium arsenide, silicon carbide, silicon, sapphire, and diamond.

[0035] In one embodiment, the interpolation structure limiter (300) can be a reflective limiter or an absorptive limiter.

[0036] In one embodiment, the input terminal (100) and the output terminal (200) are GSG structures.

[0037] In one embodiment, to verify the effectiveness of the present invention in improving power tolerance while optimizing small-signal performance, a comparative experiment was further conducted.

[0038] Specifically, the experimental comparison results are as follows: Figure 6-9 As shown, Figure 6 Schematic diagrams of insertion loss curves for limiters with common structures and interpolation structures are provided. Figure 7 Schematic diagrams of the input standing wave ratio (VSWR) curves for limiters with common structures and interpolation structures are provided. Figure 8 Schematic diagrams of the output standing wave ratio (SWR) curves of limiters with common structures and interpolation structures are provided. Figure 9A schematic diagram of leakage level curves for limiters with common and interpolated structures is provided. It is clearly shown that the limiter chip using the interpolated diode has 0.1 dB lower insertion loss, 0.1-0.2 VSWR, and approximately 0.5 dB lower limiting level compared to the one using the common diode structure. Furthermore, power handling experiments reveal that the limiter chip using the interpolated diode structure exhibits a 2 dB improvement in power handling capability. Therefore, based on the experimental results, it is evident that the limiter chip using the interpolated diode structure of this invention, compared to the commonly used diode structure, can simultaneously optimize small-signal performance and improve power handling capability.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A limiter chip based on an interpolation structure, characterized in that, include: A substrate, and an input terminal (100), an output terminal (200), an interpolation structure limiter (300), and a matching circuit (400) disposed on the substrate; The input terminal (100), the output terminal (200), and the interpolation structure limiter (300) are connected through the matching circuit (400), and the input terminal (100) and the output terminal (200) are respectively connected to the two ends of the matching circuit (400); The interdigitated structure limiter (300) includes a first-level interdigitated structure limiting branch (301), a second-level interdigitated structure limiting branch (302), and a third-level interdigitated structure limiting branch (303); The first-stage interpolation structure limiting stub (301) includes six interpolation structure diodes (10), and the second-stage interpolation structure limiting stub (302) and the third-stage interpolation structure limiting stub (303) each include two interpolation structure diodes (10). The interpolation structure diode includes two anodes and one cathode, with both sides of the anodes being wrapped by the cathode.

2. The chip according to claim 1, characterized in that, The chip also includes a ground hole (500) which is connected to a matching circuit (400).

3. The chip according to claim 1, characterized in that, The substrate includes any one or more of gallium arsenide, silicon carbide, silicon, sapphire, and diamond.

4. The chip according to claim 1, characterized in that, The interdigitated structure limiter (300) includes a reflective limiter or an absorptive limiter.

5. The chip according to claim 1, characterized in that, The input terminal (100) and output terminal (200) are GSG structures.

Images