Duty cycle adjustment circuit, adjustment method and memory

Abstract

The embodiment of the present disclosure provides a duty cycle adjustment circuit, an adjustment method and a memory. The duty cycle adjustment circuit comprises a first adjustment module and a second adjustment module, wherein the output end of the first adjustment module is connected with the input end of the second adjustment module; the first adjustment module is used for adjusting the rising edge time or the falling edge time of a first clock signal and inverting the first clock signal based on a first duty cycle control signal set, so as to obtain a second clock signal; the second adjustment module is used for adjusting the falling edge time or the rising edge time of the second clock signal and inverting the second clock signal based on a second duty cycle control signal set, so as to obtain a target clock signal; wherein the first adjustment module and the second adjustment module are of the same structure, and the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a duty cycle adjustment circuit, adjustment method, and memory. Background Technology

[0002] Delay-locked loops (DLLs) have high requirements for the duty cycle of the clock signal. Related technologies typically use binary architecture circuits to adjust the duty cycle, which suffers from poor step characteristics and results in poor linearity of the clock signal's duty cycle. To address this issue, the cell size of the duty cycle adjustment circuit needs to be changed, a design that is difficult to implement in traditional methods. Summary of the Invention

[0003] This disclosure provides a duty cycle adjustment circuit, adjustment method, and memory.

[0004] On one hand, this disclosure provides a duty cycle adjustment circuit, the circuit including: a first adjustment module and a second adjustment module, wherein the output terminal of the first adjustment module is connected to the input terminal of the second adjustment module; the first adjustment module is used to: adjust the rising edge time or falling edge time of a first clock signal and invert the first clock signal based on a first duty cycle control signal set to obtain a second clock signal; the second adjustment module is used to: adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal based on a second duty cycle control signal set to obtain a target clock signal; wherein the first adjustment module and the second adjustment module have the same structure, and the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

[0005] In some embodiments, the first adjustment module includes: a first adjustment unit, the first adjustment unit including different types of transistors; the first duty cycle control signal set including a first control signal set, the first control signal set including a first control signal group and a second control signal group, the control signals corresponding to the same configuration bit in the first control signal group and the second control signal group forming a pair of control signals; the first control signal set is used to control the conduction rate of different types of transistors in the first adjustment unit; the first adjustment unit is used to adjust the rise time or fall time of the first clock signal and invert the first clock signal based on the first pair of control signals in the first control signal set to obtain the second clock signal.

[0006] In some embodiments, the first adjustment unit includes a first transistor group consisting of a plurality of transistors connected in series, the first transistor group including two types of transistors, and the ratio of the two types of transistors is 1:1.

[0007] In some embodiments, the first transistor group includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor connected in series; wherein the first transistor, the second transistor, and the third transistor are P-type transistors; the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors; the first gate of the first transistor and the sixth gate of the sixth transistor are both used to receive the first clock signal; the second gate of the second transistor and the third gate of the third transistor are both used to receive one signal of the first pair of control signals in the first control signal set; and the fourth gate of the fourth transistor and the fifth gate of the fifth transistor are both used to receive the other signal of the first pair of control signals in the first control signal set.

[0008] In some embodiments, the first adjustment module further includes R second adjustment units connected in parallel with the first adjustment unit, the second adjustment units including transistors of different types; the first duty cycle control signal set further includes a first enable signal set; the first enable signal set includes a first enable signal group and a second enable signal group, the enable signals corresponding to the same configuration bit in the first enable signal group and the second enable signal group form a pair of enable signals; the first control signal set is further used to control the conduction rate of different types of transistors in the second adjustment unit; the first adjustment unit is used to: adjust the rise time or fall time of the first clock signal and invert the first clock signal based on the first pair of control signals in the first control signal set. A first sub-output signal is obtained; the r-th second adjustment unit is used to: adjust the rise time or fall time of the first clock signal and invert the first clock signal based on the (r+1)-th pair of control signals in the first control signal set and the r-th pair of enable signals in the first enable signal set to obtain the (r+1)-th sub-output signal; the value of r is a positive integer greater than or equal to 1 and less than or equal to R-1; the R-th second adjustment unit is used to: adjust the rise time or fall time of the first clock signal and invert the first clock signal based on the (R+1)-th pair of control signals in the first control signal set to obtain the (R+1)-th sub-output signal; the second clock signal is jointly determined by the first sub-output signal to the (R+1)-th sub-output signal.

[0009] In some embodiments, any one of the second adjustment units includes S second transistor groups and T third transistor groups, wherein the T third transistor groups, the T second transistor groups, and the output terminal of the first adjustment unit are all coupled to a first node for outputting the second clock signal; each second transistor group is used to receive a pair of enable signals from the first clock signal and a first enable signal set; each third transistor group is used to receive a pair of control signals from the first clock signal and the first control signal set; S is 0 or 1, and T is a positive integer greater than or equal to 1.

[0010] In some embodiments, the second adjustment unit includes one of the following: a second transistor group and a third transistor group; a second transistor group and three third transistor groups; or six third transistor groups.

[0011] In some embodiments, the second transistor group includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor connected in series; the seventh gate of the seventh transistor and the tenth gate of the tenth transistor are both used to receive the first clock signal, and the eighth gate of the eighth transistor and the ninth gate of the ninth transistor are used to receive a pair of enable signals from the first enable signal set; the third transistor group includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor connected in series; the eleventh gate of the eleventh transistor and the fourteenth gate of the fourteenth transistor are both used to receive the first clock signal, and the twelfth gate of the twelfth transistor and the thirteenth gate of the thirteenth transistor are used to receive a pair of control signals from the first control signal set.

[0012] In some embodiments, the value of R is 4, the first second adjustment unit and the second second adjustment unit each include one second transistor group and one third transistor group, the third second adjustment unit includes one second transistor group and three third transistor groups, and the fourth second adjustment unit includes six third transistor groups; the number of configuration bits in the first control signal set is 5.

[0013] In some embodiments, the circuit further includes: a decoding module, a first generation module, and a second generation module; wherein, the decoding module is configured to: receive two configuration signals and generate a first control signal set based on the two configuration signals; the first generation module is configured to generate a second control signal set in a second duty cycle control signal set based on the first control signal set; the second generation module is configured to generate a first enable signal set and a second enable signal set in the second duty cycle control signal set based on the first control signal set; the first adjustment module is configured to: adjust the rise time or fall time of the first clock signal and invert the first clock signal based on the first control signal set and the first enable signal set to obtain the second clock signal; the second adjustment module is configured to: adjust the fall time or rise time of the second clock signal and invert the second clock signal based on the second control signal set and the second enable signal set to obtain the target clock signal.

[0014] In some embodiments, the first generation module includes a NOT gate for performing NOT operations on the control signals in the first control signal set to obtain the second control signal set; the second generation module includes R-1 first generation units and R-1 second generation units; each first generation unit includes a NOR gate and a first NOT gate connected to the output of the NOR gate; each second generation unit includes a NAND gate and a second NOT gate connected to the output of the NAND gate.

[0015] On the other hand, embodiments of this disclosure provide a memory including a duty cycle adjustment circuit as described in any of the above embodiments.

[0016] In another aspect, embodiments of this disclosure provide a duty cycle adjustment method, comprising: adjusting the rising edge time or falling edge time of a first clock signal and inverting the first clock signal based on a first duty cycle control signal set to obtain a second clock signal; adjusting the falling edge time or rising edge time of the second clock signal and inverting the second clock signal based on a second duty cycle control signal set to obtain a target clock signal; wherein the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

[0017] In some embodiments, the first duty cycle control signal set includes a first control signal set, which includes a first control signal group and a second control signal group. Control signals corresponding to the same configuration bit in the first control signal group and the second control signal group form a pair of control signals. The step of adjusting the rise time or fall time of the first clock signal and inverting the first clock signal based on the first duty cycle control signal set to obtain the second clock signal includes: adjusting the rise time or fall time of the first clock signal and inverting the first clock signal based on the first pair of control signals in the first control signal set to obtain the second clock signal.

[0018] In some embodiments, the first duty cycle control signal set further includes a first enable signal set; the first enable signal set includes a first enable signal group and a second enable signal group, wherein the enable signals corresponding to the same configuration bit in the first enable signal group and the second enable signal group form a pair of enable signals;

[0019] The step of adjusting the rise time or fall time of the first clock signal and inverting the first clock signal based on the first duty cycle control signal set to obtain the second clock signal includes:

[0020] Based on the first pair of control signals in the first control signal set, the rise time or fall time of the first clock signal is adjusted and the first clock signal is inverted to obtain a first sub-output signal; based on the (r+1)th pair of control signals in the first control signal set and the rth pair of enable signals in the first enable signal set, the rise time or fall time of the first clock signal is adjusted and the first clock signal is inverted to obtain the (r+1)th sub-output signal; the value of r is a positive integer greater than or equal to 1 and less than or equal to R-1; based on the (R+1)th pair of control signals in the first control signal set, the rise time or fall time of the first clock signal is adjusted and the first clock signal is inverted to obtain the (R+1)th sub-output signal; the second clock signal is determined based on the first sub-output signal to the (R+1)th sub-output signal.

[0021] In some embodiments, when the first control signal group in the first duty cycle control signal set changes from 01111 to 00000, the duty cycle of the first clock signal gradually decreases; when the second control signal group in the first duty cycle control signal set changes from 10000 to 11111, the duty cycle of the first clock signal gradually increases.

[0022] In this embodiment, the duty cycle adjustment circuit includes a first adjustment module and a second adjustment module. The first adjustment module adjusts the rise time or fall time of the first clock signal and inverts the first clock signal to obtain a second clock signal. The second adjustment module adjusts the fall time or rise time of the second clock signal and inverts the second clock signal to obtain a target clock signal. In other words, by adjusting the first clock signal using the first and second adjustment modules, a target clock signal with a different duty cycle from the first clock signal is obtained. This improves the linearity of the duty cycle without increasing design complexity. Attached Figure Description

[0023] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0024] Figure 1 A schematic diagram of the composition structure of a duty cycle adjustment circuit provided in an embodiment of this disclosure;

[0025] Figure 2 A schematic diagram of the composition structure of another duty cycle adjustment circuit provided in an embodiment of this disclosure;

[0026] Figure 3 A schematic diagram illustrating the composition of a first adjustment module provided in an embodiment of this disclosure;

[0027] Figure 4 This is a schematic diagram of the composition structure of a first transistor group provided in an embodiment of the present disclosure;

[0028] Figure 5 A schematic diagram illustrating the composition of a first adjustment module provided in an embodiment of this disclosure;

[0029] Figures 6 to 8 A schematic diagram of the composition structure of a second adjustment unit provided in an embodiment of this disclosure;

[0030] Figure 9 A schematic diagram showing the connection between a first adjustment unit and a second adjustment unit provided in an embodiment of this disclosure;

[0031] Figure 10 A schematic diagram of the composition structure of another duty cycle adjustment circuit provided in the embodiments of this disclosure;

[0032] Figure 11 A schematic diagram of the signal truth values ​​in a first control signal group, a first enable signal group, and a third enable signal group provided in an embodiment of this disclosure;

[0033] Figure 12A schematic diagram of the signal truth values ​​in a second control signal group, a second enable signal group, and a fourth enable signal group provided in an embodiment of this disclosure;

[0034] Figure 13 A timing diagram of a first clock signal, a second clock signal, and a target clock signal provided for embodiments of this disclosure;

[0035] Figure 14 A timing diagram of another first clock signal, a second clock signal, and a target clock signal provided for an embodiment of this disclosure;

[0036] Figure 15 A schematic diagram of the composition structure of another duty cycle adjustment circuit provided in an embodiment of this disclosure;

[0037] Figure 16 A schematic diagram illustrating the composition structure of a first generation module provided in an embodiment of this disclosure;

[0038] Figure 17 A schematic diagram illustrating the composition structure of a second generation module provided in an embodiment of this disclosure;

[0039] Figure 18 A schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure;

[0040] Figure 19 This is a schematic diagram illustrating the implementation process of a duty cycle adjustment method provided in an embodiment of this disclosure. Detailed Implementation

[0041] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0043] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] This disclosure provides a duty cycle adjustment circuit, referencing... Figure 1 The duty cycle adjustment circuit 10 includes: a first adjustment module 11 and a second adjustment module 12, wherein the output terminal of the first adjustment module 11 is connected to the input terminal of the second adjustment module 12;

[0047] The first adjustment module 11 is used to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first duty cycle control signal set to obtain the second clock signal;

[0048] The second adjustment module 12 is used to: adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal based on the second duty cycle control signal set to obtain the target clock signal;

[0049] The first adjustment module 11 and the second adjustment module 12 have the same structure, and the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

[0050] Here, duty cycle refers to the time occupied by the high level within one cycle; the duty cycle adjustment circuit can be applied to memory, such as dynamic random access memory (DRAM) or synchronous dynamic random access memory (SDRAM), etc., and the embodiments disclosed herein are not limited thereto.

[0051] Here, the first adjustment module and the second adjustment module can be any module formed by combining a variety of basic electrical components, capable of adjusting the rising edge time or falling edge time of the clock signal and inverting the clock signal. This disclosure does not limit this.

[0052] Here, the first duty cycle control signal set is a set consisting of at least two control signals, while the second duty cycle control signal set is similar to the first duty cycle control signal set.

[0053] Since the first adjustment module 11 and the second adjustment module 12 have the same structure, and the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set, the number of control signals in the first and second duty cycle control signal sets is the same, and the number is generally even. For example, the first duty cycle control signal set may include 2 control signals, or it may include 4, 8, or other even numbers of control signals. Furthermore, since the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set, the control signals in the first duty cycle control signal set can be inverted using an inverter to obtain the second duty cycle control signal set.

[0054] Here, the first clock signal can be a clock signal whose duty cycle needs to be adjusted. The first adjustment module adjusts the rising or falling edge time of the first clock signal and inverts it to obtain a second clock signal; the second adjustment module adjusts the falling or rising edge time of the obtained second clock signal and inverts it to obtain a target clock signal. Thus, the duty cycle of the target clock signal is different from that of the first clock signal. It can also be seen that the second clock signal is an intermediate signal in the process of adjusting the duty cycle of the first clock signal.

[0055] In this embodiment, the duty cycle adjustment circuit includes a first adjustment module and a second adjustment module. The first adjustment module adjusts the rise time or fall time of the first clock signal and inverts the first clock signal to obtain a second clock signal. The duty cycle of the second clock signal is different from that of the first clock signal. The second adjustment module adjusts the fall time or rise time of the second clock signal and inverts the second clock signal to obtain a target clock signal. In other words, by adjusting the first clock signal through the first and second adjustment modules, a target clock signal with a different duty cycle from the first clock signal is obtained. This improves the linearity of the duty cycle without increasing design complexity.

[0056] In some embodiments, reference Figure 2 The duty cycle adjustment circuit 10 further includes: a third adjustment module 13 connected in parallel with the first adjustment module 11, and a fourth adjustment module 14 connected in parallel with the second adjustment module 12; wherein the output terminal of the third adjustment module 13 is connected to the input terminal of the fourth adjustment module 14.

[0057] The first adjustment module 11 is also used to adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first duty cycle control signal set to obtain the first output signal;

[0058] The third adjustment module 13 is used to obtain a second output signal based on the received first clock signal and the switching ratio control signal, and to determine the second clock signal based on the first output signal and the second output signal.

[0059] The second adjustment module 12 is also used to adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal based on the second duty cycle control signal set to obtain the third output signal;

[0060] The fourth adjustment module 14 is used to output a fourth output signal based on the received second clock signal and the switching ratio control signal, and to determine the target clock signal based on the third output signal and the fourth output signal.

[0061] The third adjustment module 13 and the fourth adjustment module 14 have the same structure.

[0062] It should be noted that the third and fourth adjustment modules can adjust the first clock signal bilaterally, that is, simultaneously adjust the rising and falling slopes of the first clock signal (for example, increasing the rising slope and decreasing the falling slope), and make the changes in the rising and falling edges the same, so that the duty cycle of the adjusted clock signal will not change. In practical applications, the third and fourth adjustment modules can be called the Main Path Duty Cycle Correct (MDCC) modules. In implementation, the third and fourth adjustment modules can be any modules formed by combining various basic electrical components, capable of adjusting the duty cycle of the first clock signal in the same direction, for example, a delay module composed of multiple transistors.

[0063] The third adjustment module further adjusts the rising or falling edge slope of the first clock signal based on the switching ratio control signal and inverts the first clock signal to obtain a second output signal. The first output signal from the first adjustment module and the second output signal from the third adjustment module are superimposed to obtain the second clock signal. The fourth adjustment module further adjusts the falling or rising edge slope of the second clock signal based on the switching ratio control signal and inverts the second clock signal to obtain a fourth output signal. The third output signal from the second adjustment module and the fourth output signal from the fourth adjustment module are superimposed to obtain the target clock signal.

[0064] The first adjustment module and the second adjustment module can adjust the rising edge time or falling edge time of the clock signal, but the adjustment range of the duty cycle of the first clock signal is small, so it can be called the duty cycle auxiliary adjustment module.

[0065] The switching ratio control signal can control the ratio of different transistors in the third and fourth adjustment modules, thereby adjusting the duty cycle of the clock signal.

[0066] In this embodiment, the duty cycle adjustment circuit includes a first adjustment module, a second adjustment module, a third adjustment module, and a fourth adjustment module. The first and second adjustment modules can adjust the rise time or fall time of the clock signal and invert the clock signal based on a duty cycle control signal set, thereby increasing or decreasing the duty cycle of the first clock signal. The third and fourth adjustment modules can perform bilateral adjustment of the first clock signal based on a switching ratio control signal. Thus, while the first and second adjustment modules adjust the duty cycle of the first clock signal, the third adjustment module can bilaterally adjust the rise and fall times of the first clock signal, further reducing the rise time or fall time of the first clock signal.

[0067] In some embodiments, reference Figure 3 The first adjustment module 11 includes a first adjustment unit 111, which includes transistors of different types. Here, the first adjustment unit may include P-type metal-oxide-semiconductor (PMOS) transistors and N-type metal-oxide-semiconductor (NMOS) transistors. In implementation, the number of each type of transistor can be designed as needed, and this disclosure is not limited in this respect.

[0068] The first duty cycle control signal set includes a first control signal set, which includes a first control signal group and a second control signal group. Control signals corresponding to the same configuration bit in the first control signal group and the second control signal group form a pair of control signals. The first control signal set is used to control the conduction rate of different types of transistors in the first adjustment unit 111.

[0069] Similarly, the second duty cycle control signal set includes a second control signal set, which includes a third control signal group and a fourth control signal group. The control signals corresponding to the same configuration bit in the third control signal group and the fourth control signal group form a pair of control signals. The second control signal set is used to control the conduction rate of different types of transistors in the first adjustment unit 111 in the second adjustment module 12.

[0070] The first adjustment unit 111 is used to adjust the rising edge time or falling edge time of the first clock signal CKI and invert the first clock signal CKI based on the first pair of control signals in the first control signal set, so as to obtain the second clock signal MD or the first output signal.

[0071] Here, the first control signal set may include the first control signal group DCCCTRL0B. <x:0>Second control signal group DCCCTRL1B <x:0>Where X can be any integer greater than 0. X+1 is the number of configuration bits in the first control signal set, and the number of configuration bits can be determined according to the number of adjustment units in the first adjustment module.

[0072] For example, if the first adjustment module has 5 adjustment units, then the number of configuration bits in the first control signal set is 5. Thus, the first control signal group DCCCTRL0B<4:0> has 5 control signals, where DCCCTRL0B<4:0> includes DCCCTRL0B. <4> DCCCTRL0B <3> DCCCTRL0B <2> DCCCTRL0B <1> and DCCCTRL0B <0> Similarly, the second control signal group DCCCTRL1B<4:0> also has 5 control signals, among which the second control signal group DCCCTRL1B<4:0> includes DCCCTRL1B <4> DCCCTRL1B <3> DCCCTRL1B <2> DCCCTRL1B <1> and DCCCTRL1B <0> .

[0073] Here, the control signals corresponding to the same configuration bit in the first and second control signal groups form a pair of control signals, referring to the control signal DCCCTRL0B. <0> and control signal DCCCTRL1B <0> This can form the first pair of control signals, control signal DCCCTRL0B <1> and control signal DCCCTRL1B <1> This can form a second pair of control signals, control signal DCCCTRL0B <2> and control signal DCCCTRL1B <2> A third pair of control signals can be formed, control signal DCCCTRL0B <3> and control signal DCCCTRL1B <3> This can form a fourth pair of control signals, control signal DCCCTRL0B <4> and control signal DCCCTRL1B <4> This can form a fifth pair of control signals. In some embodiments, the two control signals in each pair of control signals can be out of phase.

[0074] It should be noted that, when the duty cycle adjustment circuit 10 includes a third adjustment module 13 and a fourth adjustment module 14, the first adjustment unit 111 is used to adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first pair of control signals in the first control signal set to obtain a first output signal. Then, the second clock signal is determined jointly based on the first output signal and the second output signal output by the third adjustment unit 13.

[0075] In the absence of the third adjustment module 13 and the fourth adjustment module 14 in the duty cycle adjustment circuit 10, the first adjustment unit 111 is used to adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first pair of control signals in the first control signal set to obtain the second clock signal.

[0076] In this embodiment, the first adjustment module includes a first adjustment unit, which includes different types of transistors. The conduction rate of the different types of transistors in the first adjustment unit is controlled by a first control signal set, thereby controlling the rise time or fall time of the output second clock signal to vary within a certain range. The conduction rate of the different types of transistors in the second adjustment unit is controlled by a second control signal set, thereby controlling the rise time or fall time of the output target clock signal to vary within a certain range. In this way, the design difficulty is reduced while adjusting the duty cycle of the clock signal.

[0077] In some embodiments, reference Figure 4 The first adjustment unit includes a first transistor group 1111 composed of multiple transistors connected in series. The first transistor group 1111 includes two types of transistors, and the ratio of the two types of transistors is 1:1.

[0078] Here, the first transistor group may include any even number of transistors of two types, for example, it may include two N-type transistors, two P-type transistors, or four N-type transistors, four P-type transistors, and so on. Figure 4 The first transistor group 1111 shown includes 6 transistors, of which three are N-type transistors and three are P-type transistors.

[0079] In some embodiments, continue to refer to Figure 4 The first transistor group 1111 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6 connected in series; wherein, the first transistor M1, the second transistor M2, and the third transistor M3 are P-type transistors, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are N-type transistors.

[0080] The first gate G1 of the first transistor M1 and the sixth gate G6 of the sixth transistor M6 are both used to receive the first clock signal CKI. The second gate G2 of the second transistor M2 and the third gate G3 of the third transistor M3 are both used to receive a control signal DCCCTRL0B from the first pair of control signals in the first control signal set. <0> The fourth gate G4 of the fourth transistor M4 and the fifth gate G5 of the fifth transistor M5 are both used to receive another control signal DCCCTRL1B from the first pair of control signals in the first control signal set. <0> The source of the first transistor M1 is connected to the power supply signal, the source of the sixth transistor M6 is connected to the ground signal, and the drains of the third transistor M3 and the fourth transistor are both connected to the output terminal of the first adjustment module to output the second clock signal MD.

[0081] In this embodiment of the disclosure, a simple first transistor group formed by connecting multiple transistors in series is used as the first adjustment unit, which simplifies the composition of the duty cycle adjustment circuit.

[0082] In some embodiments, reference Figure 5 The first adjustment module 11 also includes R second adjustment units 112 connected in parallel with the first adjustment unit 111, and the second adjustment unit 112 includes transistors of different types;

[0083] The first duty cycle control signal set also includes a first enable signal set; the first enable signal set includes a first enable signal group and a second enable signal group, and the enable signals corresponding to the same configuration bit in the first enable signal group and the second enable signal group form a pair of enable signals.

[0084] Correspondingly, the second duty cycle control signal set also includes a second enable signal set; the second enable signal set includes a third enable signal group and a fourth enable signal group, and the enable signals corresponding to the same configuration bit in the third enable signal group and the fourth enable signal group form a pair of enable signals;

[0085] The first set of control signals is also used to control the conduction rate of different types of transistors in the second adjustment unit;

[0086] The first adjustment unit 111 is used to: adjust based on the first pair of control signals in the first control signal set, namely the control signal DCCCTRL0B <0> and control signal DCCCTRL1B <0> Adjust the rising or falling edge time of the first clock signal CKI and invert it to obtain the first sub-output signal Y0.

[0087] The r-th second adjustment unit 112 is used to: based on the (r+1)-th pair of control signals in the first control signal set, i.e., control signal DCCCTRL0B <r>and control signal DCCCTRL1B <r>And the r-th pair of enable signals in the first enable signal set, namely AUX_0B <r>and AUX_1B <r>Adjust the rising or falling edge time of the first clock signal CKI and invert the first clock signal to obtain the (r+1)th sub-output signal Yr; the value of r is a positive integer greater than or equal to 1 and less than or equal to R-1.

[0088] The Rth second adjustment unit 112 is used to: based on the (R+1)th pair of control signals in the first control signal set, namely control signal DCCCTRL0B <r>and control signal DCCCTRL1B <r>Adjust the rising or falling edge time of the first clock signal CKI and invert the first clock signal to obtain the (R+1)th sub-output signal YR;

[0089] The second clock signal MD is determined by the first sub-output signal Y0 to the (R+1)th sub-output signal YR.

[0090] Here, the enable signals in the first enable signal set can control whether the second adjustment unit outputs a signal. In implementation, the number of configuration bits in the first enable signal set can be determined according to the number of second transistor groups in the adjustment units of the first adjustment module. For example, if the first adjustment unit includes five adjustment units and each of the five adjustment units includes three second transistor groups, then the number of configuration bits in the first enable signal set is three.

[0091] Since the first adjustment module and the second adjustment module have the same structure, and the enable signals in the first and second enable signal sets are complementary, the number of enable signals in both sets is the same, and is generally an even number. For example, the first enable signal set may include an even number of enable signals such as 2, 4, 6, or 8. Furthermore, the first enable signal set may include a first enable signal group AUX_0B. <z:1>Second enable signal group AUX_1B <z:1>The second enable signal set may include the third enable signal group AUX_0. <z:1>and the fourth enable signal group AUX_1 <z:1>Where Z can be the total number of enable signals in the first enable signal group, and Z can be any integer greater than or equal to 1. Since the signals in the second enable signal set are complementary to the signals in the first enable signal set, the enable signals in the first enable signal set can be inverted using an inverter to obtain the second enable signal set.

[0092] For example, the first enable signal set may include 6 enable signals, wherein the first enable signal group AUX_0B<3:1> includes AUX_0B <3> AUX_0B <2> and AUX_0B <1> The second enable signal group AUX_1B<3:1> includes AUX_1B <3> AUX_1B <2> and AUX_1B <1> .

[0093] The enable signals corresponding to the same configuration bit in the first and second enable signal groups form a pair of enable signals, which can refer to the enable signal AUX_0B. <1> and enable signal AUX_1B <1> This can be combined into a pair of enable signals, the enable signal being AUX_0B. <2> and enable signal AUX_1B <2> This can be combined into a pair of enable signals, the enable signal being AUX_0B. <3> and enable signal AUX_1B <3> They can form a pair of enable signals.

[0094] One pair of enable signals from the first pair to the r-th pair can be input through the input terminals EN_AUX and ENB_AUX of the second adjustment unit, respectively. Similarly, one pair of control signals from the first pair to the (R+1)-th pair can be input through the input terminals EN and ENB of either the second or first adjustment unit.

[0095] For example, the first pair of control signals DCCCTRL0B <0> and DCCCTRL1B <0> The second pair of control signals DCCCTRL0B are input through the input terminals EN and ENB of the first adjustment unit 111, respectively. <1> and DCCCTRL1B <1> The inputs are respectively through the input terminals EN and ENB of the second adjustment unit 112.

[0096] In this embodiment, the first adjustment module includes not only a first adjustment unit, but also R second adjustment units connected in series with the first adjustment unit. The second adjustment units include different types of transistors. The second clock signal is jointly determined by the first adjustment unit and the R second adjustment units. This achieves different linearities over a total range while reducing design complexity.

[0097] In some embodiments, any one of the second adjustment units includes S second transistor groups and T third transistor groups, wherein the T third transistor groups, the S second transistor groups and the output terminal of the first adjustment unit are all coupled to a first node for outputting a second clock signal.

[0098] Each second transistor group is used to receive a pair of enable signals, which are the first clock signal and the first enable signal; each third transistor group is used to receive a pair of control signals, which are the first clock signal and the first control signal; S is 0 or 1, and T is a positive integer greater than or equal to 1.

[0099] Here, when S equals 0, the second adjustment unit includes only the third transistor group; when S equals 1, the second adjustment unit includes both the third transistor group and the second transistor group. In both cases, the number of the third transistor group can be set according to the actual linearity requirements, and this embodiment does not limit this.

[0100] In this embodiment of the disclosure, the second adjustment unit includes S second transistor groups and T third transistor groups. In implementation, the number of second transistor groups and third transistor groups can be set according to the actual linearity requirements, so as to meet different requirements.

[0101] In some embodiments, reference Figure 6 , Figure 7 or Figure 8 The second transistor group 1121 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10 connected in series. The seventh gate G7 of the seventh transistor M7 and the tenth gate G10 of the tenth transistor M10 are both used to receive the first clock signal CKI. The eighth gate G8 of the eighth transistor M8 and the ninth gate G9 of the ninth transistor M9 can be used as input terminals ENB_AUX and EN_AUX, respectively, to receive a pair of enable signals from the first enable signal set. For example, the eighth gate G8 and the ninth gate G9 are respectively used to receive the enable signal AUX_0B. <1> and AUX_1B <1> .

[0102] Continue to refer to Figure 6 , Figure 7 or Figure 8 The third transistor group 1122 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14 connected in series. The eleventh gate G11 of the eleventh transistor M11 and the fourteenth gate G14 of the fourteenth transistor M14 are both used to receive the first clock signal CKI. The twelfth gate G12 of the twelfth transistor M12 and the thirteenth gate G13 of the thirteenth transistor M13 can be used as input terminals ENB and EN, respectively, to receive a pair of control signals from the first control signal set, such as the control signal DCCCTRL0B. <0> and control signal DCCCTRL1B <0> .

[0103] In some embodiments, reference Figure 6 One of the second adjustment units may include a second transistor group 1121 and a third transistor group 1122. (See reference) Figure 7 One of the second adjustment units may include a second transistor group 1121 and three third transistor groups 1122. (See reference) Figure 8 One of the second adjustment units may include six third transistor groups 1122. In other embodiments, one of the second adjustment units may also include five third transistor groups and one second transistor group, etc. Those skilled in the art can set the number of second transistor groups and third transistor groups included in any second adjustment unit as needed, and this disclosure does not limit this.

[0104] refer to Figure 9 It can be seen that the output terminals of the second transistor group 1121, the third transistor group 1122, and the first adjustment unit 111 in the second adjustment unit 112 are all coupled to the first node N1 for outputting the second clock signal MD.

[0105] In some embodiments, the number R of the second adjustment units is 4, the first and second second adjustment units each include one second transistor group and one third transistor group, the third second adjustment unit includes one second transistor group and three third transistor groups, and the fourth second adjustment unit includes six third transistor groups; the number of configuration bits in the first control signal set is 5.

[0106] Here, the number of configuration bits in the first control signal set can refer to the number of bits of the signal in the first control signal group or the second control signal group in the first control signal set, that is, the number of control signals in the first control signal group or the second control signal group.

[0107] The following will combine Figure 4 , Figures 6 to 14 The duty cycle adjustment circuit 10 in the embodiments of this disclosure will be further explained. (See reference...) Figure 10 The first adjustment module 11 includes:

[0108] The first adjustment unit 111 is used to: adjust based on the first pair of control signals DCCCTRL0B in the first control signal set. <0> and DCCCTRL1B <0> Adjust the rising or falling edge time of the first clock signal CKI and invert the first clock signal to obtain the first sub-output signal Y0.

[0109] The first second adjustment unit 112 is used to: adjust the second pair of control signals DCCCTRL0B based on the first control signal set. <1> and DCCCTRL1B <1> And the first pair of enable signals AUX_0B in the first enable signal set. <1> and AUX_1B <1> Adjust the rising or falling edge time of the first clock signal CKI and invert the first clock signal to obtain the second sub-output signal Y1.

[0110] The second adjustment unit 112 is used to: adjust the third pair of control signals DCCCTRL0B based on the first control signal set. <2> and DCCCTRL1B <2> And the second pair of enable signals AUX_0B in the first enable signal set. <2> and AUX_1B <2> Adjust the rising or falling edge time of the first clock signal CKI and invert the first clock signal to obtain the third sub-output signal Y2.

[0111] The third second adjustment unit 112 is used for: based on the fourth pair of control signals DCCCTRL0B in the first control signal set. <3> and DCCCTRL1B <3> And the third pair of enable signals AUX_0B in the first enable signal set. <3> and AUX_1B <3> Adjust the rising or falling edge time of the first clock signal CKI and invert the first clock signal to obtain the fourth sub-output signal Y3.

[0112] The fourth second adjustment unit 112 is used for: based on the fifth pair of control signals DCCCTRL0B in the first control signal set. <4> and DCCCTRL1B <4> The rising or falling edge time of the first clock signal CKI is adjusted and the first clock signal is inverted to obtain the fifth sub-output signal Y4. The output terminals of the first adjustment unit 111 and the first to fourth second adjustment units are all coupled to the first node N1. The second clock signal MD is determined by the first sub-output signal Y0 to the fifth sub-output signal Y4.

[0113] Similarly, the first adjustment unit 111 and the first to fourth second adjustment units 112 in the second adjustment module 12 respectively output the sixth sub-output signal Y5, the seventh sub-output signal Y6, the eighth sub-output signal Y7, the ninth sub-output signal Y8, and the tenth sub-output signal Y9. The target clock signal CKO is determined by the sixth sub-output signal Y5 to the tenth sub-output signal Y9.

[0114] When the duty cycle adjustment circuit 10 includes the third adjustment module 13 and the fourth adjustment module 14, the second clock signal MD is determined by the second output signal and the first sub-output signal Y0 to the fifth sub-output signal Y4; the target clock signal CKO is determined by the fourth output signal and the sixth sub-output signal Y5 to the tenth sub-output signal Y9.

[0115] In implementation, the composition structure of the first adjustment unit 111 in the first adjustment module 11 can be referred to Figure 4 The composition of the first and second adjustment units 112 can be referred to Figure 6 The composition of the third second adjustment unit 112 can be referenced. Figure 7 The composition of the fourth second adjustment unit 112 can be referenced. Figure 8 Furthermore, the connection relationship between the first adjustment unit 111 and the second adjustment unit 112 can be referred to... Figure 9 .

[0116] The second adjustment module 12 has the same structure as the first adjustment module 11. The second adjustment module 12 also includes the first adjustment unit 111 and the first to fourth second adjustment units 112, which will not be described in detail here.

[0117] The control signals in the first control signal group DCCCTRL0B<4:0> are used to control the conduction rate of the P-type transistors in each adjustment unit of the first adjustment module 11; the control signals in the second control signal group DCCCTRL1B<4:0> are used to control the conduction rate of the N-type transistors in each adjustment unit of the first adjustment module 11; the control signals in the third control signal group DCCCTRL1T<4:0> are used to control the conduction rate of the N-type transistors in each adjustment unit of the second adjustment module 12; and the control signals in the fourth control signal group DCCCTRL0T<4:0> are used to control the conduction rate of the P-type transistors in each adjustment unit of the second adjustment module 12.

[0118] In this embodiment of the disclosure, the control signals in the first duty cycle control signal set and the second duty cycle control signal set can be adjusted so that the duty cycle of the target clock signal is greater than the duty cycle of the first clock signal, or so that the duty cycle of the target clock signal is less than the duty cycle of the first clock signal. These two cases will be described below.

[0119] Case 1: By adjusting the control signals in the first control signal group DCCCTRL0B<4:0> of the first duty cycle control signal set, for example, by keeping the control signals in the second control signal group unchanged and controlling the first control signal group DCCCTRL0B<4:0> to change from 01111 to 00000, the duty cycle of the first clock signal gradually decreases, that is, the duty cycle of the target clock signal gradually becomes less than the duty cycle of the first clock signal.

[0120] The working process of the first adjustment module 11 is explained below:

[0121] Because the control signal in the first control signal group DCCCTRL0B<4:0> controls the... Figure 10 In the first adjustment module 11, the more P-type transistors in each adjustment unit are turned on when the first control signal group DCCCTRL0B<4:0> changes from 01111 to 00000, the shorter the rise time of the inverted signal of the first clock signal becomes, which can increase the duty cycle of the inverted signal of the first clock signal.

[0122] When the first control signal group DCCCTRL0B<4:0> is 01111 and the second control signal group DCCCTRL1B<4:0> remains unchanged, the control signal DCCCTRL0B connected to the first adjustment unit 111 is... <0> If the value is 1, the P-type transistor in the first adjustment unit 111 is turned off; the control signal DCCCTRL0B connected to the fourth second adjustment unit 112... <4> If the value is 0, then the P-type transistor in the fourth second adjustment unit 112 is turned on. Additionally, from... Figure 11 and Figure 12 As can be seen, the enable signal values ​​in the first enable signal group AUX_0B<3:1> and the second enable signal group AUX_1B<3:1> are both disabled, meaning that the first to third second adjustment units 112 are all turned off. Therefore, when the first control signal group DCCCTRL0B<4:0> is 01111, only the fourth second adjustment unit 112 in the first adjustment module 11 adjusts the rising edge time of the inverted signal of the first clock signal.

[0123] When the first control signal group DCCCTRL0B<4:0> is 00000 and the second control signal group DCCCTRL1B<4:0> remains unchanged, the P-type transistors in the first adjustment unit 111 and the first to fourth second adjustment units 112 are all turned on. Additionally, from Figure 11 and Figure 12 As can be seen, the true values ​​of the enable signals in the first enable signal group AUX_0B<3:1> and the second enable signal group AUX_1B<3:1> are both "enable", meaning that the first to third second adjustment units 112 are all enabled. Therefore, the first adjustment unit 111 and the first to fourth second adjustment units 112 can all adjust the rise time of the inverted signal of the first clock signal. When the first control signal group DCCCTRL0B<4:0> gradually decreases from 01111 to 00000, Figure 13 The rising edge time of the second clock signal MD gradually decreases.

[0124] The working process of the second adjustment module 12 is explained below:

[0125] Since the second adjustment module 12 and the first adjustment module 11 have the same structure, except that the control signals are inverted, the third control signal group DCCCTRL1T<4:0> is the inverted signal of the first control signal group DCCCTRL0B<4:0>. Therefore, when the first control signal group DCCCTRL0B<4:0> changes from 01111 to 00000, the third control signal group DCCCTRL1T<4:0> changes from 10000 to 11111.

[0126] Since the control signals in the third control signal group DCCCTRL1T<4:0> control the N-type transistors in each adjustment unit of the second adjustment module 12, when the third control signal group DCCCTRL1T<4:0> changes from 10000 to 11111, the more N-type transistors in each adjustment unit are turned on, the shorter the falling edge time of the inverted signal of the second clock signal will be, which can reduce the duty cycle of the inverted signal of the second clock signal.

[0127] When the third control signal group DCCCTRL1T<4:0> is 10000 and the fourth control signal group DCCCTRL0T<4:0> remains unchanged, the control signal DCCCTRL1T connected to the first adjustment unit 111 is... <0> If the value is 0, the N-type transistor in the first adjustment unit 111 is turned off; the control signal DCCCTRL1T connected to the fourth second adjustment unit 112 is also turned off. <4> If the value is 1, then the N-type transistor in the fourth second adjustment unit 112 is turned on. Additionally, from... Figure 11 and Figure 12 As can be seen, the enable signal values ​​in the third enable signal group AUX_0<3:1> and the fourth enable signal group AUX_1<3:1> are both disabled, meaning that the first to third second adjustment units 112 are all turned off. Therefore, when the third control signal group DCCCTRL1T<4:0> is 10000, only the fourth second adjustment unit 112 in the second adjustment module 12 adjusts the falling edge time of the inverted signal of the second clock signal.

[0128] When the third control signal group DCCCTRL1T<4:0> is 11111 and the fourth control signal group DCCCTRL0T<4:0> remains unchanged, the N-type transistors in the first adjustment unit 111 and the first to fourth second adjustment units 112 are all turned on. Additionally, from... Figure 11 and Figure 12 It can be seen that the true values ​​of the enable signals in the third enable signal group AUX_0<3:1> and the fourth enable signal group AUX_1<3:1> are both "enable", meaning that the first to third second adjustment units 112 are all turned on. Therefore, the first adjustment unit 111 and the first to fourth second adjustment units 112 can all adjust the falling edge time of the inverted signal of the second clock signal. It can be seen from the above that when the first control signal group DCCCTRL0B<4:0> gradually decreases along the direction from 01111 to 00000, Figure 13 The falling edge time of the target clock signal CKO is gradually reduced, which can gradually reduce the duty cycle of the first clock signal.

[0129] In summary, by gradually decreasing the first control signal group DCCCTRL0B<4:0> along the direction from 01111 to 00000, the duty cycle of the first clock signal CKI can be gradually reduced. Figure 13 As shown, compared to the first clock signal CKI, the rising edge time of the target clock signal CKO output by the second adjustment module 12 remains unchanged, while the falling edge time gradually decreases, and the pulse width gradually narrows. That is, the slope of the rising edge of the output target clock signal CKO remains unchanged, while the slope of the falling edge gradually decreases, thereby making the duty cycle of the target clock signal CKO gradually smaller than that of the first clock signal CKI.

[0130] It should be noted that when the clock signal duty cycle is adjusted by gradually decreasing the first control signal group DCCCTRL0B<4:0> from 01111 to 00000 and gradually increasing the third control signal group DCCCTRL1T<4:0> from 10000 to 11111, the second control signal group DCCCTRL1B<4:0> and the fourth control signal group DCCCTRL0T<4:0> will not adjust the clock signal edge time.

[0131] Case 2: By adjusting the control signals in the second control signal group DCCCTRL1B<4:0> of the first duty cycle control signal set, for example, by controlling the second control signal group DCCCTRL1B<4:0> to change from 10000 to 11111, the duty cycle of the first clock signal is gradually increased, that is, the duty cycle of the target clock signal is gradually greater than the duty cycle of the first clock signal.

[0132] The working process of the first adjustment module 11 is explained below:

[0133] Because the control signals in the second control signal group DCCCTRL1B<4:0> control the... Figure 10 In the first adjustment module 11, when the second control signal group DCCCTRL1B<4:0> changes from 10000 to 11111, the more N-type transistors in each adjustment unit are turned on, the shorter the falling edge time of the inverted signal of the first clock signal becomes, thus reducing the duty cycle of the inverted signal of the first clock signal.

[0134] When the first control signal group DCCCTRL0B<4:0> remains unchanged and the second control signal group DCCCTRL1B<4:0> is 10000, the control signal DCCCTRL1B connected to the first adjustment unit 111 is... <0> If the value is 0, the N-type transistor in the first adjustment unit 111 is turned off; the control signal DCCCTRL1B connected to the fourth second adjustment unit 112 is... <4> If the value is 1, then the N-type transistor in the fourth second adjustment unit 112 is turned on. Additionally, from... Figure 11 and Figure 12 As can be seen, the enable signal values ​​in the first enable signal group AUX_0B<3:1> and the second enable signal group AUX_1B<3:1> are both disabled, meaning that the first to third second adjustment units 112 are all turned off. Therefore, when the second control signal group DCCCTRL1B<4:0> is 10000, only the fourth second adjustment unit 112 in the first adjustment module 11 adjusts the falling edge time of the inverted signal of the first clock signal.

[0135] When the first control signal group DCCCTRL0B<4:0> remains unchanged and the second control signal group DCCCTRL1B<4:0> is 11111, the N-type transistors in the first adjustment unit 111 and the first to fourth second adjustment units 112 are all turned on. Additionally, from Figure 11 and Figure 12 As can be seen, the true values ​​of the enable signals in the first enable signal group AUX_0B<3:1> and the second enable signal group AUX_1B<3:1> are both "enable", meaning that the first to third second adjustment units 112 are all enabled. Therefore, the first adjustment unit 111 and the first to fourth second adjustment units 112 can all adjust the falling edge time of the inverted signal of the first clock signal. When the control second control signal group DCCCTRL1B<4:0> gradually increases from 10000 to 11111, Figure 13 The falling edge time of the second clock signal MD gradually decreases.

[0136] The working process of the second adjustment module 12 is explained below:

[0137] Since the control signals in the fourth control signal group DCCCTRL0T<4:0> control the P-type transistors in each adjustment unit of the second adjustment module 12, when the fourth control signal group DCCCTRL0T<4:0> changes from 01111 to 00000, the more P-type transistors in each adjustment unit are turned on, the shorter the rise time of the inverted signal of the second clock signal will be, which can increase the duty cycle of the inverted signal of the second clock signal.

[0138] When the third control signal group DCCCTRL1T<4:0> remains unchanged and the fourth control signal group DCCCTRL0T<4:0> is 01111, the control signal DCCCTRL0T connected to the first adjustment unit 111 is... <0> If the value is 1, the P-type transistor in the first adjustment unit 111 is turned off; the control signal DCCCTRLOT connected to the fourth second adjustment unit 112 is also turned off. <4> If the value is 0, then the P-type transistor in the fourth second adjustment unit 112 is turned on. Additionally, from... Figure 11 and Figure 12 As can be seen, the enable signal values ​​in the third enable signal group AUX_0<3:1> and the fourth enable signal group AUX_1<3:1> are both disabled, meaning that the first to third second adjustment units 112 are all turned off. Therefore, when the fourth control signal group DCCCTRL0T<4:0> is 01111, only the fourth second adjustment unit 112 in the second adjustment module 12 adjusts the rising edge time of the inverted signal of the second clock signal.

[0139] When the third control signal group DCCCTRL1T<4:0> remains unchanged and the fourth control signal group DCCCTRL0T<4:0> is 00000, the P-type transistors in the first adjustment unit 111 and the first to fourth second adjustment units 112 are all turned on. Additionally, from... Figure 11 and Figure 12 As can be seen, the true values ​​of the enable signals in the third enable signal group AUX_0<3:1> and the fourth enable signal group AUX_1<3:1> are both "enable", meaning that the first to third second adjustment units 112 are all turned on. Therefore, the first adjustment unit 111 and the first to fourth second adjustment units 112 can all adjust the rising edge time of the inverted signal of the second clock signal. It can be seen from the above that when the control signal group DCCCTRL1B<4:0> gradually increases from 10000 to 11111, Figure 13 The rising edge time of the target clock signal CKO is gradually reduced, which allows the duty cycle of the first clock signal to gradually increase.

[0140] In summary, when the control signal group DCCCTRL1B<4:0> gradually increases along the direction from 10000 to 11111, from... Figure 14 As can be seen, compared to the first clock signal CKI, the rising edge time of the target clock signal CKO output by the second adjustment module 12 will gradually decrease while the falling edge time remains unchanged. That is, the rising edge slope of the output target clock signal CKO gradually increases while the falling edge slope remains unchanged, and the pulse width gradually widens, thereby making the duty cycle of the target clock signal CKO gradually greater than that of the first clock signal CKI.

[0141] It should be noted that when the clock signal duty cycle is adjusted by gradually increasing the second control signal group DCCCTRL1B<4:0> from 10000 to 11111 and gradually decreasing the fourth control signal group DCCCTRL0T<4:0> from 01111 to 00000, the first control signal group DCCCTRL0B<4:0> and the third control signal group DCCCTRL1T<4:0> will not adjust the clock signal edge time.

[0142] In some embodiments, reference Figure 15 Duty cycle adjustment circuit 10: first adjustment module 11, second adjustment module 12, decoding module 15, first generation module 16, and second generation module 17; wherein,

[0143] Decoding module 15 is used to: receive two configuration signals and generate a first control signal set based on the two configuration signals; first generation module 16 is used to generate a second control signal set in the second duty cycle control signal set based on the first control signal set; second generation module 17 is used to generate a first enable signal set in the first control signal set and a second enable signal set in the second duty cycle control signal set based on the first control signal set; first adjustment module 11 is used to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first control signal set and the first enable signal set to obtain a second clock signal; second adjustment module 12 is used to: adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal based on the second control signal set and the second enable signal set to obtain a target clock signal.

[0144] Here, the two configuration signals can be DCCCTRL0B. <x:0>and DCCCTRL1B <x:0>Configuration signal DCCCTRL0B <x:0>and DCCCTRL1B <x:0>There are X+1 configuration bits, which are used to adjust the slope of the rising or falling edge of the clock signal, thereby adjusting the duty cycle of the clock signal.

[0145] In implementation, the first generation module may include an inverter, which can invert the control signals in the first control signal set to obtain the second control signal set.

[0146] In this embodiment, the duty cycle adjustment circuit may further include a decoding module, a first generation module, and a second generation module. The decoding module outputs a first control signal set based on a configuration signal, the first generation module outputs a second control signal set based on the first control signal set, and the second generation module outputs a first enable signal set and a second enable signal set based on the first control signal set. Therefore, in use, only the configuration signal and the first clock signal need to be input to obtain the target clock signal; there is no need to additionally input signals from the first duty cycle control signal set (including the first control signal set and the first enable signal set) and the second duty cycle control signal set (including the second control signal set and the second enable signal set), thereby simplifying operation.

[0147] In some embodiments, reference Figure 16 The first generation module 16 includes a NOT gate 161, which is used to perform NOT operation on the control signals in the first control signal set to obtain the second control signal set.

[0148] In some embodiments, reference Figure 17 The second generation module 17 includes R-1 first generation units 171 and R-1 second generation units 172. Here, Figure 17 The diagram only shows three first generation units 171 and three second generation units 172 as an example. In practice, the number of first generation units and second generation units may be one less than the number of second adjustment units. The number of first generation units and second generation units may also be determined based on the number of second transistor groups in the second adjustment units.

[0149] Each first generation unit 171 includes a NOR gate 1711 and a first NOT gate 1712 connected to the output of the NOR gate 1711. Each second generation unit 172 includes a NAND gate 1721 and a second NOT gate 1722 connected to the output of the NAND gate 1721.

[0150] For example, continue to refer to Figure 17 The control signal DCCCTRL0B in the first control signal set can be controlled by an NOR gate 1711. <1> and control signal DCCCTRL0B <4> Perform a NOR operation to obtain the enable signal AUX_0 in the third enable signal group. <1> The first NOT gate 1712 is used to enable the signal AUX_0. <1> Perform a NOT operation to obtain the enable signal AUX_0B from the first enable signal group. <1> Similarly, a NOR gate 1711 can be used to control the control signal DCCCTRL0B in the first control signal set. <2> and control signal DCCCTRL0B <4> Perform a NOR operation to obtain the enable signal AUX_0 in the third enable signal group. <2> The first NOT gate 1712 is used to enable the signal AUX_0. <2> Perform a NOT operation to obtain the enable signal AUX_0B from the first enable signal group. <2> Similarly, a NOR gate 1711 can be used to control the control signal DCCCTRL0B in the first control signal set. <3> and control signal DCCCTRL0B <4> Perform a NOR operation to obtain the enable signal AUX_0 in the third enable signal group. <3> The first NOT gate 1712 is used to enable the signal AUX_0. <3> Perform a NOT operation to obtain the enable signal AUX_0B from the first enable signal group. <3> .

[0151] For example, continue to refer to Figure 17 The control signal DCCCTRL1B in the first control signal set can be controlled by a NAND gate 1721. <1> and control signal DCCCTRL1B <4> Perform a NAND operation to obtain the enable signal AUX_1 in the fourth enable signal group. <1> The second NOT gate 1722 is used to enable the signal AUX_1. <1> Perform a NOT operation to obtain the enable signal AUX_1B from the second enable signal group. <1> Similarly, a NAND gate 1721 can be used to control the control signal DCCCTRL1B in the first control signal set. <2> and control signal DCCCTRL1B <4> Perform a NOR operation to obtain the enable signal AUX_1 in the fourth enable signal group. <2> The second NOT gate 1722 is used to enable the signal AUX_1. <2> Perform a NOT operation to obtain the enable signal AUX_1B from the second enable signal group. <2> Similarly, a NAND gate 1721 can be used to control the control signal DCCCTRL1B in the first control signal set. <3> and control signal DCCCTRL1B <4> Perform a NOR operation to obtain the enable signal AUX_1 in the fourth enable signal group. <3> The second NOT gate 1722 is used to enable the signal AUX_1. <3> Perform a NOT operation to obtain the enable signal AUX_1B from the second enable signal group. <3> .

[0152] This disclosure provides a memory, with reference to... Figure 18 The memory 20 includes the duty cycle adjustment circuit 10 in any of the above embodiments.

[0153] This disclosure provides a duty cycle adjustment method applied to a duty cycle adjustment circuit, with reference to... Figure 19 The method includes steps S101 and S102, wherein:

[0154] Step S101: Based on the first duty cycle control signal set, adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal to obtain the second clock signal;

[0155] Step S102: Based on the second duty cycle control signal set, adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal to obtain the target clock signal.

[0156] The signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

[0157] In this embodiment of the present disclosure, based on a first duty cycle control signal set, the rising edge time or falling edge time of the first clock signal is adjusted and the first clock signal is inverted to obtain a second clock signal; based on a second duty cycle control signal set, the falling edge time or rising edge time of the second clock signal is adjusted and the second clock signal is inverted to obtain a target clock signal, thereby changing the duty cycle of the first clock signal.

[0158] In some embodiments, the first duty cycle control signal set includes a first control signal set, the first control signal set includes a first control signal group and a second control signal group, and the control signals corresponding to the same configuration bit in the first control signal group and the second control signal group form a pair of control signals.

[0159] The implementation of step S101 may include: step S1011a, based on the first pair of control signals in the first control signal set, adjusting the rising edge time or falling edge time of the first clock signal and inverting the first clock signal to obtain the second clock signal.

[0160] In some embodiments, the first duty cycle control signal set further includes a first enable signal set; the first enable signal set includes a first enable signal group and a second enable signal group, and the enable signals corresponding to the same configuration bit in the first enable signal group and the second enable signal group form a pair of enable signals;

[0161] The implementation of step S101 may include:

[0162] Step S1011b: Based on the first pair of control signals in the first control signal set, adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal to obtain the first sub-output signal;

[0163] Step S1011c: Based on the (r+1)th pair of control signals in the first control signal set and the rth pair of enable signals in the first enable signal set, adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal to obtain the (r+1)th sub-output signal; the value of r is a positive integer greater than or equal to 1 and less than or equal to R-1.

[0164] Step S1011d: Based on the R+1th pair of control signals in the first control signal set, adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal to obtain the R+1th sub-output signal.

[0165] The second clock signal is determined based on the first sub-output signal to the (R+1)th sub-output signal.

[0166] In some embodiments, when the first control signal group in the control signal set for controlling the first duty cycle changes from 01111 to 00000, the duty cycle of the first clock signal gradually decreases.

[0167] When the second control signal group in the control signal set for controlling the first duty cycle changes from 10000 to 11111, the duty cycle of the first clock signal gradually increases.

[0168] In this embodiment of the disclosure, when the control signal in the first duty cycle control signal set is increased, the adjustment range of the duty cycle is also increased by a certain value, thereby improving the linearity of the duty cycle.

[0169] The duty cycle adjustment circuit provided in this embodiment is similar to the duty cycle adjustment method provided in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0170] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0171] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0172] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0173] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims. < / r> < / r> < / r> < / r> < / r> < / r>

Claims

1. A duty cycle adjustment circuit, characterized in that, include: The system comprises a first adjustment module, a second adjustment module, a third adjustment module connected in parallel with the first adjustment module, and a fourth adjustment module connected in parallel with the second adjustment module; wherein the output terminal of the first adjustment module is connected to the input terminal of the second adjustment module, and the output terminal of the third adjustment module is connected to the input terminal of the fourth adjustment module. The first adjustment module is used to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first duty cycle control signal set to obtain the first output signal; The third adjustment module is used to: adjust the rising edge slope or falling edge slope of the first clock signal based on the switching ratio control signal to obtain a second output signal, wherein the first output signal and the second output signal are superimposed to form a second clock signal; The second adjustment module is used to: adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal based on the second duty cycle control signal set to obtain a third output signal; The fourth adjustment module is used to: adjust the rising edge slope or falling edge slope of the second clock signal based on the switching ratio control signal, and output a fourth output signal, wherein the third output signal and the fourth output signal are superimposed to form a target clock signal; The first adjustment module and the second adjustment module have the same structure, the third adjustment module and the fourth adjustment module have the same structure, and the signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

2. The circuit according to claim 1, characterized in that, The first adjustment module includes: a first adjustment unit, wherein the first adjustment unit includes transistors of different types; The first duty cycle control signal set includes a first control signal set, which includes a first control signal group and a second control signal group. The control signals corresponding to the same configuration bit in the first control signal group and the second control signal group form a pair of control signals. The first control signal set is used to control the conduction rate of different types of transistors in the first adjustment unit. The first adjustment unit is used to adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first pair of control signals in the first control signal set to obtain the second clock signal.

3. The circuit according to claim 2, characterized in that, The first adjustment unit includes a first transistor group consisting of multiple transistors connected in series. The first transistor group includes two types of transistors, and the ratio of the two types of transistors is 1:

1.

4. The circuit according to claim 3, characterized in that, The first transistor group includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor connected in series; Wherein, the first transistor, the second transistor, and the third transistor are P-type transistors; the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors; The first gate of the first transistor and the sixth gate of the sixth transistor are both used to receive the first clock signal, the second gate of the second transistor and the third gate of the third transistor are both used to receive one signal of the first pair of control signals in the first control signal set, and the fourth gate of the fourth transistor and the fifth gate of the fifth transistor are both used to receive the other signal of the first pair of control signals in the first control signal set.

5. The circuit according to any one of claims 2 to 4, characterized in that, The first adjustment module further includes R second adjustment units connected in parallel with the first adjustment unit, the second adjustment units including transistors of different types; The first duty cycle control signal set further includes a first enable signal set; the first enable signal set includes a first enable signal group and a second enable signal group, and the enable signals corresponding to the same configuration bit in the first enable signal group and the second enable signal group form a pair of enable signals; The first set of control signals is also used to control the conduction rate of different types of transistors in the second adjustment unit; The first adjustment unit is configured to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first pair of control signals in the first control signal set to obtain a first sub-output signal; The r-th second adjustment unit is configured to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the (r+1)-th pair of control signals in the first control signal set and the r-th pair of enable signals in the first enable signal set to obtain the (r+1)-th sub-output signal; wherein the value of r is a positive integer greater than or equal to 1 and less than or equal to R-1. The Rth second adjustment unit is used to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the R+1th pair of control signals in the first control signal set to obtain the R+1th sub-output signal. The second clock signal is determined by the first sub-output signal to the (R+1)th sub-output signal.

6. The circuit according to claim 5, characterized in that, Each of the second adjustment units includes S second transistor groups and T third transistor groups, wherein the T third transistor groups, the S second transistor groups, and the output terminal of the first adjustment unit are all coupled to a first node for outputting the second clock signal; Each of the second transistor groups is used to receive a pair of enable signals from the first clock signal and the first enable signal; Each of the third transistor groups is configured to receive a pair of control signals from the first clock signal and the first control signal. S is 0 or 1, and T is a positive integer greater than or equal to 1.

7. The circuit according to claim 6, characterized in that, The second adjustment unit includes one of the following: a second transistor group and a third transistor group; One second transistor group and three third transistor groups; The six third transistor groups.

8. The circuit according to claim 6 or 7, characterized in that, The second transistor group includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor connected in series; The seventh gate of the seventh transistor and the tenth gate of the tenth transistor are both used to receive the first clock signal, and the eighth gate of the eighth transistor and the ninth gate of the ninth transistor are used to receive a pair of enable signals from the first enable signal set. The third transistor group includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor connected in series; the eleventh gate of the eleventh transistor and the fourteenth gate of the fourteenth transistor are both used to receive the first clock signal, and the twelfth gate of the twelfth transistor and the thirteenth gate of the thirteenth transistor are used to receive a pair of control signals from the first control signal set.

9. The circuit according to claim 6 or 7, characterized in that, The value of R is 4. The first and second second adjustment units each include one second transistor group and one third transistor group. The third second adjustment unit includes one second transistor group and three third transistor groups. The fourth second adjustment unit includes six third transistor groups. The number of configuration bits in the first control signal set is 5.

10. The circuit according to claim 5, characterized in that, The circuit further includes: a decoding module, a first generation module, and a second generation module; wherein... The decoding module is configured to: receive two configuration signals and generate the first control signal set based on the two configuration signals; The first generation module is configured to generate a second control signal set from the second duty cycle control signal set based on the first control signal set; The second generation module is used to generate the first enable signal set and the second enable signal set in the second duty cycle control signal set based on the first control signal set; The first adjustment module is configured to: adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal based on the first control signal set and the first enable signal set to obtain the second clock signal; The second adjustment module is configured to: adjust the falling edge time or rising edge time of the second clock signal and invert the second clock signal based on the second control signal set and the second enable signal set, so as to obtain the target clock signal.

11. The circuit according to claim 10, characterized in that, The first generation module includes a NOT gate, used to perform NOT operation on the control signals in the first control signal set to obtain the second control signal set; The second generation module includes R-1 first generation units and R-1 second generation units; Each of the first generation units includes a NOR gate and a first NOT gate connected to the output of the NOR gate; Each of the second generation units includes a NAND gate and a second NOT gate connected to the output of the NAND gate.

12. A memory, characterized in that, include: The duty cycle adjustment circuit as described in any one of claims 1 to 11.

13. A method for adjusting the duty cycle of a clock signal, characterized in that, include: Based on the first duty cycle control signal set, the rising edge time or falling edge time of the first clock signal is adjusted and the first clock signal is inverted to obtain the first output signal; Based on the switching ratio control signal, the rising edge slope or falling edge slope of the first clock signal is adjusted to obtain the second output signal. The first output signal and the second output signal are superimposed to form the second clock signal. Based on the second duty cycle control signal set, the falling edge time or rising edge time of the second clock signal is adjusted and the second clock signal is inverted to obtain the third output signal; Based on the switching ratio control signal, the rising edge slope or falling edge slope of the second clock signal is adjusted to output a fourth output signal. The third output signal and the fourth output signal are superimposed to form the target clock signal. The signals in the second duty cycle control signal set are complementary to the signals in the first duty cycle control signal set.

14. The method according to claim 13, characterized in that, The first duty cycle control signal set includes a first control signal set, which includes a first control signal group and a second control signal group. The control signals corresponding to the same configuration bit in the first control signal group and the second control signal group form a pair of control signals. The step of adjusting the rise time or fall time of the first clock signal and inverting the first clock signal based on the first duty cycle control signal set to obtain the second clock signal includes: Based on the first pair of control signals in the first control signal set, the rising edge time or falling edge time of the first clock signal is adjusted and the first clock signal is inverted to obtain the second clock signal.

15. The method according to claim 14, characterized in that, The first duty cycle control signal set further includes a first enable signal set; the first enable signal set includes a first enable signal group and a second enable signal group, and the enable signals corresponding to the same configuration bit in the first enable signal group and the second enable signal group form a pair of enable signals; The step of adjusting the rise time or fall time of the first clock signal and inverting the first clock signal based on the first duty cycle control signal set to obtain the second clock signal includes: Based on the first pair of control signals in the first control signal set, the rising edge time or falling edge time of the first clock signal is adjusted and the first clock signal is inverted to obtain the first sub-output signal; Based on the (r+1)th pair of control signals in the first control signal set and the rth pair of enable signals in the first enable signal set, the rising edge time or falling edge time of the first clock signal is adjusted and the first clock signal is inverted to obtain the (r+1)th sub-output signal; the value of r is a positive integer greater than or equal to 1 and less than or equal to R-1. Based on the R+1th pair of control signals in the first control signal set, adjust the rising edge time or falling edge time of the first clock signal and invert the first clock signal to obtain the R+1th sub-output signal. The second clock signal is determined based on the first sub-output signal to the (R+1)th sub-output signal.

16. The method according to claim 15, characterized in that, When the first control signal group in the first duty cycle control signal set changes from 01111 to 00000, the duty cycle of the first clock signal gradually decreases. When the second control signal group in the first duty cycle control signal set changes from 10000 to 11111, the duty cycle of the first clock signal gradually increases.

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