Substrate processing apparatus and substrate processing method

Abstract

The device is configured to include: a shared conveying mechanism that is used for conveying mutually separate first and second sections in a conveying path, conveying substrates to a first relay module included in the first section and a second relay module included in the second section, respectively, among a plurality of relay modules; and a determination unit that determines which relay module among the first and second relay modules to convey the substrate to, based on the conveying status of the substrates in each section from the first and second relay modules to the relay module in front of the nearest processing module, viewed from the downstream side of the conveying path.

Description

Technical Field

[0001] This disclosure relates to a substrate processing apparatus and a substrate processing method. Background Technology

[0002] In the manufacturing process of semiconductor devices, various processes such as photolithography are performed on the semiconductor wafer (hereinafter referred to as wafer), which serves as a substrate. As a substrate processing apparatus for processing wafers, it is sometimes configured as a transport mechanism that sequentially transports wafers from multiple processing modules that perform different processes.

[0003] Patent Document 1 discloses a substrate transport apparatus that performs a first action and a second action other than the first action. The first action is a transport operation from a processing unit that processes a substrate to a substrate accumulation unit, and the second action is, for example, a substrate transport operation between processing units. It is described that the first action is preferably performed when a need to perform the first action arises during the second action, and the second action is preferentially performed in other cases.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 4417134 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] This disclosure provides a technique for achieving high throughput in a substrate processing apparatus for transferring and processing substrates between multiple processing modules.

[0009] Solution for solving the problem

[0010] The substrate processing apparatus disclosed herein includes: a module group comprising a plurality of processing modules for processing substrates respectively, and a plurality of relay modules for respectively loading the substrates and transferring the substrates between the plurality of processing modules; a plurality of transfer mechanisms, wherein the plurality of transfer mechanisms use a common transfer mechanism to transfer the substrates into and out of the processing modules, and use different transfer mechanisms to transfer the substrates into and out of the relay modules, the plurality of transfer mechanisms respectively transferring within an assigned section in a substrate transfer path formed by the module group, so as to sequentially transfer the substrates in the transfer path; and a common transfer mechanism constituting the plurality of processing modules. A conveying mechanism is provided for conveying the substrate to a first interval and a second interval that are separate from each other in the conveying path of the substrate, and conveying the substrate to a first relay module included in the first interval and a second relay module included in the second interval of the plurality of relay modules respectively; and a determining unit determines which relay module of the first relay module and the second relay module to convey the substrate to based on the conveying status of the substrate in each interval from the first relay module and the second relay module to the downstream side of the conveying path up to the nearest relay module in front of the processing module.

[0011] The effects of the invention

[0012] According to this disclosure, a high throughput can be achieved in a substrate processing apparatus for transferring and processing substrates between multiple processing modules. Attached Figure Description

[0013] Figure 1 This is a cross-sectional top view of a coating and developing apparatus as one embodiment of the present disclosure.

[0014] Figure 2 This is a longitudinal sectional side view of the coating and developing apparatus.

[0015] Figure 3 This is a schematic diagram showing the general configuration of the modules and conveying mechanism in the coating and developing apparatus.

[0016] Figure 4 This is a top view of the processing block located in the coating and developing apparatus.

[0017] Figure 5 This is a longitudinal sectional side view of the interface block located in the coating and developing apparatus.

[0018] Figure 6 This is a schematic diagram showing the wafer transport path in the coating and developing apparatus.

[0019] Figure 7 This is an illustrative diagram showing the layers a wafer passes through.

[0020] Figure 8 This is a schematic diagram showing the wafer transport process.

[0021] Figure 9 This is a schematic diagram showing the wafer transport process.

[0022] Figure 10 This is a schematic diagram showing the wafer transport process.

[0023] Figure 11 This is a schematic diagram showing the wafer transport process.

[0024] Figure 12 This is a schematic diagram showing the wafer transport process.

[0025] Figure 13 This is a schematic diagram showing the wafer transport process.

[0026] Figure 14 This is a schematic diagram showing the wafer transport process.

[0027] Figure 15 This is a schematic diagram showing the wafer transport process.

[0028] Figure 16 This is a schematic diagram showing the wafer transport process.

[0029] Figure 17 This is a schematic diagram showing the wafer transport path.

[0030] Figure 18 This is a schematic diagram showing the wafer transport process. Detailed Implementation

[0031] Reference Figure 1 Cross-sectional top view and Figure 2 The coating and developing apparatus 1, which is an embodiment of the substrate processing apparatus of this disclosure, will be described using a longitudinal sectional front view. The coating and developing apparatus 1 is configured such that a carrier block D1, an inspection block D2, a processing block D3, and an interface block D4 are arranged in a horizontal row and connected to each other. In the following description, the arrangement direction of the blocks D1 to D4 will be defined as the left-right direction, with the carrier block D1 side designated as the left side and the interface block D4 side designated as the right side. An immersion exposure machine (EIF) for performing immersion exposure is connected to the right side of the interface block D4. Furthermore, regarding the front-rear direction of the coating and developing apparatus, the side in front, where the carrier block D1 is on the left and the interface block D4 is on the right, will be defined as the front side, and the side in the deepest part will be defined as the rear side.

[0032] The coating and developing apparatus 1 comprises numerous modules and numerous conveying mechanisms (conveyor arms). Multiple wafers W are transported in batches from the external carrier C of the coating and developing apparatus 1. For each wafer W, the numerous conveying mechanisms within the coating and developing apparatus 1 transport its assigned section within the conveying path, causing the wafer W to move sequentially through the modules constituting the conveying path. Thus, after undergoing a series of processing steps, the wafer W returns to the carrier C. Furthermore, for illustration purposes, in... Figure 2 In the middle, a portion of the conveying mechanism is shown deviating to the left or right. Figure 1 The location shown is [the location].

[0033] A module is a location for placing wafers W, including a processing module (process module) that processes the wafers W and a relay module (designated as a relay module) that places the wafers W to relay the transfer of wafers W between processing modules. The relay module includes a transfer module TRS, a buffer module SBU, and a temperature adjustment module ICPL. The TRS and SBU are configured to hold multiple wafers W longitudinally. For example, these modules may have multiple pins or stages located at different heights, on which wafers W are placed. The area where wafers W are placed on pins or stages is called a slot; the SBU has more slots than the TRS. Furthermore, the temperature adjustment module ICPL has a stage for adjusting the temperature of the placed wafers W.

[0034] To further explain the modules, for each of the aforementioned relay modules, wafer W is moved in by one conveyor mechanism and moved out by another. That is, the conveyor mechanisms used for moving in and out are different. On the other hand, for the processing module, a common conveyor mechanism is used for both moving in and out of wafer W. The processing module performs liquid processing and heat treatment on wafer W, and this processing also includes inspection of wafer W. Furthermore, during the conveying control described later, the exposure machine EIF is also treated as a processing module.

[0035] The aforementioned transfer modules TRS are located throughout the device. In the following descriptions and figures, each TRS will sometimes be labeled with a number to distinguish it from the others. These numbers are assigned according to the order in which wafer W is transported along the transport path. Furthermore, as a processing module, temperature control modules SCPL, configured similarly to ICPL, are located throughout the device to adjust the temperature of wafer W. These SCPLs, like the TRSs, are also labeled with numbers according to the transport sequence. Additionally, the number of TRSs and SCPLs located in the same steps along the transport path is specified in the figures. Figure 2 In order to avoid complicating the diagram, the number of elements shown is less than the actual number.

[0036] Figure 3 The arrangement of the modules and conveying mechanism in the coating and developing apparatus 1 is shown in summary. However, to avoid complicating the description, the representation of several modules installed in the actual apparatus is omitted. Additionally, in Figure 3 In the diagram, the arrows with dotted lines represent the outline of the transport path of wafer W within the device. When there are multiple modules destined for wafer W, wafer W is transported to a specific module.

[0037] The following describes each component of the coating and developing apparatus 1. The carrier block D1 includes multiple carrier stages 11 for holding the aforementioned carrier C, and a CRA serving as a transport mechanism for transferring wafers W between the carrier C and the coating and developing apparatus 1. The inspection block D2 includes an inspection module WIS for inspecting wafers W before processing by the coating and developing apparatus 1, and an inspection module YSM for inspecting wafers W after processing by the coating and developing apparatus 1, and transfers wafers W to various heights of the processing block D3.

[0038] From left to right, in the center of the front and rear of inspection block D2, the following are arranged sequentially: a stack of transfer modules TRS (TRS1, TRS13), the MRA (middle mechanism) serving as a conveying mechanism, and tower T1. Inspection module WIS is located above TRS1 and TRS13, and inspection module YSM is located behind the MRA. The MRA has access to TRS1, TRS13, each inspection module, and some modules included in tower T1. MPRA, serving as a conveying mechanism, is located behind tower T1 and has access to all modules of tower T1.

[0039] Tower T1 is constructed by stacking a large number of transfer modules (TRS) and a large number of temperature adjustment modules (SCPL). Processing block D3 is constructed by stacking unit blocks E1 to E6, which will be described in detail later. Corresponding to the structure of processing block D3, the transfer mechanism in tower T1, located at each unit block E (E1 to E6), is capable of transferring wafers W at a certain height and is equipped with transfer modules (TRS3 to TRS5, TRS11) and temperature adjustment modules (SCPL1 to SCPL4). In addition to the TRS for transferring each unit block E, tower T1 also includes TRS (TRS2, TRS12) for transferring wafers W within inspection block D2.

[0040] Next, processing block D3 will be described. Processing block D3 is constructed by stacking unit blocks E (E1 to E6) sequentially from bottom to top, each used for liquid processing and heat treatment of wafer W. The same processing is performed between unit blocks E1 and E2, between E3 and E4, and between E5 and E6. In unit blocks E1 and E2, an anti-reflective film is formed and the back side of wafer W is cleaned before exposure. In unit blocks E3 and E4, a resist film is formed on the anti-reflective film and a protective film is formed to protect the resist film during immersion exposure. In unit blocks E5 and E6, development processing is performed. Therefore, wafer W is transported between unit blocks in the order of E1, E2→E3, E4→E1, E2→E5, E6. The wafer W is transported in transport path 21, which is separated according to each unit block E. However, for the right side of unit blocks E1 and E2, transport path 21 is not separated, forming transport path 22 across unit blocks E1 and E2.

[0041] Reference Figure 4 The unit block E3 is illustrated by a top view. The aforementioned transport path 21 extends laterally. Along the front side of the transport path 21, three resist coating modules (COT) and three protective film forming solution coating modules (ITC) are arranged. At the rear side of the transport path 21, eleven heating modules (PAB) and an inspection module (WES) for inspecting the wafer W after the protective film formation are arranged. Of the eleven heating modules (PAB), some are arranged in two overlapping stages and are configured along the transport path 21. Furthermore, a portion of the heating modules (PAB) are used for heating the wafer W after resist film formation, while another portion of the heating modules (PAB) are used for heating the wafer W after protective film formation. A transport mechanism (PRA3) is provided on the transport path 21. PRA3 is used to access the modules located in unit block E3, as well as the modules located at the height of unit block E3 in towers T1 and T2 (described later).

[0042] Unit block E4 has the same structure as unit block E3. Regarding unit block E5, the description focuses on the differences from units E3 and E4. Eight developing modules (DEVs) are located in front of transport path 21. In practice, multiple DEVs supplying different developers are used, but detailed descriptions are omitted. Six heating modules (PEBs) for post-exposure baking and an inspection module (WISD) for inspecting the wafer W after development are located behind transport path 21. Unit block E6 has the same structure as unit block E5. The transport mechanisms corresponding to PRA3 located in units E4 to E6 are... Figure 2 These are represented as PRA4 to PRA6.

[0043] Next, refer to Figure 1The unit block E1 will be described focusing on its differences from unit block E3. As mentioned above, regarding the transport path of unit block E1, the left side is configured as transport path 21, which is separate from the transport path of unit block E2, and the right side is configured as transport path 22, which is connected to the transport path of unit block E2. Three anti-reflective coating coating modules BCT are provided in front of transport path 21. Six heating modules PAB for heating the wafer W after anti-reflective coating formation and a hydrophobic treatment module CWH for hydrophobic treatment of wafer W are provided behind transport path 21. PRA1 is provided in transport path 21 as a transport mechanism corresponding to PRA3.

[0044] Describing unit block E2, its left side is constructed in the same manner as the left side of unit block E1, and a PRA2 corresponding to PRA3 is provided on transport path 21. Furthermore, a total of six back-side cleaning modules (BSTs) are provided in front of and behind the aforementioned transport path 22 spanning unit blocks E1 and E2, with two arranged on each side along the transport path 22. A PRAI, serving as a shared transport mechanism in unit blocks E1 and E2, is provided on transport path 22 for accessing each BST and each module located at the height of unit blocks E1 and E2 in tower T2 (described later).

[0045] Next, refer to the viewpoint indicating a top-down perspective. Figure 1 and longitudinal sectional side view Figure 5 Let's describe interface block D4. The aforementioned tower T2 is located on the left side of the center, in front of and behind interface block D4. Tower T2 is constructed by stacking multiple interface modules TRS (TRS6 to TRS10) and multiple temperature adjustment modules ICPL. On the upper right front of tower T2, four cleaning modules PIR are arranged vertically. Each PIR is used to clean and remove the protective film from the wafer W after EIF exposure and before PEB. A buffer module SBU is located on the upper right rear of tower T2.

[0046] Interface block D4 includes IRAMC, IRAMB, and IRAI as transport mechanisms. Transport mechanism IRAMC is located on the right side of tower T2, at the center of the front and rear of interface block D4, and is used to access the cleaning module PIR, the buffer module SBU, and the various TRS units from the top to the center of tower T2. Transport mechanism IRAMB is located at the rear of tower T2 and is used to access modules and SBU units at various heights of tower T2. Transport mechanism IRAI is used to access the exposure unit EIF, the ICPL located on the lower side of tower T2, and the TRS units at the center of tower T2.

[0047] Supplementary descriptions are provided for each conveying mechanism installed within the coating and developing apparatus 1. Each conveying mechanism includes a substrate holding section 31, a base 32, and a moving section 33 (see reference). Figure 5The substrate holding part 31 moves forward and backward on the base 32. The base 32 is configured to rotate freely and move up and down freely about a vertical axis via the moving part 33. Regarding CRA, PRA1 to PRA6, PRAI and IRAI, a horizontal moving mechanism 34 is provided for moving the moving part 33 in the horizontal direction, which is configured to access each of the described modules and each carrier C.

[0048] Each of the transport mechanisms PRA1 to PRA6, PRAI, and IRAMC has two substrate holding sections 31, which move independently forward and backward on the base 32. Therefore, with these transport mechanisms, a wafer W can be received from the module by moving one substrate holding section 31 forward and backward, and then the other substrate holding section 31 enters the module to deliver the held wafer W to the module. In other words, the wafer W can be replaced in the module without lateral movement or rotation of the base 32. The following transport can be defined as a replacement transport: a wafer W is transported from a module preceding the module to the module to be replaced, then the wafer W is replaced in the module to be replaced, and finally, the wafer W received through replacement is transported to a module following the module to be replaced.

[0049] The coating and developing apparatus 1 includes a control unit 10 (see reference). Figure 1 The control unit 10 is a computer, equipped with a program, memory, and CPU. The program contains a set of steps that enable the execution of a series of actions within the coating and developing apparatus 1. Furthermore, the control unit 10 outputs control signals to each part of the coating and developing apparatus 1 via this program to control the operation of each part. This allows for the transport and processing of the wafer W according to this embodiment. The aforementioned program is stored on a storage medium such as an optical disc, hard disk, or DVD and installed into the control unit 10.

[0050] Next, refer to Figure 6 This describes the transfer of wafer W and the series of processes performed on wafer W in the coating and developing apparatus 1. Figure 6 The upper part is a schematic diagram of the coating and developing apparatus 1, used to represent the transport path of the wafer W. Figure 6 The lower part of the module is labeled according to the conveying sequence. Below each module, the conveying mechanism used for moving the module in and out is shown. The upper side shows the conveying mechanism used for moving in, and the lower side shows the conveying mechanism used for moving out.

[0051] The wafer W is removed from the carrier C by the CRA of the carrier block D1 and transported to the transfer module TRS1 of the inspection block D2. After being inspected by the MRA and transported to the inspection module WIS, the wafer W is transported by the MRA to the TRS2 of tower T1, and further transported by the MPRA to the TRS3 of tower T1.

[0052] The wafer W, which is transferred to TRS3, is moved by PRA1 or PRA2 in unit blocks E1 and E2 in the order of CWH, SCPL1, BCT, PAB. After undergoing hydrophobication treatment, temperature adjustment, anti-reflective coating formation, and heat treatment in sequence, it is transferred to TRS4. Then, the MPRA moves the wafer W from TRS4 to TRS5.

[0053] The wafer W in TRS5 is transported by PRA3 or PRA4 in unit block E3 or E4 in the following order: SCPL2 of tower T1, resist coating module COT, heating module PAB, SCPL3 of tower T1, chemical coating module ITC, heating module PAB, and inspection module WES. Thus, after undergoing temperature adjustment, resist film formation, heat treatment, temperature adjustment again, protective film formation, heat treatment, and inspection in sequence, the wafer W is transported by PRA3 or PRA4 to TRS6 of tower T2.

[0054] Wafer W, after being transferred to TRS6, is moved from IRAMC to SBU and held there before being transferred by IRAMB to TRS7 in tower T2. Then, after being back-side cleaned by PRAI at BST, wafer W is transferred to TRS8 and then to ICPL by IRAMB. Finally, wafer W is transferred by IRAMAI to the EIF exposure unit for exposure of the resist film according to the specified pattern.

[0055] After wafer W is removed from the exposure unit EIF by IRA and transported to TRS9 in tower T2, it is further transported by IRAMC to the cleaning module PIR for cleaning, and then by IRAMC to TRS10. Wafer W transported to TRS10 is then moved by PRA5 or PRA6 in unit blocks E5 or E6 in the order of heating module PEB, SCPL4, developing module DEV, and inspection module WISD. Thus, wafer W undergoes heat treatment, temperature adjustment, developing, and inspection in sequence. During developing, a resist pattern is formed according to the exposed pattern. Afterwards, wafer W is transported by PRA5 or PRA6 to TRS11 in tower T1, and after being transported by MPRA to TRS12, it is transported by MRA to the inspection module YSM for inspection. Finally, MRA transports wafer W to TRS13, and CRA returns wafer W to carrier C.

[0056] In the aforementioned wafer W transport path, the range within which a transport mechanism transports wafer W is designated as a "layer". For example, regarding PRA3, as described above, transport occurs from TRS5 to TRS6, and therefore the modules within this range constitute a layer corresponding to PRA3. Thus, a layer corresponds to the intervals of the transport path divided by each transport mechanism responsible for transport. Regarding each layer, the layer corresponding to a transport mechanism other than PRA (PRA1 to PRA6) is labeled with the same name as that transport mechanism. Therefore, these layers are designated as CRA layer, MRA layer, MPRA layer, PRAI layer, IRAI layer, IRAMB layer, and IRAMC layer. The layers corresponding to PRA1 and PRA2 are designated as BCT layers, the layers corresponding to PRA3 and PRA4 are designated as COT / ITC layers, and the layers corresponding to PRA5 and PRA6 are designated as DEV layers. Therefore, when viewed in layers, wafer W is transported in the following order: CRA layer → MRA layer → MPRA layer → BCT layer → MPRA layer → COT / ITC layer → IRAMC layer → IRAMB layer → PRAI layer → IRAMB layer → IRAI layer → IRAMC layer → DEV layer → MPRA layer → MRA layer → CRA layer.

[0057] In the BCT, COT / ITC, and DEV layers, the transport mechanisms of each layer move sequentially and cyclically within the modules of that layer, replacing the wafer W as described above with each module except for the module at the layer's entrance and exit. Thus, in each of these layers, wafer W is transported sequentially from the upstream module to the downstream module. The IRAMC and PRAI layers can also be transported in the same manner as the BCT layers, but the decision to perform replacement transport in these layers is based on the block cycle time (block CT), a time parameter calculated for each layer. Furthermore, performing replacement transport enables transport (cyclic transport) in which the transport mechanisms move cyclically within each module of the layer. By performing cyclic transport, movement of the transport mechanisms within the layer is suppressed, thereby efficiently transporting the wafer W.

[0058] The block CT described above will now be explained. Each batch of wafers W on each carrier C corresponds to a process task (PJ), which specifies the processing procedure for the wafers W. Based on this processing procedure, the "processing time of wafer W" + "time required before and after processing" = "module using time (MUT) of wafer W required in the module" is calculated for each processing module. Furthermore, the MUT of processing modules at the same step in the transport path is divided by the total number of usable processing modules, and this value is used as the MUT cycle time (MUTCT). An example of MUTCT calculation is shown. In unit blocks E1 and E2, there are 3 BCTs each, for a total of 6 BCTs, and it is assumed that all of these BCTs are usable. Moreover, when the MUT of a BCT is set to 66.0 seconds, the MUTCT of that BCT is 66.0 seconds / 6 = 11.0 seconds.

[0059] Then, the maximum value of the MUTCT is determined for each layer. In the BCT layer, as described above, wafer W is transported in the order TRS3→CWH→SCPL1→BCT→TRS4, ​​and the processing modules within the layer are CWH, SCPL1, and BCT. Therefore, the maximum value of the MUTCT calculated for these processing modules is determined. For example, the MUTCT of BCT described above is set to 11.0 seconds and is determined to be the maximum value. That is to say, when the arm cycle time as the transport time of wafer W is not considered (described later), the processing speed of wafer W in the BCT layer is limited by BCT.

[0060] Next, the arm operation number will be explained. The arm operation number refers to the number of times the conveying mechanism (conveyor arm) moves the wafer W from the layer's entrance to its exit. In the BCT layer, the wafer W is moved between 5 modules as described above, therefore the arm operation number is 4, which is the number of modules. The set time required for one arm operation is predetermined, for example, set to 3.7 seconds. Furthermore, the arm cycle time (ACT) = arm operation number × set time ÷ number of layers performing the same process. In the BCT layer, these are set in unit blocks E1 and E2, and they perform the same process, therefore the number of layers performing the same process is 2. Therefore, ACT = 4 × 3.7 ÷ 2 = 7.4 seconds.

[0061] When the maximum value of MUTCT is compared with ACT in the BCT layer, the maximum value of MUTCT, 11.0 seconds, is greater than that of ACT, 7.4 seconds. Therefore, the speed limit for productivity in the BCT layer is not the operation of the transport mechanism, but the processing time in the BCT. Thus, in the layer, the maximum value of MUTCT is compared with ACT, and the larger one is set as the block CT. The block CT calculated in this way is the time required for one cycle of transport in the layer, that is, the time required for the transport mechanism to perform one transport between each module it is responsible for, which is equivalent to the expected time interval for transporting wafer W to the next layer. Furthermore, as mentioned above, the processing time of the processing module is used in the calculation of block CT, but the processing time of the exposure machine EIF is determined by obtaining information about the removal interval of wafer W from the exposure machine EIF from the control unit 10.

[0062] Figure 7 The layers are arranged in the order of the wafer W's transport path, and the calculated block CT (unit: seconds) is shown below each layer. Furthermore, the values ​​of these block CTs are recorded to aid understanding of the transport control described later and may not necessarily correspond to actual values. For the block CTs of the BCT layers, values ​​different from those shown in the explanation of the block CT calculation method described above are displayed. Additionally, for layers such as the MPRA layer and the IRAMC layer, wafer W passes through them multiple times. Since the block CTs are calculated and defined as described above, the block CTs are the same for the same layers, thus the same block CT values ​​are recorded for the same layers in each part of the figure. (See reference...) Figures 8 to 16 The diagram is used to illustrate how it is set up. Figure 7 The transfer performed by the transfer mechanism IRAMC in the case of calculating block CT as shown is illustrated. In these diagrams, the modules within interface block D4 are shown arranged longitudinally according to the transfer sequence of wafer W.

[0063] Regarding the transport organization IRAMC, such as Figure 6 , Figure 7 The diagram shows a shared conveying mechanism used for conveying data from the transfer module TRS6 to the buffer module SBU (second section), the transfer module TRS9 to the cleaning module PIR, and the transfer module TRS10 (first section) along the conveying path. PIR is equivalent to a processing module, and TRS10, SBU, and TRS9 are equivalent to the first, second, and third relay modules, respectively.

[0064] Let's define the point in time when wafer W in PIR finishes processing and becomes ready to be moved out, but wafer W is not yet moved to TRS9. Figure 8At this point, the IRAMC transport mechanism waits for the transfer of wafer W from PIR to TRS10. The upper limit of this waiting time (waiting time) is determined based on the block CT mentioned above. More specifically, it is determined based on the block CTs of the layers preceding the layer in the transport path. Furthermore, in the case of multiple identical layers on the transport path, the layer in which the waiting occurs refers to the layer in the step where the waiting occurs. That is, although wafer W passes through the IRAMC layer twice, the IRAMC layer passed through the second time meets the criteria for the layer in which the waiting occurs.

[0065] like Figure 7 As shown, the preceding layers of the IRAMC layer during the waiting period include CRA, MRA, MPRA, BCT, MPRA, COT / ITC, IRAMC, IRAMB, PRAI, and IRAI layers. Furthermore, the block CT intervals for the CRA, MRA, MPRA, BCT, COT / ITC, IRAMC, IRAMB, PRAI, and IRAI layers are 7.5 seconds, 3.7 seconds, 6.6 seconds, 9.9 seconds, 7.2 seconds, 8.9 seconds, 7.4 seconds, 9.0 seconds, and 10.0 seconds, respectively. Therefore, the maximum value is 10.0 seconds for the IRAI layer. As already stated, the block CT is the time for one cycle of transport in each layer; therefore, the wafer W is typically transported to the IRAMC layer at 10.0-second intervals. Therefore, the waiting time is determined to be 10 seconds. That is, it is set to automatically wait for a maximum of 10.0 seconds from the time point when the PIR transfers wafer W.

[0066] During the 10.0-second wait time, when wafer W is transferred from the IRAI layer to TRS9 ( Figure 9 The IRAMC conveying mechanism performs replacement transport. That is, the wafer W receiving TRS9 ( Figure 10 Replace wafer W in PIR, and then transfer the processed wafer W from PIR to TRS10. Figure 11 On the other hand, if wafer W is not transferred to TRS9 even after a 10.0-second waiting period, it is determined whether there is a wafer W that the transfer mechanism IRAMC can transfer (whether there is wafer W at the transfer source and the module serving as the transfer destination is empty). That is, for TRS6→SBU and PIR→TRS10, it is determined whether a transfer can be performed. If only PIR→TRS10 transfer is possible, the transfer is performed. That is, the wafer W waiting to be transferred from PIR is transferred to TRS10. Figure 12 ).

[0067] On the other hand, suppose that after the aforementioned waiting time, both TRS6→SBU and PIR→TRS10 are determined to be capable of being transferred. In this case, it is determined how many wafers W exist in each interval from the relay module that transfers wafer W by the transfer mechanism IRAMC downstream of the transfer path up to the relay module immediately preceding the nearest processing module.

[0068] The interval in which the number of wafers W is determined (denoted as the wafer count interval) will be explained in more detail. Wafer W is transported by the transport mechanism IRAMC to the SBU, which acts as a relay module. The nearest downstream processing module from this SBU is the BST (refer to...). Figure 6 There is a relay module, TRS7, included in the PRAI layer, between BST and SBU. Therefore, SBU~TRS7 is one of the intervals for determining the number of sheets. Figure 13 The value is enclosed in dashed lines and indicated as 41. Furthermore, wafer W is transferred from IRAMC to TRS10, therefore TRS10 is included in the sheet count determination interval. Moreover, when viewed downstream from TRS10, the next module immediately following is the PEB (refer to) which is a processing module. Figure 6 Therefore, there is no module downstream of TRS10 that serves as the determination object. Consequently, only one TRS10 constitutes another sheet count determination interval. Figure 13 The number of wafers W is enclosed in dashed lines and denoted as 42. The number of wafers W is compared between these wafer count determination intervals 41 and 42 to determine which wafer count determination interval has the fewest wafers W. Furthermore, the transport mechanism IRAMC operates to transport the module to the wafer count determination interval with the fewest wafers W.

[0069] exist Figure 13 In the example shown, after a 10-second waiting period, there are 3 wafers W in SBU, 1 wafer W being transferred from SBU to TRS7 by the IRAMB transfer mechanism, and 0 wafers W in TRS7. Therefore, there are a total of 4 wafers W in wafer count determination interval 41. On the other hand, there is only 1 wafer W in TRS10, which is wafer count determination interval 42. Therefore, regarding the number of wafers W, SBU~TRS7 (4 wafers) > TRS10 (1 wafer), and the number of wafers in wafer count determination interval 42 (TRS10) is less. Therefore, IRAMC performs PIR→TRS10 transfer ( Figure 14 ).

[0070] The following description is as follows: Figure 13 , Figure 14The reason for the IRAMC conveying mechanism to transport wafers W as shown is that, in the conveying path, wafers W accumulate from a certain relay module downstream to the relay module immediately preceding the nearest processing module. This means that although wafers W are being transported to a certain relay module, there are pre-transported wafers W that are being transported to that processing module. If many pre-transported wafers W are present, even if wafers W are transported downstream from a certain relay module, it takes time for those wafers W to be processed in the aforementioned processing module. Conversely, if few pre-transported wafers W are present, there is a risk of increased intervals between wafers W being transported to the processing module, leading to a decrease in device productivity. In other words, the IRAMC mechanism is selected to transport which step of the conveying path of wafers W to supply an appropriate number of wafers W to each processing module.

[0071] Additionally, set to pass Figure 13 The comparison of the number of wafers W between the sheet count determination intervals 41 and 42 shows that the numbers are the same. In this case, for each interval of TRS6→SBU and TRS9→PIR→TRS10, the number of empty slots (slots not carrying wafers W) of the relay modules serving as the transport source is compared. That is, the number of empty slots in TRS6 is compared with the number of empty slots in TRS9, and the transport mechanism IRAMC accepts wafers W from the module with fewer empty slots and transports them downstream.

[0072] Specifically, for example, let's assume that the number of wafers W present in SBU~TRS7 (=sheet count determination interval 41) and TRS10 (=sheet count determination interval 42) is the same, with one wafer W each. In this case, the comparison of the number of empty slots between TRS6 and TRS9 is performed as described above. Figure 15 In the example, the number of slots in each TRS is set to 3, and it is shown that 1 wafer W is loaded into TRS6 and 0 wafer W is loaded into TRS9. Therefore, regarding empty slots (in Figure 15 The quantity of TRS6 (represented by dashed lines) is less than that of TRS9, therefore the IRAMC conveying mechanism performs the transfer of TRS6 to SBU. Figure 16 When the number of wafers W to be transferred in a module increases to the point that the slots are full, there is a backlog in the transfer process on the upstream side of that module. To prevent this, the wafers W to be transferred are selected in this way.

[0073] Suppose that if the result of comparing the number of empty slots is the same for TRS6 and TRS9 (which are the criteria for judgment), then the next step of the previous transfer is performed. That is, in the IRAMC layer, transfers are performed for TRS6→SBU, TRS9→PIR, and PIR→TRS10. If the previous transfer was TRS6→SBU, then the control is to perform a transfer for TRS9→PIR; if the previous transfer was TRS9→PIR, then the control is to perform a transfer for PIR→TRS10; and if the previous transfer was PIR→TRS10, then the control is to perform a transfer for TRS6→SBU. However, as explained so far, wafer W has not yet reached TRS9. Therefore, in this IRAMC layer, in fact, if the number of empty slots is the same, and the previous transfer was PIR→TRS10, then the transfer for TRS6→SBU is performed only for the current control. The process of making the next step after the previous transfer is also described in detail in the transfer instructions in the MPRA layer.

[0074] Additionally, when the IRAMC conveyor is not currently conveying wafer W, it will quickly move wafer W to the SBU while conveying wafer W to TRS6. Even if it is conveyed via... Figure 8 As explained, while waiting for wafer W to be transferred from PIR, wafer W is transferred to TRS6, and the transfer mechanism IRAMC immediately transfers wafer W to SBU. This is to prevent the following situation from occurring: TRS6, which can accommodate fewer wafers W than SBU, becomes congested, thus preventing the transfer of subsequent wafers W to TRS6.

[0075] For passing Figures 9-12 The description of the waiting time set during replacement in PIR is supplemented. As already stated, when wafer W can be removed from PIR but not transferred to TRS9, the waiting time is calculated based on the block CT of each layer. As mentioned above, the block CT of each layer is calculated based on the number of modules that can be used. That is, the waiting time during the transfer of a wafer W of PJ is not fixed and varies depending on the status of the modules at each layer.

[0076] The various comparisons, determinations, decisions, and calculations for transport control in the IRAMC layer described above are performed by the control unit 10. Hereinafter, the transport control performed in the MPRA layer and PRAI layer will be explained sequentially, focusing on the differences from transport in the IRAMC layer. The various determinations, decisions, and calculations for performing this transport control are also performed by the control unit 10, which constitutes the decision unit.

[0077] In the MPRA layer, such as Figure 6As shown, the wafer W is transported in three separate sections along its transport path: TRS2→TRS3, TRS4→TRS5, and TRS11→TRS12. If only one of these three sections can be transported, that section is transported. Conversely, if multiple sections can be transported, the transport is performed in a different manner. Figures 13-16 The explanation explains that the decision of which transport to perform in the IRAMC layer, either TRS6→SBU or PIR→TRS10, also determines which section to transport.

[0078] Reference Figure 17 , Figure 18 The decision to move wafers in the MPRA layer will be described in detail below. First, it is determined how many wafers W are present in each wafer count determination interval, looking downstream from the relay module that can be moved by the MPRA mechanism, up to the relay module immediately preceding the nearest processing module. Then, wafers W are moved to the relay modules in the wafer count determination intervals with fewer wafers. For example, it is assumed that wafers W can be moved in any of the following intervals: TRS2→TRS3, TRS4→TRS5, and TRS11→TRS12. Since CWH, SCPL2, and YSM, which are processing modules, are immediately located downstream of TRS3, TRS5, and TRS12 respectively, the wafer count determination intervals are TRS3, TRS5, and TRS12 (in Figure 17 (The upper part is indicated by a dashed arrow). That is, it is decided to move wafer W to modules with fewer wafers W in these TRS3, TRS5, and TRS12 modules. Figure 17 In the example shown, one wafer W is transported in TRS3, and two wafers W are transported in TRS5 and TRS12. Therefore, TRS3 has the fewest wafers W, so... Figure 17 As shown in the lower part, TRS2→TRS3 is transported.

[0079] When comparing the number of wafers W within the wafer count determination interval, and the number of wafers W in TRS3, TRS5, and TRS12 is the same, the number of empty slots in the relay modules that serve as the transfer source from MPRA to these modules is compared. Then, wafers W are transferred from the module with fewer empty slots. For example, in... Figure 18 As indicated by the dashed arrows at the top, the relay modules serving as the transfer sources for TRS3, TRS5, and TRS12 are TRS2, TRS4, ​​and TRS11, respectively. Figure 18 In the example shown, two wafers W are transported in TRS2, and one wafer W is transported in both TRS5 and TRS12. Therefore, TRS2 has the fewest empty slots. Figure 18As shown in the lower part, TRS2→TRS3 is transported.

[0080] Furthermore, when the number of empty slots in the transport sources is the same, the next step of the previous transport is performed. That is, if the previous transport was TRS2→TRS3, then TRS4→TRS5 is performed; if the previous transport was TRS4→TRS5, then TRS11→TRS12 is performed; and if the previous transport was TRS11→TRS12, then TRS2→TRS3 is performed. To further explain the reason for performing the next step in this way, consider that when the number of empty slots in the transport sources is the same, the layer that determines the transport destination of wafer W becomes the speed limit for transporting wafer W in the device, and wafer W is accumulated in this transport source. In addition, consider that in this layer, due to the aforementioned cyclic transport, the number of empty slots in each transport source becomes the same. If the transport is set to be carried out in a loop, it is expected that the loop will continue. Therefore, as described above, the next step of the transport that was just carried out will be carried out.

[0081] Next, the transport in the PRAI layer will be explained. The PRAI layer includes the back-side cleaning module (BST) as a processing module. Similar to the IRAM layer, it is determined whether to perform replacement transport in this BST. Therefore, if the processing in the BST ends at a certain time, the TRS7 (refer to...) of the preceding stage of the BST... Figure 6 If wafer W is transferred, PRAI accepts wafer W, replaces wafer W in BST, and transfers the received wafer W to TRS8.

[0082] If wafer W is not transferred to TRS7 after processing in BST, a waiting time is set in the same manner as for transfer in the IRAMC layer described above. This waiting time is set to be the longest time in the block CT of the layer preceding the PRAI layer. Therefore, in the case of... Figure 7 In the case of calculating block CT, the largest block CT in the layer preceding the PRAI layer is 9.9 seconds for the BCT layer, therefore this 9.9 seconds is set as the waiting time. If wafer W is moved to TRS7 before this waiting time has elapsed, the PRAI transport mechanism performs a replacement transport. If wafer W is not moved to TRS7 even after the waiting time has elapsed, the PRAI transport mechanism will move the wafer W processed in BST to TRS8. In other words, no replacement is performed in BST.

[0083] Furthermore, in the BST, the aforementioned waiting period is not observed during PJ switching. Specifically, if a PJ wafer W finishes processing in the BST and the next wafer W to be transferred to the BST is a wafer W from another PJ, no waiting occurs. For a PJ wafer W, it is immediately transferred to TRS8 as soon as the transfer mechanism PRAI is capable of transferring it. This is because the pressure within the BST sometimes changes during PJ switching. If a replacement is enabled, there is a risk that after the transfer mechanism PRAI receives a PJ wafer W from the BST, it cannot transfer the next PJ wafer W to the BST until the pressure change ends. In other words, by enabling no waiting, the stopping of the transfer performed by the transfer mechanism PRAI is prevented.

[0084] Similar to BST, the aforementioned waiting period does not occur during PJ switching at PIR. This is because the preparation work (reticle replacement, etc.) performed during PJ switching in the EIF (exposure equipment) preceding PIR takes time. In other words, after processing a PJ wafer W in PIR, it takes a relatively long time until it is transferred to another PJ wafer W.

[0085] Furthermore, for example, the wafer W to be replaced in the BST has not yet reached the processing module immediately preceding the BST (i.e., WES, see reference) from the BST's perspective. Figure 6 In the case of a wafer W, it takes a long time until the wafer W reaches the BST, so no waiting is performed. Similarly, if the wafer W to be replaced in the PIR has not reached the processing module immediately preceding the PIR (i.e., the EIF, see reference) from the PIR's perspective, no waiting is performed. Figure 6 In the case where a relatively long time is required until the wafer W reaches the PIR, no waiting is performed. It is possible to determine whether to wait based on the transport status of subsequent wafers W in the preceding processing module of the replacement module. Furthermore, the decision to wait is not limited to the arrival status of wafers W in the processing module immediately preceding the replacement module; for example, it can also be based on the arrival status of wafers W in the two or more preceding processing modules from the replacement module.

[0086] As described above, according to the coating and developing apparatus 1, wafers W are transported by a common transport mechanism in mutually separated sections (inter-steps) along the transport path. During this transport, the section in which wafer W is transported is determined based on the transport status of the wafer W as viewed downstream from the relay module being transported by this transport mechanism, up to the relay module in front of the nearest processing module. This prevents the transport of wafers W to the processing modules at the forefront of each section from being delayed. Consequently, the coating and developing apparatus 1 can achieve a high throughput.

[0087] Furthermore, in the IRAMC layer, when determining which zone to move wafer W to, as described above, the moving status of wafer W in the IRAMC layer is considered not only, but also the moving status of TRS7 in the PRAI layer, which is not accessed by the IRAMC moving mechanism. In this way, in addition to considering the moving status of wafer W in the layer where the moving destination is selected, the moving status of wafer W in other downstream layers is also considered to determine which zone to move wafer W to. Therefore, the aforementioned delayed moving of wafer W to the processing module can be more reliably prevented, improving the device throughput.

[0088] Furthermore, when replacement transport cannot be performed in the PIR within the IRAMC layer, transport within a selected area is performed as described above. In other words, replacement transport is prioritized. Since wafer W is continuously moved in and out of a module through replacement transport, the more replacement transport is performed, the more the movement of the IRAMC transport mechanism between modules is suppressed, thereby reducing the number of IRAMC transport mechanism operation steps. Therefore, by prioritizing replacement transport as described above, a higher throughput can be achieved more reliably.

[0089] Furthermore, a waiting time is set to determine whether a replacement transfer should be performed in the PRAI and IRAMC layers. This waiting time is based on the block CT in each layer preceding the layer containing the processing module that is the object of the replacement transfer. After the waiting time has elapsed, no replacement transfer is performed, and the processed wafer W is removed from the processing module. Therefore, it prevents the transfer mechanism from waiting futilely for a replacement in the event of transfer delays to the PRAI and IRAMC layers. As a result, a higher throughput can be obtained more reliably.

[0090] Furthermore, regarding block CT, as already described, it is calculated based on the MUTs (Methods Understand) of the processing modules in each layer and the number of modules that can be used. Therefore, even if the number of usable modules changes due to factors such as failures or maintenance, an appropriate latency is set, thus preventing a decrease in the frequency of replacement transfers in the PRAI and IRAMC layers, thereby enabling more reliable high throughput. Moreover, the latency is not limited to the maximum value of the block CT in each layer preceding the layer to which replacement is performed; for example, an arbitrary correction value can be added.

[0091] In addition, such as through Figure 15 , Figure 18As described above, in the example above, the decision on which of the multiple separate sections to transport wafers is made based on the number of empty slots (the number of substrates that can be transported) in the relay module that serves as the source for taking out wafers W by the transport mechanism, but is not limited to being based on the number of empty slots. For example, this decision can also be made based on the ratio of the slots into which wafers W have been transported to the total number of slots. In other words, the above decision can be made based on the transport status of wafers W in the relay module that serves as the source for taking out wafers W by the transport mechanism.

[0092] Furthermore, when determining the number of wafers W transported by the transport mechanism based on the transport status of the wafers W in the section from the relay module being transported downstream by the transport mechanism to the relay module in front of the nearest processing module, it is not limited to setting the transport status of wafers W as the number of wafers W. For example, it could also be set as the ratio of the slots of the relay modules present in that section into which wafers W are transported to the total number of slots. However, sometimes the number of slots between relay modules is different. For example, as mentioned above, the number of slots in the SBU and TRS is different. Therefore, in order to control the transport status of each section and transport more reliably to prevent a decrease in throughput, it is preferable to set the transport status as the number of wafers W.

[0093] The modules mounted in the apparatus are not limited to the examples described above. Therefore, the substrate processing apparatus of this disclosure is not limited to the coating and developing apparatus 1. For example, it may be configured as an apparatus structure that includes a module for coating a solution for forming an insulating film, a module for supplying an adhesive for bonding wafers W together, etc.

[0094] Furthermore, it is assumed that the transport decision based on the transport status of wafer W, as described above, is not performed in the MPRA layer and IRAMC layer. Instead, the waiting time based on block CT and the replacement transport during that waiting time are calculated in each layer of the IRAMC layer and PRAI layer. Even in this case, the effects described above, which are achieved by appropriately setting the waiting time, can still be obtained, thereby improving the throughput of the device.

[0095] Furthermore, it should be understood that all points in the disclosed embodiments are illustrative rather than restrictive. The above embodiments can be omitted, substituted, or modified in various ways without departing from the appended claims and their spirit, and the above embodiments can also be combined with each other.

[0096] Explanation of reference numerals in the attached figures

[0097] 1: Coating and developing apparatus; 10: Control unit; IRAMB: Transfer mechanism; IRAMC: Transfer mechanism; SBU: Buffer module; TRS10: Transfer module; PIR: Post-exposure cleaning module; W: Wafer.

Claims

1. A substrate processing apparatus comprising: The module group includes multiple processing modules that process the substrate respectively, and multiple relay modules that respectively carry the substrate to transport the substrate between the multiple processing modules. Multiple conveying mechanisms are provided. These multiple conveying mechanisms use a common conveying mechanism to move the substrate into and out of the processing module, and use different conveying mechanisms to move the substrate into and out of the relay module. The multiple conveying mechanisms each carry out conveying in an assigned section in the conveying path of the substrate composed of the module group, so as to convey the substrate sequentially in the conveying path. A shared conveying mechanism, constituting one of the plurality of conveying mechanisms, is used for conveying the substrate to a first section and a second section that are separate from each other in the conveying path of the substrate, and conveys the substrate to a first relay module included in the first section and a second relay module included in the second section, respectively; and The decision unit determines which relay module (first or second) the common conveying mechanism should deliver the substrate to, based on the conveying status of the substrate in each interval from the first relay module and the second relay module downstream of the conveying path up to the nearest relay module in front of the processing module. in, The transport status of the substrates in each interval up to the nearest relay module of the processing module is the number of substrates in each interval, and the common transport mechanism operates to transport the substrates to the relay module in the interval with fewer substrates.

2. The substrate processing apparatus according to claim 1, characterized in that, The decision-making unit makes the decision based on the transport status of the substrate in each relay module in the relay module upstream of the first relay module in the first interval and the relay module upstream of the second relay module in the second interval.

3. The substrate processing apparatus according to claim 2, characterized in that, The substrate conveying status in each relay module of the upstream relay module of the first relay module and the upstream relay module of the second relay module is the number of substrates that can be conveyed to each relay module.

4. The substrate processing apparatus according to claim 2, characterized in that, The decision-making unit makes the decision based on the interval through which the common conveying mechanism has just moved the substrate.

5. The substrate processing apparatus according to claim 1, characterized in that, The interval from the first relay module downstream of the transport path to the nearest relay module in front of the processing module, or the interval from the second relay module downstream of the transport path to the nearest relay module in front of the processing module, includes relay modules that do not transport the substrate via the common transport mechanism.

6. The substrate processing apparatus according to claim 1, characterized in that, The first interval includes a processing module located upstream of the first relay module and a third relay module located upstream of the processing module. The shared conveying mechanism includes multiple holding parts, each holding a substrate for replacing a substrate processed in the first processing module with a substrate moved out from the third relay module. The decision-making unit makes the decision when it is able to remove the processed substrate from the processing module and when the substrate is not being transferred to the third relay module.

7. The substrate processing apparatus according to claim 6, characterized in that, The decision-making unit sets a timeframe from when the processed substrate can be removed from the processing module until the transfer based on the decision is performed.

8. The substrate processing apparatus according to claim 7, characterized in that, The decision-making unit calculates the estimated time interval for transporting substrates to subsequent intervals in the transport path, for each interval divided by each transport mechanism responsible for transporting substrates that is earlier than the first interval. The time settings are based on the expected time intervals for each interval.

9. The substrate processing apparatus according to claim 8, characterized in that, The estimated time interval is calculated based on the number of processing modules included in an interval and the required residence time of the substrate in that processing module.

10. A substrate processing method, comprising the following steps: The substrate is processed separately using multiple processing modules; The substrate is placed in multiple relay modules respectively to transfer the substrate between the multiple processing modules; The substrate is moved into and out of the processing module via a common conveying mechanism. The substrate of the relay module is moved in and out using different conveying mechanisms. In the transport path of the substrate, which is composed of a module group including the plurality of processing modules and the plurality of relay modules, the substrate is transported sequentially in the transport path by transporting the substrate in intervals allocated to the plurality of transport mechanisms. The transfer of materials to the first relay module and the second relay module is performed through a shared transfer mechanism that constitutes one of the plurality of transfer mechanisms and is used to transfer materials to the first relay module and the second relay module, which are separated from each other in the transfer path of the substrate. The shared mechanism includes a first section of a first relay module constituting the plurality of relay modules and a second section of a second relay module constituting the plurality of relay modules. Based on the transport status of the substrate in each interval from the first relay module and the second relay module downstream of the transport path, up to the nearest relay module in front of the processing module, the common transport mechanism determines which of the first and second relay modules the substrate will be transported to. in, The transport status of the substrates in each interval up to the nearest relay module of the processing module is the number of substrates in each interval, and the common transport mechanism operates to transport the substrates to the relay module in the interval with fewer substrates.

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