Electronic devices, semiconductor wafers, chip packaging structures and their fabrication methods

Abstract

An electronic device, a semiconductor wafer, a chip packaging structure, and a method for manufacturing the same are disclosed. The semiconductor wafer (100) includes a wafer body (110), a passivation layer (120), and a buffer layer (130). The wafer body (110) includes at least one top metal layer (111). The passivation layer (120) covers at least the outer surface of the top metal layer (111), and the buffer layer (130) covers at least the side of the passivation layer (120) facing away from the top surface of the top metal layer (111). This allows the portion of the packaging layer above the top metal layer (111) to be directly deposited on the buffer layer (130) during the packaging process. This alleviates the packaging stress exerted by the packaging layer on the passivation layer (120) on top of the top metal layer (111), thereby ensuring that the passivation layer (120) on top of the top metal layer (111) does not crack during the packaging process. This ensures the waterproof performance of the chip packaging structure and, consequently, the reliability of the chip packaging structure in HAST testing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit packaging technology, and in particular to an electronic device, a semiconductor wafer, a chip packaging structure, and a method for manufacturing the same. Background Technology

[0002] Currently, semiconductor devices, due to their high integration, can perform functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting solar energy into electrical energy, and creating visual projections for television displays. They are widely used in entertainment, communications, power conversion, military applications, aerospace, bicycles, industrial controllers, and office equipment. Semiconductor devices are formed by dividing a semiconductor wafer containing integrated circuits into individual integrated circuit chips, and then packaging these individual integrated circuit chips using various packaging technologies.

[0003] In related technologies, to protect the outer surface of the active region of a semiconductor wafer used to fabricate semiconductor devices, a passivation layer is applied to the surface of the top metal layer of the active region of the semiconductor wafer to isolate moisture and provide insulation. Simultaneously, during the packaging process of the semiconductor die formed after dicing the semiconductor wafer, a sealing layer or similar encapsulation layer is applied to the surface of the passivation layer facing away from the top metal layer to provide physical support for the semiconductor chip packaging structure.

[0004] However, when the encapsulation layer is deposited on the top passivation layer, the top passivation layer is prone to cracking due to encapsulation stress, allowing external moisture to enter the interior of the chip package structure, which can cause the semiconductor chip package structure to fail during the highly accelerated temperature and humidity stress test (HAST). Summary of the Invention

[0005] This application provides an electronic device, a semiconductor wafer, a chip packaging structure, and a method for manufacturing the same. It can prevent the passivation layer from cracking due to packaging stress when a sealing agent or other packaging layer is applied to the surface of the top passivation layer away from the top metal layer during the packaging process. This ensures that external moisture will not enter the semiconductor packaging structure and guarantees the reliability of the chip packaging structure in HAST testing.

[0006] In a first aspect, embodiments of this application provide a semiconductor wafer, including: a top metal layer, a passivation layer, and a buffer layer; the passivation layer covers at least the outer surface of the top metal layer, and the buffer layer covers at least the side of the passivation layer opposite to the top surface of the top metal layer.

[0007] This embodiment of the application achieves insulation between the top metal layer and the external environment by covering the outer surface of the top metal layer with a passivation layer, preventing external moisture from entering the wafer body from the outer surface of the top metal layer. Simultaneously, a buffer layer is provided on the side of the passivation layer facing away from the top surface of the top metal layer. During the packaging process, the portion of the packaging layer above the top metal layer is directly deposited on the buffer layer, alleviating the packaging stress exerted by the packaging layer on the passivation layer above the top metal layer. This ensures that the passivation layer on top of the top metal layer will not crack during packaging, thus guaranteeing the waterproof performance of the chip packaging structure and ensuring its reliability in HAST testing. Furthermore, the buffer layer also acts as a barrier against moisture, further improving the waterproof performance of the semiconductor wafer and the packaging structure.

[0008] In one possible implementation of the first aspect, the buffer layer extends to the side of the passivation layer away from the side of the top metal layer.

[0009] By also providing a buffer layer on the side of the passivation layer away from the top metal layer, the packaging layer will not be directly deposited on the side of the passivation layer away from the top metal layer during the packaging process of the semiconductor wafer. This effectively protects both the top and side passivation layers of the top metal layer, further ensuring the waterproofness of the chip packaging structure formed by the semiconductor wafer packaging and its effectiveness in HAST testing.

[0010] In one possible implementation of the first aspect, the buffer layer located on the side of the top metal layer is flush with the buffer layer located on the top surface of the top metal layer. This ensures that the buffer layer protects the passivation layer during the packaging process of the semiconductor wafer, while simplifying the fabrication process of depositing the buffer layer on the passivation layer, thereby improving the fabrication efficiency of the semiconductor wafer.

[0011] In one possible implementation of the first aspect, the buffer layer located on the top surface of the top metal layer is higher than the buffer layer located on the side surface of the top metal layer.

[0012] In practical applications, during the packaging process of semiconductor wafers, the packaging layer is deposited from directly above the passivation layer towards the wafer body. Therefore, it is very easy to damage the passivation layer on top of the top metal layer. Therefore, by setting the buffer layer located on the top surface of the top metal layer to be higher than the side surface of the top metal layer, the buffer layer on top of the top metal layer can effectively alleviate the downward packaging stress of the packaging layer during the deposition process. This further improves the protection effect of the buffer layer on the top surface of the top metal layer, ensuring that the passivation layer at this location will not crack. At the same time, it also saves the amount of the buffer layer used, thus saving the manufacturing cost of semiconductor wafers.

[0013] In one possible implementation of the first aspect, the semiconductor wafer further includes a bottom metal layer and a dielectric layer sequentially stacked on a substrate, wherein the bottom metal layer is located between the dielectric layer and the substrate.

[0014] A top metal layer is disposed on a portion of the surface of the dielectric layer that is away from the bottom metal layer, and a passivation layer extends from the surface of the top metal layer to the surface of the dielectric layer.

[0015] A buffer layer is also provided on the surface of the passivation layer away from the dielectric layer.

[0016] This embodiment of the application provides passivation layers on both the surface of the top metal layer and the surface of the dielectric layer, thus protecting the active area surface of the semiconductor wafer and providing effective electrical insulation and moisture isolation from the external environment. Simultaneously, a buffer layer is provided on the surface of the passivation layer facing away from the dielectric layer. This allows the encapsulation layer to be deposited directly on the buffer layer during the packaging process without disrupting the structure of the passivation layer on the dielectric layer, thereby ensuring the structural stability of the passivation layer across the entire surface of the active area of ​​the semiconductor wafer. Furthermore, providing a buffer layer on the passivation layer across the entire surface of the active area of ​​the semiconductor wafer further simplifies the buffer layer fabrication process, improves the semiconductor wafer manufacturing efficiency, and also enhances the waterproof performance of the semiconductor wafer.

[0017] In one possible implementation of the first aspect, the buffer layer opposite to the surface of the dielectric layer and the buffer layer opposite to the top surface of the passivation layer are flush, so that the buffer layer protects the structure of the passivation layer on the dielectric layer and the passivation layer on the top metal layer. Furthermore, by setting the height of the buffer layer on the surface of the active region of the semiconductor wafer to be uniform, the flatness of the side of the buffer layer opposite to the passivation layer is ensured. This allows for the uniform and orderly deposition of encapsulation layers such as sealants on the flat surface of the buffer layer during the packaging process, while also improving the uniformity of the deposition density of the encapsulation layers on the buffer layer, thereby ensuring the structural stability and sealing performance of the chip packaging structure.

[0018] In one possible implementation of the first aspect, the buffer layer on the top of the passivation layer away from the top of the top metal layer is higher than the buffer layer on the surface of the passivation layer away from the dielectric layer. Because the passivation layer on top of the top metal layer is highly susceptible to damage from encapsulation stress, by setting the buffer layer on the top of the passivation layer away from the top of the top metal layer to be higher than the buffer layer on the surface of the passivation layer away from the dielectric layer, the protection of the passivation layer on top of the top metal layer is further enhanced, preventing this portion of the passivation layer from cracking due to encapsulation stress during the encapsulation process.

[0019] In one possible implementation of the first aspect, the top metal layer comprises multiple top metals, which are spaced apart along the surface of the dielectric layer away from the bottom metal layer. During the packaging process, the multiple top metals are electrically connected to corresponding pins on the substrate, achieving high integration of the packaged structure formed by the semiconductor wafer. Simultaneously, a buffer layer disposed on each top metal provides protection for the passivation layer between each top metal and the buffer layer during the packaging process, further ensuring the water resistance and HAST effectiveness of the highly integrated chip package structure.

[0020] In one possible implementation of the first aspect, the buffer layer is made of any one of the following materials: poly(p-phenylenebenzobisoxazole) fiber, silicon material, or polyimide.

[0021] By setting the buffer layer to be made of any one of the following materials: poly(p-phenylene benzobisoxazole) fiber, silicon material, and polyimide, the encapsulation stress acting on the passivation layer during the deposition process of the encapsulation layer is effectively absorbed, thereby relieving the encapsulation stress and ensuring that the passivation layer will not crack during the encapsulation process.

[0022] In one possible implementation of the first aspect, the thickness of the buffer layer located on the top surface of the passivation layer away from the top metal layer is 8 μm to 5 μm.

[0023] By setting the thickness of the buffer layer located on the top surface of the passivation layer away from the top metal layer within the above range, the packaging stress generated during the packaging process of the semiconductor wafer is relieved, and the process of setting contact pads on the top metal layer inside the buffer layer is prevented from being too thick. This not only improves the packaging efficiency of the semiconductor wafer, but also ensures the reliability of the electrical connection between the top metal layer and the substrate.

[0024] Secondly, embodiments of this application provide a chip packaging structure, including a substrate, a sealant, and a semiconductor wafer as described above;

[0025] The substrate is placed on one side of the substrate in the semiconductor wafer. The top metal layer of the semiconductor wafer is electrically connected to the substrate. A sealant is wrapped around the outer surface of the semiconductor wafer and the substrate.

[0026] The chip packaging structure of this application embodiment achieves the upright mounting process of the semiconductor wafer by placing the substrate on one side of the semiconductor wafer's substrate. Simultaneously, after electrically connecting the top metal layer to the substrate, a sealant is wrapped around the outer surfaces of the semiconductor wafer and the substrate to provide structural protection, making the mechanical structure of the semiconductor packaging structure more stable and providing electrical insulation. Furthermore, when the sealant is deposited on the outer surface of the semiconductor wafer, the buffer layer of the semiconductor wafer alleviates the packaging stress generated during sealant deposition, ensuring that the packaging stress does not cause the passivation layer inside the buffer layer to crack. This ensures the waterproofness of the chip packaging structure and guarantees that the chip packaging structure will not fail during HAST testing.

[0027] In one possible implementation of the second aspect, a first contact pad is provided on the buffer layer, and the first contact pad is electrically connected to the top metal layer through a passivation layer and a via of the buffer layer.

[0028] A second contact pad is formed on the substrate. The first contact pad and the second contact pad are connected by a metal lead. The metal lead is located inside the sealant to protect the metal lead.

[0029] In one possible implementation of the second aspect, the metal leads are located outside the buffer layer, and the second contact pads are located outside the projection area of ​​the semiconductor wafer on the substrate.

[0030] By leading the metal leads out to the outside of the buffer layer and then to the substrate from the outside of the buffer layer, not only is stable signal transmission between the top metal layer and the substrate within the chip package structure guaranteed, but the assembly process of the metal leads within the chip package structure is also simplified, thereby improving the manufacturing efficiency of the chip package structure.

[0031] In one possible implementation of the second aspect, the chip packaging structure also includes an adhesive;

[0032] The substrate and the semiconductor wafer body are connected by an adhesive, which not only improves the stability of the connection between the substrate and the semiconductor wafer, but also simplifies the connection efficiency between the two.

[0033] Thirdly, embodiments of this application also provide a chip packaging structure, including a substrate, a bottom filler, and a semiconductor wafer as described above;

[0034] The substrate is disposed on the side of the buffer layer of the semiconductor wafer away from the top metal layer. The top metal layer of the semiconductor wafer is electrically connected to the substrate, and the bottom filler fills the gap between the semiconductor wafer and the substrate.

[0035] The chip packaging structure of this application embodiment achieves the flip-chip process by placing the substrate on the side of the buffer layer of the semiconductor wafer away from the top metal layer. Simultaneously, after electrically connecting the top metal layer of the semiconductor wafer to the substrate, a filler is filled into the gap between the semiconductor wafer and the substrate to provide structural support for the substrate and semiconductor wafer. This reduces the stress between the semiconductor wafer and the substrate caused by the mismatch in thermal expansion coefficients, thereby improving the reliability of the electrical connection between the substrate and the top metal layer. Furthermore, during the filling process, the buffer layer on the semiconductor wafer effectively absorbs the packaging stress exerted by the filler on the passivation layer inside the buffer layer, alleviating the packaging stress and preventing damage to the passivation layer on one side of the buffer layer during filling. This ensures the waterproofness of the chip packaging structure and guarantees that the chip packaging structure will not fail during HAST testing.

[0036] In one possible implementation of the third aspect, the chip package structure also includes electrical connectors;

[0037] A first contact pad is provided on the buffer layer, and the first contact pad is electrically connected to the top metal layer through a passivation layer and a via in the buffer layer; a second contact pad is formed on the substrate, and an electrical connector is provided between the first contact pad and the second contact pad, with both ends of the electrical connector being electrically connected to the first contact pad and the second contact pad, respectively.

[0038] By incorporating electrical connectors, not only is the mechanical connection between the substrate and the semiconductor wafer more stable, but the stability of signal conduction between the substrate and the top metal layer of the semiconductor wafer is also ensured.

[0039] In one possible implementation of the third aspect, the electrical connector is a bump or a copper pillar.

[0040] Fourthly, embodiments of this application provide an electronic device including the chip packaging structure described above.

[0041] By setting the above-mentioned chip packaging structure in electronic devices, a buffer layer is set between the encapsulation layer such as the sealant or underfiller of the chip packaging structure and the passivation layer of the semiconductor wafer. This buffer layer helps to alleviate the encapsulation stress generated during the deposition of the encapsulation layer, thereby ensuring that the encapsulation stress will not cause the passivation layer in the chip packaging structure to crack, thus ensuring the waterproofness of the chip packaging structure. In this way, not only is the working performance of the electronic device guaranteed, but the electronic device will also be guaranteed not to fail in the HAST test.

[0042] Fifthly, embodiments of this application provide a method for fabricating a chip packaging structure, the method comprising:

[0043] Provide the chip body;

[0044] A passivation layer is formed on the outer surface of the top metal layer of the wafer body;

[0045] A buffer layer is deposited on at least one side of the passivation layer away from the top surface of the top metal layer to form a semiconductor wafer;

[0046] The semiconductor wafer body is mounted on the substrate on the side away from the buffer layer, and the top metal layer of the wafer body is electrically connected to the substrate.

[0047] A sealant is wrapped around the outer surfaces of both the semiconductor wafer and the substrate to form a chip packaging structure.

[0048] The chip packaging structure of this application embodiment achieves a proper mounting process for the semiconductor wafer by placing the substrate on the side of the semiconductor wafer body away from the buffer layer. Simultaneously, after electrically connecting the top metal layer to the substrate, a sealant is wrapped around the outer surfaces of the semiconductor wafer and the substrate to provide structural protection, making the mechanical structure of the semiconductor packaging structure more stable and providing electrical insulation. Furthermore, when the sealant is deposited on the outer surface of the semiconductor wafer, the buffer layer of the semiconductor wafer alleviates the packaging stress generated during sealant deposition, ensuring that the packaging stress does not cause the passivation layer inside the buffer layer to crack. This ensures the waterproofness of the chip packaging structure and guarantees that the chip packaging structure will not fail during HAST testing.

[0049] In one possible implementation of the fifth aspect, a wafer body is provided, comprising:

[0050] A bottom metal layer is formed on the substrate;

[0051] A dielectric layer is formed on the bottom metal layer;

[0052] A top metal layer is formed on a portion of the dielectric layer.

[0053] In one possible implementation of the fifth aspect, the top metal layer of the wafer body is electrically connected to the substrate, including:

[0054] The portion of the buffer layer and passivation layer located on top of the top metal layer is etched away to expose the top metal layer;

[0055] A first contact pad is formed on the top metal layer, and the contact pad extends to the outside of the buffer layer;

[0056] A second contact pad is formed on the substrate, and the first contact pad and the second contact pad are electrically connected by a metal lead; wherein the second contact pad is located outside the projection area of ​​the wafer body on the substrate, and the metal lead is located outside the buffer layer.

[0057] By leading the metal leads out to the outside of the buffer layer and then to the substrate from the outside of the buffer layer, not only is stable signal transmission between the top metal layer and the substrate within the chip package structure guaranteed, but the assembly process of the metal leads within the chip package structure is also simplified, thereby improving the manufacturing efficiency of the chip package structure.

[0058] In one possible implementation of the fifth aspect, the metal lead is encased inside a sealant to protect the metal lead.

[0059] In one possible implementation of the fifth aspect, the wafer body is mounted on a substrate on the side facing away from the buffer layer, including:

[0060] An adhesive is applied to the surface of the substrate or the side of the wafer body away from the buffer layer;

[0061] The side of the wafer body away from the buffer layer is adhered to the substrate.

[0062] The substrate and the wafer body are connected by an adhesive, which not only improves the stability of the connection between the substrate and the semiconductor wafer, but also simplifies the connection efficiency between the two.

[0063] Sixthly, embodiments of this application provide a method for fabricating a chip packaging structure, the method comprising:

[0064] Provide the chip body;

[0065] A passivation layer is formed on the outer surface of the top metal layer of the wafer body;

[0066] A buffer layer is deposited on at least one side of the passivation layer away from the top surface of the top metal layer to form a semiconductor wafer;

[0067] A substrate is placed on the side of the buffer layer away from the wafer body, and the top metal layer of the wafer body is electrically connected to the substrate.

[0068] Filler is used to fill the gap between the semiconductor wafer and the substrate to form a chip packaging structure.

[0069] The chip packaging structure of this application realizes the flip-chip process by placing the substrate on the side of the buffer layer of the semiconductor wafer away from the wafer body. Simultaneously, after electrically connecting the top metal layer of the semiconductor wafer to the substrate, a filler is filled into the gap between the semiconductor wafer and the substrate to provide structural support for the substrate and semiconductor wafer. This reduces the stress between the semiconductor wafer and the substrate caused by the mismatch of thermal expansion coefficients, thereby improving the reliability of the electrical connection between the substrate and the top metal layer. Furthermore, during the filling process, the buffer layer on the semiconductor wafer effectively absorbs the packaging stress exerted by the filler on the passivation layer inside the buffer layer, alleviating the packaging stress and preventing damage to the passivation layer during filling. This ensures the waterproofness of the chip packaging structure and guarantees that the chip packaging structure will not fail during HAST testing.

[0070] In one possible implementation of the sixth aspect, a wafer body is provided, comprising:

[0071] A bottom metal layer is formed on the substrate;

[0072] A dielectric layer is formed on the bottom metal layer;

[0073] A top metal layer is formed on a portion of the dielectric layer.

[0074] In one possible implementation of the sixth aspect, electrically connecting the top metal layer of the wafer body to the substrate includes:

[0075] An electrical connector is fabricated on the side of the buffer layer away from the passivation layer, and the electrical connector is electrically connected to the top metal layer.

[0076] The substrate is disposed at the end of the electrical connector away from the buffer layer, and the substrate is electrically connected to the end of the electrical connector away from the buffer layer.

[0077] By incorporating electrical connectors, not only is the mechanical connection between the substrate and the semiconductor wafer more stable, but the stability of signal conduction between the substrate and the top metal layer of the semiconductor wafer is also ensured.

[0078] In one possible implementation of the sixth aspect, the electrical connector is electrically connected to the top metal layer, including:

[0079] The portion of the buffer layer and passivation layer located on top of the top metal layer is etched away to expose the top metal layer;

[0080] A first contact pad is formed on the top metal layer, and the first contact pad extends through the outside of the buffer layer;

[0081] The end of the electrical connector near the buffer layer is electrically connected to the first contact pad.

[0082] By setting a first contact pad that exposes the buffer layer on the top metal layer, the end of the electrical connector near the buffer layer is electrically connected to the top metal layer through the first contact pad, which improves the portability and reliability of the electrical connection between the electrical connector and the top metal layer.

[0083] In one possible implementation of the sixth aspect, the substrate is electrically connected to the end of the electrical connector away from the buffer layer, including:

[0084] A second contact pad is fabricated on the substrate, and the end of the electrical connector away from the buffer layer is electrically connected to the second contact pad.

[0085] By fabricating a second contact pad on the substrate, the end of the electrical connector away from the buffer layer is electrically connected to the corresponding pin on the substrate through the second contact pad, thereby improving the portability and reliability of the electrical connection between the electrical connector and the substrate. Attached Figure Description

[0086] Figure 1 This is a schematic diagram of the structure of a traditional semiconductor wafer;

[0087] Figure 2 This is a schematic diagram of a chip packaging structure formed by a traditional semiconductor wafer in a top-mounted manner;

[0088] Figure 3 This is a schematic diagram of a chip packaging structure formed by flip-chip bonding of traditional semiconductor wafers.

[0089] Figure 4 This is a schematic diagram of the structure of the semiconductor wafer provided in Embodiment 1 of this application;

[0090] Figure 5 This is a schematic diagram of a chip packaging structure formed by packaging a semiconductor wafer in a positive mounting manner according to Embodiment 1 of this application;

[0091] Figure 6 This is a schematic diagram of a chip packaging structure formed by flip-chip packaging of a semiconductor wafer according to Embodiment 1 of this application;

[0092] Figure 7 This is a schematic diagram of the wafer body in the method for manufacturing the upright chip packaging structure provided in Embodiment 1 of this application;

[0093] Figure 8 This is a schematic diagram of a passivation layer provided on the outer surface of the top metal layer of the wafer body in the fabrication method of the upright chip packaging structure provided in Embodiment 1 of this application.

[0094] Figure 9This is a schematic diagram of the semiconductor wafer structure in the method for manufacturing the upright chip package structure provided in Embodiment 1 of this application;

[0095] Figure 10 This is a schematic diagram of the structure after the semiconductor wafer and substrate are assembled in the method for manufacturing the upright chip packaging structure provided in Embodiment 1 of this application;

[0096] Figure 11 This is a schematic diagram of the method for manufacturing a standard chip package structure provided in Embodiment 1 of this application, in which a sealant is wrapped around the outer surface of the semiconductor wafer and the substrate.

[0097] Figure 12 This is a schematic diagram of the structure after the semiconductor wafer and substrate are assembled in the method for manufacturing the flip-chip package structure provided in Embodiment 1 of this application;

[0098] Figure 13 This is a schematic diagram of the filling of the bottom filler between the semiconductor wafer and the substrate in the method for manufacturing the flip-chip packaging structure provided in Embodiment 1 of this application;

[0099] Figure 14 This is a schematic diagram of the first structure of the semiconductor wafer provided in Embodiment 2 of this application;

[0100] Figure 15 This is a schematic diagram of a second structure of a semiconductor wafer provided in Embodiment 2 of this application;

[0101] Figure 16 This is a schematic diagram of the first structure of the semiconductor wafer provided in Embodiment 3 of this application;

[0102] Figure 17 This is a schematic diagram of the second structure of the semiconductor wafer provided in Embodiment 3 of this application;

[0103] Figure 18 This is a schematic diagram of a chip packaging structure formed in a positive mounting manner using the second structure of the semiconductor wafer provided in Embodiment 3 of this application;

[0104] Figure 19 This is a schematic diagram of a chip packaging structure formed by flip-chip method for the second structure of the semiconductor wafer provided in Embodiment 3 of this application.

[0105] Explanation of reference numerals in the attached figures:

[0106] 100 - Semiconductor wafer; 200 - Chip packaging structure;

[0107] 1. 110 - Wafer body; 3. 120 - Passivation layer; 130 - Buffer layer; 140 - First contact pad; 4. 210 - Substrate; 211 - Second contact pad; 5. 220 - Metal lead; 6. 230 - Sealant; 240 - Adhesive; 7. 250 - Bottom filler; 260 - Electrical connector;

[0108] 2. 111 - Top metal layer; 112 - Substrate; 113 - Bottom metal layer; 114 - Dielectric layer. Detailed Implementation

[0109] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.

[0110] Semiconductor devices are commonly found in modern electronic devices. These semiconductor devices include, but are not limited to, one or more functional components such as light-emitting diodes, small-signal transistors, resistors, capacitors, inductors, and power metal-oxide-semiconductor field-effect transistors.

[0111] Because of their high integration, semiconductor devices can perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electrical energy, and creating visual projections for television displays. Furthermore, these semiconductor devices are widely used in entertainment, communications, power conversion, military applications, aerospace, automotive, industrial controllers, and office equipment.

[0112] Figure 1 This is a schematic diagram of a traditional semiconductor wafer. (Refer to...) Figure 1 As shown, in related technologies, the wafer body 1 of a semiconductor wafer 100 includes active electrical components and passive electrical components, which are electrically connected to form a functional circuit within the semiconductor wafer 100. Active electrical components, such as transistors and diodes, have the ability to control current flow, while passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationship necessary for performing the circuit function. The semiconductor wafer 100 may be a bare die.

[0113] The active electrical components, passive electrical components, and circuit connection components of the wafer body 1 are formed from layers of materials with different electrical properties. In practice, these layers can be formed using various deposition techniques, the specific technique of which depends on the type of material being deposited. (Refer to...) Figure 1 As shown, exemplarily, the wafer body 1 may specifically include a top metal layer 2 located on top of the wafer body 1 to form a circuit connection layer of the wafer body 1. The top metal layer 2 may be made of soft metal materials such as titanium, copper, nickel, and gold.

[0114] To achieve electrical insulation between the semiconductor wafer 100 and the external environment and to prevent external moisture from entering the semiconductor wafer 100, a passivation layer 3 is applied to the outer surface of the active surface of the semiconductor wafer 100, i.e., the top metal layer 2. This passivation layer 3 can be made of one or more hard materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or hafnium dioxide (HfO2). Simultaneously, the passivation layer 3 also protects the active surface of the semiconductor wafer 100.

[0115] Before forming a semiconductor device, the semiconductor wafer 100 needs to be packaged to achieve structural support and environmental isolation, thus forming a chip package structure.

[0116] Figure 2 This is a schematic diagram of a traditional semiconductor wafer package structure formed in a top-mounted manner. Figure 3 This is a schematic diagram of a traditional semiconductor wafer chip package structure formed using a flip-chip method. (Refer to...) Figure 2 and Figure 3 As shown, in practical applications, the semiconductor wafer 100 has two packaging methods: upright and flip-chip.

[0117] Reference Figure 2 As shown, when packaging the semiconductor wafer 100 in a top-mount manner, the wafer body 1 of the semiconductor wafer is first fixed to the substrate 4 on the side opposite to the passivation layer 3. Then, the top metal layer 2 of the semiconductor wafer is electrically connected to the corresponding pins on the substrate 4 via metal leads 5. This enables signal conduction between the semiconductor chip package structure and other system components, such as a PCB board, when the substrate 4 is electrically connected, thus realizing the function of the semiconductor chip package structure. Finally, a sealant 6 is deposited on the outer surfaces of the semiconductor wafer and the substrate 4 to provide physical support and electrical isolation for the semiconductor chip package structure, forming a top-mount chip package structure, i.e., a semiconductor device. It is understood that the sealant 6 also serves to prevent external moisture from entering the chip package structure.

[0118] The sealant 6 can be made of hard materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), and alumina (Al2O3), or soft materials such as polyimide and poly-p-phenylenebenzobisthiazole (PBO).

[0119] Reference Figure 3As shown, when the semiconductor wafer 100 is packaged in a flip-chip manner, the substrate 4 is first placed on the side of the semiconductor wafer close to the top metal layer 2. Then, the top metal layer 2 of the semiconductor wafer is electrically connected to the corresponding pins on the substrate 4. This enables signal conduction between the semiconductor chip package structure and other system components, such as a PCB board, when the substrate 4 is electrically connected, thus realizing the function of the semiconductor chip package structure. Finally, the gap between the semiconductor wafer 100 and the substrate 4 is filled with a bottom filler 7. The bottom filler 7 can be composed of epoxy resin or silicon dioxide.

[0120] The bottom filler 7 fills the gap between the semiconductor wafer 100 and the substrate 4 to provide physical support for the semiconductor wafer 100 and the substrate 4, reduce the stress between the semiconductor wafer 100 and the substrate 4 caused by the mismatch of thermal expansion coefficients, prevent the pads that make electrical connections between the substrate 4 and the semiconductor wafer 100 from breaking, and make the signal conduction between the semiconductor wafer 100 and the substrate 4 more reliable. In addition, the bottom filler 7 also plays a certain role in isolating moisture.

[0121] In practical applications, the chip package structure 200 is electrically connected to the PCB board via the substrate 4 to achieve signal conduction between the chip package structure 200 and the PCB board, thereby realizing the function of the chip package structure 200 as a semiconductor device.

[0122] As described above, in a conventional chip package structure, the passivation layer 3 and the sealant 6 simultaneously prevent moisture from entering the chip package structure from the outside. In a flip-chip chip package structure, the passivation layer 3 and the underfill 7 also simultaneously prevent moisture from entering the chip package structure. That is to say, in the chip package structure, the passivation layer 3 and the encapsulation layer provide two layers of isolation against external moisture, further improving the moisture barrier effect. Specifically, the encapsulation layer provides initial isolation against moisture, while the passivation layer 3 provides secondary isolation. If either the encapsulation layer or the passivation layer 3 cracks, external moisture will enter the chip, causing the semiconductor chip package structure to fail in the HAST test.

[0123] Because the top metal layer 2 of the semiconductor wafer is made of a relatively soft material, while the passivation layer 3 is made of a relatively hard material, when the semiconductor wafer is packaged in a top-mount manner, the sealant 6 is easily deposited on the outer surface of the semiconductor wafer. This can cause the passivation layer 3 on top of the top metal layer 2 to crack due to packaging stress, allowing external moisture to enter the chip packaging structure and leading to failure of the semiconductor chip packaging structure during HAST testing. HAST is a highly accelerated temperature and humidity stress test, a highly accelerated reliability testing method for electronic components based on temperature and humidity.

[0124] When semiconductor wafers are packaged in a flip-chip manner, the bottom filler 7 fills the gap between the semiconductor wafer and the substrate 4. However, the passivation layer 3 on top of the top metal layer 2 may crack due to the packaging stress, allowing external moisture to enter the interior of the chip packaging structure, which may cause the semiconductor chip packaging structure to fail in the HAST test.

[0125] To address the aforementioned issues, this application embodiment covers a buffer layer on the side of the passivation layer of the semiconductor wafer facing away from the top surface of the top metal layer. This allows the portion of the encapsulation layer, such as the sealant, located above the top metal layer during the packaging process to be directly deposited onto the buffer layer. This alleviates the packaging stress exerted by the encapsulation layer on the passivation layer above the top metal layer, ensuring that the passivation layer on top of the top metal layer does not crack during packaging. This guarantees the waterproof performance of the chip packaging structure and, consequently, the reliability of the chip packaging structure in HAST testing. It is understood that the encapsulation layer in this application embodiment specifically refers to the sealant in a conventional chip packaging structure or the underfill in a flip-chip packaging structure.

[0126] The following describes in detail the semiconductor wafer of this application and the chip packaging structure formed by the semiconductor wafer using three specific embodiments.

[0127] Example 1

[0128] Figure 4 This is a schematic diagram of the structure of a semiconductor wafer provided in Embodiment 1 of this application. (Refer to...) Figure 4 As shown, this application embodiment provides a semiconductor wafer 100, including a wafer body 110, a passivation layer 120, and a buffer layer 130. The wafer body 110 includes a top metal layer 111. Figure 4 As shown, the top metal layer 111 may specifically include two top metal layers spaced apart. Of course, in other examples, the number of top metal layers 111 may include, but is not limited to, two.

[0129] For example, the wafer body 110 may include a bottom metal layer 113 and a dielectric layer 114 sequentially stacked on a substrate 112, with the bottom metal layer 113 located between the dielectric layer 114 and the substrate 112, and the top metal layer 111 disposed in a portion of the dielectric layer 114 on the side away from the bottom metal layer 113.

[0130] It is worth noting that in this embodiment, each top metal layer 111 is a cuboid, cube, or cylinder, etc. The top surface of the top metal layer 111 is specifically the surface of each top metal layer facing away from the dielectric layer 114, and the side surface of the top metal layer 111 refers to the circumference of each top metal layer around its own vertical axis. In other examples, the top metal layer may also be a hemispherical or spherical structure, in which case the top surface of the top metal layer refers to the partially arcuate surface facing away from the dielectric layer 114, and the side surface of the top metal layer refers to the circumference of the side surface around its own vertical axis.

[0131] For ease of understanding, Figure 4 In the top metal layer 111, the top surface of each top metal is marked as a, and the side surface of each top metal is marked as b.

[0132] The substrate 112 may include active and passive devices, such as transistors, capacitors, resistors, and combinations thereof. A bottom metal layer 113 and a top metal layer 111 form a circuit interconnect structure via an intermediate dielectric layer 114. This circuit interconnect structure is electrically interconnected with the active and passive devices in the substrate 112 according to the circuit design within the semiconductor wafer 100, thereby forming digital or analog circuits within the wafer body 110 to achieve the specific functions of the semiconductor chip package structure (also known as a chip) formed by the semiconductor wafer 100.

[0133] In some examples, the substrate 112 may be made of semiconductor materials such as silicon (Si), germanium (Ge), diamond (C), silicon carbide (SiC), gallium arsenide (GaAs), and gallium nitride (GaN). The bottom metal layer 113 and the top metal layer 111 may be made of one or more metal materials such as copper (Cu), aluminum (Al), gold (Au), and gold (Ag).

[0134] The dielectric layer 114 in the wafer body 110 can be made of photosensitive materials such as PBO and polyimide, or it can be made of materials such as silicon nitride and silicon oxide. In specific fabrication, the dielectric layer 114 can be formed by spin coating, lamination or CVD.

[0135] To achieve circuit interconnection between the bottom metal layer 113 and the top metal layer 111 on both sides of the dielectric layer 114, after forming the dielectric layer 114 on the surface of the bottom metal layer 113 facing away from the substrate 112, the dielectric layer 114 can be patterned to form an opening that exposes the bottom metal layer 113. A conductive material is then filled into this opening, allowing the top metal layer 111 subsequently deposited on the dielectric layer 114 to achieve circuit interconnection with the bottom metal layer 113 through this conductive material. The conductive material can be the same as the material of either the bottom metal layer 113 or the top metal layer 111; no limitation is imposed here.

[0136] It is understood that in the above example, the wafer body 110 includes two metal layers, namely a bottom metal layer 113 and a top metal layer 111. The two metal layers are interconnected to form a circuit interconnect structure electrically connected to the substrate 112. In other examples, the wafer body 110 may also consist of multiple metal layers and a dielectric layer located between two adjacent metal layers, so as to form a circuit interconnect structure electrically connected to devices within the substrate 112 through multiple metal layers. The embodiments of this application do not limit the number of metal layers.

[0137] Reference Figure 4 As shown, in this embodiment of the application, the outer surface of the top metal layer 111 located on the dielectric layer 114 includes a top surface a and a side surface b of the top metal layer 111. For example, in this embodiment of the application, each top metal 111a of the top metal layer 111 includes a top surface a and a side surface b.

[0138] In this embodiment, the passivation layer 120 covers at least the outer surface of the top metal layer 111, and the buffer layer 130 covers at least the side of the passivation layer 120 away from the top surface of the top metal layer 111.

[0139] For example, such as Figure 4 As shown, in Embodiment 1 of this application, the passivation layer 120 covers the outer surface of the top metal layer 111, and the buffer layer 130 covers the side of the passivation layer 120 away from the top surface of the top metal layer 111. That is, a buffer layer 130 is covered above the top surface a of each top metal layer, and the outer edge of the buffer layer 130 extends to be perpendicular to the outer edge of the top surface a of each top metal layer (e.g., ...). Figure 4 (The direction indicated by the middle arrow z) is flush with the surface. In other examples, the passivation layer 120 may also cover areas of the wafer body 110 other than the top metal layer 111 (see below for details). Figure 16 As shown), the buffer layer 130 can also cover other areas of the passivation layer 120 except for the side facing away from the top surface of the top metal layer 111 (see below for details). Figure 15 and Figure 16 (As shown).

[0140] In this embodiment, a passivation layer 120 is covered on both the top surface a and the side surface b of the top metal layer 111. This ensures that the outer surface of the top metal layer 111 of the semiconductor wafer 100 is insulated from the outside before packaging, and also prevents external moisture from entering the wafer body 110 from the outer surface of the top metal layer 111.

[0141] In addition, during the packaging process, the top surface a of the semiconductor wafer 100, located on the top metal layer 111, is provided with a first contact pad 140 that penetrates the passivation layer 120 (see below for details). Figure 5 The contents shown are connected to the external substrate or other components to form a signal connection. In this way, while ensuring that the top metal layer 111 can communicate with the outside, it effectively ensures the insulation effect between the other areas of the top metal layer 111 except for the first contact pad 140 and the outside. It also prevents moisture passing through the encapsulation layer from entering the wafer body 110 from the other surfaces of the top metal layer 111 except for the first contact pad 140.

[0142] Since the top metal layer 111 of the semiconductor wafer 100 is made of soft metal materials such as titanium, copper, nickel, and gold, and the passivation layer 120 is made of harder materials such as silicon dioxide (SiO2) and silicon nitride (Si3N4), in order to prevent the passivation layer 3 from cracking due to the encapsulation stress of the sealant and other encapsulation layers during the packaging process, this embodiment of the application provides a buffer layer 130 on the side of the passivation layer 120 away from the top surface of the top metal layer 111. Specifically, the buffer layer 130 in this embodiment of the application can be made of any of the following soft materials: poly-p-phenylenebenzobisthiazole (PBO), silicon glass (SOG), or polyimide (PI).

[0143] It is understood that in other examples, the buffer layer 130 may also be made of other soft materials, and there is no limitation on the material of the buffer layer 130 here.

[0144] In this embodiment, a soft buffer layer 130 is provided on the side of the passivation layer 120 away from the top surface of the top metal layer 111. In this way, during the packaging process, the portion of the packaging layer above the top metal layer 111 of the semiconductor wafer 100 is directly deposited on the buffer layer 130. The soft buffer layer 130 can effectively absorb the packaging stress acting on the passivation layer 120 during the deposition process of the packaging layer, thereby alleviating the packaging stress acting on the passivation layer 120. This ensures that the passivation layer 120 on top of the top metal layer 111 will not crack during the packaging process, thus ensuring the waterproof performance of the chip packaging structure and the reliability of the chip packaging structure in the HAST test.

[0145] Figure 5 This is a schematic diagram of a chip packaging structure formed by packaging a semiconductor wafer in a positive manner according to Embodiment 1 of this application.

[0146] Reference Figure 5 As shown, the semiconductor wafer 100 in this embodiment of the application forms a chip package structure in a front-mounted manner. The chip package structure may include a substrate 210, a sealant 230, and the aforementioned semiconductor wafer 100. The substrate 210 is disposed on the back side of the substrate 112 (hereinafter referred to as the back side of the semiconductor wafer 100). For example, the substrate 210 can be bonded to the back side of the semiconductor wafer 100 by an adhesive 240, so as to improve the connection stability between the substrate 210 and the semiconductor wafer 100 while simplifying the connection efficiency between the two. In specific implementation, the adhesive 240 can be any suitable adhesive, epoxy resin, chip adhesion film, etc.

[0147] In the specific packaging process, the adhesive 240 can be applied in advance to the back side of the semiconductor wafer 100 or the surface of the substrate 210. Of course, the adhesive 240 can also be applied to both the back side of the semiconductor wafer 100 and the surface of the substrate 210 at the same time.

[0148] Continue to refer to Figure 5 The top metal layer 111 of the semiconductor wafer 100 is electrically connected to the substrate 210, thereby enabling signal conduction between the semiconductor chip package structure and other system components, such as a PCB board, when the substrate 210 is electrically connected to them, thus realizing the function of the semiconductor chip package structure. A sealant 230, acting as an encapsulation layer, wraps around the outer surfaces of the semiconductor wafer 100 and the substrate 210 to provide physical support and electrical isolation for the semiconductor chip package structure.

[0149] In practical applications, when the sealant 230 is deposited on the outer surface of the semiconductor wafer 100, it is usually deposited from the top of the semiconductor wafer 100 downwards, i.e. towards the substrate 210. Therefore, the downward packaging stress is larger in the packaging stress generated on the outer surface of the semiconductor wafer 100, and the passivation layer 120 on the outer surface of the top metal layer 111 is also easily damaged by the packaging stress of the external deposits.

[0150] Based on this, in the embodiment of this application, when manufacturing the semiconductor wafer 100, a buffer layer 130 is provided on the side of the passivation layer 120 facing away from the top surface of the top metal layer 111. In this way, when the semiconductor wafer 100 is packaged, the sealant 230 located on top of the top metal layer 111 will be directly deposited on the buffer layer 130. The buffer layer 130 can absorb the sealant 230 and transfer it to the passivation layer 120 at the bottom of the buffer layer 130, thereby relieving the packaging stress and ensuring the stability of the mechanical structure of the passivation layer 120 on top of the top metal layer 111. This, in turn, ensures the waterproofness of the chip packaging structure and its reliability in HAST testing.

[0151] Reference Figure 5 As shown, when the top metal layer 111 of the semiconductor wafer 100 is electrically connected to the substrate 210, a first contact pad 140 is formed on the passivation layer 120. This first contact pad 140 passes through vias in the passivation layer 120 and the buffer layer 130 and is electrically connected to the top metal layer 111. Simultaneously, a second contact pad 211 is formed on the substrate 210. The first contact pad 140 and the second contact pad 211 are connected by metal leads 220, thereby achieving electrical connection between the top metal layer 111 and the substrate 210. This also improves the reliability of signal transmission and the ease of assembly between the top metal layer 111 and the substrate 210. It is understood that the fabrication processes of the first contact pad 140 and the second contact pad 211 can be directly referred to in the relevant content of existing technology, and will not be elaborated here.

[0152] In addition, after the sealant 230 is deposited on the outer surface of the semiconductor wafer 100 and the substrate 210, the metal lead 220 used to realize signal transmission is also located inside the sealant 230 to protect the metal lead 220.

[0153] Continue to refer to Figure 5As shown, in a specific implementation, the second contact pad 211 is set outside the projection area of ​​the semiconductor wafer 100 on the substrate 210. Meanwhile, since the top of the first contact pad 140 is exposed outside the buffer layer 130, the metal lead 220 can extend from the outside of the buffer layer 130 and the outer surface of the semiconductor wafer 100 to the substrate 210, thereby making the routing of the metal lead 220 more convenient and faster, and improving the manufacturing efficiency of the chip packaging structure.

[0154] Figure 6 This is a schematic diagram of a chip package structure formed by flip-chip packaging of a semiconductor wafer according to Embodiment 1 of this application. (Refer to...) Figure 6 As shown, the semiconductor wafer 100 in this embodiment of the application forms a chip package structure in a flip-chip manner. The chip package structure may include a substrate 210, a bottom filler 250, and the semiconductor wafer 100.

[0155] The substrate 210 is disposed on the side of the buffer layer 130 of the semiconductor wafer 100 away from the wafer body 110. The top metal layer 111 of the semiconductor wafer 100 is electrically connected to the substrate 210, thereby enabling signal conduction between the semiconductor chip packaging structure and other system components when the substrate 210 is electrically connected to other system components such as PCB board, and realizing the function of the semiconductor chip packaging structure.

[0156] When the top metal layer 111 of the semiconductor wafer 100 is electrically connected to the substrate 210, similar to the upright mounting method, a first contact pad 140 can be formed on the top of the top metal layer 111, i.e., on the side facing the substrate 210. This first contact pad 140 passes through the passivation layer 120 and the buffer layer 130 sequentially, and is exposed to the outside of the buffer layer 130. Correspondingly, a second contact pad 211 corresponding to the first contact pad 140 is provided on the substrate 210. Simultaneously, to ensure the stability of the substrate 210 on the buffer layer 130 side of the semiconductor wafer 100, an electrical connector 260 is provided between the first contact pad 140 and the second contact pad 211. The two ends of the electrical connector 260 are respectively soldered to the first contact pad 140 and the second contact pad 211 to achieve electrical connection between the top metal layer 111 and the substrate 210, thereby ensuring stable signal transmission between the semiconductor wafer 100 and the substrate 210.

[0157] Meanwhile, by soldering the substrate 210 to one end of the electrical connector 260 via the second pad 211, the connection between the substrate 210 and the semiconductor wafer 100 is made more stable.

[0158] To achieve electrical conduction between the semiconductor wafer 100 and the substrate 210, the electrical connector 260 can be a bump. For example, the electrical connector 260 can be a microbump or a controlled collapse chip connection (C4), where the controlled collapse chip connection is also called a controlled collapse bump. The structure and composition of the microbump and the controlled collapse bump in this application can be directly referred to the description in the prior art. In some examples, the electrical connector 260 can also be a copper pillar (CuP) deposited on the first contact pad 140 and extending toward the substrate 210. This copper pillar can be soldered to the second contact pad 211 via solder bumps.

[0159] Continue to refer to Figure 6 The bottom filler 250, which serves as the encapsulation layer, fills the gap between the semiconductor wafer 100 and the substrate 210 to provide physical support for the semiconductor wafer 100 and the substrate 210, reduce the stress between the semiconductor wafer 100 and the substrate 210 caused by the mismatch of thermal expansion coefficients, prevent the breakage of the pads that make electrical connection between the substrate 210 and the electrical connector 260, and make the signal conduction between the semiconductor wafer 100 and the substrate 210 more reliable.

[0160] It should be noted that in the fabrication process of the flip-chip package structure, the wafer body 110 of the semiconductor wafer 100, facing away from the top metal layer 111 (i.e., the back side of the semiconductor wafer 100), is placed on the fabrication substrate. The substrate 210 is moved by a pick-and-place device to the side of the buffer layer 130 of the semiconductor wafer 100 (i.e., the front side of the semiconductor wafer 100), and the top metal layer 110 is electrically connected to the substrate 210. Then, the gap between the front side of the semiconductor wafer 100 and the substrate 210 is filled with underfill 250. Therefore, the underfill 250 deposited between the semiconductor wafer 100 and the substrate 210 has a tendency to sink downwards (away from the substrate 210), which will generate packaging stress on the surface of the semiconductor wafer 100 facing the substrate 210. This can easily cause the passivation layer 120 on the top surface of the top metal layer 110 to crack due to packaging stress.

[0161] Based on this, in this embodiment of the application, a buffer layer 130 is provided on the passivation layer 120 on the top surface of the top metal layer 110. In this way, the bottom filler 250 located on the side of the passivation layer 120 facing the substrate 210 is directly deposited on the buffer layer 130 to relieve the packaging stress acting on the passivation layer 120, thereby ensuring the structural stability of the passivation layer 120 during the semiconductor wafer 100 packaging process, and thus ensuring the waterproofness of the chip packaging structure and its reliability in HAST testing.

[0162] In some scenarios, two or more semiconductor wafers 100 are stacked and packaged together. Signal transmission between adjacent semiconductor wafers 100 can be achieved through metal leads 220 or electrical connectors 260. Therefore, in possible embodiments, the substrate 210 can also be one or more semiconductor wafers 100, so that the chip packaging structure of this application embodiment becomes a stacked die product.

[0163] Understandably, in stacked die products, since the active area surface of each semiconductor wafer 100, i.e. the surface of the top metal layer 111, is covered with a hard passivation layer 120, in order to prevent the passivation layer 120 from being damaged by encapsulation stress when the sealant 230 and other encapsulation layers are deposited on the outer surface of each semiconductor wafer 100, a buffer layer 130 is provided on the side of the passivation layer 120 of each semiconductor wafer 100 away from the top surface of the top metal layer 111, thereby protecting the passivation layer 120 of each semiconductor wafer 100, and thus ensuring the waterproofness of the stacked die product and its effectiveness in the HAST test.

[0164] In addition, the buffer layer 130 disposed on the top surface of the passivation layer 120 away from the top metal layer 111 in this embodiment of the application also serves to block moisture, thereby further improving the waterproof performance of the semiconductor wafer 100 and the chip packaging structure.

[0165] For example, the thickness h of the buffer layer 130 located on the passivation layer 120 away from the top surface of the top metal layer 111 (see...) Figure 5 The thickness h of the buffer layer 130 located on the passivation layer 120 away from the top surface of the top metal layer 111 can be a suitable discrete value such as 8μm, 10μm, 12μm, or 15μm.

[0166] During the packaging process, the semiconductor wafer 100 needs to be patterned to create holes in the buffer layer 130 and passivation layer 120 to expose the top metal layer 111 below the passivation layer 120. Then, a first contact pad 140 is formed on the top metal layer 111, and the top of the first contact pad 140 is exposed to the outside of the buffer layer 120.

[0167] In this embodiment, the thickness of the buffer layer 130 located on the passivation layer 120 away from the top surface of the top metal layer 111 is set in the range of 8μm to 15μm. This ensures that the semiconductor wafer 100 formed by the semiconductor wafer 100 can alleviate the packaging stress generated when the packaging layer is deposited on the buffer layer 130 during the packaging process. It also prevents the buffer layer 130 from being too thick and affecting the process of setting the first contact pad 140 that passes through the passivation layer 120 and the buffer layer 130. This not only improves the packaging efficiency of the semiconductor wafer 100 formed by the semiconductor wafer 100, but also ensures the reliability of the electrical connection between the top metal layer 111 and the substrate 210.

[0168] Figure 7 This is a schematic diagram of the wafer body in the method for manufacturing the upright chip package structure provided in Embodiment 1 of this application. Figure 8 This is a schematic diagram of a passivation layer provided on the outer surface of the top metal layer of the wafer body in the fabrication method of the upright chip packaging structure provided in Embodiment 1 of this application. Figure 9 This is a schematic diagram of the semiconductor wafer structure in the method for manufacturing the upright chip package structure provided in Embodiment 1 of this application. Figure 10 This is a schematic diagram of the structure after the semiconductor wafer and substrate are assembled in the method for manufacturing the upright chip package structure provided in Embodiment 1 of this application. Figure 11 This is a schematic diagram of the method for manufacturing a standard chip package structure according to Embodiment 1 of this application, in which a sealant is wrapped around the outer surface of the semiconductor wafer and the substrate. Figure 12 This is a schematic diagram of the semiconductor wafer and substrate assembled in the fabrication method of the flip-chip package structure provided in Embodiment 1 of this application. (Refer to...) Figures 7 to 12 As shown in the embodiments of this application, a method for manufacturing a chip package structure formed by a positive packaging method is also provided, as detailed below:

[0169] S101, Provides chip body 110.

[0170] Reference Figure 7 As shown, a wafer body 110 is provided. Specifically, the wafer body 110 may be fabricated as follows: a bottom metal layer 113 is deposited on the surface of a substrate 120 using metal deposition processes such as PVD, CVD, or electroplating; a dielectric layer 114 is then formed on the bottom metal layer 113 using existing methods such as spin coating, lamination, or CVD; openings exposing the bottom metal layer 113 are formed on the dielectric layer 114 using patterning or other methods, and conductive material is filled into these openings; finally, a top metal layer 111 is deposited on a portion of the surface of the dielectric layer 114 using existing metal deposition processes, so that the top metal layer 111 forms a circuit interconnect structure with the bottom metal layer 113 through the conductive material. The top metal layer 111 includes multiple top metal layers spaced apart on the dielectric layer 114.

[0171] S102. A passivation layer 120 is formed on the outer surface of the top metal layer 111.

[0172] Reference Figure 8 As shown, after S101 is completed, a passivation layer 120 is formed on the top surface a and side surface b of each top metal layer 111 by means of printing, spin coating, spraying, etc., so as to insulate against the outside and prevent external moisture from entering the wafer body 110.

[0173] S103. A buffer layer 130 is deposited on the side of the passivation layer 120 away from the top surface of the top metal layer 111 to form a semiconductor wafer 100.

[0174] Reference Figure 9 As shown, after S102 is completed, a buffer layer 130 is formed on the side of the passivation layer 120 away from the top surface a of the top metal layer 111 by existing methods such as spin coating and printing, so as to prevent the passivation layer 120 on the top surface of the top metal layer 111 from cracking due to encapsulation stress when the sealant 230 is deposited subsequently.

[0175] S104. The wafer body 110 of the semiconductor wafer 100 is mounted on the substrate 210 on the side away from the buffer layer 130, and the top metal layer 111 of the wafer body 110 is electrically connected to the substrate 210.

[0176] Reference Figure 10 As shown, the wafer body 110 of the semiconductor wafer 100 is mounted on the back side of the substrate 112, away from the buffer layer 130. For example, an adhesive 240 can be coated on the surface of the substrate 210 or the back side of the substrate 112, or on both the surface of the substrate 210 and the surface of the substrate 112. The substrate 210 can be bonded to the back side of the semiconductor wafer 100 by the adhesive 240, thereby improving the connection stability between the substrate 210 and the semiconductor wafer 100 while simplifying the connection efficiency between the two. In some examples, the adhesive 240 can be any suitable adhesive, epoxy resin, chip adhesion film, etc.

[0177] Specifically, the electrical connection process between the top metal layer 111 of the wafer body 110 and the substrate 210 may include:

[0178] First, the portion of the buffer layer 130 and passivation layer 120 located at the top of the top metal layer 111 is removed to expose the top metal layer 111. For example, the buffer layer 130 and passivation layer 120 can be patterned to form a via exposing the top metal layer 111. Alternatively, when the buffer layer 130 and passivation layer 120 are photosensitive materials, the buffer layer 130 and passivation layer 120 can be exposed to light to form a via exposing the top metal layer 130. Another option is to use anisotropic etching to etch away the portion of the buffer layer 130 and passivation layer 120 located at the top of the top metal layer 111 to expose the top metal layer 111. This application does not limit the process for removing the portion of the buffer layer 130 and passivation layer 120 located at the top of the top metal layer 111.

[0179] Next, a first contact pad 140 is formed on the top metal layer 111, and the contact pad 140 extends through an opening to the outside of the buffer layer 130. Correspondingly, a second contact pad 211 is formed on the substrate 210.

[0180] Finally, the first contact pad 140 and the second pad 211 are electrically connected by metal leads 220, thereby completing the electrical interconnection between the semiconductor wafer 100 and the substrate 210.

[0181] The second contact pad 211 is positioned outside the projection area of ​​the semiconductor wafer 100 on the substrate 210. Since the top of the first contact pad 140 is exposed outside the buffer layer 130, the metal lead 220 can extend from the outside of the buffer layer 130 and the outer surface of the semiconductor wafer 100 to the substrate 210, making the routing of the metal lead 220 more convenient and faster, and improving the manufacturing efficiency of the chip packaging structure.

[0182] S106. A sealant 230 is wrapped around the outer surfaces of both the semiconductor wafer 100 and the substrate 210 to form a chip packaging structure.

[0183] Reference Figure 11 As shown, after S104 is completed, a sealant 230 is wrapped around the outer surfaces of both the semiconductor wafer 100 and the substrate 210, and the metal lead 220 used to realize signal transmission is also located inside the sealant 230 to protect the metal lead 220.

[0184] In this embodiment of the application, when fabricating the semiconductor wafer 100, a buffer layer 130 is provided on the side of the passivation layer 120 facing away from the top surface of the top metal layer 111. In this way, when the semiconductor wafer 100 is packaged, the sealant 230 located on top of the top metal layer 111 will be directly deposited on the buffer layer 130. The buffer layer 130 can absorb the sealant 230 and transfer it to the passivation layer 120 at the bottom of the buffer layer 130, thereby relieving the packaging stress, ensuring the stability of the mechanical structure of the passivation layer 120 on top of the top metal layer 111, and thus ensuring the waterproofness of the chip packaging structure and its reliability in HAST testing.

[0185] Figure 12 This is a schematic diagram of the structure after the semiconductor wafer and substrate are assembled in the method for manufacturing the flip-chip package structure provided in Embodiment 1 of this application; Figure 13 This is a schematic diagram of the filling of a bottom filler between the semiconductor wafer and the substrate in the fabrication method of the flip-chip packaging structure provided in Embodiment 1 of this application. (Refer to...) Figure 7 , Figure 8 , Figure 9 , Figure 12 and Figure 13 As shown in the embodiments of this application, a method for manufacturing a chip package structure formed by flip-chip packaging is also provided, as detailed below:

[0186] S101, Provides chip body 110;

[0187] S102. A passivation layer 120 is formed on the outer surface of the top metal layer 111;

[0188] S103. A buffer layer 130 is deposited on the side of the passivation layer 120 away from the top surface of the top metal layer 111 to form a semiconductor wafer 100.

[0189] It is understood that steps S101, S102, and S103 in this method are consistent with the specific steps S101, S102, and S103 of the above-mentioned method for fabricating a chip package structure formed in a positive mounting manner. For details, please refer to... Figures 7 to 9 The described structure and related text will not be elaborated upon here.

[0190] S104. The substrate 210 is placed on the side of the buffer layer 130 of the semiconductor wafer 100 away from the wafer body 110, and the top metal layer 111 of the wafer body 110 is electrically connected to the substrate 210.

[0191] Reference Figure 12As shown, after the semiconductor wafer 100 is formed, the substrate 210 is disposed on the side of the buffer layer 130 of the semiconductor wafer 100 away from the wafer body 110, i.e., the front side of the semiconductor wafer 100, and the top metal layer 111 of the semiconductor wafer 100 is electrically connected to the substrate 210. Thus, when the substrate 210 is electrically connected to other system components, such as PCB boards, the semiconductor chip packaging structure can achieve signal conduction with other system components, thereby realizing the function of the semiconductor chip packaging structure.

[0192] The process of electrically connecting the top metal layer 111 of the semiconductor wafer 100 to the substrate 210 includes:

[0193] Continue to refer to Figure 13 As shown, similar to the fabrication process of the chip package structure formed by the above-described upright mounting, a first contact pad 140 is first formed on the side of the passivation layer 130 facing the substrate 210, and the first contact pad 140 is electrically connected to the top metal layer 111 through vias in the passivation layer 120 and the buffer layer 130. Accordingly, a second contact pad 211 corresponding to the first contact pad 140 is provided on the substrate 210.

[0194] Next, an electrical connector 260 is provided between the first contact pad 140 and the second contact pad 211. The two ends of the electrical connector 260 are respectively soldered to the first contact pad 140 and the second contact pad 211 to realize the electrical connection between the top metal layer 111 and the substrate 210, thereby ensuring the stable transmission of signals between the semiconductor wafer 100 and the substrate 210.

[0195] In addition, the electrical connector 260 makes the substrate 210 more stable on the buffer layer 130 side of the semiconductor wafer 100.

[0196] S105. Fill the gap between the semiconductor wafer 100 and the substrate 210 with bottom filler 250.

[0197] Reference Figure 13 As shown, after S104 is completed, the gap between the semiconductor wafer 100 and the substrate 210 is filled with underfill 250 to provide physical support for the semiconductor wafer 100 and the substrate 210, reduce the stress between the semiconductor wafer 100 and the substrate 210 caused by the mismatch of thermal expansion coefficients, avoid the breakage of the electrical connection pads between the substrate 210 and the top metal layer 111, and improve the welding reliability between the semiconductor wafer 100 and the substrate 210.

[0198] It is understood that, in the embodiments of this application, the upper surface of the gap between the semiconductor wafer 100 and the substrate 210 is a portion of the dielectric layer 114 of the semiconductor wafer 100 and the surface of the buffer layer 130 facing the substrate 210, and the lower surface of the gap is the surface of the substrate 210 facing the semiconductor wafer 100.

[0199] In this embodiment, a buffer layer 130 is provided on the passivation layer 120 on the top surface of the top metal layer 111. In this way, the bottom filler 250 located on the side of the passivation layer 120 facing the substrate 210 is directly deposited on the buffer layer 130 to relieve the packaging stress acting on the passivation layer 120, thereby ensuring the structural stability of the passivation layer 120 during the semiconductor wafer 100 packaging process, and thus ensuring the waterproofness of the chip packaging structure and its reliability in HAST testing.

[0200] Example 2

[0201] Figure 14 This is a schematic diagram of the first structure of the semiconductor wafer provided in Embodiment 2 of this application; Figure 15 This is a schematic diagram of a second structure of a semiconductor wafer provided in Embodiment 2 of this application. (Refer to...) Figure 14 and Figure 15 As shown, based on Embodiment 1, the buffer layer 130 of this application embodiment extends to the side of the passivation layer 120 facing away from the top metal layer 111. That is to say, in the semiconductor wafer 100 of this application embodiment, the outer surface of the passivation layer 120 facing away from the top metal layer 111 is covered with the buffer layer 130. Figure 14 In the diagram, a represents the top surface of the top metal layer 111, and b represents the side surface of the top metal layer 111.

[0202] Understandably, the bottom of the buffer layer 130, located on the side of the passivation layer 120 away from the top metal layer 111, is deposited on the surface of the dielectric layer 114.

[0203] In this embodiment, a buffer layer 130 is also provided on the side of the passivation layer 120 away from the side of the top metal layer 111. This prevents the sealing agent 230 and other encapsulation layers from being directly deposited on the side of the passivation layer 120 away from the side of the top metal layer 111 during the packaging process of the semiconductor wafer 100 formed by cutting the semiconductor wafer 100. This effectively protects both the top and side passivation layers 120 of the top metal layer 111, further ensuring the water resistance and effectiveness of the chip packaging structure made from the semiconductor wafer 100 in the HAST test.

[0204] Reference Figure 14As shown, in one possible implementation, the buffer layer 130 located on the side of the top metal layer 111 is flush with the buffer layer 130 located on top of the top metal layer 111. In other words, the buffer layer 130 located on the side of the top metal layer 111 and the top surface of the buffer layer 130 located on the top surface of the top metal layer 111 are on the same plane.

[0205] This configuration not only ensures the protection of the passivation layer 120 by the buffer layer 130 during the packaging process of the semiconductor wafer 100 formed by cutting the semiconductor wafer 100, but also simplifies the fabrication process of depositing the buffer layer 130 on the passivation layer 120, thereby improving the fabrication efficiency of the semiconductor wafer 100.

[0206] In addition, by setting the side surface of the buffer layer 130 away from the dielectric layer 140 on the same horizontal plane, the flatness of the upper surface of the buffer layer 130 is ensured, so that the sealing agent 230 and other encapsulation layers are uniformly and orderly deposited on the flat surface of the buffer layer 130 during the encapsulation process. At the same time, the uniformity of the deposition density of the encapsulation layer on the buffer layer 130 is improved, thereby ensuring the structural stability and sealing of the chip packaging structure.

[0207] Reference Figure 15 As shown, in another possible implementation, the buffer layer 130 located on the top surface of the top metal layer 111 is higher than the buffer layer 130 located on the side surface of the top metal layer 111.

[0208] It should be understood that during the packaging process, the packaging layer of the semiconductor wafer 100 formed by the semiconductor wafer 100 is deposited from directly above the passivation layer 120 toward the wafer body 110, which can easily damage the passivation layer 120 on top of the top metal layer 111. Therefore, this example sets the buffer layer 130 located on the top surface of the top metal layer 111 to be higher than the side surface of the top metal layer 111. This allows the buffer layer 130 on top of the top metal layer 111 to effectively alleviate the downward packaging stress of the packaging layer during deposition, further improving the protective effect of the buffer layer 130 on the passivation layer 120 on the top surface of the top metal layer 111, ensuring that the passivation layer 120 at this location does not crack.

[0209] Meanwhile, since the top surface of the buffer layer 130 on the side of the top metal layer 111 does not need to extend to the upper surface of the buffer layer 130 on top of the top metal layer 111, the amount of the entire buffer layer 130 is saved, thereby saving the manufacturing cost of the semiconductor wafer 100.

[0210] Example 3

[0211] Figure 16 This is a schematic diagram of the first structure of the semiconductor wafer provided in Embodiment 3 of this application; Figure 17This is a schematic diagram of the second structure of the semiconductor wafer provided in Embodiment 3 of this application.

[0212] Reference Figure 16 and Figure 17 As shown, unlike Embodiment 1 and Embodiment 2, in the semiconductor wafer 100 of this application embodiment, the passivation layer 120 extends from the outer surface of the top metal layer 111 to the surface of the dielectric layer 140 away from the substrate 120. In other words, the passivation layer 120 is provided on the surface of the active region of the semiconductor wafer 100, i.e., the front side, so that the surface of the active region of the semiconductor wafer is protected by the passivation layer, thereby playing the role of effective electrical insulation and isolation of moisture from the outside world.

[0213] In addition, a buffer layer 130 is also provided on the surface of the passivation layer 120 away from the dielectric layer 140, so that during the packaging process of the semiconductor wafer 100 formed by the semiconductor wafer 100, the sealing agent 230 and other packaging layers are directly deposited on the buffer layer 130 without damaging the structure of the passivation layer 120 on the dielectric layer 140, thereby ensuring the structural stability of the passivation layer 120 on the entire surface of the active region of the semiconductor wafer 100.

[0214] In this embodiment, a buffer layer 130 is provided on the entire active area surface of the semiconductor wafer 100. Thus, when depositing the buffer layer 130, the buffer layer 130 can be deposited circle by circle around the axis l from the center of the active area surface of the semiconductor wafer 100 by spin coating or other methods until the buffer layer 130 is deposited on the entire front side of the semiconductor wafer 100, thereby completing the fabrication of the buffer layer 130. This simplifies the fabrication process of the buffer layer 130, improves the fabrication efficiency of the semiconductor wafer 100, and further improves the waterproof performance of the semiconductor wafer 100.

[0215] Reference Figure 16 As shown, in one possible implementation, the buffer layer 130 of the passivation layer 120 away from the surface of the dielectric layer 140 can be flush with the buffer layer 130 of the passivation layer 120 away from the top surface of the top metal layer 111. In other words, in this example, the surface of the buffer layer 130 of the semiconductor wafer 100 away from the passivation layer 120 is on the same horizontal plane.

[0216] This configuration not only ensures that the buffer layer 130 protects the passivation layer 120 on the dielectric layer 140 and the passivation layer 120 on the top metal layer 111, but also ensures the flatness of the surface of the buffer layer 130 facing away from the passivation layer 120. This allows for the uniform and orderly deposition of encapsulation layers such as the sealant 230 on the flat surface of the buffer layer 130 during the encapsulation process. It also improves the uniformity of the deposition density of the encapsulation layers on the buffer layer 130, thereby ensuring the structural stability and sealing of the chip package structure.

[0217] Reference Figure 17 As shown, in another possible implementation, the passivation layer 120 is away from the top of the buffer layer 130 on the top of the top metal layer 111, which is higher than the passivation layer 120 away from the surface of the dielectric layer 140.

[0218] In practice, the passivation layer 120 on top of the top metal layer 111 is easily damaged by the packaging stress. Therefore, in this example, the buffer layer 130 located on the passivation layer 120 away from the top of the top metal layer 111 is set to be higher than the surface of the passivation layer 120 away from the dielectric layer 140, so as to further improve the protection of the passivation layer 120 on top of the top metal layer 111 and prevent this part of the passivation layer 120 from cracking due to the packaging stress of the packaging layer during the packaging process.

[0219] Figure 18 This is a schematic diagram of a chip packaging structure formed in a positive mounting manner using the second structure of the semiconductor wafer provided in Embodiment 3 of this application; Figure 19 This is a schematic diagram of a chip packaging structure formed by flip-chip method for the second structure of the semiconductor wafer provided in Embodiment 3 of this application.

[0220] Reference Figure 18 As shown, when the semiconductor wafer 100 provided in this application embodiment is fabricated in a forward-mounted manner to form a chip package structure, the metal lead 220 extends from the outside of the entire buffer layer 130 to the substrate 210, so as to simplify the wiring process of the metal lead 220 and thereby improve the fabrication efficiency of the chip package structure.

[0221] Reference Figure 19 As shown, when the semiconductor wafer 100 provided in this application embodiment is fabricated into a chip package structure in a flip-chip manner, the gap between the semiconductor wafer 100 and the substrate 210 is formed by the surface of the buffer layer 130 and the surface of the substrate 210, and the bottom filler 250 is filled between the surface of the buffer layer 130 and the surface of the substrate 210.

[0222] This application also provides a circuit board, which includes a chip packaging structure of any of the above embodiments.

[0223] This application also provides an electronic device, which includes any one of the chip packaging structures of any of the above embodiments.

[0224] By setting the above-mentioned chip packaging structure in the electronic device, a buffer layer 130 is set between the encapsulation layer such as the sealant 230 or the underfill 250 and the passivation layer 120 in the chip packaging structure, so as to alleviate the encapsulation stress generated during the deposition of the encapsulation layer, thereby ensuring that the encapsulation stress will not cause the passivation layer 120 in the chip packaging structure to crack, thus ensuring the waterproofness of the chip packaging structure. In this way, not only is the working performance of the electronic device guaranteed, but the electronic device will also be guaranteed not to fail in the HAST test.

[0225] It should be noted that the electronic devices provided in the embodiments of this application may include, but are not limited to, mobile or fixed terminals with chip packaging structures such as mobile phones, tablets, laptops, ultra-mobile personal computers (UMPCs), handheld computers, walkie-talkies, netbooks, POS machines, personal digital assistants (PDAs), wearable devices, and virtual reality devices.

Claims

1. A semiconductor wafer, characterized in that, include: The substrate comprises a top metal layer, a passivation layer, a buffer layer, and a bottom metal layer and a dielectric layer sequentially stacked on the substrate, wherein the bottom metal layer is located between the dielectric layer and the substrate. The top metal layer is disposed on a portion of the dielectric layer facing away from the bottom metal layer. The passivation layer covers the outer surface of the top metal layer and extends from the surface of the top metal layer to the surface of the dielectric layer. The buffer layer covers the side of the passivation layer facing away from the top surface of the top metal layer and covers the surface of the passivation layer facing away from the dielectric layer. The buffer layer on the passivation layer facing away from the top surface of the top metal layer is higher than the buffer layer on the passivation layer facing away from the surface of the dielectric layer. The buffer layer is used to allow the encapsulation layer to be deposited on the buffer layer during the semiconductor wafer packaging process, so as to alleviate the packaging stress exerted by the encapsulation layer on the passivation layer. The thickness of the buffer layer located on the passivation layer away from the top surface of the top metal layer is 8μm~5μm.

2. The semiconductor wafer according to claim 1, characterized in that, The top metal layer includes multiple top metals, and the multiple top metals are spaced apart along the surface of the dielectric layer away from the bottom metal layer.

3. The semiconductor wafer according to any one of claims 1-2, characterized in that, The buffer layer is made of any one of the following materials: poly(p-phenylenebenzobisoxazole) fiber, silicon material, or polyimide.

4. A chip packaging structure, characterized in that, Includes a substrate, a sealant, and a semiconductor wafer as described in any one of claims 1-3; The substrate is disposed on one side of the substrate in the semiconductor wafer, the top metal layer of the semiconductor wafer is electrically connected to the substrate, and the sealant is wrapped around the outer surfaces of the semiconductor wafer and the substrate.

5. The chip packaging structure according to claim 4, characterized in that, The buffer layer is provided with a first contact pad, and the first contact pad is electrically connected to the top metal layer through the passivation layer and the via of the buffer layer. A second contact pad is formed on the substrate, and the first contact pad and the second contact pad are connected by a metal lead, which is located inside the sealant.

6. The chip packaging structure according to claim 5, characterized in that, The metal leads are located outside the buffer layer, and the second contact pad is located outside the projection area of ​​the semiconductor wafer on the substrate.

7. The chip packaging structure according to any one of claims 4-6, characterized in that, The chip packaging structure also includes an adhesive; The substrate and the wafer body of the semiconductor die are connected by the adhesive.

8. A chip packaging structure, characterized in that, Includes a substrate, a bottom filler, and a semiconductor wafer as described in any one of claims 1-3; The substrate is disposed on the side of the buffer layer of the semiconductor wafer away from the top metal layer. The top metal layer of the semiconductor wafer is electrically connected to the substrate. The bottom filler fills the gap between the semiconductor wafer and the substrate.

9. The chip packaging structure according to claim 8, characterized in that, The chip packaging structure also includes electrical connectors; The buffer layer is provided with a first contact pad, and the first contact pad is electrically connected to the top metal layer through the passivation layer and the via of the buffer layer. A second contact pad is formed on the substrate, and the electrical connector is disposed between the first contact pad and the second contact pad, with both ends of the electrical connector being electrically connected to the first contact pad and the second contact pad, respectively.

10. The chip packaging structure according to claim 9, characterized in that, The electrical connector is a protrusion or a copper pillar.

11. An electronic device, characterized in that, Includes the chip packaging structure described in any one of claims 4-10.

12. A method for fabricating a chip packaging structure, characterized in that, The method includes: A bottom metal layer is formed on the substrate; A dielectric layer is formed on the bottom metal layer; A top metal layer is formed on a portion of the dielectric layer to form the wafer body; A passivation layer is formed on the outer surface of the top metal layer, and the passivation layer extends from the surface of the top metal layer to the surface of the dielectric layer; A buffer layer is deposited on at least one side of the passivation layer away from the top surface of the top metal layer and on the surface of the passivation layer away from the dielectric layer to form a semiconductor wafer; wherein the buffer layer on the passivation layer away from the top surface of the top metal layer is higher than the buffer layer on the surface of the passivation layer away from the dielectric layer, and the thickness of the buffer layer on the passivation layer away from the top surface of the top metal layer is 8μm~5μm; The wafer body of the semiconductor wafer is mounted on a substrate on the side away from the buffer layer, and the top metal layer of the wafer body is electrically connected to the substrate. A sealant is wrapped around the outer surfaces of both the semiconductor wafer and the substrate to form a chip packaging structure.

13. The method for fabricating a chip packaging structure according to claim 12, characterized in that, The step of electrically connecting the top metal layer of the wafer body to the substrate includes: Remove the portion of the buffer layer and the passivation layer located on top of the top metal layer to expose the top metal layer; A first contact pad is formed on the top metal layer, and the contact pad extends through to the outside of the buffer layer; A second contact pad is formed on the substrate, and the first contact pad and the second contact pad are electrically connected by a metal lead; wherein the second contact pad is located outside the projection area of ​​the wafer body on the substrate, and the metal lead is located outside the buffer layer.

14. The method for fabricating a chip packaging structure according to claim 13, characterized in that, The metal leads are encased inside the sealant.

15. The method for fabricating a chip packaging structure according to any one of claims 12-14, characterized in that, Mounting the wafer body on the substrate on the side facing away from the buffer layer includes: An adhesive is applied to the surface of the substrate or the side of the wafer body opposite to the buffer layer; The wafer body is adhered to the substrate on the side facing away from the buffer layer.

16. A method for fabricating a chip packaging structure, characterized in that, The method includes: A bottom metal layer is formed on the substrate; A dielectric layer is formed on the bottom metal layer; A top metal layer is formed on a portion of the dielectric layer to form the wafer body; A passivation layer is formed on the outer surface of the top metal layer of the wafer body, and the passivation layer extends from the surface of the top metal layer to the surface of the dielectric layer; A buffer layer is deposited on at least one side of the passivation layer away from the top surface of the top metal layer and on the surface of the passivation layer away from the dielectric layer to form a semiconductor wafer; wherein the buffer layer on the passivation layer away from the top surface of the top metal layer is higher than the buffer layer on the surface of the passivation layer away from the dielectric layer, and the thickness of the buffer layer on the passivation layer away from the top surface of the top metal layer is 8μm~5μm; A substrate is disposed on the side of the buffer layer of the semiconductor wafer away from the wafer body, and the top metal layer of the wafer body is electrically connected to the substrate. Fill the gap between the semiconductor wafer and the substrate with a filler to form a chip packaging structure.

17. The method for fabricating a chip packaging structure according to claim 16, characterized in that, Electrically connecting the top metal layer of the wafer body to the substrate includes: An electrical connector is fabricated on the side of the buffer layer opposite to the passivation layer, and the electrical connector is electrically connected to the top metal layer; The substrate is disposed at the end of the electrical connector away from the buffer layer, and the substrate is electrically connected to the end of the electrical connector away from the buffer layer.

18. The method for fabricating a chip packaging structure according to claim 17, characterized in that, The electrical connector is electrically connected to the top metal layer, including: The portion of the buffer layer and the passivation layer located on top of the top metal layer is etched away to expose the top metal layer; A first contact pad is formed on the top metal layer, and the first contact pad extends through to the outside of the buffer layer; The end of the electrical connector near the buffer layer is electrically connected to the first contact pad.

19. The method for fabricating a chip packaging structure according to claim 17, characterized in that, The substrate is electrically connected to the end of the electrical connector away from the buffer layer, including: A second contact pad is formed on the substrate, and the end of the electrical connector away from the buffer layer is electrically connected to the second contact pad.

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