Test structure for integrated circuits

Abstract

Embodiments of the present application relate to the technical field of integrated circuits, and specifically relate to a test structure of an integrated circuit. Embodiments of the present application aim to solve the problem of lack of test structure of an integrated circuit in the related art. In the test structure of the integrated circuit, the first N-type heavily doped region and the second N-type heavily doped region have a first distance, and the second N-type heavily doped region and the first P-type heavily doped region have a second distance; at least one of the first distance and the second distance is adjusted, and the electrical parameters of the integrated circuit corresponding to the test structure are tested. The corresponding relationship between these electrical parameters and the corresponding first distance and second distance can represent the latching characteristic of the parasitic NPN transistor, and according to the latching characteristic, the first distance and the second distance of the integrated circuit with the test structure can be set, so as to avoid the latching effect of the integrated circuit with the test structure in the working process, and improve the reliability of the chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a test structure for integrated circuits. Background Technology

[0002] Latch-up is a parasitic effect unique to CMOS technology, which can severely lead to circuit failure and even chip burnout. In CMOS integrated circuits, parasitic NPN transistors are extremely unstable. Under the influence of electrostatic discharge or related voltage transients, NPN transistors are prone to latch-up. When latch-up occurs, the NPN transistor is in an amplified state, with the emitter junction forward biased and the collector junction reverse biased. A low-resistance path is formed between the power supply voltage and ground, and the positive feedback loop keeps the circuit in a low-resistance path, generating a large current and causing permanent damage to the chip.

[0003] To ensure chip reliability, latch-up effects in integrated circuits must be avoided. Therefore, during the chip development phase, it is necessary to test various parasitic NPN transistor structures that may exist in the integrated circuit and extract the corresponding rule parameters for integrated circuit design to avoid latch-up effects. Summary of the Invention

[0004] This invention provides a test structure for integrated circuits to address the technical problem of the lack of test structures for integrated circuits in related technologies.

[0005] In a first aspect, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0006] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0007] The first N-type heavily doped region, the second N-type heavily doped region, and the first P-type heavily doped region are all located on a P-type substrate; there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0008] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0009] In one possible implementation, the first N-type heavily doped region, the second N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0010] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0011] Secondly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0012] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0013] Wherein, the first N-type heavily doped region is located in the N-well, the second N-type heavily doped region and the first P-type heavily doped region are both located on the P-type substrate, and the N-well is located on the P-type substrate;

[0014] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0015] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0016] In one possible implementation, the N-well, the second N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0017] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0018] Thirdly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0019] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0020] Wherein, the first N-type heavily doped region is located in a deep N-well, the second N-type heavily doped region and the first P-type heavily doped region are both located on a P-type substrate, the deep N-well is located in an N-well, and the N-well is located on the P-type substrate;

[0021] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0022] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0023] In one possible implementation, the deep N-well, the second N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0024] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0025] Fourthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0026] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0027] Wherein, the second N-type heavily doped region is located in the N-well, the first N-type heavily doped region and the first P-type heavily doped region are both located on the P-type substrate, and the N-well is located on the P-type substrate;

[0028] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0029] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0030] In one possible implementation, the N-well, the first N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0031] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0032] Fifthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0033] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0034] Wherein, the second N-type heavily doped region is located in the deep N-well, the first N-type heavily doped region and the first P-type heavily doped region are both located on the P-type substrate, the deep N-well is located in the N-well, and the N-well is located on the P-type substrate;

[0035] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0036] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0037] In one possible implementation, the deep N-well, the first N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0038] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0039] Sixthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0040] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0041] Wherein, the first N-type heavily doped region is located in the first N-well, the second N-type heavily doped region is located in the second N-well, the first P-type heavily doped region is located on the P-type substrate, and the first N-well and the second N-well are located on the P-type substrate;

[0042] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0043] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0044] In one possible implementation, the first N-well, the second N-well, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0045] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0046] In a seventh aspect, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0047] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0048] Wherein, the first N-type heavily doped region is located in the first N-well, the second N-type heavily doped region is located in the deep N-well, the first P-type heavily doped region is located on the P-type substrate, the first N-well is located on the P-type substrate, the deep N-well is located in the second N-well, and the second N-well is located on the P-type substrate;

[0049] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0050] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0051] In one possible implementation, the first N-well, the deep N-well, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0052] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0053] Eighthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0054] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0055] Wherein, the second N-type heavily doped region is located in the first N-well, the first N-type heavily doped region is located in the deep N-well, the first P-type heavily doped region is located on the P-type substrate, the first N-well is located on the P-type substrate, the deep N-well is located in the second N-well, and the second N-well is located on the P-type substrate;

[0056] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0057] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0058] In one possible implementation, the first N-well, the deep N-well, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0059] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0060] Ninthly, embodiments of the present invention provide a test structure for an integrated circuit, comprising:

[0061] A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region;

[0062] Wherein, the first N-type heavily doped region is located in the first deep N-well, the second N-type heavily doped region is located in the second deep N-well, the first P-type heavily doped region is located on the P-type substrate, the first deep N-well is located in the first N-well, the second deep N-well is located in the second N-well, and the first N-well and the second N-well are located on the P-type substrate.

[0063] There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region;

[0064] The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0065] In one possible implementation, the first deep N-well, the second deep N-well, and the first heavily doped P-type region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0066] In one possible implementation, the P-type substrate has a parasitic resistance, a first end of which is connected to the first heavily doped P-type region, and a second end of which is connected to the base of the parasitic NPN transistor.

[0067] The integrated circuit test structure provided by this invention includes a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type and first P-type heavily doped regions. A first distance exists between the first and second N-type heavily doped regions, and a second distance exists between the second N-type and first P-type heavily doped regions. By adjusting at least one of the first and second distances, the electrical parameters of the integrated circuit corresponding to the test structure are tested. The correspondence between these electrical parameters and the corresponding first and second distances characterizes the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, the first and second distances of the integrated circuit with this test structure can be set, thereby avoiding latch-up effects during operation and improving chip reliability. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 A schematic diagram of a wafer structure provided in an embodiment of the present invention;

[0070] Figure 2 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 1 ;

[0071] Figure 3 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 1 ;

[0072] Figure 4 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 2 ;

[0073] Figure 5 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 2 ;

[0074] Figure 6 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 3 ;

[0075] Figure 7 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 3 ;

[0076] Figure 8 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 4 ;

[0077] Figure 9 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 4 ;

[0078] Figure 10 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 5 ;

[0079] Figure 11 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 5 ;

[0080] Figure 12 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 6 ;

[0081] Figure 13 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 6 ;

[0082] Figure 14 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 7 ;

[0083] Figure 15 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 7 ;

[0084] Figure 16 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 8 ;

[0085] Figure 17 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 8 ;

[0086] Figure 18 A top view of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 9 ;

[0087] Figure 19 A cross-section of a test structure for an integrated circuit provided in an embodiment of the present invention. Figure 9 .

[0088] Explanation of reference numerals in the attached figures:

[0089] 10: Wafer; 11: Grain; 12: Die-cutting lane;

[0090] 20, 30, 40, 50, 60, 70, 80, 90, 100: P-type substrate;

[0091] 21, 31, 41, 51, 61, 71, 81, 91, 101: First N-type heavily doped region;

[0092] 22, 32, 42, 52, 62, 72, 82, 92, 102: Second N-type heavily doped region;

[0093] 311, 412, 521, 622: N-well;

[0094] 411, 621, 821, 911: Deep N-well;

[0095] 711, 811, 921, 1012: First N-well;

[0096] 721, 822, 912, 1022: Second N-well;

[0097] 1011: First deep N-well; 1021: Second deep N-well;

[0098] 23, 33, 43, 53, 63, 73, 83, 93, 103: First P-type heavily doped region;

[0099] 24, 34, 44, 54, 64, 74, 84, 94, 104: Parasitic resistance. Detailed Implementation

[0100] To ensure chip reliability, latch-up effects in integrated circuits must be avoided. Therefore, during the chip development phase, it is necessary to test various parasitic NPN transistor structures that may exist in the integrated circuit and extract the corresponding rule parameters for integrated circuit design to avoid latch-up effects.

[0101] In view of this, embodiments of the present invention provide a test structure for an integrated circuit, including a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region. A first distance exists between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance exists between the second N-type heavily doped region and the first P-type heavily doped region. By adjusting at least one of the first distance and the second distance, the electrical parameters of the integrated circuit corresponding to the test structure are tested. The correspondence between these electrical parameters and the corresponding first and second distances characterizes the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, the first and second distances of the integrated circuit with this test structure can be set, thereby avoiding latch-up effects during operation and improving chip reliability.

[0102] The following describes several optional implementations of the present invention with reference to the accompanying drawings. Those skilled in the art should understand that the following implementations are merely illustrative and not exhaustive. Based on these implementations, those skilled in the art may replace, splice, or combine certain features or examples, and these should still be considered as the disclosure of the present invention.

[0103] like Figure 1 As shown, an embodiment of the present invention provides a test structure for an integrated circuit that can be disposed on a wafer 10. The wafer 10 includes a plurality of dies 11 and scribe lines 12 located between the dies 11. Specifically, the test structure for the integrated circuit provided in this embodiment of the present invention can be disposed within the scribe lines 12. The equivalent circuit corresponding to the test structure for the integrated circuit is the same as that of the integrated circuit disposed on the die 11, so that the electrical parameters of the integrated circuit on the die 11 can be tested by using the test structure for testing the integrated circuit, thereby avoiding latch-up effects during operation of the integrated circuit on the die 11.

[0104] It should be noted that the electrical parameters tested can include the trigger voltage for latch-up, the holding voltage for maintaining the latch-up effect, the trigger current, and the holding current. A higher trigger voltage makes latch-up less likely, and a higher holding voltage makes it less likely to maintain the latch-up effect. For example, if the normal operating voltage is 1.1V, a trigger voltage of 1.2V would greatly increase the risk of latch-up, while a trigger voltage of 2V would significantly reduce the risk. Similarly, the holding voltage operates on the same principle. It is important to note that the holding voltage is generally lower than the trigger voltage.

[0105] The integrated circuit test structure includes a first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type and first P-type heavily doped regions. A first distance exists between the first and second N-type heavily doped regions, and a second distance exists between the second N-type and first P-type heavily doped regions. By adjusting at least one of the first and second distances, the electrical parameters of the integrated circuit corresponding to the test structure are tested, namely, the latch-up trigger voltage, the latch-up sustaining voltage, the current during latch-up triggering, and the current during latch-up sustaining. The correspondence between these electrical parameters and the corresponding first and second distances characterizes the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, the first and second distances of the integrated circuit with this test structure can be set, thereby preventing latch-up during operation and improving chip reliability.

[0106] It is worth noting that the test structure of this integrated circuit can be tested using a transmission line pulse generator (TLP): connect the contact of the transmission line pulse generator to the pin of the test structure of the integrated circuit, inject current into the pin, and test the electrical parameters of the latch-up effect of this integrated circuit test structure.

[0107] The following is a brief introduction to nine types of integrated circuit test structures, such as... Figures 2 to 19 As shown in the figure, N+ refers to the N-type heavily doped region, and P+ refers to the P-type heavily doped region.

[0108] Reference Figure 2 and Figure 3 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 21, a first P-type heavily doped region 23, and a second N-type heavily doped region 22 located between the first N-type heavily doped region 21 and the first P-type heavily doped region 23; wherein the first N-type heavily doped region 21, the second N-type heavily doped region 22, and the first P-type heavily doped region 23 are all located on a P-type substrate 20; there is a first distance between the first N-type heavily doped region 21 and the second N-type heavily doped region 22, and a second distance between the second N-type heavily doped region 22 and the first P-type heavily doped region 23; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0109] Furthermore, the first N-type heavily doped region 21, the second N-type heavily doped region 22, and the first P-type heavily doped region 23 constitute a parasitic NPN transistor, and the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0110] Furthermore, the P-type substrate 20 has a parasitic resistor 24, the first end of which is connected to the first heavily doped P-type region 23, and the second end of which is connected to the base of the parasitic NPN transistor.

[0111] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 3 As shown, the first N-type heavily doped region 21 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 22 and the first P-type heavily doped region 23 can be connected to the ground terminal VSS.

[0112] Specifically, the base of the parasitic NPN transistor is a P-type substrate 20, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 24, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current or voltage of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0113] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0114] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0115] Reference Figure 4 and Figure 5This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 31, a first P-type heavily doped region 33, and a second N-type heavily doped region 32 located between the first N-type heavily doped region 31 and the first P-type heavily doped region 33; wherein, the first N-type heavily doped region 31 is located within an N-well 311, and the second N-type heavily doped region 32 and the first P-type heavily doped region 33 are both located on a P-type substrate 30, and the N-well 311 is located on the P-type substrate 30; there is a first distance between the first N-type heavily doped region 31 and the second N-type heavily doped region 32, and a second distance between the second N-type heavily doped region 32 and the first P-type heavily doped region 33; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0116] Furthermore, the N-well 311, the second N-type heavily doped region 32, and the first P-type heavily doped region 33 constitute a parasitic NPN transistor, and the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0117] Furthermore, the P-type substrate 30 has a parasitic resistor 34, the first end of which is connected to the first heavily doped P-type region 33, and the second end of which is connected to the base of the parasitic NPN transistor.

[0118] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 5 As shown, the first N-type heavily doped region 31 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 32 and the first P-type heavily doped region 33 can be connected to the ground terminal VSS.

[0119] Specifically, the base of the parasitic NPN transistor is a P-type substrate 30, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 34, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground terminal VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0120] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0121] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0122] Reference Figure 6 and Figure 7 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 41, a first P-type heavily doped region 43, and a second N-type heavily doped region 42 located between the first N-type heavily doped region 41 and the first P-type heavily doped region 43; wherein, the first N-type heavily doped region 41 is located within a deep N-well 411, the second N-type heavily doped region 42 and the first P-type heavily doped region 43 are both located on a P-type substrate 40, the deep N-well 411 is located within an N-well 412, and the N-well 412 is located on the P-type substrate 40; there is a first distance between the first N-type heavily doped region 41 and the second N-type heavily doped region 42, and a second distance between the second N-type heavily doped region 42 and the first P-type heavily doped region 43; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0123] Furthermore, the deep N-well 411, the second N-type heavily doped region 42, and the first P-type heavily doped region 43 constitute a parasitic NPN transistor, and the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0124] Furthermore, the P-type substrate 40 has a parasitic resistor 44, the first end of which is connected to the first heavily doped P-type region 43, and the second end of which is connected to the base of the parasitic NPN transistor.

[0125] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 7 As shown, the first N-type heavily doped region 41 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 42 and the first P-type heavily doped region 43 can be connected to the ground terminal VSS.

[0126] Specifically, the base of the parasitic NPN transistor is a P-type substrate 40, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 44, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground terminal VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0127] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0128] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0129] Reference Figure 8 and Figure 9 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 51, a first P-type heavily doped region 53, and a second N-type heavily doped region 52 located between the first N-type heavily doped region 51 and the first P-type heavily doped region 53; wherein, the second N-type heavily doped region 52 is located within an N-well 521, the first N-type heavily doped region 51 and the first P-type heavily doped region 53 are both located on a P-type substrate 50, and the N-well 521 is located on the P-type substrate 50; there is a first distance between the first N-type heavily doped region 51 and the second N-type heavily doped region 52, and a second distance between the second N-type heavily doped region 52 and the first P-type heavily doped region 53; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0130] Furthermore, the N-well 521, the first N-type heavily doped region 51, and the first P-type heavily doped region 53 constitute a parasitic NPN transistor, and the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0131] Furthermore, the P-type substrate 50 has a parasitic resistor 54, the first end of which is connected to the first heavily doped P-type region 53, and the second end of which is connected to the base of the parasitic NPN transistor.

[0132] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 9 As shown, the first N-type heavily doped region 51 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 52 and the first P-type heavily doped region 53 can be connected to the ground terminal VSS.

[0133] Specifically, the base of the parasitic NPN transistor is a P-type substrate 50, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 54, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground terminal VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0134] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0135] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0136] Reference Figure 10 and Figure 11 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 61, a first P-type heavily doped region 63, and a second N-type heavily doped region 62 located between the first N-type heavily doped region 61 and the first P-type heavily doped region 63; wherein, the second N-type heavily doped region 62 is located within a deep N-well 621, the first N-type heavily doped region 61 and the first P-type heavily doped region 63 are both located on a P-type substrate 60, the deep N-well 621 is located within an N-well 622, and the N-well 622 is located on the P-type substrate 60; there is a first distance between the first N-type heavily doped region 61 and the second N-type heavily doped region 62, and a second distance between the second N-type heavily doped region 62 and the first P-type heavily doped region 63; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0137] Furthermore, the deep N-well 621, the first N-type heavily doped region 61, and the first P-type heavily doped region 63 constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0138] Furthermore, the P-type substrate 60 has a parasitic resistor 64, the first end of which is connected to the first heavily doped P-type region 63, and the second end of which is connected to the base of the parasitic NPN transistor.

[0139] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 11 As shown, the first N-type heavily doped region 61 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 62 and the first P-type heavily doped region 63 can be connected to the ground terminal VSS.

[0140] Specifically, the base of the parasitic NPN transistor is a P-type substrate 60, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 64, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0141] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0142] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0143] Reference Figure 12 and Figure 13 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 71, a first P-type heavily doped region 73, and a second N-type heavily doped region 72 located between the first N-type heavily doped region 71 and the first P-type heavily doped region 73; wherein, the first N-type heavily doped region 71 is located within a first N-well 711, the second N-type heavily doped region 72 is located within a second N-well 721, the first P-type heavily doped region 73 is located on a P-type substrate 70, and the first N-well 711 and the second N-well 721 are located on a P-type substrate 70; a first distance exists between the first N-type heavily doped region 71 and the second N-type heavily doped region 72, and a second distance exists between the second N-type heavily doped region 72 and the first P-type heavily doped region 73; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0144] Furthermore, the first N-well 711, the second N-well 721, and the first P-type heavily doped region 73 constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0145] Furthermore, the P-type substrate 70 has a parasitic resistor 74, the first end of which is connected to the first heavily doped P-type region 73, and the second end of which is connected to the base of the parasitic NPN transistor.

[0146] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 13 As shown, the first N-type heavily doped region 71 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 72 and the first P-type heavily doped region 73 can be connected to the ground terminal VSS.

[0147] Specifically, the base of the parasitic NPN transistor is a P-type substrate 70, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 74, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0148] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0149] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0150] Reference Figure 14 and Figure 15 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 81, a first P-type heavily doped region 83, and a second N-type heavily doped region 82 located between the first N-type heavily doped region 81 and the first P-type heavily doped region 83; wherein, the first N-type heavily doped region 81 is located within a first N-well 811, the second N-type heavily doped region 82 is located within a deep N-well 821, the first P-type heavily doped regions 83 are all located on a P-type substrate 80, the first N-well 811 is located on the P-type substrate 80, the deep N-well 821 is located within a second N-well 822, and the second N-well 822 is located on the P-type substrate 80; a first distance exists between the first N-type heavily doped region 81 and the second N-type heavily doped region 82, and a second distance exists between the second N-type heavily doped region 82 and the first P-type heavily doped region 83; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0151] Furthermore, the first N-well 811, the deep N-well 821, and the first P-type heavily doped region 83 constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0152] Furthermore, the P-type substrate 80 has a parasitic resistor 84, the first end of which is connected to the first heavily doped P-type region 83, and the second end of which is connected to the base of the parasitic NPN transistor.

[0153] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 15 As shown, the first N-type heavily doped region 81 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 82 and the first P-type heavily doped region 83 can be connected to the ground terminal VSS.

[0154] Specifically, the base of the parasitic NPN transistor is a P-type substrate 80, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 84, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0155] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0156] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0157] Reference Figure 16 and Figure 17 This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 91, a first P-type heavily doped region 93, and a second N-type heavily doped region 92 located between the first N-type heavily doped region 91 and the first P-type heavily doped region 93; wherein, the second N-type heavily doped region 92 is located within a first N-well 921, the first N-type heavily doped region 91 is located within a deep N-well 911, the first P-type heavily doped regions 93 are all located on a P-type substrate 90, the first N-well 921 is located on the P-type substrate 90, the deep N-well 911 is located within a second N-well 912, and the second N-well 912 is located on the P-type substrate 90; a first distance exists between the first N-type heavily doped region 91 and the second N-type heavily doped region 92, and a second distance exists between the second N-type heavily doped region 92 and the first P-type heavily doped region 93; the test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0158] Furthermore, the first N-well 921, the deep N-well 911, and the first P-type heavily doped region 93 constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0159] Furthermore, the P-type substrate 90 has a parasitic resistor 94, the first end of which is connected to the first heavily doped P-type region 93, and the second end of which is connected to the base of the parasitic NPN transistor.

[0160] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 17 As shown, the first N-type heavily doped region 91 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 92 and the first P-type heavily doped region 93 can be connected to the ground terminal VSS.

[0161] Specifically, the base of the parasitic NPN transistor is a P-type substrate 90, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 94, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0162] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0163] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0164] Reference Figure 18 and Figure 19This embodiment provides a test structure for an integrated circuit, including: a first N-type heavily doped region 101, a first P-type heavily doped region 103, and a second N-type heavily doped region 102 located between the first N-type heavily doped region 101 and the first P-type heavily doped region 103; wherein, the first N-type heavily doped region 101 is located within a first deep N-well 1011, the second N-type heavily doped region 102 is located within a second deep N-well 1021, and the first P-type heavily doped regions 103 are all located on a P-type substrate 100, and the first deep N-well 101... 1 is located within the first N-well 1012, and the second deep N-well 1021 is located within the second N-well 1022. The first N-well 1012 and the second N-well 1022 are located on the P-type substrate 100. There is a first distance between the first heavily doped N-type region 101 and the second heavily doped N-type region 102, and a second distance between the second heavily doped N-type region 102 and the first heavily doped P-type region 103. The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

[0165] Furthermore, the first deep N-well 1011, the second deep N-well 1021, and the first P-type heavily doped region 103 constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

[0166] Furthermore, the P-type substrate 100 has a parasitic resistor 104, the first end of which is connected to the first heavily doped P-type region 103, and the second end of which is connected to the base of the parasitic NPN transistor.

[0167] Before testing the integrated circuit test structure of this embodiment, it needs to be electrically connected. Specifically, as follows: Figure 19 As shown, the first N-type heavily doped region 101 can be connected to the power supply voltage VDD, and the second N-type heavily doped region 102 and the first P-type heavily doped region 103 can be connected to the ground terminal VSS.

[0168] Specifically, the base of the parasitic NPN transistor is a P-type substrate 100, and the gain from the base to the collector can reach tens of times. In the equivalent circuit formed by the parasitic NPN transistor and the parasitic resistor 104, the parasitic NPN transistor exists in two states: a high-resistance blocking state and a low-resistance latch-up state. When there is no external interference and no triggering, the parasitic NPN transistor is in the high-resistance blocking state, which is also the initial state of the parasitic NPN transistor. At this time, the current gain is very small, and the latch-up effect will not occur. When the collector current of the parasitic NPN transistor suddenly increases to a preset value, the parasitic NPN transistor may leave the high-resistance blocking state and enter the low-resistance latch-up state. At this time, the parasitic NPN transistor will form a negative resistance state between the power supply voltage VDD and the ground VSS. At this time, only a very small current is needed to continuously drive the amplification state of the parasitic NPN transistor, the emitter junction is forward biased, and the collector junction is reverse biased, that is, latch-up is formed.

[0169] When testing the integrated circuit test structure of this embodiment, with the first distance L1 and the second distance L2 set to the first set of values, the voltage applied to the power supply terminal VDD is gradually increased from 0V, for example, from 0V to 2V. The current between the power supply terminal VDD and the ground terminal VSS is monitored. When the current between the power supply terminal VDD and the ground terminal VSS suddenly increases, it is determined that a latch-up effect has occurred. In this way, the correspondence between the first set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained, which is to say, the latch-up characteristics of the parasitic NPN transistor are obtained. By adjusting at least one of the first distance L1 and the second distance L2, a second set of values ​​can be obtained. Then, by using the above test method, the correspondence between the second set of values ​​and the trigger voltage for latch-up, the sustaining voltage for latch-up, the current when latch-up is triggered, and the current during the latch-up sustaining phase can be obtained. By analogy, multiple sets of correspondences can be obtained. Based on the obtained correspondences, the first distance and the second distance of the integrated circuit with the test structure can be set, thereby avoiding latch-up effect during operation of the integrated circuit with the test structure and improving the reliability of the chip.

[0170] The integrated circuit test structure provided in this embodiment tests the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of a first distance and a second distance. The correspondence between these electrical parameters and the corresponding first and second distances can characterize the latch-up characteristics of the parasitic NPN transistor. Based on these latch-up characteristics, design rules for integrated circuits with this test structure can be defined, thereby avoiding latch-up effects during operation and improving chip reliability.

[0171] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; The first N-type heavily doped region, the second N-type heavily doped region, and the first P-type heavily doped region are all located on a P-type substrate; there is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

2. The integrated circuit test structure according to claim 1, characterized in that, The first N-type heavily doped region, the second N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

3. The integrated circuit test structure according to claim 2, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

4. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the first N-type heavily doped region is located in the N-well, the second N-type heavily doped region and the first P-type heavily doped region are both located on the P-type substrate, and the N-well is located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

5. The integrated circuit test structure according to claim 4, characterized in that, The N-well, the second N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

6. The integrated circuit test structure according to claim 5, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

7. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the first N-type heavily doped region is located in a deep N-well, the second N-type heavily doped region and the first P-type heavily doped region are both located on a P-type substrate, the deep N-well is located in an N-well, and the N-well is located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

8. The test structure for an integrated circuit according to claim 7, characterized in that, The deep N-well, the second N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

9. The integrated circuit test structure according to claim 8, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

10. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the second N-type heavily doped region is located in the N-well, the first N-type heavily doped region and the first P-type heavily doped region are both located on the P-type substrate, and the N-well is located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

11. The test structure for an integrated circuit according to claim 10, characterized in that, The N-well, the first N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

12. The test structure for an integrated circuit according to claim 11, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

13. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the second N-type heavily doped region is located in the deep N-well, the first N-type heavily doped region and the first P-type heavily doped region are both located on the P-type substrate, the deep N-well is located in the N-well, and the N-well is located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

14. The test structure for an integrated circuit according to claim 13, characterized in that, The deep N-well, the first N-type heavily doped region, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

15. The test structure for an integrated circuit according to claim 14, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

16. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the first N-type heavily doped region is located in the first N-well, the second N-type heavily doped region is located in the second N-well, the first P-type heavily doped region is located on the P-type substrate, and the first N-well and the second N-well are located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

17. The test structure for an integrated circuit according to claim 16, characterized in that, The first N-well, the second N-well, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

18. The test structure for an integrated circuit according to claim 17, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

19. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the first N-type heavily doped region is located in the first N-well, the second N-type heavily doped region is located in the deep N-well, the first P-type heavily doped region is located on the P-type substrate, the first N-well is located on the P-type substrate, the deep N-well is located in the second N-well, and the second N-well is located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

20. The test structure for an integrated circuit according to claim 19, characterized in that, The first N-well, the deep N-well, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

21. The test structure for an integrated circuit according to claim 20, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

22. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the second N-type heavily doped region is located in the first N-well, the first N-type heavily doped region is located in the deep N-well, the first P-type heavily doped region is located on the P-type substrate, the first N-well is located on the P-type substrate, the deep N-well is located in the second N-well, and the second N-well is located on the P-type substrate; There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

23. The test structure for an integrated circuit according to claim 22, characterized in that, The first N-well, the deep N-well, and the first P-type heavily doped region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

24. The test structure for an integrated circuit according to claim 23, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

25. A test structure for an integrated circuit, characterized in that, include: A first N-type heavily doped region, a first P-type heavily doped region, and a second N-type heavily doped region located between the first N-type heavily doped region and the first P-type heavily doped region; Wherein, the first N-type heavily doped region is located in the first deep N-well, the second N-type heavily doped region is located in the second deep N-well, the first P-type heavily doped region is located on the P-type substrate, the first deep N-well is located in the first N-well, the second deep N-well is located in the second N-well, and the first N-well and the second N-well are located on the P-type substrate. There is a first distance between the first N-type heavily doped region and the second N-type heavily doped region, and a second distance between the second N-type heavily doped region and the first P-type heavily doped region; The test structure is used to test the electrical parameters of the integrated circuit corresponding to the test structure by adjusting at least one of the first distance and the second distance.

26. The test structure for an integrated circuit according to claim 25, characterized in that, The first deep N-well, the second deep N-well, and the first heavily doped P-type region constitute a parasitic NPN transistor; the test structure is used to test the latch-up characteristics of the parasitic NPN transistor.

27. The test structure for an integrated circuit according to claim 26, characterized in that, The P-type substrate has a parasitic resistance, with a first end connected to the first heavily doped P-type region and a second end connected to the base of the parasitic NPN transistor.

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