Techniques for memory system configuration using queue refill time

Abstract

This application relates to techniques for memory system configuration using queue refill time. A memory system can receive a command from a host system and can add the command to a command queue that includes a set of commands to be executed by the memory system. The memory system can determine a queue refill time for the command queue using a measurement of at least one queue tag of the command queue and can adjust at least one resource of the command queue in response to the determined queue refill time. In some instances, the memory system can reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth of the command queue, or any combination thereof, among other options, based on the queue refill time.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 243,321, filed April 28, 2021, entitled “Techniques for memory system configuration using queue refill time”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to techniques for configuring memory systems that utilize queue refill time. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any of these multiple possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even without an external power supply. Summary of the Invention

[0006] Describe a device. In some instances, the device may include a memory device and a controller coupled to the memory device. The controller may be configured to cause the device to: receive commands from a host system; add commands to a command queue, wherein the command queue contains a set of commands to be executed by the memory system, and wherein each of the commands in the set corresponds to a corresponding queue tag of the command queue; measure a queue refill time of the command queue based on a queue tag of the command queue; and adjust at least one resource for the command queue based on the queue refill time.

[0007] A non-transitory computer-readable medium for storing code is described. In some instances, the code may contain instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a command from a host system; add the command to a command queue, wherein the command queue contains a set of commands to be executed by a memory system, and wherein each of the commands in the set corresponds to a corresponding queue tag of the command queue; measure a queue refill time of the command queue based on a queue tag of the command queue; and adjust at least one resource for the command queue based on the queue refill time.

[0008] Describe a method. In some instances, the method may include: receiving a command from a host system; adding the command to a command queue, wherein the command queue contains a set of commands to be executed by a memory system, and wherein each of the commands in the set corresponds to a corresponding queue tag of the command queue; measuring the queue refill time of the command queue based on a queue tag of the command queue; and adjusting at least one resource for the command queue based on the queue refill time. Attached Figure Description

[0009] Figure 1 and 2 This describes an example of a system that supports a technique for configuring a memory system to utilize queue refill time, based on examples disclosed herein.

[0010] Figure 3 This document describes an example of a command queue configuration that supports a memory system configuration for using queue refill time, based on examples disclosed herein.

[0011] Figure 4 This document describes an example of a process flow that supports a memory system configuration using queue refill time, based on examples disclosed herein.

[0012] Figure 5 A block diagram of a memory system is shown, based on examples disclosed herein, supporting techniques for configuring memory systems to utilize queue refill time.

[0013] Figure 6The flowchart illustrates one or more methods for configuring a memory system using queue refill time, based on examples disclosed herein. Detailed Implementation

[0014] A memory system that communicates electronically with a host system can receive one or more commands from the host system. For example, a memory system can receive a read command to read the logical state of one or more memory cells of the memory device of the memory system, or receive a write command to write the logical state to one or more memory cells of the memory device. Some memory systems may be able to execute more than one command at a time or store more than one command for execution. In such instances, the memory system may be configured to have a command queue. The command queue may store a list of commands to be executed by the memory system or currently being executed by the memory system (or both). Each command in the command queue may be associated with a corresponding queue tag (e.g., a queue entry in the list of commands), where the number of queue tags in the command queue may be referred to as the queue depth. If the memory system finishes executing the command for a given queue tag, the memory system may remove the command from the command queue. The host system may send new commands to the memory system, and the memory system may refill a given queue tag with the new command. The time it takes to refill a queue tag with a new command may be referred to as the refill time, and the command queue may have a queue refill time associated with the refill time of one or more queue tags in the command queue. A memory system can allocate a certain amount of resources (e.g., a certain amount of processing power and memory resources) to the command queue. However, during the command queue refill time, some of the allocated resources may go unused due to the potentially inaccurate allocation of the amount of resources available for the command queue, thus actually reducing the efficiency of the memory system.

[0015] To efficiently utilize memory system resources, the memory system can reallocate command queue resources in response to a measured queue refill time. In some instances, the memory system can perform operations, such as running tests, such as benchmarks, to measure the queue refill time of the command queue. During the test, such as the benchmark, the command queue can be filled to a specific queue depth (e.g., a queue depth of 1, 8, or 32). The memory system can measure the queue refill time as the time between the completion of a command and the re-insertion of a new command from the same queue tag from the benchmark. Once the memory system determines the queue refill time, it can reallocate resources (e.g., processing resources, memory resources, or both, and other resources) to the command queue. For example, the memory system can use command queue resources to perform other tasks during the queue refill time, or the memory system can reduce processing power by a certain amount during the queue refill time. During the duration of the queue refill time, the memory system can reduce processing power by reducing one or more clock speeds associated with the command queue or by reducing the voltage supplied to the processor. In some other instances, the memory system may not utilize the full queue depth and can adjust the queue depth in response to the queue refill time. In such instances, the memory system can adjust command queue resources to match the adjusted queue depth, and the additional resources can be reused for other processes. Alternatively, the memory system can adjust the parallelism of the memory devices, the type of commands used to access the memory devices of the memory system, or the amount of memory cells allocated to the command queue. Using the methods described herein, the memory system can improve system efficiency by aligning resource usage with memory system capabilities in terms of queue refill time, queue depth, and command queue resources.

[0016] Firstly, in reference Figure 1 and 2 The features of this disclosure are described in the context of systems and apparatuses. (Referencing...) Figure 3 Command queue configuration and reference Figure 4 Additional features of this disclosure are described in the context of the process flow. (See references.) Figure 5 and 6 These and other features of this disclosure are further illustrated in the context of device diagrams and flowcharts relating to techniques for configuring memory systems using queue refill time, and are described in the context of said device diagrams and flowcharts.

[0017] Figure 1 This describes an example of system 100 that supports a memory system configuration for using queue refill time, based on examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0019] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0020] System 100 may include a host system 105, which may be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0021] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more such interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0022] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0023] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled and communicate with the memory device 130 to perform operations at the memory device 130 that are generally referred to as access operations, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0025] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0026] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or operations related to the functions attributed to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, the data may be stored in local memory 120 and may be available in local memory 120 for subsequent retrieval or manipulation (e.g., updates) by the host system 105 according to a caching strategy (e.g., reduced latency relative to memory device 130).

[0027] Although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may (e.g., on the same die or within the same package) include a local controller 135 that can perform operations on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described herein, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0031] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Compared to SLC memory cells, multi-level memory cells can provide greater storage density, but in some cases, this may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0032] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0033] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0034] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Furthermore, in some cases, NAND memory cells may be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0035] System 100 may include any number of non-transitory computer-readable media that support techniques for using memory system configurations that utilize queue refill times. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0036] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is an MNAND system.

[0037] In some instances, memory system 110 may receive multiple commands from host system 105 at a given time and may store these commands in a command queue. The command queue may be an instance of a list of running commands (e.g., commands being executed by memory system 110 or awaiting execution by the memory system). Each command in the command queue may be associated with a corresponding queue tag, and the number of commands present in the command queue at a given time may be referred to as the queue depth. Once memory system 110 executes a command stored at a given queue tag, the command at that tag may be removed from the command queue, and a new command may be added to the command queue at that given queue tag. In some instances, system 100 may spend time repopulating a given queue tag with new commands. During this time, at least a portion of the resources allocated to the command queue may be unused. For example, a subset of the resources associated with processing the command queue may be unused, resulting in power consumption at memory system 110 not having a corresponding performance gain.

[0038] As described herein, memory system 110 can measure the queue refill time of a command queue and can adjust resources used for the command queue in response to the queue refill time. In some instances, memory system 110 can measure the refill time of one or more queue tags in the command queue. That is, memory system 110 can measure the time between the execution of a command for a specific queue tag and the insertion of a new command at that specific queue tag. In some instances, memory system 110 can average the refill times of one or more queue tags and set the average value as the queue refill time. In another instance, memory system 110 can determine the fastest refill time for one or more queue tags and set the fastest refill time as the queue refill time. In some instances, the queue refill time can be updated to reflect changes to memory system 110 or host system 105. Once memory system 110 determines the queue refill time, memory system 110 can adjust resources used for the command queue in response to the queue refill time. For example, memory system 110 can adjust processing resources used for the command queue in response to the queue refill time. Alternatively, memory system 110 may adjust the queue depth of the command queue in response to queue refill time, and subsequently adjust the resources allocated to the command queue to support the adjusted queue depth. Memory system 110 may adjust the parallelism of memory device 130, the type of read commands used to read data from memory device 130, the memory resources allocated to the command queue, or any combination thereof, in response to the adjusted queue depth. The method described herein allows memory system 110 to meet threshold performance requirements without excessive power consumption.

[0039] Figure 2 This describes an example of system 200 that supports a memory system configuration for using queue refill time, based on examples disclosed herein. System 200 may be as described in the references. Figure 1 An example of system 100 as described in the preceding description. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may be implemented as described in the reference. Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0040] As described herein, memory system 210 may include memory device 240 for storing data transferred between memory system 210 and host system 205, for example, in response to receiving an access command from host system 205. Memory device 240 may include, as referenced... Figure 1The memory device 240 may include one or more memory devices as described. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0041] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, for example, for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described in the reference. Figure 1 The aspects of the local controller 135 described.

[0042] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used to translate data between the host system 205 and the memory device 240 (e.g., as shown by data path 250), and may be collectively referred to as the data path component.

[0043] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, the buffered data can be stored or transmitted (or both). Buffer 225 may include relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators or both, to allow for rapid storage of data into and from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0044] The temporary storage of data in buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it can be overwritten with data from an additional access command). Additionally, buffer 225 may be a non-cached buffer. That is, the host system 205 cannot directly read data from buffer 225. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0045] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in the reference... Figure 1 An example of the described memory system controller 115. Bus 235 can be used for communication between system components.

[0046] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, when the memory system 210 processes more than one access command from the host system 205 simultaneously. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) can be located anywhere within the memory system 210.

[0047] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210). Alternatively, memory system 210 may include data bus 280. Data bus 280 may support data path 250 or be an instance of said data path. Data bus 280 may allow data transfer between subsets of system components in memory system 210. For example, data bus 280 may be connected to a combination of these or another subset of buffer 225, interface 220, storage controller 230 or components, and may allow buffer 225, interface 220, storage controller 230 or a combination of these or other components to exchange data.

[0048] If host system 205 transmits an access command to memory system 210, interface 220 can receive the command, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered as the front end of memory system 210. Upon receiving each access command, interface 220 can, for example, transmit the command to memory system controller 215 via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0049] The memory system controller 215 can determine whether an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving a command from command queue 260. After, for example, the command has been retrieved from command queue 260 by memory system controller 215, the command can be removed from the command queue. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0050] After confirming that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0051] In either case, the memory system controller 215 may use the buffer 225, particularly for the temporary storage of data received from or sent to the host system 205. The buffer 225 may be considered as an intermediate part of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations within the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0052] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the write command, for example via firmware (e.g., controller firmware).

[0053] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating where the data associated with each command is stored in buffer 225 can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed simultaneously.

[0054] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the data to be stored within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0055] After written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0056] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain an entry for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating the location in buffer 225 where data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is to be retrieved, either from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the locations within memory device 240 used for storing data (e.g., performing wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, via the storage controller 230 or the memory system controller 215.

[0057] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0058] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to buffer 225 has been completed.

[0059] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data to be retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data to be stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of data to be stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0060] After data has been stored in buffer 225 by storage controller 230, the data can be transferred from buffer 225 and sent to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0061] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in, first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into buffer 225 and stored therein, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0062] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0063] As described herein, memory system 210 can adjust the resources allocated to command queue 260 based on its refill time. Memory system 210 can accept multiple commands from host system 205 at a given time and can push these commands into command queue 260. Each command in command queue 260 may correspond to a corresponding queue tag, and the number of commands in command queue 260 at a given time may be referred to as the queue depth. In some instances, the threshold queue depth of memory system 210 may be 32. That is, memory system 210 can allocate memory resources to command queue 260 such that the number of commands stored in command queue 260 does not exceed 32.

[0064] In some instances, memory system 210 can determine the queue refill time of command queue 260 by performing benchmark tests. Benchmark tests can be used to determine the threshold performance of memory system 210 at a specific queue depth (e.g., queue depths 1, 8, 32, or some other queue depth). During benchmark testing, host system 205 can send multiple commands (e.g., read commands for randomly reading from a benchmark, write commands for randomly writing to a benchmark, or some other set of commands) to memory system 210 to fill command queue 260 to the specific queue depth.

[0065] After command queue 260 is filled (e.g., to a specific queue depth), memory system 210 can measure the refill time of one or more queue tags in the command queue. The refill time can be measured as the time it takes for interface 220 to insert a new command at a given queue tag after a command previously stored at that queue tag has been executed by memory system 210. In some instances, memory system 210 can average the refill times of one or more queue tags and set the queue refill time of command queue 260 as the average. In some other instances, memory system 210 can set the queue refill time of command queue 260 as the fastest refill time among the measured refill times of one or more queue tags. In some instances, memory system 210 can use one or more timers (or one or more clocks) to measure the refill time of one or more queue tags. In some instances, one or more timers may be included at interface 220, and each queue tag in the one or more queue tags may be associated with a timer (e.g., the same timer or different timers). A timer for a given queue tag may be started upon receiving a completion signal (e.g., from memory system controller 215) indicating that memory system 210 has executed a command for the given queue tag, and stopped after a new command is inserted at the given queue tag. Alternatively, the refill time may be calculated using stored timestamps (e.g., timestamps indicating that a command was removed from command queue 260 at the given queue tag and timestamps indicating that a command was inserted into command queue 260 at the given queue tag). In some instances, refill time measurements 275 (e.g., measured refill times for one or more queue tags, queue refill time for command queue 260, or both) may be stored by memory system 210 at, for example, interface 220, memory system controller 215, one or more memory devices 240, or a combination thereof. Similarly, command queue 260 may be stored at interface 220, memory system controller 215, or another component of memory system 210 (e.g., in a cache, such as an SRAM cache).

[0066] In some instances, memory system 210 may update command queue 260 over time. For example, memory system 210 may perform a second benchmark test and determine a second queue refill time. If the second queue refill time differs from the current queue refill time, memory system 210 may update the queue refill time to reflect the second queue refill time (e.g., in refill time measurement result 275).

[0067] After determining the queue refill time of command queue 260, memory system 210 may adjust one or more resources allocated to command queue 260. In some instances, memory system 210 may adjust the processing resources allocated to command queue 260 in response to the queue refill time. For example, memory system 210 may reallocate a portion of the processing resources associated with command queue 260 to other tasks during the duration of the queue refill time. In some instances, memory system 210 may reallocate processing resources to perform queue tags different from those being refilled. In another instance, memory system 210 may reduce the amount of processing resources allocated to the command queue during the queue refill time. For example, memory system 210 may reduce (or gate) one or more clock speeds associated with command queue 260, or reduce the voltage supplied to the processor (e.g., CPU), for one or more components (e.g., CPU, internal system bus, low-density parity check (LDPC) engine, or open NAND flash interface (ONFI)) during the duration of the queue refill time. In some instances, the amount by which clock speed or voltage can be reduced can be scaled based on the queue refill time. That is, the faster the queue refill time, the less the clock speed and voltage can be reduced.

[0068] In some instances, memory system 210 may adjust the queue depth of command queue 260 in response to queue refill time, and memory system 210 may correspondingly adjust the resources allocated to command queue 260 based on the adjusted queue depth. In some instances, memory system 210 may not consistently reach a queue depth or threshold queue depth (e.g., a maximum queue depth of 32) for command queue 260 as specified by a benchmark test. For example, memory system 210 may execute commands for command queue 260 while interface 220 is filling command queue 260. As an example, the specific queue depth for the benchmark test may be 32, but command queue 260 may typically fail to reach a queue depth less than 32. For example, although the resources allocated to command queue 260 support a threshold queue depth of 32, in actual implementation, memory system 210 may use commands to load command queue 260 to a different threshold queue depth (e.g., the actual operating maximum queue depth of 16). In such instances, memory system 210 may reduce the threshold queue depth (e.g., the maximum queue depth) of command queue 260. For example, memory system 210 may reduce the threshold queue depth from a first threshold queue depth (e.g., a threshold queue depth of 32) to a threshold queue depth less than 32 (e.g., a threshold queue depth of 16). In some instances, memory system 210 may predict the threshold queue depth of command queue 260 based on benchmarks, or more specifically, measured queue refill times, and may adjust the threshold queue depth to the predicted threshold queue depth.

[0069] After adjusting the threshold queue depth of command queue 260, memory system 210 may adjust the resources used for command queue 260 to match the adjusted threshold queue depth. In some instances, memory system 210 may adjust the parallelism of memory devices 240 to match the adjusted threshold queue depth. That is, memory system 210 may turn on or off one or more memory devices 240 to process access commands of command queue 260 to support the adjusted threshold queue depth. In some instances, memory system 210 may adjust the threshold queue depth from a first queue depth to a second queue depth, where the first queue depth is greater than the second queue depth. In such instances, memory system 210 may turn off one or more memory devices 240 (or, additionally, revoke one or more connections activated to one or more memory devices 240). The number of memory devices 240 that can be turned on or off may depend on the difference between the first queue depth and the second queue depth. In some instances, if memory system 210 contains multiple processors (e.g., CPUs) operating in parallel, memory system 210 may similarly adjust the parallelism of the processors in response to an adjusted threshold queue depth (e.g., deactivating one or more processors in response to reducing the threshold queue depth of command queue 260).

[0070] In some instances, the read algorithm used to access memory device 240 may be modified to support the adjusted threshold queue depth. That is, memory system 210 may adjust the amount of data read from memory device 240 for a given read command. For queue depths below the threshold, memory system 210 may utilize cache reads (e.g., sensing and retrieving 1 to 4 pages of data), and for queue depths below different thresholds, memory system 210 may utilize fast reads (sensing and retrieving up to 4 kilobytes (KB) of data). In some instances, memory system 210 may adjust the memory resources used for command queue 260 to support the adjusted threshold queue depth. For example, memory system 210 may adjust the cache size allocated to memory system 210 (e.g., SRAM cache size). Command queue 260 may be stored in a cache, and memory system 210 may reduce the cache size if the threshold queue depth decreases. Alternatively, memory system 210 may reallocate cache (e.g., resources initially allocated to or managed by the cache) to serve other operations not associated with host data management.

[0071] In some instances, memory system 210 may store a lookup table containing queue refill times and associated adjustments (e.g., resource adjustments) for those queue refill times. Memory system 210 may store the lookup table at interface 220, memory system controller 215, or one or more memory devices 240. The lookup table may contain a set of queue refill times (e.g., a range of queue refill times), and each queue refill in the set may contain an indication of how to adjust the processor's clock speed, processor voltage, threshold queue depth of command queue 260, parallelism of memory device 240, processor parallelism, type of read command used to access memory device 240, cache size of memory system 210, or a combination thereof. If memory system 210 determines a queue refill time, it may compare that queue refill time with the queue refill time in the lookup table and adjust the resources for command queue 260 accordingly. By adjusting the resources used for command queue 260 in response to the measured queue refill time, memory system 210 can improve its performance in terms of efficiency and power consumption. Furthermore, if the queue refill time changes dynamically, memory system 210 can determine the updated queue refill time and update the resource adjustments for command queue 260 accordingly, thereby supporting updates to the operation of queue resource management in response to changes in the use of command queue 260.

[0072] Figure 3 This describes an example of a command queue configuration 300 that supports techniques for configuring memory systems using queue refill times, based on examples disclosed herein. In some instances, the command queue configuration 300 may implement features of systems 100 and 200. For example, command queue 305 and table 325 may be as described in the references... Figure 2 Examples of the described command queue 260 and refill time measurement result 275. In some instances, command queue 305 may be located at the interface between the memory system and the host system. The interface may be coupled to the host system via connection 315-a, and the interface may be coupled to the memory system or a component of the memory system via connection 315-b. In some cases, command queue 305 may be stored in the memory system's cache (e.g., SRAM cache) or at the memory system controller. In some instances, command queue 305 may contain multiple queue tags 310 (e.g., 32 queue tags).

[0073] For reference Figure 2As described, the memory system can undergo benchmarking to determine the queue refill time of command queue 305. During benchmarking, the interface can receive multiple commands from the host system via connection 315-a to load into command queue 305. For example, the memory system can receive multiple commands and can add each command to command queue 305 at a specific queue label 310 (e.g., queue labels 0, 1, 2, 3, 4, 5, and at most 31 for a threshold queue depth of 32).

[0074] In some instances, the memory system can execute commands stored in command queue 305. For example, the memory system can execute a command at queue tag 2. After the command is executed, the memory system can remove the command from queue tag 310 and record a first timestamp associated with the removal of the command. For example, the memory system can remove a command from command queue 305 at queue tag 2 and record the timestamp associated with queue tag 2 (e.g., t) in table 325. 2,2 The memory system removes the timestamp associated with the command from command queue 305 at queue tag 310. After removing the command from command queue 305, the memory system can add a new command to command queue 305 at the same queue tag 310, and can record a second timestamp associated with adding the command to command queue 305. For example, the memory system can add a new command to command queue 305 at queue tag 2, and record a timestamp associated with the command added to command queue 305 at queue tag 2 (e.g., t). 2,1 The new command is added to the timestamp associated with command queue 305 at the specified location. After the memory system determines the first and second timestamps of a given queue label 310, the memory system or host system can determine the refill time of the given queue label 310 by calculating the difference (Δt) between the second and first timestamps.

[0075] In some instances, the memory system may store one or all of the first timestamp, the second timestamp, and the refill time in Table 325. Table 325 may be as referenced. Figure 2 An example of the described refill time measurement result 275. Table 325 may contain a number of columns, each corresponding to a different queue label 310 of command queue 305, such that the memory system can record and store a first timestamp, a second timestamp, and a refill time for each queue label 310 of command queue 305 (e.g., 32 columns for a threshold queue depth of 32). In some instances, the memory system may perform a second benchmark test and update the values ​​of the first timestamp, second timestamp, and refill time in Table 325 as the result of the second benchmark test. In some instances, it may be based on... Figure 3 The different formats described herein are stored in Table 325.

[0076] In some instances, the memory system or host system may determine the queue refill time of command queue 305 based on values ​​stored in table 325 (e.g., calculating the queue refill time using said values). For example, the memory system may select the refill time of table 325 with the lowest value and set said lowest value as the queue refill time of command queue 305. In some instances, the memory system or host system may average the refill times of table 325 and set said average as the queue refill time of command queue 305. Using the queue refill time, the memory system may adjust the resources used for command queue 305. For example, the memory system may adjust the internal clock speed during the queue refill time or reallocate processing resources to other tasks during the queue refill time, as referenced. Figure 2 The discussion.

[0077] Alternatively, the memory system may adjust the queue depth of command queue 305 (e.g., a threshold queue depth) in response to queue refill time. During benchmarking, the memory system may add commands to command queue 305 to reach a specific queue depth (e.g., a queue depth of 32). However, in some cases, commands may be executed by the memory system while it is filling command queue 305. For example, the memory system may fill command queue 305 to queue tag 3, and the memory system may execute a command stored at queue tag 2. If command queue 305 has queue tags 0 to 3 that are refilled with incoming commands, and queue tags 4 to 31 are not used, then the threshold queue depth of 32 for command queue 305 may be excessive (e.g., corresponding to a relatively inefficient allocation of resources to command queue 305). Therefore, the measured queue refill time may not reflect the queue refill time at the threshold queue depth, but rather the queue refill time at a queue depth less than the threshold queue depth. Using this information, the memory system can predict the threshold queue depth (e.g., the actual operational threshold queue depth) and adjust the threshold queue depth to the predicted queue depth. For example, the memory system can predict a queue depth of 4 and adjust the threshold queue depth of command queue 305 (from 32) to 4. That is, command queue 305 can contain queue labels 0, 1, 2, and 3.

[0078] After adjusting the threshold queue depth, the memory system can also adjust resources to match the adjusted threshold queue depth. For example, the memory system can deactivate or reallocate a portion of the processing resources used for command queue 305. The memory system can deactivate processing resources associated with queue tags 4 to 31, or the memory system can reallocate said processing resources to other tasks (e.g., executing commands for queue tags 0, 1, 2, and 3). Alternatively or additionally, the memory system can adjust the parallelism of the memory devices, the parallelism of the processors, the read commands used to access the memory devices, or the cache size of the memory system, as referenced. Figure 2 As described. By adjusting the threshold queue depth in response to queue refill time and aligning the resources of command queue 305 with the adjusted threshold queue depth, the memory system can improve performance and reduce power consumption.

[0079] Figure 4 This describes an example of process flow 400 that supports a memory system configuration for using queue refill time, based on examples disclosed herein. Process flow 400 may be derived from a memory system (or one or more components thereof), such as those described in the references. Figure 1 and 2 The described memory system 110 or memory system 210 performs this operation. The memory system can be determined, for example, as referenced... Figure 2 and 3 The command queue refill time of the described command queue 260 or command queue 305 can be used to adjust resources in response to the determined queue refill time. In some cases, alternative instances of the following can be implemented, some of which may be performed in a different order than described or not at all. Additionally or alternatively, operations may include additional features not mentioned below, or other processes may be added.

[0080] At 405, a command is received from the host system. The command may be an instance of an access command (e.g., a write command or a read command). That is, the command may be associated with accessing one or more memory devices of the memory system.

[0081] At position 410, a command is added to the command queue. The command queue can contain a set of commands to be executed by (or currently being executed by) the memory system. The number of commands in the command queue is called the queue depth. In some cases, the command queue can support storing a threshold (e.g., a maximum) number of commands at a time, referred to as the threshold queue depth or maximum queue depth. In some instances, the memory system can add commands to the command queue at a specific queue label (e.g., an empty queue label where no commands are currently stored).

[0082] At 415, the queue refill time of the command queue can be measured. Measuring the queue refill time may involve measuring the refill time of one or more queue tags of the command queue. An example of refill time may be the time taken by the memory system to add a second command (different from the first command) to the queue tag after the execution of the first command at the queue tag. In some instances, the memory system may use the fastest refill time of one or more queue tags as the queue refill time. In some instances, the memory system may use the average of the refill times of one or more queue tags as the queue refill time. In some instances, the memory system may store the refill times of one or more queue tags and the queue refill time of the command queue at a memory device of the memory system. In some cases, the memory system may calculate threshold performance based on the queue refill time (e.g., using the queue refill time to calculate threshold performance). For example, the memory system may multiply the queue refill time by an amount of queue depth and determine the performance of the memory system in terms of operations per second.

[0083] At point 420, it can be determined whether the change in the command queue refill time meets the threshold. (See reference...) Figure 2 and 3 As described, the queue refill time can be updated as conditions change by running one or more additional benchmarks. The memory system can compare the queue refill time measured at 415 locations with past queue refill times and determine whether the difference between the measured queue refill time and the past queue refill time meets a threshold.

[0084] At 425, the resources used for the command queue are not adjusted (e.g., if a change in the queue refill time fails to meet the threshold used to trigger an update to the resource allocation).

[0085] At 430, the resources used for the command queue are adjusted based on the measured queue refill time. In some instances, the memory system may adjust the processing resources used for the command queue in response to the queue refill time. For example, the memory system may use at least a portion of the processing resources used for the command queue to execute one or more tasks during the duration of the queue refill time, deactivate at least a portion of the processing resources used for the command queue, or adjust the processor's clock rate or voltage. Alternatively, the memory system may adjust the queue depth of the command queue (e.g., a threshold queue depth, such as a maximum queue depth) in response to the queue refill time. In some instances, the memory system may adjust the resources used for the command queue to support the adjusted queue depth. For example, the memory system may adjust the number of memory devices operating in parallel or the number of processors operating in parallel in response to the adjusted queue depth. Alternatively, the memory system may determine the type of read command used to read one or more memory devices, or may adjust the amount of memory resources allocated to a cache (e.g., an SRAM cache) in response to the adjusted queue depth.

[0086] Aspects of process flow 400 may be implemented by controllers and other components in a system (e.g., system 100 or system 200). For example, a memory system controller of a memory system may execute one or more aspects of process flow 400. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to the memory system). For example, when executed by a controller (e.g., a memory system controller), the instructions may cause the controller to perform the operation of process flow 400.

[0087] Figure 5 A block diagram 500 illustrates a memory system 520 that supports a memory system configuration for using queue refill time, based on examples disclosed herein. The memory system 520 may be as described in the references... Figures 1 to 4 Examples of aspects of the described memory system. Memory system 520 or its various components may be examples of various aspects of the means for performing memory system configurations using queue refill times as described herein. For example, memory system 520 may include command manager 525, queue manager 530, refill time manager 535, resource manager 540, performance manager 545, queue depth manager 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0088] Command manager 525 may be configured or otherwise support components for receiving commands from a host system. Queue manager 530 may be configured or otherwise support components for adding commands to a command queue, wherein the command queue contains a plurality of commands to be executed by a memory system, and wherein each of the plurality of commands corresponds to a corresponding queue tag of the command queue. Refill time manager 535 may be configured or otherwise support components for measuring the queue refill time of the command queue, at least in part based on at least one queue tag of the command queue (e.g., using its measurement results). Resource manager 540 may be configured or otherwise support components for adjusting at least one resource for the command queue, at least in part based on (e.g., in response to) the queue refill time.

[0089] In some instances, to support adjustments to at least one resource for the command queue, the resource manager 540 may be configured or otherwise support components for performing one or more operations at the memory system using at least one resource for the command queue during a duration associated with the queue refill time.

[0090] In some instances, to support adjustments to at least one resource used for the command queue, the resource manager 540 may be configured or otherwise support the revocation of a component that is active for at least one resource used for the command queue during a duration associated with the queue refill time.

[0091] In some instances, to support adjustments to at least one resource used for the command queue, the resource manager 540 may be configured or otherwise support components for adjusting the processor's clock rate during a duration associated with the queue refill time.

[0092] In some instances, to support adjustments to at least one resource used for the command queue, the resource manager 540 may be configured or otherwise support components for adjusting the processor voltage during a duration associated with the queue refill time.

[0093] In some instances, to support adjustments to at least one resource used for the command queue, the resource manager 540 may be configured or otherwise support a component for adjusting the queue depth of the command queue (e.g., a threshold queue depth, such as a maximum queue depth) from a first number of queue labels to a second number of queue labels, the queue depth corresponding to a threshold number of commands supported by the command queue.

[0094] In some instances, the resource manager 540 may be configured or otherwise support components for adjusting, at least in part, the number of memory devices operating in parallel on the memory system, the number of processors operating in parallel on the memory system, or both, based on (e.g., in response to) adjusting queue depth.

[0095] In some instances, the resource manager 540 may be configured or otherwise support components for determining the type of read command to be used by the memory system for read operations, at least in part based on (e.g., in response to) adjusting the queue depth.

[0096] In some instances, the resource manager 540 may be configured or otherwise supported to include components for adjusting the amount of memory resources allocated to the cache based at least in part on (e.g., in response to) adjusting the queue depth.

[0097] In some instances, the resource manager 540 may be configured or otherwise support components for reallocating at least a portion of resources to a command queue associated with a first queue label number but not a second queue label number, based at least in part on (e.g., in response to) adjusting the queue depth. In some instances, the first queue label number is greater than the second queue label number.

[0098] In some instances, the queue depth manager 550 may be configured or otherwise supported to include components for predicting a threshold queue depth at least in part based on (e.g., in response to) queue refill time, wherein the queue depth of the command queue is adjusted to the predicted threshold queue depth.

[0099] In some instances, a command is added to a command queue at a first queue tag, and command manager 525 may be configured or otherwise support components for executing the command. Queue manager 530 may be configured or otherwise support components for removing a command from a first queue tag of the command queue at least in part based on (e.g., directly in response to) the execution of the command. Command manager 525 may be configured or otherwise support components for receiving a second command from a host system, and queue manager 530 may be configured or otherwise support components for adding a second command to a command queue at a first queue tag at least in part based on (e.g., due to) the removal of the command from the command queue, wherein the queue refill time is measured at least in part based on the removal of the command from the first queue tag and the addition of the second command to the command queue at the first queue tag (e.g., using an associated value).

[0100] In some instances, the refill time manager 535 may be configured or otherwise supported to include a component for indicating, with a first associated storage indicating the first time a command is removed from the first queue label of the command queue. In some instances, the refill time manager 535 may be configured or otherwise supported to include a component for indicating, with a second associated storage indicating the second time a second command is added to the command queue at the first queue label. In some instances, the refill time manager 535 may be configured or otherwise supported to include a component for calculating the difference between the second timestamp and the first timestamp to determine the queue refill time.

[0101] In some instances, to support the measurement of queue refill time, the refill time manager 535 may be configured or otherwise support components for measuring multiple refill times of multiple queue tags of a command queue. In some instances, to support the measurement of queue refill time, the refill time manager 535 may be configured or otherwise support components for averaging multiple refill times to determine the queue refill time.

[0102] In some instances, the refill time manager 535 may be configured or otherwise support components for storing queue refill times at a memory device of a memory system, a controller of a memory system, a command queue, or a combination thereof.

[0103] In some instances, the refill time manager 535 may be configured or otherwise support a component for adjusting the queue refill time of the command queue based at least in part on (e.g., in response to) the execution of one or more additional commands.

[0104] In some instances, the performance manager 545 may be configured or otherwise supported for components used to calculate the threshold performance of the memory system based at least in part on (e.g., according to) queue refill time, wherein at least one resource is adjusted based at least in part on (e.g., in response to) the threshold performance.

[0105] Figure 6 The flowchart illustrates a method 600 for configuring a memory system using queue refill time, based on examples disclosed herein. The operation of method 600 can be implemented by a memory system or its components as described herein. For example, it can be implemented by... (See references...) Figures 1 to 5 The described memory system performs the operations of method 600. In some instances, the memory system may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0106] At 605, the method may include receiving a command from the host system. The operation of 605 can be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 5 The described command manager 525 performs the operations of 605.

[0107] At 610, the method may include adding commands to a command queue, wherein the command queue contains a plurality of commands to be executed by the memory system, and wherein each of the plurality of commands corresponds to a corresponding queue tag of the command queue. The operation at 610 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 5 The described queue manager 530 performs the operations of 610.

[0108] At 615, the method may include measuring the queue refill time of the command queue based at least in part on at least one queue label of the command queue (e.g., using one or more values ​​associated therewith). The operation at 615 may be performed according to examples disclosed herein. In some instances, it may be performed by reference to... Figure 5 The refill time manager 535 describes the aspect of performing the operation 615.

[0109] At 620, the method may include adjusting at least one resource for the command queue based at least in part on (e.g., in response to) the queue refill time. The operation at 620 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 5 The described aspect of the operation performed by the resource manager 540 is 620.

[0110] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving commands from a host system; adding commands to a command queue, wherein the command queue contains a plurality of commands to be executed by a memory system, and wherein each of the plurality of commands corresponds to a corresponding queue tag of the command queue; measuring a queue refill time of the command queue based at least in part on at least one queue tag of the command queue; and adjusting at least one resource for the command queue based at least in part on the queue refill time.

[0111] In some instances of method 600 and the device described herein, adjusting at least one resource for the command queue may include operations, features, circuitry, logic, components, or instructions for performing one or more operations at a memory system using at least one resource for the command queue during a duration associated with a queue refill time.

[0112] In some instances of method 600 and the device described herein, adjusting at least one resource for the command queue may include operations, features, circuitry, logic, components, or instructions for deactivating at least one resource for the command queue during a duration associated with the queue refill time.

[0113] In some instances of method 600 and the device described herein, adjusting at least one resource for the command queue may include operations, features, circuitry, logic, components, or instructions for adjusting the processor's clock rate during a duration associated with the queue refill time.

[0114] In some instances of method 600 and the device described herein, adjusting at least one resource for the command queue may include operations, features, circuitry, logic, components, or instructions for adjusting the processor voltage during a duration associated with the queue refill time.

[0115] In some instances of method 600 and the device described herein, adjusting at least one resource for the command queue may include operations, features, circuitry, logic, components, or instructions for adjusting the queue depth of the command queue from a first queue label number to a second queue label number, the queue depth corresponding to a threshold number of commands supported by the command queue.

[0116] Method 600 and some examples of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for adjusting the number of memory devices operating in parallel in the memory system, the number of processors operating in parallel in the memory system, or both, at least in part based on adjusting queue depth.

[0117] Method 600 and some instances of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining the type of read command used by the memory system for read operations, at least in part based on adjusting the queue depth.

[0118] Method 600 and some instances of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for adjusting the amount of memory resources allocated to the cache, at least in part, based on adjusting the queue depth.

[0119] Method 600 and some instances of the device described herein may further include operations, features, circuit systems, logic, components, or instructions for reallocating at least a portion of resources to a command queue associated with the number of first queue tags but not associated with the number of second queue tags, based at least in part on adjusting the queue depth.

[0120] In some instances of method 600 and the devices described herein, the number of tags in the first queue may be greater than the number of tags in the second queue.

[0121] Method 600 and some instances of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for predicting a threshold queue depth at least in part based on the queue refill time, wherein the queue depth of the command queue can be adjusted to the predicted threshold queue depth.

[0122] In some instances of method 600 and the apparatus described herein, a command may be added to a command queue at a first queue tag, and the method, apparatus, and non-transitory computer-readable medium may contain other operations, features, circuitry, logic, components, or instructions for: executing the command, removing a command from a first queue tag of the command queue at least in part based on the execution of the command, receiving a second command from a host system, and adding a second command to a command queue at a first queue tag at least in part based on the removal of the command from the command queue, wherein the queue refill time may be measured at least in part based on the removal of the command from the first queue tag and the addition of the second command to the command queue at the first queue tag.

[0123] Method 600 and some instances of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: storing a first timestamp, associated with a first queue tag, indicating a first time when a command can be removed from the first queue tag of the command queue; storing a second timestamp, associated with a second queue tag, indicating a second time when a second command can be added to the command queue at the first queue tag; and calculating the difference between the second timestamp and the first timestamp to determine the queue refill time.

[0124] In some instances of method 600 and the device described herein, measuring queue refill time may include operations, features, circuitry, logic, components, or instructions for measuring multiple refill times of multiple queue tags of a command queue and averaging the multiple refill times to determine the queue refill time.

[0125] Method 600 and some examples of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for storing queue refill times at a memory device of a memory system, a controller of a memory system, a command queue, or a combination thereof.

[0126] Method 600 and some instances of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions that adjust the queue refill time of a command queue based at least in part on the execution of one or more additional commands.

[0127] Method 600 and some instances of the devices described herein may further include operations, features, circuit systems, logic, components, or instructions for calculating the threshold performance of a memory system at least in part based on queue refill time, wherein at least one resource may be adjusted at least in part based on the threshold performance.

[0128] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0129] Describe an apparatus. The apparatus may include a memory device and a controller coupled to the memory device and configured to cause the apparatus to: receive commands from a host system; add commands to a command queue, wherein the command queue contains a set of commands to be executed by the memory system, and wherein each of the commands in the set corresponds to a corresponding queue tag of the command queue; measure a queue refill time of the command queue based on a queue tag of the command queue; and adjust at least one resource for the command queue based on the queue refill time.

[0130] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0131] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there is any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0132] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. If, for example, a component of a controller couples other components together, that component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0133] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller performs the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0134] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0135] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a preceding condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0136] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other conditions or actions.

[0137] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0138] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. Each terminal may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "disconnected" or "deactivated".

[0139] The description herein, illustrated with reference to the accompanying drawings, describes example configurations and does not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0140] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0141] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0142] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0143] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0144] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, these technologies are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The above combinations are also included within the scope of computer-readable media.

[0145] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; as well as A controller, coupled to the memory device and configured to cause the device to: Receive commands from the host system; The command is added to a command queue, wherein the command queue includes a plurality of commands to be executed by the memory system, and wherein each of the plurality of commands corresponds to a corresponding queue label of the command queue; The queue refill time of the command queue is measured at least in part based on at least one queue tag of the command queue, the queue refill time corresponding to the time difference between the completion of a first command and the insertion of a new command at the same queue tag; and At least one resource used for the command queue is adjusted, at least in part, based on the queue refill time.

2. The device of claim 1, wherein the controller configured to cause the device to adjust the at least one resource for the command queue is configured to cause the device to: One or more operations are performed at the memory system using the at least one resource for the command queue during the duration associated with the queue refill time.

3. The device of claim 1, wherein the controller configured to cause the device to adjust the at least one resource for the command queue is configured to cause the device to: The activation of the at least one resource for the command queue is revoked during the duration associated with the queue refill time.

4. The device of claim 1, wherein the controller configured to cause the device to adjust the at least one resource for the command queue is configured to cause the device to: The processor's clock rate is adjusted during the duration associated with the queue refill time.

5. The device of claim 1, wherein the controller configured to cause the device to adjust the at least one resource for the command queue is configured to cause the device to: The processor voltage is adjusted during the duration associated with the queue refill time.

6. The device of claim 1, wherein the controller configured to cause the device to adjust the at least one resource for the command queue is configured to cause the device to: The queue depth of the command queue is adjusted from the number of first queue labels to the number of second queue labels, the queue depth corresponding to the threshold number of commands supported by the command queue.

7. The device of claim 6, wherein the controller is further configured to cause the device to: The number of memory devices operating in parallel in the memory system, the number of processors operating in parallel in the memory system, or both, are adjusted at least in part based on adjusting the queue depth.

8. The device of claim 6, wherein the controller is further configured to cause the device to: The type of read command to be used by the memory system for read operations is determined at least in part based on adjusting the queue depth.

9. The device of claim 6, wherein the controller is further configured to cause the device to: The amount of memory resources allocated to the cache is adjusted, at least in part, based on adjusting the queue depth.

10. The device of claim 6, wherein the controller is further configured to cause the device to: At least a portion of the resources are reallocated to the command queue, which is associated with the number of the first queue labels but not with the number of the second queue labels, based at least in part on adjusting the queue depth.

11. The device according to claim 6, wherein the number of first queue tags is greater than the number of second queue tags.

12. The device of claim 6, wherein the controller is further configured to cause the device to: A threshold queue depth is predicted at least in part based on the queue refill time, wherein the queue depth of the command queue is adjusted to the predicted threshold queue depth.

13. The device of claim 1, wherein the command is added to the command queue at a first queue tag, and the controller is further configured to cause the device to: Execute the command; The command is removed from the first queue tag of the command queue, at least in part, based on the execution of the command; Receive a second command from the host system; and The second command is added to the command queue at the first queue tag based at least in part on removing the command from the command queue, wherein the queue refill time is measured based at least in part on removing the command from the first queue tag and adding the second command to the command queue at the first queue tag.

14. The device of claim 13, wherein the controller is further configured to cause the device to: The first timestamp of the first time at which the command is removed from the first queue label of the command queue is stored in a first association with the first queue label; The second timestamp at the second time when the second command is added to the command queue at the first queue tag is stored in a second association with the first queue tag; as well as The difference between the second timestamp and the first timestamp is calculated to determine the queue refill time.

15. The device of claim 1, wherein the controller configured to cause the device to measure the queue refill time is further configured to cause the device to: Measure multiple refill times for multiple queue tags of the command queue; and The average of the multiple refill times is used to determine the queue refill time.

16. The device of claim 1, wherein the controller is further configured to cause the device to: The queue refill time is stored in the memory device of the memory system, the controller of the memory system, the command queue, or a combination thereof.

17. The device of claim 1, wherein the controller is further configured to cause the device to: The refill time of the command queue is adjusted at least in part based on the execution of one or more additional commands.

18. The device of claim 1, wherein the controller is further configured to cause the device to: The threshold performance of the memory system is calculated at least in part based on the queue refill time, and the at least one resource is adjusted at least in part based on the threshold performance.

19. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive commands from the host system; The command is added to a command queue, wherein the command queue includes a plurality of commands to be executed by the memory system, and wherein each of the plurality of commands corresponds to a corresponding queue label of the command queue; The queue refill time of the command queue is measured at least in part based on at least one queue tag of the command queue, the queue refill time corresponding to the time difference between the completion of a first command and the insertion of a new command at the same queue tag; and At least one resource used for the command queue is adjusted, at least in part, based on the queue refill time.

20. A method executed by a memory system, the method comprising: Receive commands from the host system; The command is added to a command queue, wherein the command queue includes a plurality of commands to be executed by the memory system, and wherein each of the plurality of commands corresponds to a corresponding queue label of the command queue; The queue refill time of the command queue is measured at least in part based on at least one queue tag of the command queue, the queue refill time corresponding to the time difference between the completion of a first command and the insertion of a new command at the same queue tag; and At least one resource used for the command queue is adjusted, at least in part, based on the queue refill time.

Images